From a6aa37c5024e8fc2a2517c984a2d628c91de1bb9 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 12 Oct 2021 14:31:04 -0500 Subject: [PATCH 001/505] Summit fixes (#1108) * Replace assert with throw exceptions * fix conditional branch instruction conversion to Rose instruction for ppc64le --- dataflowAPI/rose/semantics/SymEvalSemantics.C | 25 +++++++++++-------- dataflowAPI/src/RoseInsnFactory.C | 2 +- 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/dataflowAPI/rose/semantics/SymEvalSemantics.C b/dataflowAPI/rose/semantics/SymEvalSemantics.C index 0467fff718..7c3044de9f 100644 --- a/dataflowAPI/rose/semantics/SymEvalSemantics.C +++ b/dataflowAPI/rose/semantics/SymEvalSemantics.C @@ -4,8 +4,10 @@ #include #include "SymEvalSemantics.h" +#include "BaseSemantics2.h" using namespace rose::BinaryAnalysis::InstructionSemantics2; +using RoseException = BaseSemantics::Exception; /////////////////////////////////////////////////////// // StateAST @@ -194,7 +196,8 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTARM64::convert(const RegisterD break; case 128: base = Dyninst::aarch64::q0; break; - default:assert(!"invalid size of RegisterDescriptor!"); + default: + throw RoseException("invalid size of RegisterDescriptor!", nullptr); break; } mreg = Dyninst::MachRegister(base.val() + (minor - armv8_simdfpr_v0)); @@ -267,13 +270,13 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD Dyninst::MachRegister base = Dyninst::ppc32::cr0l; mreg = Dyninst::MachRegister(base.val() + offset); } else { - assert(!"bad cr register size"); + throw RoseException("bad cr register size", nullptr); } } break; case powerpc_regclass_fpscr: - assert(!"not implemented register class fpscr"); + throw RoseException("not implemented register class fpscr", nullptr); break; case powerpc_regclass_spr: { @@ -298,12 +301,12 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD mreg = Dyninst::ppc32::dec; break; default: - assert(!"not implemented special register"); + throw RoseException("not implemented special register", nullptr); } } break; case powerpc_regclass_tbr: - assert(!"not implemented regclass tbr"); + throw RoseException("not implemented regclass tbr", nullptr); break; case powerpc_regclass_msr: @@ -311,7 +314,7 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD break; case powerpc_regclass_sr: - assert(!"not implemented regclass sr"); + throw RoseException("not implemented regclass sr", nullptr); break; case powerpc_regclass_iar: @@ -361,13 +364,13 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD Dyninst::MachRegister base = Dyninst::ppc64::cr0l; mreg = Dyninst::MachRegister(base.val() + offset); } else { - assert(!"bad cr register size"); + throw RoseException("bad cr register size", nullptr); } } break; case powerpc_regclass_fpscr: - assert(!"not implemented register class fpscr"); + throw RoseException("not implemented register class fpscr", nullptr); break; case powerpc_regclass_spr: { @@ -392,12 +395,12 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD mreg = Dyninst::ppc64::dec; break; default: - assert(!"not implemented special register"); + throw RoseException("not implemented special register", nullptr); } } break; case powerpc_regclass_tbr: - assert(!"not implemented regclass tbr"); + throw RoseException("not implemented regclass tbr", nullptr); break; case powerpc_regclass_msr: @@ -405,7 +408,7 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD break; case powerpc_regclass_sr: - assert(!"not implemented regclass sr"); + throw RoseException("not implemented regclass sr", nullptr); break; case powerpc_regclass_iar: diff --git a/dataflowAPI/src/RoseInsnFactory.C b/dataflowAPI/src/RoseInsnFactory.C index b0120f5e90..dca41564ab 100644 --- a/dataflowAPI/src/RoseInsnFactory.C +++ b/dataflowAPI/src/RoseInsnFactory.C @@ -316,7 +316,7 @@ bool RoseInsnPPCFactory::handleSpecialCases(entryID iapi_opcode, // It looks like the ROSE semantics code will infer the target from // the bo field. So, what is passed in as the third operands does not matter - if(branch_target) { + if(power_op_b == iapi_opcode || power_op_bc == iapi_opcode) { rose_operands->append_operand(new SgAsmDoubleWordValueExpression(branch_target)); } else if(power_op_bcctr == iapi_opcode) { rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_ctr)); From 6f9683ec1a6b289271b0d1e73a024b65644d5494 Mon Sep 17 00:00:00 2001 From: Zixian Liu Date: Wed, 20 Oct 2021 01:06:28 +0800 Subject: [PATCH 002/505] Remove boost_system linking (#1112) boost_system is header-only in 1.69.0 which is the min version required by dyninst. Signed-off-by: sdlzx --- cmake/Boost.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/Boost.cmake b/cmake/Boost.cmake index 231f3313dd..727d04a24c 100644 --- a/cmake/Boost.cmake +++ b/cmake/Boost.cmake @@ -132,7 +132,7 @@ set(Boost_NO_BOOST_CMAKE ON) # The required Boost library components # NB: These are just the ones that require compilation/linking # This should _not_ be a cache variable -set(_boost_components atomic chrono date_time filesystem system thread timer) +set(_boost_components atomic chrono date_time filesystem thread timer) find_package(Boost ${Boost_MIN_VERSION} COMPONENTS ${_boost_components}) From 66ee56976c6a416a3c60313c4bd6f84bcd22ed4d Mon Sep 17 00:00:00 2001 From: kupsch Date: Fri, 22 Oct 2021 15:10:26 -0500 Subject: [PATCH 003/505] update minimum boost version to 1.70.0 (#1117) --- cmake/Boost.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/Boost.cmake b/cmake/Boost.cmake index 727d04a24c..53fe321ef4 100644 --- a/cmake/Boost.cmake +++ b/cmake/Boost.cmake @@ -51,7 +51,7 @@ if(Boost_FOUND) endif() # Need at least Boost-1.67 because of deprecated headers -set(_boost_min_version 1.67.0) +set(_boost_min_version 1.70.0) # Provide a default, if the user didn't specify set(Boost_MIN_VERSION ${_boost_min_version} CACHE STRING "Minimum Boost version") From 5e142effcd91f552aad8f98c075d40c7ae017f98 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 19 Oct 2021 13:46:44 -0500 Subject: [PATCH 004/505] Remove stabs from SymtabAPI --- symtabAPI/CMakeLists.txt | 1 - symtabAPI/h/Collections.h | 2 +- symtabAPI/h/Symbol.h | 3 - symtabAPI/h/Symtab.h | 4 - symtabAPI/h/Type.h | 2 - symtabAPI/src/Object-elf.C | 946 +------------- symtabAPI/src/Object-elf.h | 200 +-- symtabAPI/src/Symtab.C | 13 +- symtabAPI/src/parseStab.C | 2423 ------------------------------------ 9 files changed, 5 insertions(+), 3589 deletions(-) delete mode 100644 symtabAPI/src/parseStab.C diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 1f1f2027f7..f0d9e11c10 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -42,7 +42,6 @@ set (SRC_LIST ${SRC_LIST} src/Archive.C src/Archive-elf.C src/parseDwarf.C - src/parseStab.C src/LinkMap.C src/emitElf.C src/emitElfStatic.C diff --git a/symtabAPI/h/Collections.h b/symtabAPI/h/Collections.h index 55257a6854..0e46630729 100644 --- a/symtabAPI/h/Collections.h +++ b/symtabAPI/h/Collections.h @@ -131,7 +131,7 @@ class SYMTAB_EXPORT typeCollection /* Some debug formats allow forward references. Rather than fill in forward in a second pass, generate placeholder types, and fill them in as we go. Because we require - One True Pointer for each type (in parseStab.C), when + One True Pointer for each type, when updating a type, return that One True Pointer. */ boost::shared_ptr findOrCreateType( const int ID, Type::do_share_t ); Type* findOrCreateType(const int i) { return findOrCreateType(i, Type::share).get(); } diff --git a/symtabAPI/h/Symbol.h b/symtabAPI/h/Symbol.h index f9318e8b4a..e4e8b29830 100644 --- a/symtabAPI/h/Symbol.h +++ b/symtabAPI/h/Symbol.h @@ -77,9 +77,6 @@ class SYMTAB_EXPORT Symbol : public AnnotatableSparse friend class Aggregate; friend class relocationEntry; - friend std::string parseStabString(Module *, int linenum, char *, int, - typeCommon *); - public: struct Ptr { diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 8a7730ef06..1c1815fc7f 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -625,10 +625,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, int nlines_; unsigned long fdptr_; char *lines_; - char *stabstr_; - int nstabs_; - void *stabs_; - char *stringpool_; //Relocation sections bool hasRel_; diff --git a/symtabAPI/h/Type.h b/symtabAPI/h/Type.h index b827802e66..3349c91134 100644 --- a/symtabAPI/h/Type.h +++ b/symtabAPI/h/Type.h @@ -111,8 +111,6 @@ SYMTAB_EXPORT const char *visibility2Str(visibility_t v); class SYMTAB_EXPORT Type : public TYPE_ANNOTATABLE_CLASS { friend class typeCollection; - friend std::string parseStabString(Module *, int linenum, char *, int, - typeCommon*); static Type* upgradePlaceholder(Type *placeholder, Type *new_type); boost::weak_ptr self_; // For carrying the reference count across diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 822eb588d1..7a52479f7e 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -86,7 +86,6 @@ bool Object::truncateLineFilenames = false; string symt_current_func_name; string symt_current_mangled_func_name; -Symbol *symt_current_func = NULL; std::vector opdsymbols_; @@ -297,10 +296,6 @@ const char *BSS_NAME = ".bss"; const char *SYMTAB_NAME = ".symtab"; const char *STRTAB_NAME = ".strtab"; const char *SYMTAB_SHNDX_NAME = ".symtab_shndx"; -const char *STAB_NAME = ".stab"; -const char *STABSTR_NAME = ".stabstr"; -const char *STAB_INDX_NAME = ".stab.index"; -const char *STABSTR_INDX_NAME = ".stab.indexstr"; const char *COMMENT_NAME = ".comment"; const char *OPD_NAME = ".opd"; // PPC64 Official Procedure Descriptors // sections from dynamic executables and shared objects @@ -336,8 +331,6 @@ set debugInfoSections = list_of(string(SYMTAB_NAME)) bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, Elf_X_Shdr *&bssscnp, Elf_X_Shdr *&symscnp, Elf_X_Shdr *&strscnp, - Elf_X_Shdr *&stabscnp, Elf_X_Shdr *&stabstrscnp, - Elf_X_Shdr *&stabs_indxcnp, Elf_X_Shdr *&stabstrs_indxcnp, Elf_X_Shdr *&rel_plt_scnp, Elf_X_Shdr *&plt_scnp, Elf_X_Shdr *&got_scnp, Elf_X_Shdr *&dynsym_scnp, Elf_X_Shdr *&dynstr_scnp, Elf_X_Shdr *&dynamic_scnp, @@ -405,12 +398,6 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, rel_addr_ = 0; rel_size_ = 0; rel_entry_size_ = 0; - stab_off_ = 0; - stab_size_ = 0; - stabstr_off_ = 0; - stab_indx_off_ = 0; - stab_indx_size_ = 0; - stabstr_indx_off_ = 0; dwarvenDebugInfo = false; txtaddr = 0; @@ -750,22 +737,7 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, strscnp = scnp; strtab_addr_ = scn.sh_addr(); } - } else if (strcmp(name, STAB_INDX_NAME) == 0) { - stabs_indxcnp = scnp; - stab_indx_off_ = scn.sh_offset(); - stab_indx_size_ = scn.sh_size(); - } else if (strcmp(name, STABSTR_INDX_NAME) == 0) { - stabstrs_indxcnp = scnp; - stabstr_indx_off_ = scn.sh_offset(); - } else if (strcmp(name, STAB_NAME) == 0) { - stabscnp = scnp; - stab_off_ = scn.sh_offset(); - stab_size_ = scn.sh_size(); - } else if (strcmp(name, STABSTR_NAME) == 0) { - stabstrscnp = scnp; - stabstr_off_ = scn.sh_offset(); - } - else if ((secAddrTagMapping.find(scn.sh_addr()) != secAddrTagMapping.end()) && + } else if ((secAddrTagMapping.find(scn.sh_addr()) != secAddrTagMapping.end()) && secAddrTagMapping[scn.sh_addr()] == DT_JMPREL) { rel_plt_scnp = scnp; rel_plt_addr_ = scn.sh_addr(); @@ -1483,10 +1455,6 @@ void Object::load_object(bool alloc_syms) { Elf_X_Shdr *bssscnp = 0; Elf_X_Shdr *symscnp = 0; Elf_X_Shdr *strscnp = 0; - Elf_X_Shdr *stabscnp = 0; - Elf_X_Shdr *stabstrscnp = 0; - Elf_X_Shdr *stabs_indxcnp = 0; - Elf_X_Shdr *stabstrs_indxcnp = 0; Offset txtaddr = 0; Offset dataddr = 0; Elf_X_Shdr *rel_plt_scnp = 0; @@ -1513,7 +1481,6 @@ void Object::load_object(bool alloc_syms) { // EEL, added one more parameter if (!loaded_elf(txtaddr, dataddr, bssscnp, symscnp, strscnp, - stabscnp, stabstrscnp, stabs_indxcnp, stabstrs_indxcnp, rel_plt_scnp, plt_scnp, got_scnp, dynsym_scnp, dynstr_scnp, dynamic_scnp, eh_frame_scnp, gcc_except, interp_scnp, opd_scnp, symtab_shndx_scnp, true)) { @@ -1547,8 +1514,7 @@ void Object::load_object(bool alloc_syms) { interpreter_name_ = (char *) interp_scnp->get_data().d_buf(); } - // global symbols are put in global_symbols. Later we read the - // stab section to find the module to where they belong. + // global symbols are put in global_symbols. // Experiment : lets try to be a bit more intelligent about // how we initially size the global_symbols table. // dictionary_lite takes an initial # of bins (2nd param), @@ -1575,12 +1541,6 @@ void Object::load_object(bool alloc_syms) { no_of_symbols_ = nsymbols(); // try to resolve the module names of global symbols - // Sun compiler stab.index section - fix_global_symbol_modules_static_stab(stabs_indxcnp, stabstrs_indxcnp); - - // STABS format (.stab section) - fix_global_symbol_modules_static_stab(stabscnp, stabstrscnp); - // DWARF format (.debug_info section) fix_global_symbol_modules_static_dwarf(); @@ -2424,224 +2384,6 @@ bool Object::fix_global_symbol_modules_static_dwarf() #endif // cap_dwarf -/******************************************************** - * - * For object files only.... - * read the .stab section to find the module of global symbols - * - ********************************************************/ - -bool Object::fix_global_symbol_modules_static_stab(Elf_X_Shdr *stabscnp, Elf_X_Shdr *stabstrscnp) { - // Read the stab section to find the module of global symbols. - // The symbols appear in the stab section by module. A module begins - // with a symbol of type N_UNDF and ends with a symbol of type N_ENDM. - // All the symbols in between those two symbols belong to the module. - - if (!stabscnp || !stabstrscnp) return false; - - Elf_X_Data stabdata = stabscnp->get_data(); - Elf_X_Data stabstrdata = stabstrscnp->get_data(); - stab_entry *stabptr = NULL; - - if (!stabdata.isValid() || !stabstrdata.isValid()) return false; - - switch (addressWidth_nbytes) { - case 4: - stabptr = new stab_entry_32(stabdata.d_buf(), - stabstrdata.get_string(), - stabscnp->sh_size() / sizeof(stab32)); - break; - - case 8: - stabptr = new stab_entry_64(stabdata.d_buf(), - stabstrdata.get_string(), - stabscnp->sh_size() / sizeof(stab64)); - break; - }; - - const char *next_stabstr = stabptr->getStringBase(); - string module = "DEFAULT_MODULE"; - - // the stabstr contains one string table for each module. - // stabstr_offset gives the offset from the begining of stabstr of the - // string table for the current module. - - bool is_fortran = false; // is the current module fortran code? - - for (unsigned i = 0; i < stabptr->count(); i++) { - switch (stabptr->type(i)) { - case N_UNDF: /* start of object file */ - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - break; - - case N_ENDM: /* end of object file */ - is_fortran = false; - module = "DEFAULT_MODULE"; - break; - - case N_SO: /* compilation source or file name */ - if ((stabptr->desc(i) == N_SO_FORTRAN) || (stabptr->desc(i) == N_SO_F90)) - is_fortran = true; - - module = string(stabptr->name(i)); - break; - - case N_ENTRY: /* fortran alternate subroutine entry point */ - case N_GSYM: /* global symbol */ - // the name string of a function or object appears in the stab - // string table as : - // where is a one char code. - // we must extract the name and descriptor from the string - { - const char *p = stabptr->name(i); - // bperr("got %d type, str = %s\n", stabptr->type(i), p); - // if (stabptr->type(i) == N_FUN && strlen(p) == 0) { - - if (strlen(p) == 0) { - // GNU CC 2.8 and higher associate a null-named function - // entry with the end of a function. Just skip it. - break; - } - - const char *q = strchr(p, ':'); - unsigned len; - - if (q) { - len = q - p; - } else { - len = strlen(p); - } - - if (len == 0) { - // symbol name is empty.Skip it.- 02/12/07 -Giri - break; - } - - char *sname = new char[len + 1]; - strncpy(sname, p, len); - sname[len] = 0; - - string SymName = string(sname); - - // q points to the ':' in the name string, so - // q[1] is the symbol descriptor. We must check the symbol descriptor - // here to skip things we are not interested in, such as prototypes. - - bool res = symbols_.contains(SymName); - - if (!res && is_fortran) { - // Fortran symbols usually appear with an '_' appended in .symtab, - // but not on .stab - SymName += "_"; - res = symbols_.contains(SymName); - } - - if (res && (q == 0 || q[1] != SD_PROTOTYPE)) { - unsigned int count = 0; - dyn_c_hash_map>::const_accessor ca; - if (!symbols_.find(ca, SymName)) { - assert(!"symbols_.find(ca, SymName)"); - } - const std::vector &syms = ca->second; - - /* If there's only one, apply regardless. */ - if (syms.size() == 1) { - // TODO: set module - // symbols_[SymName][0]->setModuleName(module); - } else { - for (unsigned int j = 0; j < syms.size(); j++) { - if (syms[j]->getLinkage() == Symbol::SL_GLOBAL) { - // TODO: set module - // symbols_[SymName][j]->setModuleName(module); - count++; - } - } - } - } - break; - } - case N_FUN: - /* function */ - { - const char *p = stabptr->name(i); - - if (strlen(p) == 0) { - // Rumours are that GNU CC 2.8 and higher associate a - // null-named function entry with the end of a - // function. Just skip it. - break; - } - - const char *q = strchr(p, ':'); - - if (q == 0) { - // bperr( "Unrecognized stab format: %s\n", p); - // Happens with the Solaris native compiler (.xstabs entries?) - break; - } - - if (q[1] == SD_PROTOTYPE) { - // We see a prototype, skip it - break; - } - - unsigned long entryAddr = stabptr->val(i); - - if (entryAddr == 0) { - // The function stab doesn't contain a function address - // (happens with the Solaris native compiler). We have to - // look up the symbol by its name. That's unfortunate, since - // names may not be unique and we may end up assigning a wrong - // module name to the symbol. - unsigned len = q - p; - if (len == 0) { - // symbol name is empty.Skip it.- 02/12/07 -Giri - break; - } - - char *sname = new char[len + 1]; - strncpy(sname, p, len); - sname[len] = 0; - string nameFromStab = string(sname); - delete[] sname; - - dyn_c_hash_map>::const_accessor ca; - if (!symbols_.find(ca, nameFromStab)) { - assert(!"symbols_.find(ca, nameFromStab)"); - } - for (unsigned j = 0; j < ca->second.size(); j++) { - symsToModules_.insert({ca->second[j], module}); - } - } else { - if (!symsByOffset_.contains(entryAddr)) { - //bperr( "fix_global_symbol_modules_static_stab " - // "can't find address 0x%lx of STABS entry %s\n", entryAddr, p); - break; - } - dyn_c_hash_map>::const_accessor ca; - if (!symsByOffset_.find(ca, entryAddr)) { - assert(!"symsByOffset_.find(ca, entryAddr)"); - } - for (unsigned j = 0; j < ca->second.size(); j++) { - symsToModules_.insert({ca->second[j], module}); - } - } - break; - } - - default: - /* ignore other entries */ - break; - } - } - - delete stabptr; - - return true; -} - - // find_code_and_data(): populates the following members: // code_ptr_, code_off_, code_len_ // data_ptr_, data_off_, data_len_ @@ -2709,28 +2451,6 @@ const char *Object::elf_vaddr_to_ptr(Offset vaddr) const { return ret; } -stab_entry *Object::get_stab_info() const { - char *file_ptr = (char *) mf->base_addr(); - - // check that file has .stab info - if (stab_off_ && stab_size_ && stabstr_off_) { - switch (addressWidth_nbytes) { - case 4: // 32-bit object - return new stab_entry_32(file_ptr + stab_off_, - file_ptr + stabstr_off_, - stab_size_ / sizeof(stab32)); - break; - case 8: // 64-bit object - return new stab_entry_64(file_ptr + stab_off_, - file_ptr + stabstr_off_, - stab_size_ / sizeof(stab64)); - break; - }; - } - - return new stab_entry_64(); -} - Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), bool alloc_syms, Symtab *st) : AObject(mf_, err_func, st), @@ -2752,8 +2472,6 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), rel_plt_addr_(0), rel_plt_size_(0), rel_plt_entry_size_(0), rel_addr_(0), rel_size_(0), rel_entry_size_(0), opd_addr_(0), opd_size_(0), - stab_off_(0), stab_size_(0), stabstr_off_(0), - stab_indx_off_(0), stab_indx_size_(0), stabstr_indx_off_(0), dwarvenDebugInfo(false), loadAddress_(0), entryAddress_(0), interpreter_name_(NULL), @@ -2891,9 +2609,6 @@ const ostream &Object::dump_state_info(ostream &s) s << " rel_plt_entry_size_ = " << rel_plt_entry_size_ << endl; s << " rel_size_ = " << rel_size_ << endl; s << " rel_entry_size_ = " << rel_entry_size_ << endl; - s << " stab_off_ = " << stab_off_ << endl; - s << " stab_size_ = " << stab_size_ << endl; - s << " stabstr_off_ = " << stabstr_off_ << endl; s << " dwarvenDebugInfo = " << dwarvenDebugInfo << endl; // and dump the relocation table.... @@ -3487,166 +3202,8 @@ ObjectType Object::objType() const { void Object::getModuleLanguageInfo(dyn_hash_map *mod_langs) { string working_module; const char *ptr; - // check .stabs section to get language info for modules: - // int stab_nsyms; - // char *stabstr_nextoffset; - // const char *stabstrs = 0; - string mod_string; - // This ugly flag is set when certain (sun) fortran compilers are detected. - // If it is set at any point during the following iteration, this routine - // ends with "backtrack mode" and reiterates through all chosen languages, changing - // lang_Fortran to lang_Fortran_with_pretty_debug. - // - // This may be ugly, but it is set up this way since the information that is used - // to determine whether this flag is set comes from the N_OPT field, which - // seems to come only once per image. The kludge is that we assume that all - // fortran sources in the module have this property (they probably do, but - // could conceivably be mixed (???)). - int fortran_kludge_flag = 0; - - // "state variables" we use to accumulate potentially useful information - // A final module<->language decision is not made until we have arrived at the - // next module entry, at which point we use any and all info we have to - // make the most sensible guess - supportedLanguages working_lang = lang_Unknown; - char *working_options = NULL; - const char *working_name = NULL; - - stab_entry *stabptr = NULL; - const char *next_stabstr = NULL; -#if defined(TIMED_PARSE) - struct timeval starttime; - gettimeofday(&starttime, NULL); -#endif - - //Using the Object to get the pointers to the .stab and .stabstr - // XXX - Elf32 specific needs to be in seperate file -- jkh 3/18/99 - stabptr = get_stab_info(); - next_stabstr = stabptr->getStringBase(); - - for (unsigned int i = 0; i < stabptr->count(); i++) { - if (stabptr->type(i) == N_UNDF) {/* start of object file */ - /* value contains offset of the next string table for next module */ - // assert(stabptr->nameIdx(i) == 1); - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - } else if (stabptr->type(i) == N_OPT) { - // We can use the compiler option string (in a pinch) to guess at the source file language - // There is possibly more useful information encoded somewhere around here, but I lack - // an immediate reference.... - if (working_name) - working_options = const_cast(stabptr->name(i)); - } else if ((stabptr->type(i) == N_SO) || (stabptr->type(i) == N_ENDM)) { /* compilation source or file name */ - // We have arrived at the next source file, finish up with the last one and reset state - // before starting next - - - // XXXXXXXXXXX This block is mirrored near the end of routine, if you edit it, - // XXXXXXXXXXX change it there too. - if (working_name) { - working_lang = pickLanguage(working_module, working_options, working_lang); - if (working_lang == lang_Fortran_with_pretty_debug) - fortran_kludge_flag = 1; - (*mod_langs)[working_module] = working_lang; - - } - // XXXXXXXXXXX - - // reset "state" here - working_lang = lang_Unknown; - working_options = NULL; - - // Now: out with the old, in with the new - - if (stabptr->type(i) == N_ENDM) { - // special case: - // which is most likely both broken (and ignorable ???) - working_name = "DEFAULT_MODULE"; - } else { - working_name = stabptr->name(i); - ptr = strrchr(working_name, '/'); - if (ptr) { - ptr++; - working_name = ptr; - } - } - working_module = string(working_name); - - if ((mod_langs->find(working_module) != mod_langs->end()) && (*mod_langs)[working_module] != lang_Unknown) { - // we already have a module with this name in the map. If it has been given - // a language assignment (not lang_Unknown), we can just skip ahead - working_name = NULL; - working_options = NULL; - continue; - } else { - //cerr << __FILE__ << __LINE__ << ": Module: " <desc(i) << endl; - switch (stabptr->desc(i)) { - case N_SO_FORTRAN: - working_lang = lang_Fortran; - break; - case N_SO_F90: - working_lang = lang_Fortran; // not sure if this should be different from N_SO_FORTRAN - break; - case N_SO_AS: - working_lang = lang_Assembly; - break; - case N_SO_ANSI_C: - case N_SO_C: - working_lang = lang_C; - break; - case N_SO_CC: - working_lang = lang_CPlusPlus; - break; - default: - // currently uncovered options are lang_CMFortran, and lang_GnuCPlusPlus - // do we need to make this kind of distinction here? - working_lang = lang_Unknown; - break; - } - - } - } // end N_SO section - } // for loop - - // Need to make sure we finish up with the module we were last collecting information - // about - - // XXXXXXXXXXX see note above (find the X's) - if (working_name) { - working_lang = pickLanguage(working_module, working_options, working_lang); - if (working_lang == lang_Fortran_with_pretty_debug) - fortran_kludge_flag = 1; - (*mod_langs)[working_module] = working_lang; - } - // XXXXXXXXXXX - - if (fortran_kludge_flag) { - // XXX This code does not appear to be used anymore?? - // go through map and change all lang_Fortran to lang_Fortran_with_pretty_symtab - dyn_hash_map::iterator iter = (*mod_langs).begin(); - string aname; - supportedLanguages alang; - for (; iter != (*mod_langs).end(); iter++) { - aname = iter->first; - alang = iter->second; - if (lang_Fortran == alang) { - (*mod_langs)[aname] = lang_Fortran_with_pretty_debug; - } - } - } -#if defined(TIMED_PARSE) - struct timeval endtime; - gettimeofday(&endtime, NULL); - unsigned long lstarttime = starttime.tv_sec * 1000 * 1000 + starttime.tv_usec; - unsigned long lendtime = endtime.tv_sec * 1000 * 1000 + endtime.tv_usec; - unsigned long difftime = lendtime - lstarttime; - double dursecs = difftime/(1000 ); - cout << __FILE__ << ":" << __LINE__ <<": getModuleLanguageInfo took "<type_dbg(); @@ -3792,191 +3349,6 @@ const char *Object::interpreter_name() const { return interpreter_name_; } -/* Parse everything in the file on disk, and cache that we've done so, - because our modules may not bear any relation to the name source files. */ -void Object::parseStabFileLineInfo() { - static dyn_hash_map haveParsedFileMap; - - /* We haven't parsed this file already, so iterate over its stab entries. */ - - stab_entry *stabEntry = get_stab_info(); - if (stabEntry == NULL) return; - const char *nextStabString = stabEntry->getStringBase(); - - const char *currentSourceFile = NULL; - const char *moduleName = NULL; - Function *currentFunction = NULL; - Offset currentAddress = 0; - unsigned currentLineBase = 0; - unsigned functionLineToPossiblyAdd = 0; - - //Offset baseAddress = getBaseAddress(); - LineInformation *li_for_module = NULL; - - for (unsigned int i = 0; i < stabEntry->count(); i++) { - switch (stabEntry->type(i)) { - case N_UNDF: /* start of an object file */ - { - stabEntry->setStringBase(nextStabString); - nextStabString = stabEntry->getStringBase() + stabEntry->val(i); - - currentSourceFile = NULL; - } - break; - - case N_SO: /* compilation source or file name */ - { - const char *sourceFile = stabEntry->name(i); - currentSourceFile = strrchr(sourceFile, '/'); - - if (currentSourceFile == NULL) { - currentSourceFile = sourceFile; - } else { - ++currentSourceFile; - } - Module *mod; - - moduleName = currentSourceFile; - if (!associated_symtab->findModuleByName(mod, moduleName)) { - mod = associated_symtab->getDefaultModule(); - } - li_for_module = mod->getLineInformation(); - if (!li_for_module) { - li_for_module = new LineInformation; - mod->setLineInfo(li_for_module); - } - - } - break; - - case N_SOL: /* file name (possibly an include file) */ - { - const char *sourceFile = stabEntry->name(i); - currentSourceFile = strrchr(sourceFile, '/'); - if (currentSourceFile == NULL) { - currentSourceFile = sourceFile; - } else { - ++currentSourceFile; - } - - } - break; - - case N_FUN: /* a function */ - { - if (*stabEntry->name(i) == 0) { - currentFunction = NULL; - currentLineBase = 0; - break; - } /* end if the N_FUN is an end-of-function-marker. */ - - std::vector funcs; - char stringbuf[2048]; - const char *stabstr = stabEntry->name(i); - unsigned iter = 0; - - while (iter < 2048) { - char c = stabstr[iter]; - - if ((c == ':') || (c == '\0')) { - //stabstrs use ':' as delimiter - stringbuf[iter] = '\0'; - break; - } - - stringbuf[iter] = c; - - iter++; - } - - if (iter >= 2047) { - create_printf("%s[%d]: something went horribly awry\n", FILE__, __LINE__); - continue; - } else { - switch (stabstr[iter + 1]) { - case 'F': - case 'f': - // A "good" function - break; - case 'P': - case 'p': - // A prototype function? need to discard - continue; - break; - default: - continue; - break; - }; - } - - if (!associated_symtab->findFunctionsByName(funcs, std::string(stringbuf)) - || !funcs.size()) { - continue; - } - - currentFunction = funcs[0]; - currentLineBase = stabEntry->desc(i); - functionLineToPossiblyAdd = currentLineBase; - - if (!currentFunction) continue; - currentAddress = currentFunction->getOffset(); - - } - break; - - case N_SLINE: { - unsigned current_col = 0; - - if (!currentLineBase) { - continue; - } - - unsigned newLineSpec = stabEntry->desc(i); - - // Addresses specified in SLINEs are relative to the beginning of the fn - Offset newLineAddress = stabEntry->val(i) + currentFunction->getOffset(); - - if (newLineAddress <= currentAddress) { - continue; - } - - // If we just got our first N_SLINE after a function definition - // its possible that the line number specified in the function - // definition was less than the line number that we are currently on - // If so, add an additional line number entry that encompasses - // the line number of the original function definition in addition - // to this SLINE ( use the same address range) - - if (functionLineToPossiblyAdd) { - if (functionLineToPossiblyAdd < newLineSpec) { - if (li_for_module) - li_for_module->addLine(currentSourceFile, - functionLineToPossiblyAdd, - current_col, currentAddress, - newLineAddress); - } - - functionLineToPossiblyAdd = 0; - } - - if (li_for_module) - li_for_module->addLine(currentSourceFile, newLineSpec, - current_col, currentAddress, - newLineAddress); - - currentAddress = newLineAddress; - currentLineBase = newLineSpec + 1; - - } - break; - - } /* end switch on the ith stab entry's type */ - - } /* end iteration over stab entries. */ - - // haveParsedFileMap[ key ] = true; -} /* end parseStabFileLineInfo() */ - class open_statement { public: open_statement() { reset(); } @@ -4391,7 +3763,6 @@ void Object::parseDwarfFileLineInfo() void Object::parseFileLineInfo() { if (parsedAllLineInfo) return; - parseStabFileLineInfo(); parseDwarfFileLineInfo(); parsedAllLineInfo = true; @@ -4403,7 +3774,6 @@ void Object::parseTypeInfo() { gettimeofday(&starttime, NULL); #endif - parseStabTypes(); Dwarf **typeInfo = dwarf->type_dbg(); if (!typeInfo) return; DwarfWalker walker(associated_symtab, *typeInfo); @@ -4420,318 +3790,6 @@ void Object::parseTypeInfo() { #endif } -void Object::parseStabTypes() { - types_printf("Entry to parseStabTypes for %s\n", associated_symtab->name().c_str()); - stab_entry *stabptr = NULL; - const char *next_stabstr = NULL; - - unsigned i; - char *modName = NULL; - string temp; - char *ptr = NULL, *ptr2 = NULL, *ptr3 = NULL; - bool parseActive = false; - - std::string *currentFunctionName = NULL; - Symbol *commonBlockVar = NULL; - string *commonBlockName = NULL; - boost::shared_ptr commonBlock = NULL; - - Module *mod; - typeCollection *tc = NULL; - -#if defined(TIMED_PARSE) - struct timeval starttime; - gettimeofday(&starttime, NULL); - unsigned int pss_count = 0; - double pss_dur = 0; - unsigned int src_count = 0; - double src_dur = 0; - unsigned int fun_count = 0; - double fun_dur = 0; - struct timeval t1, t2; -#endif - - - stabptr = get_stab_info(); - if (!stabptr) { - types_printf("\tWarning: no stab ptr, returning immediately\n"); - return; - } - - //Using the Object to get the pointers to the .stab and .stabstr - // XXX - Elf32 specific needs to be in seperate file -- jkh 3/18/99 - next_stabstr = stabptr->getStringBase(); - types_printf("\t Parsing %lu stab entries\n", stabptr->count()); - for (i = 0; i < stabptr->count(); i++) { - switch (stabptr->type(i)) { - case N_UNDF: /* start of object file */ - /* value contains offset of the next string table for next module */ - // assert(stabptr->nameIdx(i) == 1); - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - - //N_UNDF is the start of object file. It is time to - //clean source file name at this moment. - /* - if(currentSourceFile){ - delete currentSourceFile; - currentSourceFile = NULL; - delete absoluteDirectory; - absoluteDirectory = NULL; - delete currentFunctionName; - currentFunctionName = NULL; - currentFileInfo = NULL; - currentFuncInfo = NULL; - } - */ - break; - - case N_ENDM: /* end of object file */ - break; - - case N_SO: /* compilation source or file name */ - /* bperr("Resetting CURRENT FUNCTION NAME FOR NEXT OBJECT FILE\n");*/ -#ifdef TIMED_PARSE - src_count++; - gettimeofday(&t1, NULL); -#endif - symt_current_func_name = ""; // reset for next object file - symt_current_mangled_func_name = ""; // reset for next object file - symt_current_func = NULL; - - modName = const_cast(stabptr->name(i)); - // cerr << "checkpoint B" << endl; - ptr = strrchr(modName, '/'); - // cerr << "checkpoint C" << endl; - if (ptr) { - ptr++; - modName = ptr; - } - if (associated_symtab->findModuleByName(mod, modName)) { - tc = typeCollection::getModTypeCollection(mod); - parseActive = true; - if (!mod) { - create_printf("%s[%d]: FIXME\n", FILE__, __LINE__); - } else if (!tc) { - create_printf("%s[%d]: FIXME\n", FILE__, __LINE__); - } else - tc->clearNumberedTypes(); - } else { - //parseActive = false; - mod = associated_symtab->getDefaultModule(); - tc = typeCollection::getModTypeCollection(mod); - types_printf("\t Warning: failed to find module name matching %s, using %s\n", modName, - mod->fileName().c_str()); - } - -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - src_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - //src_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000) ; -#endif - break; - case N_SLINE: - break; - default: - break; - } - if (parseActive || !is_aout()) { - std::vector bpfv; - switch (stabptr->type(i)) { - case N_FUN: -#ifdef TIMED_PARSE - fun_count++; - gettimeofday(&t1, NULL); -#endif - //all we have to do with function stabs at this point is to assure that we have - //properly set the var currentFunctionName for the later case of (parseActive) - symt_current_func = NULL; - int currentEntry = i; - int funlen = strlen(stabptr->name(currentEntry)); - ptr = new char[funlen + 1]; - strcpy(ptr, stabptr->name(currentEntry)); - while (strlen(ptr) != 0 && ptr[strlen(ptr) - 1] == '\\') { - ptr[strlen(ptr) - 1] = '\0'; - currentEntry++; - strcat(ptr, stabptr->name(currentEntry)); - } - char *colonPtr = NULL; - if (currentFunctionName) delete currentFunctionName; - if (!ptr || !(colonPtr = strchr(ptr, ':'))) - currentFunctionName = NULL; - else { - char *tmp = new char[colonPtr - ptr + 1]; - strncpy(tmp, ptr, colonPtr - ptr); - tmp[colonPtr - ptr] = '\0'; - currentFunctionName = new string(tmp); - // Shouldn't this be a function name lookup? - std::vector syms; - if (!associated_symtab->findSymbol(syms, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - if (!associated_symtab->findSymbol(syms, - "_" + *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - string fortranName = *currentFunctionName + string("_"); - if (associated_symtab->findSymbol(syms, - fortranName, - Symbol::ST_FUNCTION, - mangledName)) { - delete currentFunctionName; - currentFunctionName = new string(fortranName); - } - } - } - syms.clear(); - delete[] tmp; - } - delete[] ptr; -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - fun_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - //fun_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000); -#endif - break; - } - if (!parseActive) continue; - switch (stabptr->type(i)) { - case N_BCOMM: { - // begin Fortran named common block - string tmp = string(stabptr->name(i)); - commonBlockName = &tmp; - // find the variable for the common block - - //TODO? change this. findLocalVar will cause an infinite loop - std::vector vars; - if (!associated_symtab->findSymbol(vars, - *commonBlockName, - Symbol::ST_OBJECT, - mangledName)) { - if (!associated_symtab->findSymbol(vars, - *commonBlockName, - Symbol::ST_OBJECT, - mangledName, - true)) - commonBlockVar = NULL; - else - commonBlockVar = vars[0]; - } else - commonBlockVar = vars[0]; - if (!commonBlockVar) { - // //bperr("unable to find variable %s\n", commonBlockName); - } else { - commonBlock = tc->findVariableType(*commonBlockName, Type::share); - if (!commonBlock->isCommonType()) { - // its still the null type, create a new one for it - commonBlock = Type::make_shared(*commonBlockName); - tc->addGlobalVariable(commonBlock); - } - // reset field list - commonBlock->asCommonType().beginCommonBlock(); - } - break; - } - case N_ECOMM: { - //copy this set of fields - if (!currentFunctionName) break; - if (!associated_symtab->findSymbol(bpfv, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - if (!associated_symtab->findSymbol(bpfv, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName, - true)) { - // //bperr("unable to locate current function %s\n", currentFunctionName->c_str()); - } else { - Symbol *func = bpfv[0]; - commonBlock->asCommonType().endCommonBlock(func, (void *) commonBlockVar->getOffset()); - } - } else { - if (bpfv.size() > 1) { - // warn if we find more than one function with this name - // //bperr("%s[%d]: WARNING: found %d funcs matching name %s, using the first\n", - // __FILE__, __LINE__, bpfv.size(), currentFunctionName->c_str()); - } - Symbol *func = bpfv[0]; - commonBlock->asCommonType().endCommonBlock(func, (void *) commonBlockVar->getOffset()); - } - //TODO?? size for local variables?? - // // update size if needed - // if (commonBlockVar) - // commonBlockVar->setSize(commonBlock->getSize()); - commonBlockVar = NULL; - commonBlock.reset(); - break; - } - // case C_BINCL: -- what is the elf version of this jkh 8/21/01 - // case C_EINCL: -- what is the elf version of this jkh 8/21/01 - case 32: // Global symbols -- N_GYSM - case 38: // Global Static -- N_STSYM - case N_FUN: - case 128: // typedefs and variables -- N_LSYM - case 160: // parameter variable -- N_PSYM - case 0xc6: // position-independant local typedefs -- N_ISYM - case 0xc8: // position-independant external typedefs -- N_ESYM -#ifdef TIMED_PARSE - pss_count++; - gettimeofday(&t1, NULL); -#endif - if (stabptr->type(i) == N_FUN) symt_current_func = NULL; - ptr = const_cast(stabptr->name(i)); - while (ptr[strlen(ptr) - 1] == '\\') { - //ptr[strlen(ptr)-1] = '\0'; - ptr2 = const_cast(stabptr->name(i + 1)); - ptr3 = (char *) malloc(strlen(ptr) + strlen(ptr2) + 1); - strcpy(ptr3, ptr); - ptr3[strlen(ptr) - 1] = '\0'; - strcat(ptr3, ptr2); - ptr = ptr3; - i++; - // XXX - memory leak on multiple cont. lines - } - // bperr("stab #%d = %s\n", i, ptr); - // may be nothing to parse - XXX jdd 5/13/99 - - temp = parseStabString(mod, stabptr->desc(i), (char *) ptr, stabptr->val(i), &commonBlock->asCommonType()); - if (temp.length()) { - //Error parsing the stabstr, return should be \0 - // //bperr( "Stab string parsing ERROR!! More to parse: %s\n", - // temp.c_str()); - // //bperr( " symbol: %s\n", ptr); - } -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - pss_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - // pss_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000); -#endif - break; - default: - break; - } - } - } -#if defined(TIMED_PARSE) - struct timeval endtime; - gettimeofday(&endtime, NULL); - unsigned long lstarttime = starttime.tv_sec * 1000 * 1000 + starttime.tv_usec; - unsigned long lendtime = endtime.tv_sec * 1000 * 1000 + endtime.tv_usec; - unsigned long difftime = lendtime - lstarttime; - double dursecs = difftime/(1000 ); - cout << __FILE__ << ":" << __LINE__ <<": parseTypes("<< mod->fileName() - <<") took "<(ptr); } - const char *getStringBase() { return stabstr; } - - protected: - void *stabptr; - const char *stabstr; - long nsyms; -}; - -class stab_entry_32 : public stab_entry { - public: - stab_entry_32(void *_stabptr = 0, const char *_stabstr = 0, long _nsyms = 0) - : stab_entry(_stabptr, _stabstr, _nsyms) { } - virtual ~stab_entry_32() {} - - const char *name(int i = 0) { - if (!stabptr) { - return "bad_name"; - } - return stabstr + ((stab32 *)stabptr)[i].name; - } - unsigned long nameIdx(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab32 *)stabptr)[i].name; - } - unsigned char type(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].type; - } - unsigned char other(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].other; - } - unsigned short desc(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].desc; - } - unsigned long val(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab32 *)stabptr)[i].val; - } -}; - -class stab_entry_64 : public stab_entry { - public: - stab_entry_64(void *_stabptr = 0, const char *_stabstr = 0, long _nsyms = 0) - : stab_entry(_stabptr, _stabstr, _nsyms) { } - virtual ~stab_entry_64() {} - - const char *name(int i = 0) { - if (!stabptr) { - return "bad_name"; - } - return stabstr + ((stab64 *)stabptr)[i].name; - } - unsigned long nameIdx(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab64 *)stabptr)[i].name; - } - unsigned char type(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].type; - } - unsigned char other(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].other; - } - unsigned short desc(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].desc; - } - unsigned long val(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab64 *)stabptr)[i].val; - } -}; - -// Types -#define N_UNDF 0x00 /* start of object file */ -#define N_GSYM 0x20 /* global symbol */ -#define N_FUN 0x24 /* function or procedure */ -#define N_STSYM 0x26 /* initialized static symbol */ -#define N_LCSYM 0x28 /* unitialized static symbol */ -#define N_ROSYM 0x2c /* read-only static symbol */ -#define N_OPT 0x3c /* compiler options */ -#define N_ENDM 0x62 /* end module */ -#define N_SO 0x64 /* source directory and file */ -#define N_ENTRY 0xa4 /* fortran alternate subroutine entry point */ -#define N_BCOMM 0xe2 /* start fortran named common block */ -#define N_ECOMM 0xe4 /* start fortran named common block */ - -// Language code -- the desc field in a N_SO entry is a language code -#define N_SO_AS 1 /* assembler source */ -#define N_SO_C 2 /* K & R C source */ -#define N_SO_ANSI_C 3 /* ANSI C source */ -#define N_SO_CC 4 /* C++ source */ -#define N_SO_FORTRAN 5 /* fortran source */ -#define N_SO_PASCAL 6 /* Pascal source */ -#define N_SO_F90 7 /* Fortran90 source */ - -//line information data -#define N_SLINE 0x44 /* line number in text segment */ -#define N_SOL 0x84 /* name of the include file*/ - -// Symbol descriptors -// The format of a name is ": -// The following are the descriptors of interest -#define SD_GLOBAL_FUN 'F' /* global function or procedure */ -#define SD_PROTOTYPE 'P' /* function prototypes */ -#define SD_GLOBAL_VAR 'G' /* global variable */ - -// end of stab declarations class pdElfShdr; class Symtab; @@ -277,9 +94,7 @@ class Object : public AObject bool emitDriver(std::string fName, std::set &allSymbols, unsigned flag); const char *elf_vaddr_to_ptr(Offset vaddr) const; - bool hasStabInfo() const { return ! ( !stab_off_ || !stab_size_ || !stabstr_off_ ); } bool hasDwarfInfo() const { return dwarvenDebugInfo; } - stab_entry * get_stab_info() const; std::string getFileName() const; void getModuleLanguageInfo(dyn_hash_map *mod_langs); void parseFileLineInfo(); @@ -467,14 +282,6 @@ class Object : public AObject Offset opd_addr_; unsigned opd_size_; - Offset stab_off_; // .stab section - unsigned stab_size_; // .stab section - Offset stabstr_off_; // .stabstr section - - Offset stab_indx_off_; // .stab.index section - unsigned stab_indx_size_; // .stab.index section - Offset stabstr_indx_off_; // .stabstr.index section - bool dwarvenDebugInfo; // is DWARF debug info present? Offset loadAddress_; // The object may specify a load address // Set to 0 if it may load anywhere @@ -524,8 +331,6 @@ class Object : public AObject bool loaded_elf( Offset &, Offset &, Elf_X_Shdr* &, Elf_X_Shdr* &, Elf_X_Shdr* &, - Elf_X_Shdr* &, Elf_X_Shdr* &, - Elf_X_Shdr* &, Elf_X_Shdr* &, Elf_X_Shdr*& rel_plt_scnp, Elf_X_Shdr*& plt_scnp, Elf_X_Shdr*& got_scnp, Elf_X_Shdr*& dynsym_scnp, Elf_X_Shdr*& dynstr_scnp, Elf_X_Shdr*& dynamic_scnp, Elf_X_Shdr*& eh_frame, @@ -536,7 +341,6 @@ class Object : public AObject Symbol *handle_opd_symbol(Region *opd, Symbol *sym); void handle_opd_relocations(); void parse_opd(Elf_X_Shdr *); - void parseStabFileLineInfo(); public: void parseDwarfFileLineInfo(); void parseLineInfoForAddr(Offset addr_to_find); @@ -551,7 +355,6 @@ class Object : public AObject bool dwarf_parse_aranges(::Dwarf *dbg, std::set& dies_seen); void parseDwarfTypes(Symtab *obj); - void parseStabTypes(); void load_object(bool); void load_shared_object(bool); @@ -586,8 +389,7 @@ class Object : public AObject void find_code_and_data(Elf_X &elf, Offset txtaddr, Offset dataddr); - bool fix_global_symbol_modules_static_stab(Elf_X_Shdr *stabscnp, - Elf_X_Shdr *stabstrscnp); + bool fix_global_symbol_modules_static_dwarf(); void get_valid_memory_areas(Elf_X &elf); diff --git a/symtabAPI/src/Symtab.C b/symtabAPI/src/Symtab.C index a0a90a558d..da5cbea0e4 100644 --- a/symtabAPI/src/Symtab.C +++ b/symtabAPI/src/Symtab.C @@ -175,7 +175,6 @@ boost::shared_ptr Symtab::setupBuiltinTypes() // NOTE: integral type mean twos-complement // -1 int, 32 bit signed integral type - // in stab document, size specified in bits, system size is in bytes builtInTypes->addBuiltInType(Type::make_shared(-1, 4, "int", true)); // -2 char, 8 bit type holding a character. GDB treats as signed builtInTypes->addBuiltInType(Type::make_shared(-2, 1, "char", true)); @@ -323,8 +322,6 @@ SYMTAB_EXPORT Symtab::Symtab(MappedFile *mf_) : sorted_everyFunction(false), isTypeInfoValid_(false), nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(false), @@ -356,8 +353,6 @@ SYMTAB_EXPORT Symtab::Symtab() : sorted_everyFunction(false), isTypeInfoValid_(false), nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(false), @@ -932,7 +927,7 @@ void Symtab::setModuleLanguages(dyn_hash_map *m { if (!mod_langs->size()) return; // cannot do anything here - // this case will arise on non-stabs platforms until language parsing can be introduced at this level + // this case will arise until language parsing can be introduced at this level Module *currmod = NULL; //int dump = 0; @@ -1085,8 +1080,6 @@ Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : sorted_everyFunction(false), isTypeInfoValid_(false), nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(defensive_bin), @@ -1158,8 +1151,6 @@ Symtab::Symtab(unsigned char *mem_image, size_t image_size, sorted_everyFunction(false), isTypeInfoValid_(false), nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), @@ -1442,8 +1433,6 @@ Symtab::Symtab(const Symtab& obj) : sorted_everyFunction(false), isTypeInfoValid_(obj.isTypeInfoValid_), nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(obj.isDefensiveBinary_), diff --git a/symtabAPI/src/parseStab.C b/symtabAPI/src/parseStab.C deleted file mode 100644 index 4cfffd2d4a..0000000000 --- a/symtabAPI/src/parseStab.C +++ /dev/null @@ -1,2423 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -#include "symutil.h" -#include "Symtab.h" // For looking up compiler type -#include "Symbol.h" -#include "Function.h" -#include "Variable.h" -#include "Module.h" -#include "Collections.h" -#include "annotations.h" -#include "common/src/headers.h" -#include "compiler_annotations.h" -#include "Type-mem.h" - -#include "debug.h" - -using namespace Dyninst; -using namespace Dyninst::SymtabAPI; - -/* -#include "BPatch.h" -#include "debug.h" -*/ - -extern std::string symt_current_func_name; -extern std::string symt_current_mangled_func_name; -extern Function *symt_current_func; -namespace Dyninst{ -namespace SymtabAPI{ - std::string parseStabString(Module *mod, int linenum, char *stabstr, - int framePtr, typeCommon *commonBlock = NULL); -} -} - -// Forward references for parsing routines -static int parseSymDesc(char *stabstr, int &cnt); -static boost::shared_ptr parseConstantUse(Module *, char *stabstr, int &cnt); -static char *parseTypeDef(Module *, char *stabstr, - const char *name, int ID, unsigned int sizeHint = 0); -static int parseTypeUse(Module*, char *&stabstr, int &cnt, - const char *name); -static inline bool isSymId(char ch); -static std::string getIdentifier(char *stabstr, int &cnt, bool stopOnSpace=false); - -static std::string currentRawSymbolName; - -std::string convertCharToString(const char *ptr){ - if(ptr) - return ptr; - else - return ""; -} - -// -// Start of code to parse Stab information. -// The structure of this code is a recursive decent parser that parses -// information in stab records and builds up the corresponding BPatch_types. -// -// Each non-terminal in the grammer has a function of the form parse. -// -// The grammar for a non-terminal appears in the comments just before -// the non-terminal parsing function -// - -void vectorNameMatchKLUDGE(char *demangled_sym, std::vector &bpfv, std::vector &matches) -{ - // iterate through all matches and demangle names with extra parameters, compare - for (unsigned int i = 0; i < bpfv.size(); ++i) { - std::string l_mangled; - std::vector syms; - bpfv[i]->getSymbols(syms); - if (syms.size()) { - l_mangled = syms[0]->getMangledName(); - - std::string l_demangled_raw = P_cplus_demangle(l_mangled); - - if (l_demangled_raw == demangled_sym) { - matches.push_back(i); - } - } - } /* end iteration over function vector */ -} - -Function *mangledNameMatchKLUDGE(const char *pretty, const char *mangled, - Module *mod) -{ - - std::vector bpfv; - if (!mod->exec()->findFunctionsByName(bpfv, pretty)) { - //cerr << __FILE__ << __LINE__ << ": KLUDGE Cannot find " << pretty << endl; - return NULL; // no pretty name hits, expecting multiple - } - - //cerr << __FILE__ << __LINE__ << ": mangledNameMatchKLUDGE: language = " - //<< mod->getLanguageStr() << endl; - - if (lang_Fortran_with_pretty_debug == mod->language()) { - // debug function symbols are presented in "demangled" style. - if (bpfv.size() == 1) - return bpfv[0]; - else { - cerr << __FILE__ << __LINE__ << ": FIXME!" << endl; - return NULL; - } - } - - // demangle name with extra parameters - std::string demangled = P_cplus_demangle( mangled, true ); - char *demangled_sym = strdup(demangled.c_str()); - - std::vector matches; - - vectorNameMatchKLUDGE(demangled_sym, bpfv, matches); - - Function *ret = NULL; - - if (matches.size() == 1) {ret = bpfv[matches[0]]; goto clean_up;} - if (matches.size() > 1) goto clean_up; - - // check in the uninstrumentable pile - bpfv.clear(); - matches.clear(); - - vectorNameMatchKLUDGE(demangled_sym, bpfv, matches); - if (matches.size() == 1) {ret = bpfv[matches[0]]; goto clean_up;} - if (matches.size() > 1) goto clean_up; - - clean_up: - free( demangled_sym ); - return ret; -} - -// This function takes the stab stabstring and parses it to create a new -// type or variable object. This function only defines the type/variable -// name and ID. -// -// = : | -// :c | -// :f | -// :f,, | -// :F | -// :G | -// :r | -// :S | -// :[pPr] | -// ::T | -// :t | -// :T | -// :v | -// :V | -// :Y[Tc|Ts] -// -// = | ; -// - -std::string Dyninst::SymtabAPI::parseStabString(Module *mod, int linenum, char *stabstr, - int framePtr, typeCommon *commonBlock) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - int cnt; - int ID = 0; - int symdescID = 0; - int funcReturnID = 0; - Function *fp = NULL; - boost::shared_ptr ptrType; - boost::shared_ptr newType = NULL; // For new types to add to the collection - localVar *locVar = NULL; - cnt= 0; - - types_printf("parseStabString, mod %p/%s, linenum %d, stabstr %s\n", - (void*)mod, - (mod != NULL) ? mod->fileName().c_str() : "NULL", - linenum, - stabstr); - - std::string fName = mod->fileName(); - - /* get type or variable name */ - std::string mangledname = getIdentifier( stabstr, cnt ); - - currentRawSymbolName = mangledname; - std::string name = P_cplus_demangle( mangledname ); - - if ( !name.empty() && stabstr[cnt] != ':' ) - { - types_printf("\t returning name %s\n", name.c_str()); - return name; - } - - if (stabstr[cnt] == ':') - { - // skip to type part - cnt++; - } - - if (isSymId(stabstr[cnt])) - { - /* instance of a predefined type */ - - ID = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name.c_str(), ID); - cnt = 0; - ptrType = tc->findOrCreateType(ID, Type::share); - if (!symt_current_func) - { - // XXX-may want to use N_LBRAC and N_RBRAC to set function scope - // -- jdd 5/13/99 - // Still need to add to local variable list if in a function - - std::string modName = mod->fileName(); - //bperr("%s[%d] Can't find function %s in module %s\n", __FILE__, __LINE__, - // symt_current_mangled_func_name.c_str(), modName); - //bperr("Unable to add %s to local variable list in %s\n", - // name.c_str(), symt_current_func_name.c_str()); - } - else - { - locVar = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - if (!ptrType) { - //bperr("adding local var with missing type %s, type = %d\n", - // name, ID); - } - - symt_current_func->addLocalVar(locVar); - } - } - else if (symt_current_func) - { - // Try to find the BPatch_Function - ptrType = tc->findOrCreateType( ID, Type::share); - - locVar = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - - if (!ptrType) - { - ////bperr("adding local var with missing type %s, type = %d\n", - // name, ID); - } - - symt_current_func->addLocalVar(locVar); - } - } - else if (stabstr[cnt]) - { - std::vector bpfv; - - switch (stabstr[cnt]) { - case 'f': /*Local Function*/ - { - std::string scopeName; - std::string lfuncName; - cnt++; - - symt_current_func_name = name; - symt_current_mangled_func_name = mangledname; - - funcReturnID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - if (stabstr[cnt]==',') - { - cnt++; /*skip the comma*/ - - /* Local Function Name */ - lfuncName = getIdentifier(stabstr, cnt); - - assert(stabstr[cnt] == ','); - cnt++; /*skip the comma*/ - - /* Scope Name of Local Function */ - scopeName = getIdentifier(stabstr, cnt); - - if (stabstr[cnt]) - { - //bperr("Extra: %s\n", &stabstr[cnt]); - } - } - - if (!scopeName.length()) - { - // Not an embeded function - - ptrType = tc->findOrCreateType(funcReturnID, Type::share); - /* - The shared_ptr type_Untyped is static, so this - otherwise unsafe operation is safe. - */ - if ( !ptrType) ptrType = Symtab::type_Untyped(); - - if (!(mod->exec()->findFunctionsByName(bpfv, name))) - { - //showInfoCallback(string("missing local function ") + - // name + "\n"); - // It's very possible that we might not find a function - // that's a weak reference, and defined in multiple places - // as we only store an object from the last definition - // - // 12/08 - not sure this is necessary anymore - // due to the Function abstraction - fp = NULL; - } - else - { - if (bpfv.size() > 1) - { - // warn if we find more than one function with current_func_name - char msg[1024]; - sprintf(msg, "%s[%d]: found %d functions with name %s, using the first", - __FILE__, __LINE__, (int)bpfv.size(), name.c_str()); - // BPatch::bpatch->reportError(BPatchWarning, 0, msg); - - } - else if (!bpfv.size()) - { - //bperr("%s[%d]: SERIOUS: found 0 functions with name %s", - // __FILE__, __LINE__, name.c_str()); - break; - } - - fp = bpfv[0]; - // set return type. - fp->setReturnType(ptrType); - } - } - else - { - //bperr("%s is an embedded function in %s\n",name.c_str(), scopeName.c_str()); - } - - symt_current_func = fp; - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - cnt = strlen(stabstr); - - break; - } - - case 'F':/* Global Function */ - { - cnt++; /*skipping 'F' */ - - funcReturnID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - symt_current_func_name = name; - symt_current_mangled_func_name = mangledname; - - // - // For SunPro compilers there may be a parameter list after - // the return - // - - while (stabstr[cnt] == ';') - { - cnt++; // skip ';' - (void) parseTypeUse(mod, stabstr, cnt, ""); - } - - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - cnt = strlen(stabstr); - - ptrType = tc->findOrCreateType(funcReturnID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - std::vectorfpv; - if (!mod->exec()->findFunctionsByName(fpv, symt_current_mangled_func_name)) - //if (!mod->findSymbol(fpv, symt_current_mangled_func_name, Symbol::ST_FUNCTION, true)) - { - std::string modName = mod->fileName(); - - if (NULL == (fp = mangledNameMatchKLUDGE(symt_current_func_name.c_str(), - symt_current_mangled_func_name.c_str(), mod))) - { - //bpwarn("%s L%d - Cannot find global function with mangled name '%s' or pretty name '%s' with return type '%s' in module '%s', possibly extern\n", - // __FILE__, __LINE__, - // symt_current_mangled_func_name.c_str(), current_func_name.c_str(), - // ((ptrType->getMangledName() == NULL) ? "" : ptrType->getMangledName()), - // modName); - //char prefix[5]; - //strncpy(prefix, current_mangled_func_name, 4); - //prefix[4] = '\0'; - // mod->dumpMangled(prefix); - break; - } - } - fp = fpv[0]; - - fp->setReturnType(ptrType); - symt_current_func = fp; - fpv.clear(); - } - break; - - case 'U':/* Class Declaration - for Sun Compilers - jkh 6/6/03 */ - case 'E':/* Extern'd Global ??? - undocumented type for Sun Compilers - jkh 6/6/03 */ - case 'G':/* Global Varaible */ - cnt++; /* skip the 'G' */ - - { - /* Get variable type number */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - boost::shared_ptr BPtype; - - BPtype = tc->findOrCreateType(symdescID, Type::share); - if (BPtype) - { - Module *toUse = mod; - std::vector ret; - bool result = mod->findVariablesByName(ret, name); - if (!result) { - // Might be in a different module... - if (mod->exec()->getDefaultModule()->findVariablesByName(ret, name)) - toUse = mod->exec()->getDefaultModule(); - } - for (unsigned i=0; isetType(BPtype); - } - - typeCollection *tc_to_use = typeCollection::getModTypeCollection(toUse); - tc_to_use->addGlobalVariable(BPtype); - } - // else // what should be done in the else case??? - // the break was (probably wrongly?) part of the else - break; - } - - case 'P': // function parameter passed in a register (GNU/Solaris) - case 'R': // function parameter passed in a register - case 'v': // Fortran Local Variable - case 'X': // Fortran function return Variable (e.g. function name) - case 'p': - { - // Function Parameter - cnt++; /* skip the 'p' */ - - /* Get variable type number */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - if (stabstr[cnt] == ';') - { - // parameter type information, not used for now - cnt = strlen(stabstr); - } - // else if (stabstr[cnt]) - // { - //bperr( "\tMore to parse func param %s\n", &stabstr[cnt]); - //bperr( "\tFull String: %s\n", stabstr); - //} - - ptrType = tc->findOrCreateType(symdescID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - localVar *param; - - param = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - param->addLocation(loc); - - if (symt_current_func) - { - symt_current_func->addParam(param); - } - - break; - } - - case 'c': /* constant */ - { - cnt++; /*move past the 'c' */ - if (symt_current_mangled_func_name.length()) - { - std::vectorfpv; - if (mod->exec()->findFunctionsByName(fpv, symt_current_mangled_func_name)) - { - // found function, add parameter - fp = fpv[0]; - symt_current_func = fp; - } - fpv.clear(); - } - - ptrType = parseConstantUse(mod, stabstr, cnt); - - if (!ptrType) ptrType = Symtab::type_Untyped(); - - localVar *var; - var = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = 0; - var->addLocation(loc); - if (symt_current_func) { - symt_current_func->addParam(var); - } - } - break; - - case 'r':/* Register Variable */ - cnt++; /*move past the 'r'*/ - /* get type reference */ - - symdescID = parseSymDesc(stabstr, cnt); - break; - - case 'S':/* Global Static Variable */ - { - cnt++; /*move past the 'S'*/ - - /* get type reference */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - // lookup symbol and set type - boost::shared_ptr BPtype; - - std::string nameTrailer; - if (name.find(".") < name.length()) - { - std::string defaultNameSpace; - defaultNameSpace = name.substr(0,name.find(".")); - nameTrailer = name.substr(name.find(".")+1,name.length()-name.find(".")-1); - mod->setDefaultNamespacePrefix(defaultNameSpace); - } - else - { - nameTrailer = name; - } - - BPtype = tc->findOrCreateType(symdescID, Type::share); - - if (BPtype) - { - Symtab *img = mod->exec(); - std::vectorsyms; - if (img->findSymbol(syms, - nameTrailer, - Symbol::ST_OBJECT, - mangledName) || - img->findSymbol(syms, - nameTrailer, - Symbol::ST_OBJECT, - mangledName, - true)) - { - - tc->addGlobalVariable(BPtype); - } - } - - //else - //{ - //bperr("ERROR: unable to find type #%d for variable %s\n", - // symdescID, nameTrailer.c_str()); - //} - - break; - } - - case 't': // Type Name - cnt++; /*move past the 't'*/ - - /* get type reference */ - symdescID = parseSymDesc(stabstr, cnt); - - //Create Type. - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - //char *oldstabstr = stabstr; - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name.c_str(), symdescID); - cnt = 0; - } - else - { - //Create Type defined as a pre-exisitng type. - - ptrType = tc->findOrCreateType(symdescID, Type::share); - if (!ptrType) - { - ptrType = Symtab::type_Untyped(); - } - - // We assume that IDs are unique per type. Instead of reusing the - // underlying base ID, use a SymtabAPI-generated ID. - - auto t = Type::make_shared(ptrType, name); - - if (t) - { - tc->addOrUpdateType(t); - } - } - break; - - case ':': // :T... - skip ":" and parse 'T' - if ((stabstr[cnt+1] == 't') || (stabstr[cnt+1] == 'T')) - { - // parse as a normal typedef - parseStabString(mod, linenum, &stabstr[cnt+1], framePtr); - } - - // else - //{ - //bperr("Unknown type seen %s\n", stabstr); - //} - - break; - - case 'T':/* Aggregate type tag -struct, union, enum */ - cnt++; /*move past the 'T'*/ - - if (stabstr[cnt] == 't') - { - //C++ struct tag "T" and type def "t" - ////bperr("SKipping C++ Identifier t of Tt\n"); - cnt++; //skip it - } - - /* get type reference */ - symdescID = parseSymDesc(stabstr, cnt); - - //Create Type. - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - stabstr = parseTypeDef(mod,(&stabstr[cnt+1]),name.c_str(),symdescID); - cnt = 0; - - //if (stabstr[0]) - //{ - //bperr( "\tMore to parse aggregate type %s\n", (&stabstr[cnt])); - //bperr("\tFull String: %s\n", stabstr); - //} - - } - else - { - //Create Type defined as a pre-exisitng type. - - newType = Type::createPlaceholder(symdescID, name); - (void)newType; // unused... - } - - break; - - case 'V':/* Local Static Variable (common block vars too) */ - cnt++; /*move past the 'V'*/ - - // //bperr("parsing 'v' type of %s\n", stabstr); - /* Get variable type number */ - { - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - // lookup symbol and set type - auto BPtype = tc->findOrCreateType(symdescID, Type::share); - - if (!BPtype) - { - //bperr("ERROR: unable to find type #%d for variable %s\n", - // symdescID, name.c_str()); - break; - } - - if (commonBlock) - { - /* This variable is in a common block */ - /* add it only if not already there, common block - are re-defined for each subroutine but subroutines - define only the member they care about - */ - - bool found = false; - auto fields = commonBlock->getFields(); - if (fields) - { - for (unsigned int i=0; i < fields->size(); i++) - { - if (name == (*fields)[i]->getName()) - { - found = true; - break; - } - - int start1, start2, end1, end2; - start1 = (*fields)[i]->getOffset(); - end1 = start1 + (*fields)[i]->getSize(); - start2 = framePtr; - end2 = framePtr + BPtype->getSize(); - if ( ((start2 >= start1) && (start2 < end1)) - || ((start1 >= start2) && (start1 < end2)) ) - { - /* common block aliasing detected */ - //bpwarn("WARN: EQUIVALENCE used in %s: %s and %s\n", - // current_func_name.c_str(), name.c_str(), (*fields)[i]->getName()); - - found = true; - break; - } - } - } - - if (!found) - { - commonBlock->addField(name, BPtype, framePtr); - } - } - else - { - // put it into the local variable scope - if (symt_current_func) - { - locVar = new localVar(name, BPtype, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageAddr; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - - symt_current_func->addLocalVar(locVar); - } - - //else - //{ - //bperr("Unable to add %s to local variable list in %s\n", - // name.c_str(),current_func_name.c_str()); - //} - } - break; - } - case 'l': - // These are string literals, of the form - // name:l(type);value - // where type must be predefined, and value of of type type. - // It should be safe to ignore these. - - cnt = strlen(stabstr); - break; - - case 'Y': // C++ specific stuff - cnt++; // Skip past the 'Y' - if (stabstr[cnt] == 'I') - { - /* Template instantiation */ - cnt++; // skip past the I; - if (stabstr[cnt] == 'f') /* Template function */ - { - while (stabstr[cnt] != '@') cnt++; - cnt++; // Skip past '@' - cnt++; // Skip past ';' - cnt++; // Skip past ';' - while (stabstr[cnt] != ':') cnt++; - // Create fake stab string that cuts out template garbage - char *dupstring = strdup(stabstr); - strcpy(dupstring, mangledname.c_str()); - strcat(dupstring, stabstr+cnt); - parseStabString(mod, linenum, dupstring, framePtr, commonBlock); - free(dupstring); - } - } - cnt = strlen(stabstr); - break; - - default: - //bperr( "Unknown symbol descriptor: %c\n", stabstr[cnt]); - //bperr( " : %s\n", stabstr); - break; - } - } - - return(&stabstr[cnt]); -} /* end of parseStabString */ - - -// -// Is the current character a valid prefix for a symDesc non-terminal? -// -inline bool isSymId(char ch) -{ - return ((ch == '(') || isdigit(ch) || (ch == '-')); -} - -// -// parse a Symbol Descriptor ID -// symDesc = | (,) -// -int parseSymDesc(char *stabstr, int &cnt) -{ - int id; - int lid; - int hid; - int sign = 1; - bool newForm = false; - - hid = 0; //file-number - // parse both an int and (int,int) format (file-number, type ID) - if (stabstr[cnt] == '(') { - cnt++; - while (isdigit(stabstr[cnt])) { - hid = hid * 10 + stabstr[cnt] - '0'; - cnt++; - } - - // skip "," - if (stabstr[cnt] == ',') cnt++; - newForm = true; - } - - if (stabstr[cnt] == '-') { - sign = -1; - cnt++; - } - - lid = 0; //type ID - while (isdigit(stabstr[cnt])) { - lid = lid * 10 + stabstr[cnt] - '0'; - cnt++; - } - if( hid != 0 ) - assert(lid < 65536); - - // skip closing ')' - if (newForm) cnt++; - - id = hid * 65536 + lid; - id = id * sign; - - return id; -} - -// -// parse an identifier up to a ":" or "," or ";" -// -std::string getIdentifier( char *stabstr, int &cnt, bool stopOnSpace ) { - int i = 0; - int brCnt = 0; - bool idChar = true; - - while( idChar ) { - switch( stabstr[ cnt + i ] ) { - case '<': - case '(': - brCnt++; - i++; - break; - - case '>': - case ')': - brCnt--; - i++; - break; - - case ' ': - if ( !stopOnSpace ) { - i++; - break; - } // else fall through - case '\0': - case ':': - case ',': - case ';': - /* Handle case of '::' */ - if ( stabstr[ cnt + i ] == ':' && stabstr[ cnt + i + 1 ] == ':' && - (stabstr[ cnt + i + 2 ] == '_' || isalpha(stabstr[ cnt + i + 2 ])) ) { - i+=3; - break; - } - /* If we're inside a bracket and we haven't reached - the end of the string, continue. */ - if( brCnt != 0 && stabstr[ cnt + i ] != '\0' ) { - i++; - } -// else if( brCnt ) { -// //bperr( "Failed to find identifier in stabstring '%s;\n", stabstr ); -// idChar = false; -// } - else { - idChar = false; - } - break; - - default: - i++; - break; - } /* end switch */ - } /* end while */ - - char * identifier = (char *)malloc( i + 1 ); - assert( identifier ); - - strncpy( identifier, & stabstr[cnt], i ); - identifier[i] = '\0'; - cnt += i; - - std::string pd_identifier = identifier; - free(identifier); - return pd_identifier; - } /* end getIdentifier() */ - -// -// getFieldName -// -// A simplified version of getIdentifier, it only cares about finding a ':' -// - -char * getFieldName( char *stabstr, int &cnt) { - int i = 0; - bool idChar = true; - - while ( idChar ) { - switch( stabstr[ cnt + i ] ) { - case ':': - idChar = false; - break; - default: - i++; - } - } - - char * identifier = (char *) malloc(i + 1); - assert(identifier); - - strncpy(identifier, &stabstr[cnt], i); - identifier[i] = '\0'; - cnt += i; - - return identifier; -} - -// -// Parse a use of a type. -// -// = | = -// -static int parseTypeUse(Module *mod,char *&stabstr, int &cnt, - const char *name) -{ - int ret = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == '=') { - /* More Stuff to parse, call parseTypeDef */ - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name, ret); - cnt = 0; - } - return ret; -} - -// -// parseCrossRef - internal struct/union pointer -// -// = [s|u|e] -// -static char *parseCrossRef(typeCollection *moduleTypes,const char * /*name*/, - int ID, char *stabstr, int &cnt) -{ - std::string temp; - boost::shared_ptr newType; - char xreftype; - cnt++; /* skip 'x'*/ - - if ((stabstr[cnt] == 's') || // struct - (stabstr[cnt] == 'u') || // union - (stabstr[cnt] == 'e')) { // enum - xreftype = stabstr[cnt++]; - - temp = getIdentifier(stabstr, cnt); - cnt++; /*skip ':' */ - - // Find type that this one points to. - boost::shared_ptr ptrType = moduleTypes->findType(temp.c_str(), Type::share); - if (!ptrType) { - // This type name hasn't been seen before. Create the - // skeleton for it, and we'll update it later when we actually see - // it - if (xreftype == 'e') { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } else if (xreftype == 'u') { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } else { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } - assert(newType); - } - } else { - /* don't know what it is?? */ - - temp = getIdentifier(stabstr, cnt); - cnt++; /*skip ':' */ - } - - return( &(stabstr[cnt])); -} - -// -// parse the definition of an array. -// arrayDef = ar;;; | -// ar;;; | -// A -// -static boost::shared_ptr parseArrayDef(Module *mod, const char *name, - int ID, char *&stabstr, int &cnt, unsigned int sizeHint) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - char *symdesc; - int symdescID; - int elementType; - boost::shared_ptr newType; - boost::shared_ptr ptrType; - int lowbound, hibound; - - // format is ar;;; - - assert(stabstr[cnt] == 'a' || stabstr[cnt] == 'A'); - - if (stabstr[cnt ++] == 'A') { - // Open array - lowbound = 1; - hibound = 0; - elementType = parseSymDesc(stabstr, cnt); - ptrType = tc->findOrCreateType(elementType, Type::share); - } else { - // Regular (maybe) array - - if (stabstr[cnt] != 'r') { - //bperr("unknown array definition seen %s\n", &stabstr[cnt]); - return(NULL); - } - - /* array with range */ - symdesc = &(stabstr[cnt]); - - cnt++; /* skip 'r' */ - - symdescID = parseTypeUse(mod, stabstr, cnt, name); - - cnt++; /* skip semicolon */ - lowbound = parseSymDesc(stabstr, cnt); - - cnt++; /* skip semicolon */ - if (stabstr[cnt] == 'J') { - /* Fortran unbounded array */ - hibound = 0; - cnt++; - } else if (stabstr[cnt] == 'T') { - /* Fortran runtime bound array - Txx is the form (xx=digits)*/ - hibound = 0; - cnt++; - while (isdigit(stabstr[cnt])) cnt++; - } else { - hibound = parseSymDesc(stabstr, cnt); - } - - cnt++; /* skip semicolon */ - elementType = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == 'a') - { - /* multi dimensional array - Fortran style */ - /* it has no valid id, so we give it a known duplicate */ - ptrType = parseArrayDef(mod, name, 0, stabstr, cnt, sizeHint); - } - else - { - if (stabstr[cnt] == '=') - { - /* multi dimensional array */ - char *temp; - temp = parseTypeDef(mod, &(stabstr[cnt+1]), NULL, elementType); - /* parseTypeDef uses old style of returning updated stabstr, - but parseArrayDef function needs to return an updated cnt. - This simple hack updates cnt based on how far parseTypDef - advances it. jkh 12/4/00 */ - cnt = temp-stabstr; - if (stabstr[cnt] == ':') { - //C++ stuff - ////bperr("Skipping C++ rest of array def: %s\n",name ); - while (stabstr[cnt] != ';') cnt++; - } - } - ptrType = tc->findOrCreateType(elementType, Type::share); - } - } - - // //bperr("Symbol Desriptor: %s Descriptor ID: %d Type: %d, Low Bound: %d, Hi Bound: %d,\n", symdesc, symdescID, elementType, lowbound, hibound); - (void)symdesc; (void)symdescID; // otherwise unused symbols from above - - - if (ptrType) { - // Create new type - field in a struct or union - std::string tName = convertCharToString(name); - - auto newAType = Type::make_shared(ID, ptrType, lowbound, hibound, tName, sizeHint); - // Add to Collection - newType = tc->addOrUpdateType(newAType); - - return newAType; - } - - // //bperr( "parsed array def to %d, remaining %s\n", cnt, &stabstr[cnt]); - return newType; -} - -int guessSize(const char *low, const char *hi) -{ - long long l, h; - - if (low[0] == '0') - sscanf(low, "%llo", (unsigned long long *)&l); - else - sscanf(low, "%lld", &l); - if (hi[0] == '0') - sscanf(hi, "%llo", (unsigned long long *)&h); - else - sscanf(hi, "%lld", &h); - - /* - if (( low[0]=='-' && l < -2147483648LL ) - || ( l > || ( h > 2147483647LL)) - return 8; - else if (( l < -32768 ) || ( h > 32767 )) - return 4; - else if (( l < -128 ) || ( h > 127 )) - return 2; - else - return 1; - */ - if (l < 0) { // Must be signed - if (l < -2147483648LL || h > 0x7fffffffLL) - return 8; - else if (l < 0xffff8000 || h > 0x7fff) - return 4; - else if (l < 0xffffff80 || h > 0x7f) - return 2; - else - return 1; - } else { - if (h > 0xffffffffLL) - return 8; - else if (h > 0xffff) - return 4; - else if (h > 0xff) - return 2; - else - return 1; - } -} - -#if defined(i386_unknown_linux2_0) \ - || defined(x86_64_unknown_linux2_4) /* Blind duplication - Ray */ -// -// parse range type of the form: -// -// = r;;; -// -static char *parseRangeType(Module *mod, const char *name, int ID, - char *stabstr, unsigned int sizeHint = 0) -{ - int cnt, i, symdescID; - //int sign = 1; - boost::shared_ptr baseType; - - cnt = i = 0; - - assert(stabstr[0] == 'r'); - cnt++; - - // range index type - not used - symdescID = parseSymDesc(stabstr, cnt); - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - if (!mod || !tc) - { - return NULL; - } - else - { - baseType = tc->findType(symdescID, Type::share); - } - - // //bperr("\tSymbol Descriptor: %c and Value: %d\n",tmpchar, symdescID); - - cnt++; /* Discarding the ';' */ - i=0; - if (stabstr[cnt] == '-' ) { - i++; - } - - /* Getting type range or size */ - - while (isdigit(stabstr[cnt+i])) i++; - - char *low = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(low, &(stabstr[cnt]), i)) - /* Error copying size/range*/ - exit(1); - low[i] = '\0'; - - cnt = cnt + i + 1; /* Discard other Semicolon */ - i = 0; - if((stabstr[cnt]) == '-') { - i++; /* discard '-' for (long) unsigned int */ - } - //Find high bound - while (isdigit(stabstr[cnt+i])) i++; - char *hi = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(hi, &(stabstr[cnt]), i)) - /* Error copying upper range */ - exit(1); - hi[i] = '\0'; - - int j = atol(hi); - - if (j == 0) { - //Size - int size = atol(low); - - //Add to Collection - tc->addOrUpdateType(Type::make_shared(ID, size, name)); - } - else { - //Range - //Create new type - boost::shared_ptr newType; - std::string tName = convertCharToString(name); - - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : guessSize(low,hi), - low_conv, hi_conv, tName); - else - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tName); - //Add to Collection - tc->addOrUpdateType(newType); - } - free(low); - free(hi); - hi=low=NULL; - - cnt = cnt + i; - if( stabstr[cnt] == ';') - cnt++; - - return(&(stabstr[cnt])); -} - -#else -// -// parse range type of the form: -// -// = r;;; -// -static char *parseRangeType(Module *mod, const char *name, int ID, - char *stabstr, unsigned int sizeHint = 0) -{ - int cnt, i, symdescID; - boost::shared_ptr baseType; - - cnt = i = 0; - - assert(stabstr[0] == 'r'); - cnt++; - - // range index type - symdescID = parseSymDesc(stabstr, cnt); - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - baseType = tc->findType(symdescID, Type::share); - - // //bperr("\tSymbol Descriptor: %c and Value: %d\n",tmpchar, symdescID); - - cnt++; /* Discarding the ';' */ - i=0; - if (stabstr[cnt] == '-' ) { - i++; - } - - /* Getting type range or size */ - while (isdigit(stabstr[cnt+i])) i++; - - char *temp = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(temp, &(stabstr[cnt]), i)) - /* Error copying size/range*/ - exit(1); - temp[i] = '\0'; - int j = atol(temp); - - char *low = temp; - cnt = cnt + i + 1; /* Discard other Semicolon */ - i = 0; - if((stabstr[cnt]) == '-') { - i++; /* discard '-' for (long) unsigned int */ - } - - while(isdigit(stabstr[cnt+i])) - i++; - - char *hi = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(hi, &(stabstr[cnt]), i)) - /* Error copying upper range */ - exit(1); - hi[i] = '\0'; - - std::string tname = convertCharToString(name); - if ( j <= 0 ) - { - /* range */ - boost::shared_ptr newType; - - // //bperr("\tLower limit: %s and Upper limit: %s\n", low, hi); - //Create new type - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - if (low_conv < LONG_MIN) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (hi_conv > LONG_MAX) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - { - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : guessSize(low,hi), - low_conv, hi_conv, tname); - } - else - { - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tname); - } - tc->addOrUpdateType(newType); - } - else if( j > 0) - { - j = atol(hi); - if (j == 0) - { - /*size */ - int size = (int)j; - - // //bperr("\tSize of Type : %d bytes\n",size); - //Create new type - - //Add to Collection - tc->addOrUpdateType(Type::make_shared(ID, size, convertCharToString(name))); - } - else - { - /* range */ - boost::shared_ptr newType; - // //bperr("Type RANGE: ERROR!!\n"); - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : sizeof(long), - low_conv, hi_conv, tname); - else - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tname); - tc->addOrUpdateType(newType); - } - } - free(low); - free(hi); - - cnt = cnt + i; - if( stabstr[cnt] == ';') - cnt++; - - return(&(stabstr[cnt])); -} - -#endif - -// -// = @s; -// = @s;(,) -// = @s;r(,);;; -// - -// -// This may in fact be much simpler than first anticipated -// dbx only -// understands @s (size) and @P (packed) types. We only -// parse the size attribute, and should be able to get away -// with simply passing the remainder to the rest of our parser -// -static char *parseAttrType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - assert(stabstr[cnt] == '@'); - cnt++; // skip the @ - - if (stabstr[cnt] == 's') { - cnt++; - - int size = parseSymDesc(stabstr, cnt); - cnt++; // skip ';' - - char *newstr = parseTypeDef(mod, stabstr+cnt, name, ID, size); - if (newstr[0] == ';') - return newstr+1; - else - return newstr; - } else { - ////bperr(" Unable to parse Type Attribute: %s ID %d : %s\n", - // name,ID, &(stabstr[cnt])); - while (stabstr[cnt] != ';') cnt++; - cnt++; - return parseTypeDef(mod, stabstr+cnt, name, ID); - } -} -/* -static void parseAttrType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - bool includesRange = false; - char *low = NULL, *high = NULL; - - // format @s(size in bits); negative type number; - dataClass typdescr = dataTypeAttrib; - - assert(stabstr[cnt] == '@'); - cnt++; // skip the @ - - if (stabstr[cnt] == 's') { - cnt++; - - int size = parseSymDesc(stabstr, cnt); - cnt++; // skip ';' - - if (stabstr[cnt] == 'r') { - // include range at end - cnt++; - includesRange = true; - } - - int type = parseSymDesc(stabstr, cnt); - // skip ';' end of stab record ??? (at least for bool) - cnt++; - - if (includesRange) { - int len; - - // Parse out low range string. - len = 0; - if (stabstr[cnt] == '-' ) cnt++, len++; - while (isdigit(stabstr[cnt])) cnt++, len++; - cnt++; // skip ';' - - // Store the low range string. - low = (char *)malloc(sizeof(char) * (len + 1)); - assert(low); - strncpy(low, &stabstr[cnt - (len + 1)], len); - low[len] = '\0'; - - // Parse out high range string. - len = 0; - if (stabstr[cnt] == '-' ) cnt++, len++; - while (isdigit(stabstr[cnt])) cnt++, len++; - cnt++; // skip ';' - - // Store the high range string. - high = (char *)malloc(sizeof(char) * (len + 1)); - assert(high); - strncpy(high, &stabstr[cnt - (len + 1)], len); - high[len] = '\0'; - } - - // Create a new B_type that points to a builtInTypes - Type *ptrType =BPatch::bpatch->builtInTypes->findBuiltInType(type); - - if (!ptrType) ptrType = BPatch::bpatch->type_Untyped; - - Type *newType = new Type(name, ID, typdescr, size/8, ptrType); - if(!newType) { - //bperr(" Can't Allocate new type "); - exit(-1); - } - - if (includesRange) { - newType->setLow(low); - newType->setHigh(high); - free(low); - free(high); - } - - // Add type to collection - newType2 = tc->addOrUpdateType(newType); - - if (stabstr[cnt]) { - //bperr("More Type Attribute to Parse: %s ID %d : %s\n", name, - ID, &(stabstr[cnt])); - //bperr("got type = %d\n", type); - //bperr("full string = %s\n", stabstr); - } - } else { - ////bperr(" Unable to parse Type Attribute: %s ID %d : %s\n", - // name,ID, &(stabstr[cnt])); - } -} -*/ -// -// = & -// -static char *parseRefType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - /* reference to another type */ - assert(stabstr[cnt] == '&'); - cnt++; - - int refID = parseTypeUse(mod, stabstr, cnt, name); - - // Create a new B_type that points to a structure - typeCollection *tc = typeCollection::getModTypeCollection(mod); - auto ptrType = tc->findOrCreateType(refID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - std::string tName = convertCharToString(name); - - // Add to typeCollection - tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - - return(&(stabstr[cnt])); -} - -// -// Given a base class and a new type, add all visible fields to the new class -// -void addBaseClassToClass(Module *mod, int baseID, - boost::shared_ptr newType, int /*offset*/) -{ - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - - //Find base class - auto baseCl = tc->findType(baseID, Type::share); - if( ! baseCl ) { - std::string modName = mod->fileName(); - //bpwarn( "can't find base class id %d in module %s\n", baseID, modName); - baseCl = tc->addOrUpdateType(Type::make_shared(baseID)); - } - std::string fName = "{superclass}"; - newType->asFieldListType().addField( fName, baseCl, -1, visUnknown ); - - //Get field descriptions of the base type - /* - const std::vector *baseClFields = baseCl->getComponents(); - for (unsigned int fieldNum=0; fieldNum < baseClFields->size(); fieldNum++) { - Field *field = (*baseClFields)[fieldNum]; - - if (field->getVisibility() == visPrivate) - continue; //Can not add this member - - newType->addField(field->getName(), field->getTypeDesc(), field->getType(), field->getOffset()+offset, field->getVisibility()); - } - */ -} - -// -// parse a list of fields. -// Format is [A|B|C-M|N|O][c][G]:;offset;size; -// -static char *parseFieldList(Module *mod, boost::shared_ptr newType, - char *stabstr, bool sunCPlusPlus) -{ - int cnt = 0; - int size = 0; - char *compname; - int comptype= 0; - int beg_offset=0; - visibility_t _vis = visUnknown; - dataClass typedescr; - bool hasVirtuals = false; - typeCollection *tc = typeCollection::getModTypeCollection(mod); - assert(tc); - - if (stabstr[cnt] == '!') - { - //Inheritance definition, Add base class field list to the current one - //according to visibility rules. - - cnt++; //Skip '!' - - //Get # of base classes - int baseClNum = atoi(getIdentifier(stabstr, cnt).c_str()); - cnt++; //Skip ',' - - boost::shared_ptr newStructType; - if(newType->isStructType()) newStructType = newType; - //Skip information for each base class - for (int i=0; icG - if (sunCPlusPlus) cnt += 3; - - if ((stabstr[cnt] == 'u') && (stabstr[cnt+1] == ':') && (!isdigit(stabstr[cnt+2]))) - { - cnt += 2; - } - - compname = getFieldName(stabstr, cnt); - - /* - if (strlen(compname) == 0) { - //Something wrong! Most probably unhandled C++ type - //Skip the rest of the structure - while(stabstr[cnt]) cnt++; - return(&stabstr[cnt]); - } - */ - cnt++; // Skip ":" - - if ((stabstr[cnt]) == ':') - { - //Method definition - typedescr = dataFunction; - cnt++; - } - - if ((stabstr[cnt]) == '/') - { // visibility C++ - cnt++; /* get '/' */ - switch (stabstr[cnt]) { - case '0': - _vis = visPrivate; - break; - case '1': - _vis = visProtected; - break; - case '2': - _vis = visPublic; - break; - default: - _vis = visUnknown; - } - cnt++; // get visibility value - } - - // should be a typeDescriptor - comptype = parseTypeUse(mod, stabstr, cnt, ""); - - if (stabstr[cnt] == ':') - { - while (stabstr[cnt] == ':') - { - cnt++; //Discard ':' - beg_offset = 0; - size = 0; - std::string varName = getIdentifier(stabstr, cnt); - - if (typedescr == dataFunction) - { - // Additional qualifiers for methods - cnt++; //Skip ';' - cnt++; //Skip visibility - cnt++; //Skip method modifier - if (stabstr[cnt] == '*') - { - //Virtual fcn definition - hasVirtuals = true; - cnt++; //Skip '*' - while(stabstr[cnt] != ';') cnt++; //Skip vtable index - cnt++; //Skip ';' - if (stabstr[cnt] != ';') - { - parseTypeUse(mod, stabstr, cnt, ""); //Skip type number to the base class - } - cnt++; //Skip ';' - if (isSymId(stabstr[cnt])) - { - parseTypeUse(mod, stabstr, cnt, ""); - } - } else if ( (stabstr[cnt] == '.') - || (stabstr[cnt] == '?') ) - { - cnt++; //Skip '.' or '?' - if (isSymId(stabstr[cnt])) - { - parseTypeUse(mod, stabstr, cnt, ""); - } - } - } - - if (stabstr[cnt] == ';') - cnt++; //Skip ';' - } - } - else if (stabstr[cnt] == ',') - { - cnt++; // skip ',' - beg_offset = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == ',') - { - cnt++; // skip ',' - size = parseSymDesc(stabstr, cnt); - } - else - size = 0; - } - - if (stabstr[cnt] == ';') // jaw 03/15/02-- major kludge here for DPCL compat - cnt++; // needs further examination - - // //bperr("\tType: %d, Starting Offset: %d (bits), Size: %d (bits)\n", comptype, beg_offset, size); - (void)size; // otherwise unused symbol - // Add struct field to type - - auto fieldType = tc->findOrCreateType( comptype, Type::share ); - if (!fieldType) - { - //C++ compilers may add extra fields whose types might not available. - //Assign void type to these kind of fields. --Mehmet - fieldType = tc->findType("void", Type::share); - } - std::string fName = convertCharToString(compname); - if (_vis == visUnknown) - { - newType->asFieldListType().addField(fName, fieldType, beg_offset); - } - else - { - // //bperr( "Adding field '%s' to type '%s' @ 0x%x\n", compname, newType->getName(), newType ); - newType->asFieldListType().addField(fName, fieldType, beg_offset, _vis); - ////bperr("Adding Component with VISIBILITY STRUCT\n"); - } - free(compname); - } - - if (hasVirtuals && - stabstr[cnt] == ';' && - stabstr[cnt+1] == '~' && - stabstr[cnt+2] == '%') - { - cnt+=3; - while (stabstr[cnt] != ';') cnt++; - } - - // should end with a ';' - if (stabstr[cnt] == ';') - { - return &stabstr[cnt+1]; - } - else if (stabstr[cnt] == '\0') - { - return &stabstr[cnt]; - } - else - { - //bperr("invalid stab record: %s\n", &stabstr[cnt]); - abort(); - return NULL; // should not get here - } -} - - -// -// Y;;;;; -// ;;;; -// ;;; -// -static char *parseCPlusPlusInfo(Module *mod, - char *stabstr, const char *mangledName, int ID) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - int cnt; - char *name; - int structsize; - bool sunStyle = true; - bool nestedType = false; - dataClass typdescr; - - assert(stabstr[0] == 'Y'); - cnt = 1; - - if (isdigit(stabstr[cnt])) { - structsize = parseSymDesc(stabstr, cnt); - sunStyle = false; - } - - switch(stabstr[cnt]) { - case 'C': - case 'c': - typdescr = dataTypeClass; - break; - - case 'S': - nestedType = true; - DYNINST_FALLTHROUGH; - case 's': - typdescr = dataStructure; - break; - - case 'U': - nestedType = true; - DYNINST_FALLTHROUGH; - case 'u': - typdescr = dataUnion; - break; - - case 'n': // namespace - ignored - cnt = strlen(stabstr); - return(&(stabstr[cnt])); - break; - - default: - //bperr( "ERROR: Unrecognized C++ str = %s\n", stabstr); - cnt = strlen(stabstr); - return(&(stabstr[cnt])); - break; - } (void)nestedType; // unused - - cnt++; // skip to size - if (isdigit(stabstr[cnt])) { - structsize = parseSymDesc(stabstr, cnt); - } - (void)structsize; // unused - - if (stabstr[cnt] == 'V') cnt++; - if (stabstr[cnt] == '(') cnt++; - - if (sunStyle && (stabstr[cnt] != ';')) { - int len; - char *n; - - // Class or Type Name - n = &stabstr[cnt]; - while (stabstr[cnt] != ';') cnt++; - len = &stabstr[cnt] - n; - name = (char *) calloc(len + 1, sizeof(char)); - strncpy(name, n, len); - } else { - name = const_cast< char * >( mangledName ); - } - - std::string tName = convertCharToString(name); - boost::shared_ptr newType; - //Create new type - switch (typdescr) { - case dataTypeClass: - case dataStructure: - newType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - break; - case dataUnion: - newType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - break; - default: - assert(0); - } - //add to type collection - - if (sunStyle) { - cnt++; - // base class(es) - while (stabstr[cnt] != ';') { - // skip visibility flag - cnt++; - - int offset = parseSymDesc(stabstr, cnt); - - // Find base class type identifier - int baseID = parseSymDesc(stabstr, cnt); - addBaseClassToClass(mod, baseID, newType, offset); - } - - cnt++; // skip ; - } - - // parse dataMembers - stabstr = parseFieldList(mod, newType, &stabstr[cnt], sunStyle); - cnt = 0; - - if (stabstr[0]) { - // parse member functions - cnt++; - while (stabstr[cnt] && (stabstr[cnt] != ';')) { - std::string pd_funcName = getIdentifier(stabstr, cnt, true); - const char *funcName = pd_funcName.c_str(); - - funcName++; // skip ppp-code - - if (*funcName == '-') funcName++; // it's a pure vitual - - while (isdigit(*funcName)) funcName++; // skip virtual function index - funcName++; - - char *className = strdup(currentRawSymbolName.c_str()); - className[3] = 'c'; - className[strlen(className)-1] = '\0'; // remove tailing "_" - std::string methodName = std::string(className) + std::string(funcName) + std::string("_"); - - std::string fName = P_cplus_demangle( methodName ); - if( name != NULL ) { - funcName = strrchr( name, ':' ); - if( funcName ) { funcName++; } - else { funcName = name; } - } - - // should include position for virtual methods - auto fieldType = tc->findType("void", Type::share); - - newType->asFieldListType().addField( fName, Type::make_shared( ID, fieldType, fName)); - - free(name); - free(className); - if (stabstr[cnt] == ' ') cnt++; - } - } - - cnt = strlen(stabstr); - return(&(stabstr[cnt])); -} - -// -// This function takes a and parses it -// -// = | -// | -// * | Pointer to a type -// | -// f | function type -// R, | Real type -// b[u|s][c|];; | Builtin -// | -// e | -// | -// | -// k | SunPro constant -// B | SunPro volatile -// M;| Fortran CHARACTER array -// s | Structure is size -// u | Union is size -// V -// -// = : | :, -// -// It adds the typeDef to the type definition with the name name, and id ID. -// -static char *parseTypeDef(Module *mod, char *stabstr, - const char *name, int ID, unsigned int sizeHint) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - boost::shared_ptr newType; - boost::shared_ptr newFieldType; - boost::shared_ptr ptrType; - - std::string compsymdesc; - - dataClass typdescr; - int ptrID=0; - - int value; - int cnt,i,j,k; - int structsize; - int type; - cnt = i = j = k = 0; - - assert (stabstr[0] != '='); - - // //bperr( "parsing %s\n", stabstr); - if (isSymId(stabstr[0])) - { - typdescr = dataScalar; - type = parseSymDesc(stabstr, cnt); - - if (ID == type) - { - // Type:tFOO = FOO - // as far as I can tell, this only happens when defining an empty - // type (i.e. void) - - std::string tName = convertCharToString(name); - newType = tc->addOrUpdateType(Type::make_shared(ID, 0, tName)); - } - else if (stabstr[cnt] == '=') - { - // XXX - in the new type t(0,1)=(0,2)=s... is possible - // skip the second id for now -- jkh 3/21/99 - stabstr = parseTypeDef(mod, &(stabstr[cnt+i+1]), name, type); - cnt = 0; - boost::shared_ptr oldType; - - oldType = tc->findOrCreateType(type, Type::share); - if (!oldType) oldType = Symtab::type_Untyped(); - std::string tName = convertCharToString(name); - tc->addOrUpdateType(Type::make_shared(ID, oldType, tName, sizeHint)); - - } - else - { - boost::shared_ptr oldType; - std::string tName = convertCharToString(name); - oldType = tc->findOrCreateType(type, Type::share); - newType = tc->addOrUpdateType(Type::make_shared(ID, oldType, tName, sizeHint)); - } - } else { - switch (stabstr[0]) { - case 'x': //cross reference - { - parseCrossRef(tc, name, ID, stabstr, cnt); - break; - } - case '*': - { - /* pointer to another type */ - cnt++; - ptrID = parseTypeUse(mod, stabstr, cnt, NULL); - - // Create a new B_type that points to a structure - ptrType = tc->findOrCreateType(ptrID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - // Add to typeCollection - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType)); - return(&(stabstr[cnt])); - break; - } - case 'a': - case 'A': - { - (void) parseArrayDef(mod, name, ID, stabstr, cnt, sizeHint); - return (&stabstr[cnt]); - break; - } - case 'g': - { - /* function with return type and prototype */ - - // g[]*# - typdescr = dataFunction; - - cnt++; /* skip the g */ - type = parseTypeUse(mod, stabstr, cnt, name); - ptrType = tc->findOrCreateType(type, Type::share); - - { - std::string tName = convertCharToString(name); - auto newFunction = tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - if (!newFunction) { - //bpfatal(" Can't Allocate new type "); - types_printf("%s[%d]: parseTypeDef: unable to allocate newType\n", FILE__, __LINE__); - //exit(-1); - } - - while ((stabstr[cnt] != '#') && (stabstr[cnt])) { - int paramType; - paramType = parseTypeUse(mod, stabstr, cnt, name); - newType = tc->findOrCreateType(paramType, Type::share); - newFunction->asFunctionType().addParam(newType); - //newFunction2->addField(buffer, newType->getDataClass(), newType, curOffset, newType->getSize()); - } - } - - // skip # - if (stabstr[cnt] == '#') cnt++; - break; - } - case 'f': - { - /* function type */ - typdescr = dataFunction; - - cnt++; /* skip the f */ - type = parseTypeUse(mod, stabstr, cnt, name); - ptrType = tc->findOrCreateType(type, Type::share); - - - std::string tName = convertCharToString(name); - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - // cnt = strlen(stabstr); - break; - } - - case 'M': - { - /* CHARACTER ??? */ - cnt++; // skip 'M' - - int baseType = parseSymDesc(stabstr, cnt); - if (baseType != -2 || (stabstr[cnt] != ';')) { - //bperr("unexpected non character array %s\n", stabstr); - } else { - cnt++; // skip ';' - int size; - if (stabstr[cnt] == 'T') { - /* Fortran stack-based array bounds */ - size = 0; - cnt++; // skip 'T' - (void) parseSymDesc(stabstr, cnt); - } else if (stabstr[cnt] == 'J') { - /* Unbounded range */ - size = 0; - cnt++; // skip 'J'; - (void) parseSymDesc(stabstr, cnt); - } else - size = parseSymDesc(stabstr, cnt); - - ptrType = tc->findOrCreateType(baseType, Type::share); - std::string tName = convertCharToString(name); - - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType, 1, size, tName)); - } - break; - - } - case 'R': - { - // Define a floating point type - R fp-type; bytes; - cnt++; - (void) parseSymDesc(stabstr, cnt); - cnt ++; - - int bytes = parseSymDesc(stabstr, cnt); - - newType = tc->addOrUpdateType(Type::make_shared(ID, bytes, name)); - - if (stabstr[cnt] == ';') cnt++; // skip the final ';' - - // gcc 3.0 adds an extra field that is always 0 (no indication in the code why) - if (stabstr[cnt] == '0') cnt += 2; // skip the final '0;' - - break; - } - - case 'b': - { - // builtin type b - signed char-flag width; offset; nbits - int limit = strlen(&stabstr[cnt]); - - // skip to width - while (!isdigit(stabstr[cnt+i]) && (i < limit)) i++; - if (i >= limit) return(&(stabstr[cnt])); - - cnt += i; - int size = parseSymDesc(stabstr,cnt); - cnt -= i; - i++; // skip the ';' - - // skip to bits - while (stabstr[cnt+i] != ';' && (i < limit)) i++; - if (i >= limit) return(&(stabstr[cnt])); - i++; - - cnt += i; - parseSymDesc(stabstr, cnt); - - if (stabstr[cnt]) cnt++; // skip the final ';' - - //Add to Collection - newType = tc->addOrUpdateType(Type::make_shared(ID, size, name)); - - return &stabstr[cnt]; - break; - } - case 'r': // range type - { - return parseRangeType(mod, name, ID, stabstr, sizeHint); - break; - } - case 'e': // Enumerated type - { - cnt++; /* skip the 'e' */ - - // Create new Enum type - std::string tName = convertCharToString(name); - // Add type to collection - auto newEnumType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - - while (stabstr[cnt]) { - /* Get enum component value */ - compsymdesc = getIdentifier(stabstr, cnt); - cnt++; /* skip colon */ - value = parseSymDesc(stabstr, cnt); - - // add enum field to type - newEnumType->asEnumType().addConstant(compsymdesc, value); - - cnt++; /* skip trailing comma */ - if ((stabstr[cnt]) == ';') cnt++; /* End of enum stab record */ - } - break; - } - case '@': // type attribute, defines size and type (negative num) - { - return parseAttrType(mod, name, ID, stabstr, cnt); - break; - } - case '&': //XXX- Need to complete, may be more to parse jdd 4/22/99 - { - return parseRefType(mod, name, ID, stabstr, cnt); - break; - } - case 'k': // Sun constant type s - parse as - { - return parseTypeDef(mod, &stabstr[cnt+1], name, ID); - break; - } - case 'V': // volatile ? type V - parse as - case 'B': // Sun volatile type B - parse as - return parseTypeDef(mod, &stabstr[cnt+1], name, ID); - break; - - case 's': // struct - case 'u': // union - case 'T': // Fortran TYPE - { - /* Type descriptor */ - if (stabstr[cnt] == 's' || stabstr[cnt] == 'T') { - typdescr = dataStructure; - } else { - typdescr = dataUnion; - } - - cnt++; // skip to size - structsize = parseSymDesc(stabstr, cnt); - (void)structsize; // unused - - std::string tName = convertCharToString(name); - //Create new type - if (typdescr == dataStructure) { - newFieldType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - } - else { - newFieldType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - } - //add to type collection - - //TODO What if two different files have the same structure?? - char *ret = parseFieldList(mod, newFieldType, &stabstr[cnt], false); - return ret; - - break; - } - case 'Y': - { - // C++ specific stabs (Sun compiler) - return parseCPlusPlusInfo(mod, stabstr, name, ID); - break; - } - case 'Z': // What is this ??? - jkh 10/14/99 (xlc compiler uses it) - { - return (&stabstr[1]); - break; - } - case '#': - { - //Class method definition - cnt++; //Skip '#' - if (stabstr[cnt] == '#') { - //Get return type - cnt++; //Skip '#' - parseTypeUse(mod, stabstr, cnt, name); - } - else { - while(1) { - //Skip class type, return typ and arg types - parseTypeUse(mod, stabstr, cnt, name); - if (stabstr[cnt] == ',') - cnt++; - else if (stabstr[cnt] == ';') - break; - } - } - - cnt++; //Skip ';' - return(&(stabstr[cnt])); - break; - } - default: - //bperr( "ERROR: Unrecognized str = %s\n", &stabstr[cnt]); - // return NULL; - // Null probably isn't the right choice here. - cnt = strlen(stabstr); - break; - } - } - - return(&(stabstr[cnt])); -} /* end of parseTypeDef*/ - -// -// parseConstantUse - parse a constant (used by Fortran PARAMETERS) -// -// = =i | -// =r -// -// -static boost::shared_ptr parseConstantUse(Module *mod, char *stabstr, int &cnt) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - // skip = - cnt++; - - boost::shared_ptr ret; - - if (stabstr[cnt] == 'i') { - ret = tc->findType("integer*4", Type::share); - } else if (stabstr[cnt] == 'r') { - ret = tc->findType("double", Type::share); - } else if (stabstr[cnt] == 's') { - ret = tc->findType("char *", Type::share); - } else { - //bperr("unknown constant type %s\n", &stabstr[cnt]); - ret = NULL; - } - - cnt = strlen(stabstr); - - return ret; -} - From 116a55c942e2a820c0ffc281ff1775bcb48f4ace Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 19 Oct 2021 13:49:10 -0500 Subject: [PATCH 005/505] Remove stabs from BPatch --- dyninstAPI/h/BPatch_module.h | 5 +---- dyninstAPI/h/BPatch_sourceObj.h | 2 -- dyninstAPI/src/BPatch_collections.h | 2 +- dyninstAPI/src/BPatch_module.C | 1 - 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/dyninstAPI/h/BPatch_module.h b/dyninstAPI/h/BPatch_module.h index 41900c507d..0785246bec 100644 --- a/dyninstAPI/h/BPatch_module.h +++ b/dyninstAPI/h/BPatch_module.h @@ -112,7 +112,6 @@ class BPATCH_DLL_EXPORT BPatch_module: public BPatch_sourceObj{ bool getSourceObj(BPatch_Vector&); BPatch_sourceObj *getObjParent(); void parseTypes(); - char *parseStabStringSymbol(int line, char *stabstr, void *stabptr); void setDefaultNamespacePrefix(char *name); void handleUnload(); bool isExploratoryModeOn();// true if exploratory or defensive mode is on @@ -263,9 +262,7 @@ class BPATCH_DLL_EXPORT BPatch_module: public BPatch_sourceObj{ bool parseTypesIfNecessary(); BPatch_typeCollection *moduleTypes; - // In particular, we understand the type information - // in both DWARF and STABS format. - void parseStabTypes(); + // We understand the type information in DWARF format. void parseDwarfTypes(); BPatch_funcMap func_map; diff --git a/dyninstAPI/h/BPatch_sourceObj.h b/dyninstAPI/h/BPatch_sourceObj.h index c4409096c5..fc239a4b4f 100644 --- a/dyninstAPI/h/BPatch_sourceObj.h +++ b/dyninstAPI/h/BPatch_sourceObj.h @@ -44,7 +44,6 @@ typedef enum BPatch_language { BPatch_fortran, BPatch_fortran77, BPatch_fortran90, - BPatch_f90_demangled_stabstr, BPatch_fortran95, BPatch_assembly, BPatch_mixed, @@ -94,7 +93,6 @@ class BPATCH_DLL_EXPORT BPatch_sourceObj { case BPatch_fortran: return "BPatch_fortran"; case BPatch_fortran77: return "BPatch_fortran77"; case BPatch_fortran90: return "BPatch_fortran90"; - case BPatch_f90_demangled_stabstr: return "BPatch_fortran90_demangled_stabstr"; case BPatch_fortran95: return "BPatch_fortran95"; case BPatch_assembly: return "BPatch_assembly"; case BPatch_mixed: return "BPatch_mixed"; diff --git a/dyninstAPI/src/BPatch_collections.h b/dyninstAPI/src/BPatch_collections.h index 692fa7276d..e4cbad506f 100644 --- a/dyninstAPI/src/BPatch_collections.h +++ b/dyninstAPI/src/BPatch_collections.h @@ -103,7 +103,7 @@ class BPatch_typeCollection { /* Some debug formats allow forward references. Rather than fill in forward in a second pass, generate placeholder types, and fill them in as we go. Because we require - One True Pointer for each type (in parseStab.C), when + One True Pointer for each type, when updating a type, return that One True Pointer. */ BPatch_type * findOrCreateType( const int & ID ); BPatch_type * addOrUpdateType( BPatch_type * type ); diff --git a/dyninstAPI/src/BPatch_module.C b/dyninstAPI/src/BPatch_module.C index 6a7b0548e3..10dcc4d2d5 100644 --- a/dyninstAPI/src/BPatch_module.C +++ b/dyninstAPI/src/BPatch_module.C @@ -156,7 +156,6 @@ BPatch_module::BPatch_module(BPatch_addressSpace *_addSpace, break; case lang_Fortran_with_pretty_debug: - setLanguage( BPatch_f90_demangled_stabstr ); break; case lang_Fortran: From 93e74fbd990f59a747d86c310f1fb3c8cc180894 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 19 Oct 2021 13:50:31 -0500 Subject: [PATCH 006/505] Remove stabs from symbol demangling --- common/src/symbolDemangle.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/common/src/symbolDemangle.c b/common/src/symbolDemangle.c index 41fb58af33..decfecf33b 100644 --- a/common/src/symbolDemangle.c +++ b/common/src/symbolDemangle.c @@ -38,13 +38,13 @@ // Returns a malloc'd string that is the demangled symbol name. THe caller is // responsible for the freeing this memory. Returns NULL on malloc failure. // The symbol name symName is demangled using the cplus_demangle function after -// first removing any versioning suffixes (first '@') or stabs suffixes (first -// ':') to create the mangled name. If cplus_demangle fails, the mangled name +// first removing any versioning suffixes (first '@') +// to create the mangled name. If cplus_demangle fails, the mangled name // is returned unmodified. If cplus_demangle succeeds and includeParams is // false, then any clone suffixes (the first '.' to the end of the mangled // name) are appended to the value from cplus_demangle. // -// Other than the removal of versioning and stabs suffixes, and appending any +// Other than the removal of versioning suffixes, and appending any // clone suffixes if includeParams is false to the result, the result should be // equivalent to using c++filt. Below are the c++filt and cplus_demangle // options @@ -57,34 +57,34 @@ char *symbol_demangle(const char *symName, int includeParams) { int cloneOffset = -1; // offset to clone suffix - int versionOrStabsOffset = -1; // offset to version or stabs suffix - int lastOffset; // offset to version or stabs suffix + int versionOffset = -1; // offset to version suffix + int lastOffset; // offset to version suffix // if present, else null of symName - // find both clone, and then version or stabs suffixes if any + // find both clone, and then version suffixes if any for (lastOffset = 0; symName[lastOffset]; ++lastOffset) { char c = symName[lastOffset]; if (c == '.' && cloneOffset == -1) { // clone suffix start with first '.' cloneOffset = lastOffset; - } else if (c == '@' || c == ':') { - // version ('@') or stabs (':') suffix found - versionOrStabsOffset = lastOffset; + } else if (c == '@') { + // version ('@') suffix found + versionOffset = lastOffset; // stop searching break; } } - const char *mangledName = symName; // symName without version/stabs suffix + const char *mangledName = symName; // symName without version suffix char *allocatedMangledName = 0; - if (versionOrStabsOffset != -1) { - // make a copy of the symName without version or stabs suffix - allocatedMangledName = malloc(versionOrStabsOffset + 1); + if (versionOffset != -1) { + // make a copy of the symName without version suffix + allocatedMangledName = malloc(versionOffset + 1); if (allocatedMangledName == 0) { return NULL; } - memcpy(allocatedMangledName, symName, versionOrStabsOffset); - allocatedMangledName[versionOrStabsOffset] = '\0'; + memcpy(allocatedMangledName, symName, versionOffset); + allocatedMangledName[versionOffset] = '\0'; mangledName = allocatedMangledName; } From 2f3118f9ffa2708a160e69af455182a28e477af0 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 19 Oct 2021 13:54:19 -0500 Subject: [PATCH 007/505] Remove special Fortran debug handling lang_Fortran_with_pretty_debug was only for Fortran with stabs. --- dyninstAPI/src/BPatch_module.C | 3 --- symtabAPI/h/symutil.h | 1 - symtabAPI/src/Object.C | 18 ++---------------- symtabAPI/src/dwarfWalker.C | 4 +--- 4 files changed, 3 insertions(+), 23 deletions(-) diff --git a/dyninstAPI/src/BPatch_module.C b/dyninstAPI/src/BPatch_module.C index 10dcc4d2d5..cb22428225 100644 --- a/dyninstAPI/src/BPatch_module.C +++ b/dyninstAPI/src/BPatch_module.C @@ -155,9 +155,6 @@ BPatch_module::BPatch_module(BPatch_addressSpace *_addSpace, setLanguage( BPatch_cPlusPlus ); break; - case lang_Fortran_with_pretty_debug: - break; - case lang_Fortran: case lang_CMFortran: setLanguage( BPatch_fortran ); diff --git a/symtabAPI/h/symutil.h b/symtabAPI/h/symutil.h index 6ecd8f013d..0f0b1b9bf8 100644 --- a/symtabAPI/h/symutil.h +++ b/symtabAPI/h/symutil.h @@ -61,7 +61,6 @@ typedef enum { lang_CPlusPlus, lang_GnuCPlusPlus, lang_Fortran, - lang_Fortran_with_pretty_debug, lang_CMFortran } supportedLanguages; diff --git a/symtabAPI/src/Object.C b/symtabAPI/src/Object.C index f32f428f14..7fb064ce2c 100644 --- a/symtabAPI/src/Object.C +++ b/symtabAPI/src/Object.C @@ -153,7 +153,6 @@ const char *Dyninst::SymtabAPI::supportedLanguages2Str(supportedLanguages s) CASE_RETURN_STR(lang_CPlusPlus); CASE_RETURN_STR(lang_GnuCPlusPlus); CASE_RETURN_STR(lang_Fortran); - CASE_RETURN_STR(lang_Fortran_with_pretty_debug); CASE_RETURN_STR(lang_CMFortran); }; return "bad_language"; @@ -399,7 +398,7 @@ supportedLanguages AObject::pickLanguage(string &working_module, char *working_o supportedLanguages working_lang) { supportedLanguages lang = lang_Unknown; - static int sticky_fortran_modifier_flag = 0; + // (2) -- check suffixes -- try to keep most common suffixes near the top of the checklist string::size_type len = working_module.length(); if((len>2) && (working_module.substr(len-2,2) == string(".c"))) lang = lang_C; @@ -429,12 +428,7 @@ supportedLanguages AObject::pickLanguage(string &working_module, char *working_o // have the "pretty" names, we need to detect this in order to properly read the debug. if (working_lang == lang_Fortran) { - if (sticky_fortran_modifier_flag) - { - //cerr << FILE__ << __LINE__ << ": UPDATE: lang_Fortran->lang_Fortran_with_pretty_debug." << endl; - working_lang = lang_Fortran_with_pretty_debug; - } - else if (working_options) + if (working_options) { char *dbg_gen = NULL; //cerr << FILE__ << __LINE__ << ": OPT: " << working_options << endl; @@ -448,14 +442,6 @@ supportedLanguages AObject::pickLanguage(string &working_module, char *working_o if (NULL != next_dot) { *next_dot = '\0'; //terminate major version number string - int ver_maj = atoi(dbg_gen_ver_maj); - //cerr <<"Major Debug Ver. "<lang_Fortran_with_pretty_debug. " << "Major Debug Ver. "<language(); if ((lang != lang_Fortran) && - (lang != lang_CMFortran) && - (lang != lang_Fortran_with_pretty_debug)) return; + (lang != lang_CMFortran)) return; if (name[name.length()-1] == '_') { name = name.substr(0, name.length()-1); @@ -2232,7 +2231,6 @@ bool DwarfWalker::parseSubrangeAUX(Dwarf_Die entry, /* Set the default lower bound, if we know it. */ switch ( mod()->language() ) { case lang_Fortran: - case lang_Fortran_with_pretty_debug: case lang_CMFortran: loBound = "1"; break; From 328411add521bab7eea0527571d1ad6a663f46e6 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 11:14:15 -0500 Subject: [PATCH 008/505] Turn on STERILE_BUILD by default (#1118) Co-authored-by: Tim Haines --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 89e9162bda..7f394dcb8e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -7,7 +7,7 @@ set (CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) set (CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) set (CMAKE_EXPORT_COMPILE_COMMANDS ON) -set(STERILE_BUILD OFF CACHE BOOL "Do not download/build any third-party dependencies from source") +set(STERILE_BUILD ON CACHE BOOL "Do not download/build any third-party dependencies from source") LIST(FIND CMAKE_PLATFORM_IMPLICIT_LINK_DIRECTORIES "${CMAKE_INSTALL_PREFIX}/lib" isSystemDir) From b8e35371199000e15649b8c6a7b3bcca6eb88221 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 11:46:54 -0500 Subject: [PATCH 009/505] Remove stabs from documentation (#1120) This should have been part of #1113 Co-authored-by: Tim Haines --- symtabAPI/doc/1-Intro.tex | 2 +- symtabAPI/doc/4-Definitions.tex | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/symtabAPI/doc/1-Intro.tex b/symtabAPI/doc/1-Intro.tex index c3078cc9ef..39fc2a6e2a 100644 --- a/symtabAPI/doc/1-Intro.tex +++ b/symtabAPI/doc/1-Intro.tex @@ -5,7 +5,7 @@ \section{Introduction} object file headers and debug information. SymtabAPI currently supports the ELF (IA-32, AMD-64, ARMv8-64, and POWER) and PE (Windows) object file formats. In addition, it also supports the DWARF -and stabs debugging formats. +debugging format. The main goal of this API is to provide an abstract view of binaries and libraries across multiple platforms. An abstract interface provides two diff --git a/symtabAPI/doc/4-Definitions.tex b/symtabAPI/doc/4-Definitions.tex index 85600d40fe..d638d9a199 100644 --- a/symtabAPI/doc/4-Definitions.tex +++ b/symtabAPI/doc/4-Definitions.tex @@ -20,18 +20,18 @@ \subsection{Definitions} \item[Mangled Name] A mangled name for a symbol provides a way of encoding additional information about a function, structure, class or another data type in a symbol name. It is a technique used to produce unique names for programming entities in many modern programming languages. For example, the method \emph{foo} of class C with signature \emph{int C::foo(int, int)} has a mangled name \emph{\_ZN1C3fooEii} when compiled with gcc. -Mangled names may include a sequence of clone suffixes (begins with `.' that indicate a compiler synthesized function), and this may be followed by a version suffix (begins with `@') or stabs type information (begins with `:'). +Mangled names may include a sequence of clone suffixes (begins with `.' that indicate a compiler synthesized function), and this may be followed by a version suffix (begins with `@'). \item[Pretty Name] A pretty name for a symbol is the demangled user-level symbolic name without type information for the function parameters and return types. For non-mangled names, the pretty name is the symbol name. Any function clone suffixes of the symbol are appended to the result of the demangler. For example, a symbol with a mangled name \emph{\_ZN1C3fooEii} for the method \emph{int C::foo(int, int)} has a pretty name \emph{C::foo}. -Version and stabs suffixes are removed from the mangled name before conversion to the pretty name. +Version suffixes are removed from the mangled name before conversion to the pretty name. The pretty name can be obtained by running the command line tool \code{c++filt} as \code{c++filt -i -p \emph{name}}, or using the libiberty library function \code{cplus\_demangle} with options of \code{DMGL\_AUTO | DMGL\_ANSI}. \item[Typed Name] A typed name for a symbol is the demangled user-level symbolic name including type information for the function parameters. Typically, but not always, function return type information is not included. Any function clone information is also included. For non-mangled names, the typed name is the symbol name. For example, a symbol with a mangled name \emph{\_ZN1C3fooEii} for the method \emph{int C::foo(int, int)} has a typed name \emph{C::foo(int, int)}. -Version and stabs suffixes are removed from the mangled name before conversion to the typed name. +Version suffixes are removed from the mangled name before conversion to the typed name. The typed name can be obtained by running the command line tool \code{c++filt} as \code{c++filt -i \emph{name}}, or using the libiberty library function \code{cplus\_demangle} with options of \code{DMGL\_AUTO | DMGL\_ANSI | DMGL\_PARAMS}. \item[Symbol Linkage] The symbol linkage for a symbol gives information on the visibility (binding) of this symbol, whether it is visible only in the object file where it is defined (local), if it is visible to all the object files that are being linked (global), or if its a weak alias to a global symbol. \item[Symbol Type] Symbol type for a symbol represents the category of symbols to which it belongs. It can be a function symbol or a variable symbol or a module symbol. From 43e8c132eaa2eb83e27a5e60f3663a4260f0b3cf Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 11:53:22 -0500 Subject: [PATCH 010/505] Fix uninitialized variable use in DispatcherARM64::iproc_init --- dataflowAPI/rose/semantics/DispatcherARM64.C | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/dataflowAPI/rose/semantics/DispatcherARM64.C b/dataflowAPI/rose/semantics/DispatcherARM64.C index 4e84742e23..48a51c1f72 100644 --- a/dataflowAPI/rose/semantics/DispatcherARM64.C +++ b/dataflowAPI/rose/semantics/DispatcherARM64.C @@ -5291,7 +5291,7 @@ namespace rose { DispatcherARM64::getBitfieldMask(int immr, int imms, int N, bool iswmask, int datasize) { int hsbarg = (N << 6) | (~imms); - int len; + int len = 0; for (int idx = 0; idx < 7; idx++) { if ((hsbarg & 0x1) == 1) len = idx; @@ -5684,4 +5684,3 @@ namespace rose { } // namespace //using namespace rose::Diagnostics; - From bb8d0a97aeb12132741f06175922ab9b7fec1029 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 11:53:22 -0500 Subject: [PATCH 011/505] Give global annotation objects internal linkage and file scope This was technically an ODR violation because they are in two different translation units that _could_ be linked together. However, I don't think they ever were. This fix will preclude any such problem, though. --- dataflowAPI/src/stackanalysis.C | 3 +++ dyninstAPI/src/function.C | 3 +++ 2 files changed, 6 insertions(+) diff --git a/dataflowAPI/src/stackanalysis.C b/dataflowAPI/src/stackanalysis.C index 2ba8d6e103..5afd95d28f 100644 --- a/dataflowAPI/src/stackanalysis.C +++ b/dataflowAPI/src/stackanalysis.C @@ -60,6 +60,8 @@ const StackAnalysis::Height StackAnalysis::Height::bottom( const StackAnalysis::Height StackAnalysis::Height::top( StackAnalysis::Height::uninitialized, StackAnalysis::Height::TOP); +namespace +{ AnnotationClass Stack_Anno_Intervals(std::string("Stack_Anno_Intervals"), NULL); AnnotationClass @@ -68,6 +70,7 @@ AnnotationClass Stack_Anno_Insn_Effects(std::string("Stack_Anno_Insn_Effects"), NULL); AnnotationClass Stack_Anno_Call_Effects(std::string("Stack_Anno_Call_Effects"), NULL); +} template class std::list; template class std::map; diff --git a/dyninstAPI/src/function.C b/dyninstAPI/src/function.C index c224afaf3b..d9bc6e92a3 100644 --- a/dyninstAPI/src/function.C +++ b/dyninstAPI/src/function.C @@ -1703,6 +1703,8 @@ void func_instance::createTMap_internal(StackMod* mod, TMap* tMap) } } +namespace +{ AnnotationClass Stack_Anno_Intervals(std::string("Stack_Anno_Intervals"), NULL); AnnotationClass @@ -1711,6 +1713,7 @@ AnnotationClass Stack_Anno_Insn_Effects(std::string("Stack_Anno_Insn_Effects"), NULL); AnnotationClass Stack_Anno_Call_Effects(std::string("Stack_Anno_Call_Effects"), NULL); +} void func_instance::freeStackMod() { // Free stack analysis intervals StackAnalysis::Intervals *i = NULL; From f92fb49553c99155c923e0bc78cc492d1b518f59 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 12:19:44 -0500 Subject: [PATCH 012/505] Fix possible buffer overflow in BPatch::processCreate --- dyninstAPI/src/BPatch.C | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/dyninstAPI/src/BPatch.C b/dyninstAPI/src/BPatch.C index a08690cb2c..2c56465af2 100644 --- a/dyninstAPI/src/BPatch.C +++ b/dyninstAPI/src/BPatch.C @@ -1156,17 +1156,15 @@ BPatch_process *BPatch::processCreate(const char *path, const char *argv[], // just a sanity check for the exitence of struct stat statbuf; if (-1 == stat(path, &statbuf)) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): file does not exist\n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + ",...): file does not exist\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } // and ensure its a regular file: if (!S_ISREG(statbuf.st_mode)) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): not a regular file \n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + ",...): not a regular file\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } @@ -1174,9 +1172,8 @@ BPatch_process *BPatch::processCreate(const char *path, const char *argv[], if (! ( (statbuf.st_mode & S_IXUSR) || (statbuf.st_mode & S_IXGRP) || (statbuf.st_mode & S_IXOTH) )) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): not an executable \n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + "%s,...): not an executable\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } From 63747a0b8bcec99c398c69cdfd90c0dca9137caf Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 13:10:00 -0500 Subject: [PATCH 013/505] Remove unused variables from Symtab This is an ABI-breaking change. Fixes #1062 --- symtabAPI/h/Symtab.h | 4 ---- symtabAPI/src/Symtab.C | 5 ----- 2 files changed, 9 deletions(-) diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 1c1815fc7f..84788b3e28 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -622,10 +622,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, //type info valid flag bool isTypeInfoValid_; - int nlines_; - unsigned long fdptr_; - char *lines_; - //Relocation sections bool hasRel_; bool hasRela_; diff --git a/symtabAPI/src/Symtab.C b/symtabAPI/src/Symtab.C index da5cbea0e4..24f52a7c88 100644 --- a/symtabAPI/src/Symtab.C +++ b/symtabAPI/src/Symtab.C @@ -321,7 +321,6 @@ SYMTAB_EXPORT Symtab::Symtab(MappedFile *mf_) : no_of_symbols(0), sorted_everyFunction(false), isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(false), @@ -352,7 +351,6 @@ SYMTAB_EXPORT Symtab::Symtab() : no_of_symbols(0), sorted_everyFunction(false), isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(false), @@ -1079,7 +1077,6 @@ Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : no_of_symbols(0), sorted_everyFunction(false), isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(defensive_bin), @@ -1150,7 +1147,6 @@ Symtab::Symtab(unsigned char *mem_image, size_t image_size, no_of_symbols(0), sorted_everyFunction(false), isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), @@ -1432,7 +1428,6 @@ Symtab::Symtab(const Symtab& obj) : no_of_symbols(obj.no_of_symbols), sorted_everyFunction(false), isTypeInfoValid_(obj.isTypeInfoValid_), - nlines_(0), fdptr_(0), lines_(NULL), hasRel_(false), hasRela_(false), hasReldyn_(false), hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), isStaticBinary_(false), isDefensiveBinary_(obj.isDefensiveBinary_), From d652747125631678e8f755720aa2d4064bbb9923 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 25 Oct 2021 17:06:00 -0500 Subject: [PATCH 014/505] Remove unused generateSimple (#1122) This is never called in Dyninst. It also has broken logic. Fixes #1087 Co-authored-by: Tim Haines --- dyninstAPI/src/codegen-aarch64.C | 8 -------- dyninstAPI/src/codegen-aarch64.h | 4 ---- dyninstAPI/src/codegen-power.C | 35 -------------------------------- dyninstAPI/src/codegen-power.h | 3 --- 4 files changed, 50 deletions(-) diff --git a/dyninstAPI/src/codegen-aarch64.C b/dyninstAPI/src/codegen-aarch64.C index b9159326ea..f8b875e49f 100644 --- a/dyninstAPI/src/codegen-aarch64.C +++ b/dyninstAPI/src/codegen-aarch64.C @@ -624,14 +624,6 @@ void insnCodeGen::generateNOOP(codeGen &gen, unsigned size) { } } -void insnCodeGen::generateSimple(codeGen &, int, - Register, Register, - Register) -{ -assert(0); -//#warning "This function is not implemented yet!" -} - void insnCodeGen::generateRelOp(codeGen &, int, int, Register, Register, Register) { diff --git a/dyninstAPI/src/codegen-aarch64.h b/dyninstAPI/src/codegen-aarch64.h index b3a42cf063..e82a9b7d44 100644 --- a/dyninstAPI/src/codegen-aarch64.h +++ b/dyninstAPI/src/codegen-aarch64.h @@ -141,10 +141,6 @@ class insnCodeGen { static void generateRShift64(codeGen &gen, Register rs, int shift, Register ra); - static void generateSimple(codeGen &gen, - int op, Register src1, - Register src2, Register dest); - static void generateRelOp(codeGen &gen, int cond, int mode, Register rs1, Register rs2, Register rd); diff --git a/dyninstAPI/src/codegen-power.C b/dyninstAPI/src/codegen-power.C index fd1e3d8812..b20864fd07 100644 --- a/dyninstAPI/src/codegen-power.C +++ b/dyninstAPI/src/codegen-power.C @@ -941,41 +941,6 @@ void insnCodeGen::generateNOOP(codeGen &gen, unsigned size) } } -void insnCodeGen::generateSimple(codeGen &gen, int op, - Register src1, Register src2, - Register dest) -{ - instruction insn; - - int xop=-1; - insn.clear(); - XFORM_OP_SET(insn, op); - XFORM_RT_SET(insn, src1); - XFORM_RA_SET(insn, dest); - XFORM_RB_SET(insn, src2); - if (op==ANDop) { - xop=ANDxop; - /* - * FIXME: The "else if" condition and code below are commented out to remove - * a duplicate branch condition as both ANDop and ORop have the same value. - * This implies that the assignment in this branch is never executed. - * Further tests to distinguish between the AND and OR op are needed or this - * code should be eliminated - * - - } else if (op==ORop) { - xop=ORxop; - - * - */ - } else { - // only AND and OR are currently designed to use genSimpleInsn - assert(0); - } - XFORM_XO_SET(insn, xop); - insnCodeGen::generate(gen,insn); -} - void insnCodeGen::generateRelOp(codeGen &gen, int cond, int mode, Register rs1, Register rs2, Register rd, bool s) { diff --git a/dyninstAPI/src/codegen-power.h b/dyninstAPI/src/codegen-power.h index 2465e725ee..72a23629c8 100644 --- a/dyninstAPI/src/codegen-power.h +++ b/dyninstAPI/src/codegen-power.h @@ -93,9 +93,6 @@ class insnCodeGen { int shift, Register ra, bool s); static void generateNOOP(codeGen &gen, unsigned size = 4); - static void generateSimple(codeGen &gen, - int op, Register src1, - Register src2, Register dest); static void generateRelOp(codeGen &gen, int cond, int mode, Register rs1, Register rs2, Register rd, bool s); From 2e47a639674799483044fc5c2c1d67e3a07d669c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 26 Oct 2021 10:01:14 -0500 Subject: [PATCH 015/505] Remove NO_INITIALIZER_LIST_SUPPORT (#1125) Fixes #1124 Co-authored-by: Tim Haines --- dataflowAPI/src/RegisterMap.C | 737 ---------------------------------- 1 file changed, 737 deletions(-) diff --git a/dataflowAPI/src/RegisterMap.C b/dataflowAPI/src/RegisterMap.C index 90a192056b..c55de1f49c 100644 --- a/dataflowAPI/src/RegisterMap.C +++ b/dataflowAPI/src/RegisterMap.C @@ -29,11 +29,6 @@ */ #include "dataflowAPI/src/RegisterMap.h" -#include -#include -#include - -using namespace boost::assign; // We use the singleton approach, rather than static construction, to ensure the // register maps are created correctly. In at least one case (Ubuntu 12.04) they @@ -42,11 +37,6 @@ using namespace boost::assign; namespace Dyninst { namespace DataflowAPI { -#if !defined(NO_INITIALIZER_LIST_SUPPORT) && (!defined(os_windows) || _MSC_VER >= 1900) - // This doesn't fail on VS 2015, but may fail on other versions post 2010. - // This fails on VS2010; revisit when we move to VS2012. - // Also on gcc 4.3. - RegisterMap &machRegIndex_x86() { static dyn_tls RegisterMap* mrmap = NULL; if (mrmap == NULL) { @@ -867,732 +857,5 @@ RegisterMap &machRegIndex_aarch64() { return *mrmap; } -#else - // This fails on VS 2015... but not VS 2010... -RegisterMap &machRegIndex_x86() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (x86::eax, 0) - (x86::ecx, 1) - (x86::edx, 2) - (x86::ebx, 3) - (x86::esp, 4) - (x86::ebp, 5) - (x86::esi, 6) - (x86::edi, 7) - (x86::eip, 8) - (x86::cf, 9) - (x86::flag1, 10) - (x86::pf, 11) - (x86::flag3, 12) - (x86::af, 13) - (x86::flag5, 14) - (x86::zf, 15) - (x86::sf, 16) - (x86::tf, 17) - (x86::if_, 18) - (x86::df, 19) - (x86::of, 20) - (x86::flagc, 21) - (x86::flagd, 22) - (x86::nt_, 23) - (x86::flagf, 24) - (x86::rf, 25) - (x86::ds, 26) - (x86::es, 27) - (x86::fs, 28) - (x86::gs, 29) - (x86::cs, 30) - (x86::ss, 31) - (x86::oeax, 32) - (x86::fsbase, 33) - (x86::gsbase, 34) - (x86::xmm0, 35) - (x86::xmm1, 36) - (x86::xmm2, 37) - (x86::xmm3, 38) - (x86::xmm4, 39) - (x86::xmm5, 40) - (x86::xmm6, 41) - (x86::xmm7, 42) - (x86::mm0, 43) // mm0 to mm7 and st0 to st7 collapse to mm0 - (x86::cr0, 44) - (x86::cr1, 45) - (x86::cr2, 46) - (x86::cr3, 47) - (x86::cr4, 48) - (x86::cr5, 49) - (x86::cr6, 50) - (x86::cr7, 51) - (x86::dr0, 52) - (x86::dr1, 53) - (x86::dr2, 54) - (x86::dr3, 55) - (x86::dr4, 56) - (x86::dr5, 57) - (x86::dr6, 58) - (x86::dr7, 59) - (x86::tr0, 60) - (x86::tr1, 61) - (x86::tr2, 62) - (x86::tr3, 63) - (x86::tr4, 64) - (x86::tr5, 65) - (x86::tr6, 66) - (x86::tr7, 67); - } - return *mrmap; -} - -RegisterMap &machRegIndex_x86_64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (x86_64::rax, 0) - (x86_64::rcx, 1) - (x86_64::rdx, 2) - (x86_64::rbx, 3) - (x86_64::rsp, 4) - (x86_64::rbp, 5) - (x86_64::rsi, 6) - (x86_64::rdi, 7) - (x86_64::r8, 8) - (x86_64::r9, 9) - (x86_64::r10, 10) - (x86_64::r11, 11) - (x86_64::r12, 12) - (x86_64::r13, 13) - (x86_64::r14, 14) - (x86_64::r15, 15) - (x86_64::rip, 16) - (x86_64::cf, 17) - (x86_64::pf, 18) - (x86_64::af, 19) - (x86_64::zf, 20) - (x86_64::sf, 21) - (x86_64::tf, 22) - (x86_64::if_, 23) - (x86_64::df, 24) - (x86_64::of, 25) - (x86_64::nt_, 26) - (x86_64::rf, 27) - (x86_64::ds, 28) - (x86_64::es, 29) - (x86_64::fs, 30) - (x86_64::gs, 31) - (x86_64::cs, 32) - (x86_64::ss, 33) - (x86_64::orax, 34) - (x86_64::fsbase, 35) - (x86_64::gsbase, 36) - (x86_64::k0, 37) - (x86_64::k1, 38) - (x86_64::k2, 39) - (x86_64::k3, 40) - (x86_64::k4, 41) - (x86_64::k5, 42) - (x86_64::k6, 43) - (x86_64::k7, 44) - (x86_64::zmm0, 45) - (x86_64::zmm1, 46) - (x86_64::zmm2, 47) - (x86_64::zmm3, 48) - (x86_64::zmm4, 49) - (x86_64::zmm5, 50) - (x86_64::zmm6, 51) - (x86_64::zmm7, 52) - (x86_64::zmm8, 53) - (x86_64::zmm9, 54) - (x86_64::zmm10, 55) - (x86_64::zmm11, 56) - (x86_64::zmm12, 57) - (x86_64::zmm13, 58) - (x86_64::zmm14, 59) - (x86_64::zmm15, 60) - (x86_64::zmm16, 61) - (x86_64::zmm17, 62) - (x86_64::zmm18, 63) - (x86_64::zmm19, 64) - (x86_64::zmm20, 65) - (x86_64::zmm21, 66) - (x86_64::zmm22, 67) - (x86_64::zmm23, 68) - (x86_64::zmm24, 69) - (x86_64::zmm25, 70) - (x86_64::zmm26, 71) - (x86_64::zmm27, 72) - (x86_64::zmm28, 73) - (x86_64::zmm29, 74) - (x86_64::zmm30, 75) - (x86_64::zmm31, 75) - (x86_64::ymm0, 76) - (x86_64::ymm1, 77) - (x86_64::ymm2, 78) - (x86_64::ymm3, 79) - (x86_64::ymm4, 80) - (x86_64::ymm5, 81) - (x86_64::ymm6, 82) - (x86_64::ymm7, 83) - (x86_64::ymm8, 84) - (x86_64::ymm9, 85) - (x86_64::ymm10, 86) - (x86_64::ymm11, 87) - (x86_64::ymm12, 88) - (x86_64::ymm13, 89) - (x86_64::ymm14, 90) - (x86_64::ymm15, 91) - (x86_64::ymm16, 92) - (x86_64::ymm17, 93) - (x86_64::ymm18, 94) - (x86_64::ymm19, 95) - (x86_64::ymm20, 96) - (x86_64::ymm21, 97) - (x86_64::ymm22, 98) - (x86_64::ymm23, 99) - (x86_64::ymm24, 100) - (x86_64::ymm25, 101) - (x86_64::ymm26, 102) - (x86_64::ymm27, 103) - (x86_64::ymm28, 104) - (x86_64::ymm29, 105) - (x86_64::ymm30, 106) - (x86_64::ymm31, 107) - (x86_64::xmm0, 108) - (x86_64::xmm1, 109) - (x86_64::xmm2, 110) - (x86_64::xmm3, 111) - (x86_64::xmm4, 112) - (x86_64::xmm5, 113) - (x86_64::xmm6, 114) - (x86_64::xmm7, 115) - (x86_64::xmm8, 116) - (x86_64::xmm9, 117) - (x86_64::xmm10, 118) - (x86_64::xmm11, 119) - (x86_64::xmm12, 120) - (x86_64::xmm13, 121) - (x86_64::xmm14, 122) - (x86_64::xmm15, 123) - (x86_64::xmm16, 124) - (x86_64::xmm17, 125) - (x86_64::xmm18, 126) - (x86_64::xmm19, 127) - (x86_64::xmm20, 128) - (x86_64::xmm21, 129) - (x86_64::xmm22, 130) - (x86_64::xmm23, 131) - (x86_64::xmm24, 132) - (x86_64::xmm25, 133) - (x86_64::xmm26, 134) - (x86_64::xmm27, 135) - (x86_64::xmm28, 136) - (x86_64::xmm29, 137) - (x86_64::xmm30, 138) - (x86_64::xmm31, 139) - (x86_64::mm0, 140) // mm0 to mm7 and st0 to st7 collapse to mm0 - (x86_64::cr0, 141) - (x86_64::cr1, 142) - (x86_64::cr2, 143) - (x86_64::cr3, 144) - (x86_64::cr4, 145) - (x86_64::cr5, 146) - (x86_64::cr6, 147) - (x86_64::cr7, 148) - (x86_64::dr0, 149) - (x86_64::dr1, 150) - (x86_64::dr2, 151) - (x86_64::dr3, 152) - (x86_64::dr4, 153) - (x86_64::dr5, 154) - (x86_64::dr6, 155) - (x86_64::dr7, 156) - (x86_64::tr0, 157) - (x86_64::tr1, 158) - (x86_64::tr2, 159) - (x86_64::tr3, 160) - (x86_64::tr4, 161) - (x86_64::tr5, 162) - (x86_64::tr6, 163) - (x86_64::tr7, 164) - ; - } - return *mrmap; -} - -RegisterMap &machRegIndex_ppc() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (ppc32::r0, 0) - (ppc32::r1, 1) - (ppc32::r2, 2) - (ppc32::r3, 3) - (ppc32::r4, 4) - (ppc32::r5, 5) - (ppc32::r6, 6) - (ppc32::r7, 7) - (ppc32::r8, 8) - (ppc32::r9, 9) - (ppc32::r10, 10) - (ppc32::r11, 11) - (ppc32::r12, 12) - (ppc32::r13, 13) - (ppc32::r14, 14) - (ppc32::r15, 15) - (ppc32::r16, 16) - (ppc32::r17, 17) - (ppc32::r18, 18) - (ppc32::r19, 19) - (ppc32::r20, 20) - (ppc32::r21, 21) - (ppc32::r22, 22) - (ppc32::r23, 23) - (ppc32::r24, 24) - (ppc32::r25, 25) - (ppc32::r26, 26) - (ppc32::r27, 27) - (ppc32::r28, 28) - (ppc32::r29, 29) - (ppc32::r30, 30) - (ppc32::r31, 31) - (ppc32::fpr0, 32) - (ppc32::fpr1, 33) - (ppc32::fpr2, 34) - (ppc32::fpr3, 35) - (ppc32::fpr4, 36) - (ppc32::fpr5, 37) - (ppc32::fpr6, 38) - (ppc32::fpr7, 39) - (ppc32::fpr8, 40) - (ppc32::fpr9, 41) - (ppc32::fpr10, 42) - (ppc32::fpr11, 43) - (ppc32::fpr12, 44) - (ppc32::fpr13, 45) - (ppc32::fpr14, 46) - (ppc32::fpr15, 47) - (ppc32::fpr16, 48) - (ppc32::fpr17, 49) - (ppc32::fpr18, 50) - (ppc32::fpr19, 51) - (ppc32::fpr20, 52) - (ppc32::fpr21, 53) - (ppc32::fpr22, 54) - (ppc32::fpr23, 55) - (ppc32::fpr24, 56) - (ppc32::fpr25, 57) - (ppc32::fpr26, 58) - (ppc32::fpr27, 59) - (ppc32::fpr28, 60) - (ppc32::fpr29, 61) - (ppc32::fpr30, 62) - (ppc32::fpr31, 63) - (ppc32::fsr0, 64) - (ppc32::fsr1, 65) - (ppc32::fsr2, 66) - (ppc32::fsr3, 67) - (ppc32::fsr4, 68) - (ppc32::fsr5, 69) - (ppc32::fsr6, 70) - (ppc32::fsr7, 71) - (ppc32::fsr8, 72) - (ppc32::fsr9, 73) - (ppc32::fsr10, 74) - (ppc32::fsr11, 75) - (ppc32::fsr12, 76) - (ppc32::fsr13, 77) - (ppc32::fsr14, 78) - (ppc32::fsr15, 79) - (ppc32::fsr16, 80) - (ppc32::fsr17, 81) - (ppc32::fsr18, 82) - (ppc32::fsr19, 83) - (ppc32::fsr20, 84) - (ppc32::fsr21, 85) - (ppc32::fsr22, 86) - (ppc32::fsr23, 87) - (ppc32::fsr24, 88) - (ppc32::fsr25, 89) - (ppc32::fsr26, 90) - (ppc32::fsr27, 91) - (ppc32::fsr28, 92) - (ppc32::fsr29, 93) - (ppc32::fsr30, 94) - (ppc32::fsr31, 95) - (ppc32::mq, 96) - (ppc32::xer, 97) - (ppc32::lr, 98) - (ppc32::ctr, 99) - (ppc32::dsisr, 100) - (ppc32::dar, 101) - (ppc32::dec, 102) - (ppc32::sdr1, 103) - (ppc32::srr0, 104) - (ppc32::srr1, 105) - (ppc32::sprg0, 106) - (ppc32::sprg1, 107) - (ppc32::sprg2, 108) - (ppc32::sprg3, 109) - (ppc32::sprg3_ro, 109) - (ppc32::ear, 110) - (ppc32::tbl_wo, 111) - (ppc32::tbl_ro, 111) - (ppc32::tbu_wo, 112) - (ppc32::tbu_ro, 112) - (ppc32::pvr, 113) - (ppc32::ibat0u, 114) - (ppc32::ibat0l, 115) - (ppc32::ibat1u, 116) - (ppc32::ibat1l, 117) - (ppc32::ibat2u, 118) - (ppc32::ibat2l, 119) - (ppc32::ibat3u, 120) - (ppc32::ibat3l, 121) - (ppc32::dbat0u, 122) - (ppc32::dbat0l, 123) - (ppc32::dbat1u, 124) - (ppc32::dbat1l, 125) - (ppc32::dbat2u, 126) - (ppc32::dbat2l, 127) - (ppc32::dbat3u, 128) - (ppc32::dbat3l, 129) - (ppc32::pc, 130) - (ppc32::fpscw, 131) - (ppc32::fpscw0, 132) - (ppc32::fpscw1, 133) - (ppc32::fpscw2, 134) - (ppc32::fpscw3, 135) - (ppc32::fpscw4, 136) - (ppc32::fpscw5, 137) - (ppc32::fpscw6, 138) - (ppc32::fpscw7, 139) - (ppc32::msr, 140) - (ppc32::ivpr, 141) - (ppc32::ivor8, 142) - (ppc32::seg0, 143) - (ppc32::seg1, 144) - (ppc32::seg2, 145) - (ppc32::seg3, 146) - (ppc32::seg4, 147) - (ppc32::seg5, 148) - (ppc32::seg6, 149) - (ppc32::seg7, 150) - (ppc32::cr0, 151) - (ppc32::cr1, 152) - (ppc32::cr2, 153) - (ppc32::cr3, 154) - (ppc32::cr4, 155) - (ppc32::cr5, 156) - (ppc32::cr6, 157) - (ppc32::cr7, 158) - (ppc32::cr, 159) - (ppc32::sprg4, 160) - (ppc32::sprg4_ro, 160) - (ppc32::sprg5, 161) - (ppc32::sprg5_ro, 161) - (ppc32::sprg6, 162) - (ppc32::sprg6_ro, 162) - (ppc32::sprg7, 163) - (ppc32::sprg7_ro, 163); - } - return *mrmap; -} - -RegisterMap &machRegIndex_ppc_64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (ppc64::r0, 0) - (ppc64::r1, 1) - (ppc64::r2, 2) - (ppc64::r3, 3) - (ppc64::r4, 4) - (ppc64::r5, 5) - (ppc64::r6, 6) - (ppc64::r7, 7) - (ppc64::r8, 8) - (ppc64::r9, 9) - (ppc64::r10, 10) - (ppc64::r11, 11) - (ppc64::r12, 12) - (ppc64::r13, 13) - (ppc64::r14, 14) - (ppc64::r15, 15) - (ppc64::r16, 16) - (ppc64::r17, 17) - (ppc64::r18, 18) - (ppc64::r19, 19) - (ppc64::r20, 20) - (ppc64::r21, 21) - (ppc64::r22, 22) - (ppc64::r23, 23) - (ppc64::r24, 24) - (ppc64::r25, 25) - (ppc64::r26, 26) - (ppc64::r27, 27) - (ppc64::r28, 28) - (ppc64::r29, 29) - (ppc64::r30, 30) - (ppc64::r31, 31) - (ppc64::fpr0, 32) - (ppc64::fpr1, 33) - (ppc64::fpr2, 34) - (ppc64::fpr3, 35) - (ppc64::fpr4, 36) - (ppc64::fpr5, 37) - (ppc64::fpr6, 38) - (ppc64::fpr7, 39) - (ppc64::fpr8, 40) - (ppc64::fpr9, 41) - (ppc64::fpr10, 42) - (ppc64::fpr11, 43) - (ppc64::fpr12, 44) - (ppc64::fpr13, 45) - (ppc64::fpr14, 46) - (ppc64::fpr15, 47) - (ppc64::fpr16, 48) - (ppc64::fpr17, 49) - (ppc64::fpr18, 50) - (ppc64::fpr19, 51) - (ppc64::fpr20, 52) - (ppc64::fpr21, 53) - (ppc64::fpr22, 54) - (ppc64::fpr23, 55) - (ppc64::fpr24, 56) - (ppc64::fpr25, 57) - (ppc64::fpr26, 58) - (ppc64::fpr27, 59) - (ppc64::fpr28, 60) - (ppc64::fpr29, 61) - (ppc64::fpr30, 62) - (ppc64::fpr31, 63) - (ppc64::fsr0, 64) - (ppc64::fsr1, 65) - (ppc64::fsr2, 66) - (ppc64::fsr3, 67) - (ppc64::fsr4, 68) - (ppc64::fsr5, 69) - (ppc64::fsr6, 70) - (ppc64::fsr7, 71) - (ppc64::fsr8, 72) - (ppc64::fsr9, 73) - (ppc64::fsr10, 74) - (ppc64::fsr11, 75) - (ppc64::fsr12, 76) - (ppc64::fsr13, 77) - (ppc64::fsr14, 78) - (ppc64::fsr15, 79) - (ppc64::fsr16, 80) - (ppc64::fsr17, 81) - (ppc64::fsr18, 82) - (ppc64::fsr19, 83) - (ppc64::fsr20, 84) - (ppc64::fsr21, 85) - (ppc64::fsr22, 86) - (ppc64::fsr23, 87) - (ppc64::fsr24, 88) - (ppc64::fsr25, 89) - (ppc64::fsr26, 90) - (ppc64::fsr27, 91) - (ppc64::fsr28, 92) - (ppc64::fsr29, 93) - (ppc64::fsr30, 94) - (ppc64::fsr31, 95) - (ppc64::mq, 96) - (ppc64::xer, 97) - (ppc64::lr, 98) - (ppc64::ctr, 99) - (ppc64::dsisr, 100) - (ppc64::dar, 101) - (ppc64::dec, 102) - (ppc64::sdr1, 103) - (ppc64::srr0, 104) - (ppc64::srr1, 105) - (ppc64::sprg0, 106) - (ppc64::sprg1, 107) - (ppc64::sprg2, 108) - (ppc64::sprg3, 109) - (ppc64::sprg3_ro, 109) - (ppc64::ear, 110) - (ppc64::tbl_wo, 111) - (ppc64::tbl_ro, 111) - (ppc64::tbu_wo, 112) - (ppc64::tbu_ro, 112) - (ppc64::pvr, 113) - (ppc64::ibat0u, 114) - (ppc64::ibat0l, 115) - (ppc64::ibat1u, 116) - (ppc64::ibat1l, 117) - (ppc64::ibat2u, 118) - (ppc64::ibat2l, 119) - (ppc64::ibat3u, 120) - (ppc64::ibat3l, 121) - (ppc64::dbat0u, 122) - (ppc64::dbat0l, 123) - (ppc64::dbat1u, 124) - (ppc64::dbat1l, 125) - (ppc64::dbat2u, 126) - (ppc64::dbat2l, 127) - (ppc64::dbat3u, 128) - (ppc64::dbat3l, 129) - (ppc64::pc, 130) - (ppc64::fpscw, 131) - (ppc64::fpscw0, 132) - (ppc64::fpscw1, 133) - (ppc64::fpscw2, 134) - (ppc64::fpscw3, 135) - (ppc64::fpscw4, 136) - (ppc64::fpscw5, 137) - (ppc64::fpscw6, 138) - (ppc64::fpscw7, 139) - (ppc64::msr, 140) - (ppc64::ivpr, 141) - (ppc64::ivor8, 142) - (ppc64::seg0, 143) - (ppc64::seg1, 144) - (ppc64::seg2, 145) - (ppc64::seg3, 146) - (ppc64::seg4, 147) - (ppc64::seg5, 148) - (ppc64::seg6, 149) - (ppc64::seg7, 150) - (ppc64::cr0, 151) - (ppc64::cr1, 152) - (ppc64::cr2, 153) - (ppc64::cr3, 154) - (ppc64::cr4, 155) - (ppc64::cr5, 156) - (ppc64::cr6, 157) - (ppc64::cr7, 158) - (ppc64::cr, 159) - (ppc64::sprg4, 160) - (ppc64::sprg4_ro, 160) - (ppc64::sprg5, 161) - (ppc64::sprg5_ro, 161) - (ppc64::sprg6, 162) - (ppc64::sprg6_ro, 162) - (ppc64::sprg7, 163) - (ppc64::sprg7_ro, 163); - } - return *mrmap; -} - -RegisterMap &machRegIndex_aarch64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (aarch64::x0, 0) - (aarch64::x1, 1) - (aarch64::x2, 2) - (aarch64::x3, 3) - (aarch64::x4, 4) - (aarch64::x5, 5) - (aarch64::x6, 6) - (aarch64::x7, 7) - (aarch64::x8, 8) - (aarch64::x9, 9) - (aarch64::x10, 10) - (aarch64::x11, 11) - (aarch64::x12, 12) - (aarch64::x13, 13) - (aarch64::x14, 14) - (aarch64::x15, 15) - (aarch64::x16, 16) - (aarch64::x17, 17) - (aarch64::x18, 18) - (aarch64::x19, 19) - (aarch64::x20, 20) - (aarch64::x21, 21) - (aarch64::x22, 22) - (aarch64::x23, 23) - (aarch64::x24, 24) - (aarch64::x25, 25) - (aarch64::x26, 26) - (aarch64::x27, 27) - (aarch64::x28, 28) - (aarch64::x29, 29) - (aarch64::x30, 30) - (aarch64::w0, 0) - (aarch64::w1, 1) - (aarch64::w2, 2) - (aarch64::w3, 3) - (aarch64::w4, 4) - (aarch64::w5, 5) - (aarch64::w6, 6) - (aarch64::w7, 7) - (aarch64::w8, 8) - (aarch64::w9, 9) - (aarch64::w10, 10) - (aarch64::w11, 11) - (aarch64::w12, 12) - (aarch64::w13, 13) - (aarch64::w14, 14) - (aarch64::w15, 15) - (aarch64::w16, 16) - (aarch64::w17, 17) - (aarch64::w18, 18) - (aarch64::w19, 19) - (aarch64::w20, 20) - (aarch64::w21, 21) - (aarch64::w22, 22) - (aarch64::w23, 23) - (aarch64::w24, 24) - (aarch64::w25, 25) - (aarch64::w26, 26) - (aarch64::w27, 27) - (aarch64::w28, 28) - (aarch64::w29, 29) - (aarch64::w30, 30) - (aarch64::q0, 31) - (aarch64::q1, 32) - (aarch64::q2, 33) - (aarch64::q3, 34) - (aarch64::q4, 35) - (aarch64::q5, 36) - (aarch64::q6, 37) - (aarch64::q7, 38) - (aarch64::q8, 39) - (aarch64::q9, 40) - (aarch64::q10, 41) - (aarch64::q11, 42) - (aarch64::q12, 43) - (aarch64::q13, 44) - (aarch64::q14, 45) - (aarch64::q15, 46) - (aarch64::q16, 47) - (aarch64::q17, 48) - (aarch64::q18, 49) - (aarch64::q19, 50) - (aarch64::q20, 51) - (aarch64::q21, 52) - (aarch64::q22, 53) - (aarch64::q23, 54) - (aarch64::q24, 55) - (aarch64::q25, 56) - (aarch64::q26, 57) - (aarch64::q27, 58) - (aarch64::q28, 59) - (aarch64::q29, 60) - (aarch64::q30, 61) - (aarch64::q31, 62) - (aarch64::fpcr,63) - (aarch64::fpsr,64) - (aarch64::pc, 65) - (aarch64::sp, 66) - (aarch64::pstate, 67) - (aarch64::xzr, 68); - } - - return mrmap; -} - -#endif - }; }; From c25d094541220cccc8eeb1ef1de1f985e5ff643a Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 26 Oct 2021 10:24:05 -0500 Subject: [PATCH 016/505] Remove DynC tests (#1126) These have been moved to the examples repository. https://github.com/dyninst/examples/pull/25 Co-authored-by: Tim Haines --- dynC_API/make.test.module.tmpl | 39 --- dynC_API/tests/i386-unknown-linux2.4/Makefile | 36 --- dynC_API/tests/i386-unknown-nt4.0/Makefile | 36 --- dynC_API/tests/i386-unknown-winXP/Makefile | 36 --- dynC_API/tests/ppc32_linux/Makefile | 36 --- dynC_API/tests/ppc64_linux/Makefile | 36 --- dynC_API/tests/testMutatee.cpp | 62 ----- dynC_API/tests/testMutator.cpp | 135 ---------- dynC_API/tests/testStatements | 1 - dynC_API/tests/testStatements2 | 1 - dynC_API/tests/testStatements3 | 5 - .../tests/x86_64-unknown-linux2.4/Makefile | 36 --- .../tests/x86_64-unknown-linux2.4/foo.txt | 254 ------------------ 13 files changed, 713 deletions(-) delete mode 100644 dynC_API/make.test.module.tmpl delete mode 100644 dynC_API/tests/i386-unknown-linux2.4/Makefile delete mode 100644 dynC_API/tests/i386-unknown-nt4.0/Makefile delete mode 100644 dynC_API/tests/i386-unknown-winXP/Makefile delete mode 100644 dynC_API/tests/ppc32_linux/Makefile delete mode 100644 dynC_API/tests/ppc64_linux/Makefile delete mode 100644 dynC_API/tests/testMutatee.cpp delete mode 100644 dynC_API/tests/testMutator.cpp delete mode 100644 dynC_API/tests/testStatements delete mode 100644 dynC_API/tests/testStatements2 delete mode 100644 dynC_API/tests/testStatements3 delete mode 100644 dynC_API/tests/x86_64-unknown-linux2.4/Makefile delete mode 100644 dynC_API/tests/x86_64-unknown-linux2.4/foo.txt diff --git a/dynC_API/make.test.module.tmpl b/dynC_API/make.test.module.tmpl deleted file mode 100644 index fc4e2fa4e0..0000000000 --- a/dynC_API/make.test.module.tmpl +++ /dev/null @@ -1,39 +0,0 @@ -# -# Common makefile template for dyninst Tests. This file is not intended to -# be a useful Makefile in isolation; instead, it should be included -# from within an architecture-specific Makefile. -# -# $Id: make.module.tmpl,v 1.26 2008/02/20 08:31:02 jaw Exp $ -# - -SUITE_NAME = DynC -RELEASE_NUM = 5.00 -#BUILD_MARK should be (re-)defined in core/make.config.local rather than here! - -SRCS += ../$(TARGET).C - -IFLAGS += -I$(TO_CORE)/dyninstAPI/h -IFLAGS += -I$(TO_CORE)/dyninstAPI/src -IFLAGS += -I$(TO_CORE)/symtabAPI/h -IFLAGS += -I$(TO_CORE)/dynutil/h -IFLAGS += -I$(TO_CORE)/commandAPI/h -IFLAGS += -I$(TO_CORE)/commandAPI/src -IFLAGS += -I$(TO_CORE)/instructionAPI/h - -CXXFLAGS += $(BASICWARNINGS) -CFLAGS += $(BASICWARNINGS) - -# GCC has a new mangled name squisher (-fsquangle) which can be -# set to "on" by default. This causes linker problems, so we -# default to "off". - -ifdef GCC_2_95 -CFLAGS += -fno-squangle -CXXFLAGS += -fno-squangle -endif - -LIBS += -ldyninstAPI -lsymtabAPI -lcommon -L$(TO_CORE)/dynCAPI/$(PLATFORM) -ldynCAPI - -SYSLIBS += -liberty -L$(TCLTK_LIB_DIR) $(TCL_LIB) - -all: $(TARGET) diff --git a/dynC_API/tests/i386-unknown-linux2.4/Makefile b/dynC_API/tests/i386-unknown-linux2.4/Makefile deleted file mode 100644 index 53a2265345..0000000000 --- a/dynC_API/tests/i386-unknown-linux2.4/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-linux2.4 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/i386-unknown-nt4.0/Makefile b/dynC_API/tests/i386-unknown-nt4.0/Makefile deleted file mode 100644 index 10089ddf72..0000000000 --- a/dynC_API/tests/i386-unknown-nt4.0/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-nt4.0 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/i386-unknown-winXP/Makefile b/dynC_API/tests/i386-unknown-winXP/Makefile deleted file mode 100644 index 170bbf90cd..0000000000 --- a/dynC_API/tests/i386-unknown-winXP/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-winXP -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/ppc32_linux/Makefile b/dynC_API/tests/ppc32_linux/Makefile deleted file mode 100644 index a7d3dd643f..0000000000 --- a/dynC_API/tests/ppc32_linux/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = ppc32_linux -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/ppc64_linux/Makefile b/dynC_API/tests/ppc64_linux/Makefile deleted file mode 100644 index 02317ead95..0000000000 --- a/dynC_API/tests/ppc64_linux/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = ppc64_linux -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/testMutatee.cpp b/dynC_API/tests/testMutatee.cpp deleted file mode 100644 index 9183caa087..0000000000 --- a/dynC_API/tests/testMutatee.cpp +++ /dev/null @@ -1,62 +0,0 @@ -// myMutatee - -#include -int hi = 0; -int zarray[0]; -int array[5] = {1,2,3,4,5}; -int array2[5] = {6, 7, 8, 9, 10}; -int arrayField = array[2]; -struct myStructType{ - int i; - char *s; - char *sa[4]; -}mystruct = {3, "house", {"how", "now", "brown", "cow"}}; -//int i = 232; -int count(int i); - -int zomg = 2; - -int main(){ - - int i = 0; - int r = 0; - while (i < 10){ - i = count(i); - ++hi; - r = hi * 10; - } - return 0; -} - -void hello(){ -/* - using std::cout; - using std::endl; - cout << "hello!" << endl; -*/ -} - -int count(int i) { - using std::cout; - using std::endl; - if(i % 2 == 0){hello();} -// cout << "The current count is " << i << endl; - array[i % 5]++; - return i + 1; -} - -int count(int i, char *n){ - printf(n); - return i + 1; -} - -int printfWrapper(char *s){ - printf(s); - return 1; -} - -int count(char *s){ - printf("%s\n",s); - return 1; -} - diff --git a/dynC_API/tests/testMutator.cpp b/dynC_API/tests/testMutator.cpp deleted file mode 100644 index baf3017780..0000000000 --- a/dynC_API/tests/testMutator.cpp +++ /dev/null @@ -1,135 +0,0 @@ -//tester.C -#include -#include -#include - -#include "dynC.h" -#include "BPatch.h" -#include "BPatch_process.h" -#include "BPatch_snippet.h" -#include "BPatch_function.h" - -#define STATEMENT_PATH "../testStatements" -#define STATEMENT_PATH_2 "../testStatements2" -const char *MUTATEE_PATH = "myMutatee"; -const char *MUTATEE_ARGS[3]; -const char *MODULE_NAME = "testMutatee.cpp"; - - -BPatch bpatch; - -int main(){ - - using std::string; - using std::ifstream; - using std::cout; - using std::endl; - using std::getline; - - ifstream myfile(STATEMENT_PATH); - ifstream myfile2(STATEMENT_PATH_2); - - FILE *myCFILE = fopen(STATEMENT_PATH, "r"); - -// cout << "Starting binary " << MUTATEE_PATH << "... "; - BPatch_addressSpace * appProc; - bool rewrite = false; - if(rewrite){ - appProc = bpatch.openBinary(MUTATEE_PATH, true); - }else{ - appProc = bpatch.processCreate(MUTATEE_PATH, MUTATEE_ARGS); - } -// cout << "complete" << endl; - if (!appProc) return -1; - - BPatch_image *appImage = appProc->getImage(); - BPatch_module *mutatee = appImage->findModule(MODULE_NAME); - - if (mutatee == NULL){cout << "Bad Mutatee!" << endl;} - - const std::vector * functions = mutatee->getProcedures(); - - - appProc->malloc(*appImage->findType("long"), std::string("globalVar")); - - - std::vector * entry_points = (*functions)[0]->findPoint(BPatch_entry); - std::vector * exit_points = (*functions)[0]->findPoint(BPatch_exit);; - - for(unsigned int n = 1; n < functions->size(); n++){ - entry_points->push_back((*(*functions)[n]->findPoint(BPatch_entry))[0]); - exit_points->push_back((*(*functions)[n]->findPoint(BPatch_exit))[0]); - } - - -///////////////////////////////////////////////////////// - std::map *entry_snippets, exit_snippets; - entry_snippets = dynC_API::createSnippet(myCFILE, *entry_points); -// BPatch_snippet *testSn = dynC_API::createSnippet(fileString, *(*entry_points)[0]); - if(entry_snippets == NULL){ - fprintf(stderr, "entry_snippets is null.\n"); - exit(-1); - } - std::map::iterator it; - for(it = entry_snippets->begin(); it != entry_snippets->end(); ++it){ - if((*it).first == NULL){ - fprintf(stderr, "point is null.\n"); - exit(-1); - } - if((*it).second == NULL){ - fprintf(stderr, "snippet is null.\n"); - } else{ - printf("Snippet inserted\n"); - char funcName[512]; - printf("Point's function is %s.\n",((*it).first)->getFunction()->getName(funcName, 512)); - BPatchSnippetHandle *handle = appProc->insertSnippet(*(*it).second, *(*it).first); - printf("Handle is %s.\n", handle == NULL ? "null": "not null"); - } - } - -/* - for(unsigned int i = 0; i < entry_points->size(); ++i){ - if((*entry_points)[i] == NULL){ - printf("entry point %d is null \n", i); - } - BPatch_snippet *entrySnippet = dynC_API::createSnippet(fileString, *(*entry_points)[i]); - if (entrySnippet != NULL){ - appProc->insertSnippet(*entrySnippet, *(*entry_points)[i]); - } - BPatch_snippet *exitSnippet= dynC_API::createSnippet(fileString2.c_str(), *(*exit_points)[i], "exitSnippet"); - if (exitSnippet != NULL){ - appProc->insertSnippet(*exitSnippet, *(*exit_points)[i]); - } - -// BPatch_snippet *auxSnippet = dynC_API::createSnippet(&myfile2, "AuxSnippet"); - } -*/ -///////////////////////////////////////////////////////// - - -// appProc->insertSnippet(*auxSnippet, *exit_points); - - - printf("Snippet's inserted!\n"); - if(!rewrite){ - BPatch_process *aProc = static_cast(appProc); - aProc->continueExecution(); - - while (!aProc->isTerminated()){ - bpatch.waitForStatusChange(); - } - - if (aProc->terminationStatus() == ExitedNormally) { - printf("Application exited with code %d\n", aProc->getExitCode()); - } else if (aProc->terminationStatus() == ExitedViaSignal) { - printf("!!! Application exited with signal %d\n", aProc->getExitSignal()); - } else { - printf("Unknown application exit\n"); - } - }else{ - BPatch_binaryEdit *aProc = static_cast(appProc); - aProc->writeFile("myMutatee.out"); - } - - return 0; -} diff --git a/dynC_API/tests/testStatements b/dynC_API/tests/testStatements deleted file mode 100644 index 34820f2997..0000000000 --- a/dynC_API/tests/testStatements +++ /dev/null @@ -1 +0,0 @@ -func`printf("Hello.\n"); diff --git a/dynC_API/tests/testStatements2 b/dynC_API/tests/testStatements2 deleted file mode 100644 index 6e80446561..0000000000 --- a/dynC_API/tests/testStatements2 +++ /dev/null @@ -1 +0,0 @@ -inf`printf("Goodbye from %s.\n", dyninst`function_name); diff --git a/dynC_API/tests/testStatements3 b/dynC_API/tests/testStatements3 deleted file mode 100644 index e9805175d8..0000000000 --- a/dynC_API/tests/testStatements3 +++ /dev/null @@ -1,5 +0,0 @@ -//welcome to testStatements3 -{% -int f; -%} -//printf("{%d, %d, %d, %d, %d}\n", array[0], array[1], array[2], array[3], array[4]); diff --git a/dynC_API/tests/x86_64-unknown-linux2.4/Makefile b/dynC_API/tests/x86_64-unknown-linux2.4/Makefile deleted file mode 100644 index 2d72069eb7..0000000000 --- a/dynC_API/tests/x86_64-unknown-linux2.4/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = x86_64-unknown-linux2.4 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt b/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt deleted file mode 100644 index a39e1b8a17..0000000000 --- a/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt +++ /dev/null @@ -1,254 +0,0 @@ -Starting binary myMutatee... complete -Entry to parseStabTypes for ld-linux-x86-64.so.2 - Parsing 0 stab entries -Entry to parseStabTypes for myMutatee - Parsing 0 stab entries -Type lookup for dynC_internal_0 returned (nil) - bpatch type is -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -Entry to parseStabTypes for libc.so.6 - Parsing 0 stab entries -Type lookup for array returned 0x1c46f4d0 - bpatch type is -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -Type lookup for hi returned 0x1bf6c160 int - bpatch type is int -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -Type lookup for dynC_mangled_i_TestSnippet_int[3]_local returned (nil) - bpatch type is -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -mangled = dynC_mangled_i_TestSnippet_int[3]_local -Array name = int -BPatch_DyninstAllocateArray: arrayName = dynC_mangled_i_TestSnippet_int[3]_local. typeName = int. size = 3. arrayTypeName = int[3]. -BPatch_variableExpr is null? no -BPatch_DyninstAllocateArray: Var type: int[3] -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstAfindOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -Welcome to testMutatee.cpp! -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -rrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -Snippet's inserted! -Application exited with code 0 From b2c892f5548ccd2a5a2ee686eef130a683191d6d Mon Sep 17 00:00:00 2001 From: Stan Cox Date: Tue, 26 Oct 2021 17:43:14 -0400 Subject: [PATCH 017/505] Load callee's address when the callee and caller are in the same module (#1056) If the callee and caller are in the same module and pic is not required then the callee's address can be loaded directly without using a relocation. --- dyninstAPI/src/inst-aarch64.C | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/dyninstAPI/src/inst-aarch64.C b/dyninstAPI/src/inst-aarch64.C index 337a666b48..a699198422 100644 --- a/dyninstAPI/src/inst-aarch64.C +++ b/dyninstAPI/src/inst-aarch64.C @@ -651,12 +651,14 @@ Register EmitterAARCH64::emitCall(opCode op, assert(gen.rs()); - //Address of function to call in scratch register + // Address of function to call in scratch register Register scratch = gen.rs()->getScratchRegister(gen); assert(scratch != REG_NULL && "cannot get a scratch register"); gen.markRegDefined(scratch); - if (gen.addrSpace()->edit() != NULL) { + if (gen.addrSpace()->edit() != NULL + && (gen.func()->obj() != callee->obj() + || gen.addrSpace()->needsPIC())) { // gen.as.edit() checks if we are in rewriter mode Address dest = getInterModuleFuncAddr(callee, gen); @@ -666,7 +668,6 @@ Register EmitterAARCH64::emitCall(opCode op, instruction insn; insn.clear(); INSN_SET(insn, 31, 31, 0); - //INSN_SET(insn, 29, 30, disp & 0x3); INSN_SET(insn, 28, 28, 1); INSN_SET(insn, 5, 23, disp >> 2); INSN_SET(insn, 0, 4, scratch); From e5484368f75397c48f8a013a49a92eb1e9556bb2 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 28 Oct 2021 16:14:01 -0500 Subject: [PATCH 018/505] Remove usage of x86_64_cnl (#1130) This was added but never used. Co-authored-by: Tim Haines --- cmake/cap_arch_def.cmake | 3 --- 1 file changed, 3 deletions(-) diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index 6e523018d4..241e68d071 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -115,9 +115,6 @@ elseif (PLATFORM STREQUAL ppc64_linux) set (OLD_DEFINES -Dppc64_linux) set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) -elseif (PLATFORM STREQUAL x86_64_cnl) -set (OLD_DEFINES -Dx86_64_cnl -Dx86_64_unknown_linux2_4) - elseif (PLATFORM STREQUAL i386-unknown-freebsd7.2) set (OLD_DEFINES -Di386_unknown_freebsd7_0) From 1ec5bf68f80a2bc67da7ded73ca2fefb26691b78 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:26:47 -0500 Subject: [PATCH 019/505] fix unused const variable warnings --- dyninstAPI/src/codegen-x86.C | 1 - parseAPI/src/IA_power.C | 30 +++++++++++++++--------------- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/dyninstAPI/src/codegen-x86.C b/dyninstAPI/src/codegen-x86.C index 55d95f8f8f..975c006424 100644 --- a/dyninstAPI/src/codegen-x86.C +++ b/dyninstAPI/src/codegen-x86.C @@ -194,7 +194,6 @@ bool convert_to_rel32(const unsigned char*&origInsn, unsigned char *&newInsn) { // We keep array-lets that represents various fixed insns. // They are larger than necessary so static analyzers don't think // they'll be read out of bounds. -static const unsigned char illegalRep[8] = {0x0f, 0x0b}; static const unsigned char trapRep[8] = {0xCC}; diff --git a/parseAPI/src/IA_power.C b/parseAPI/src/IA_power.C index 83a7415746..4614ead532 100644 --- a/parseAPI/src/IA_power.C +++ b/parseAPI/src/IA_power.C @@ -437,21 +437,6 @@ bool IA_power::isIATcall(std::string &) const return false; } -const unsigned int B_UNCOND = 0x48000000; -const unsigned int ADDIS_R12_R12 = 0x3d8c0000; -const unsigned int ADDIS_R12_R2 = 0x3d820000; -const unsigned int ADDIS_R2_R2 = 0x3c420000; -const unsigned int ADDI_R12_R12 = 0x398c0000; -const unsigned int ADDI_R2_R2 = 0x38420000; -const unsigned int STD_R2_40R1 = 0xf8410028; -const unsigned int LD_R2_40R1 = 0xe8410028; -const unsigned int LD_R2_0R2 = 0xe8420000; -const unsigned int LD_R2_0R12 = 0xe84c0000; -const unsigned int LD_R11_0R12 = 0xe96c0000; -const unsigned int LD_R11_0R2 = 0xe9620000; -const unsigned int MTCTR_R11 = 0x7d6903a6; -const unsigned int BCTR = 0x4e800420; - typedef enum { STUB_UNKNOWN, STUB_LONG_BRANCH, @@ -462,6 +447,21 @@ typedef enum { linker_stub_t checkLinkerStub(void *insn_buf, Offset &off) { #if defined(ppc64_linux) + const unsigned int B_UNCOND = 0x48000000; + const unsigned int ADDIS_R12_R12 = 0x3d8c0000; + const unsigned int ADDIS_R12_R2 = 0x3d820000; + const unsigned int ADDIS_R2_R2 = 0x3c420000; + const unsigned int ADDI_R12_R12 = 0x398c0000; + const unsigned int ADDI_R2_R2 = 0x38420000; + const unsigned int STD_R2_40R1 = 0xf8410028; + const unsigned int LD_R2_40R1 = 0xe8410028; + const unsigned int LD_R2_0R2 = 0xe8420000; + const unsigned int LD_R2_0R12 = 0xe84c0000; + const unsigned int LD_R11_0R12 = 0xe96c0000; + const unsigned int LD_R11_0R2 = 0xe9620000; + const unsigned int MTCTR_R11 = 0x7d6903a6; + const unsigned int BCTR = 0x4e800420; + /* * Linker stubs seen from GNU's binutils. * (see the following functions in binutils' bfd/elf64-ppc.c: From 8190eab3999051b40c9930d7368581f77ae5936f Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:28:20 -0500 Subject: [PATCH 020/505] fix float to double promotion warning --- instructionAPI/h/Result.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/instructionAPI/h/Result.h b/instructionAPI/h/Result.h index 772b0ca7d7..8c5ba6993d 100644 --- a/instructionAPI/h/Result.h +++ b/instructionAPI/h/Result.h @@ -310,7 +310,7 @@ namespace Dyninst type(t), defined(true) { assert(t == sp_float || t == dp_float); - val.dblval = v; + val.dblval = (double)v; } Result(Result_Type t, double v) : type(t), defined(true) From 2e2d7d47bbb07631ab99aba1e6579b736a805d52 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:31:32 -0500 Subject: [PATCH 021/505] fix uninitialized this and variable warnings --- stackwalk/src/framestepper.C | 4 ++-- symtabAPI/h/Type.h | 8 +++++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/stackwalk/src/framestepper.C b/stackwalk/src/framestepper.C index e6384749e8..2802e2aad4 100644 --- a/stackwalk/src/framestepper.C +++ b/stackwalk/src/framestepper.C @@ -378,8 +378,8 @@ gcframe_ret_t DyninstInstFrameStepperImpl::getCallerFrame(const Frame &in, Frame return gcf_not_me; } - sw_printf("[%s:%d] - %lx reading from memory at location %lx with framePtr %lx\n", - FILE__, __LINE__, ret, framePtr + addr_width, framePtr); + sw_printf("[%s:%d] - reading from memory at location %lx with framePtr %lx\n", + FILE__, __LINE__, framePtr + addr_width, framePtr); // Read the location in the stack where the Special Value should be. // This value was inserted into the stack at inst frame creation. diff --git a/symtabAPI/h/Type.h b/symtabAPI/h/Type.h index 3349c91134..c3c9151a69 100644 --- a/symtabAPI/h/Type.h +++ b/symtabAPI/h/Type.h @@ -474,7 +474,13 @@ class SYMTAB_EXPORT typeScalar : public Type { } typeScalar(unsigned int size, std::string name = "", bool isSigned = false) - : typeScalar(this->getUniqueTypeId(), size, name, isSigned) {} + : typeScalar() + { + ID_ = this->getUniqueTypeId(); + size_ = size; + name_ = name; + props.is_signed = isSigned; + } static typeScalar *create(std::string &name, int size, Symtab *obj = NULL); bool isSigned() const { return props.is_signed; } From bbda48d592e7e7ba93c602f7cdb8a77f0a660b79 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:33:29 -0500 Subject: [PATCH 022/505] fix misleading indentation warning --- dyninstAPI/src/BPatch_point.C | 58 +++++++++++++++++------------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/dyninstAPI/src/BPatch_point.C b/dyninstAPI/src/BPatch_point.C index 29eb5c48f2..a0d5b64ed9 100644 --- a/dyninstAPI/src/BPatch_point.C +++ b/dyninstAPI/src/BPatch_point.C @@ -574,37 +574,37 @@ bool BPatchToInternalArgs(BPatch_point *point, return false; // - // Check for valid combinations of BPatch_procedureLocation & call* - // Right now we don't allow - // BPatch_callBefore + BPatch_exit - // BPatch_callAfter + BPatch_entry - // - // These combinations are intended to be used to mark the point that - // is the last, first valid point where the local variables are - // valid. This is different than the first/last instruction of - // a subroutine which is what the other combinations of BPatch_entry - // and BPatch_exit refer to. - // - if (when == BPatch_callBefore && point->getPointType() == BPatch_exit) { - BPatch_reportError(BPatchSerious, 113, - "BPatch_callBefore at BPatch_exit not supported yet"); - return false; - } - if (when == BPatch_callAfter && point->getPointType() == BPatch_entry) { - BPatch_reportError(BPatchSerious, 113, - "BPatch_callAfter at BPatch_entry not supported yet"); - return false; - } + // Check for valid combinations of BPatch_procedureLocation & call* + // Right now we don't allow + // BPatch_callBefore + BPatch_exit + // BPatch_callAfter + BPatch_entry + // + // These combinations are intended to be used to mark the point that + // is the last, first valid point where the local variables are + // valid. This is different than the first/last instruction of + // a subroutine which is what the other combinations of BPatch_entry + // and BPatch_exit refer to. + // + if (when == BPatch_callBefore && point->getPointType() == BPatch_exit) { + BPatch_reportError(BPatchSerious, 113, + "BPatch_callBefore at BPatch_exit not supported yet"); + return false; + } + if (when == BPatch_callAfter && point->getPointType() == BPatch_entry) { + BPatch_reportError(BPatchSerious, 113, + "BPatch_callAfter at BPatch_entry not supported yet"); + return false; + } - if ((point->getPointType() == BPatch_exit)) { - // XXX - Hack! - // The semantics of pre/post insn at exit are setup for the new - // defintion of using this to control before/after stack creation, - // but the lower levels of dyninst don't know about this yet. - ipWhen = callPreInsn; - } + if ((point->getPointType() == BPatch_exit)) { + // XXX - Hack! + // The semantics of pre/post insn at exit are setup for the new + // defintion of using this to control before/after stack creation, + // but the lower levels of dyninst don't know about this yet. + ipWhen = callPreInsn; + } - return true; + return true; } BPatch_procedureLocation BPatch_point::convertInstPointType_t(int intType) From e8fc36cb86b833ef9ef31a440890590481163965 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:34:21 -0500 Subject: [PATCH 023/505] fix xor operator used as power operator 2^32 should be 1LL << 32 --- instructionAPI/src/InstructionDecoder-x86.C | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C index af06c3b408..769fa4775b 100644 --- a/instructionAPI/src/InstructionDecoder-x86.C +++ b/instructionAPI/src/InstructionDecoder-x86.C @@ -1618,7 +1618,7 @@ namespace Dyninst { Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx)); Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax)); - Expression::Ptr highAddr = makeMultiplyExpression(edx, Immediate::makeImmediate(Result(u64, 2^32)), u64); + Expression::Ptr highAddr = makeMultiplyExpression(edx, Immediate::makeImmediate(Result(u64, 1LL << 32)), u64); Expression::Ptr addr = makeAddExpression(highAddr, eax, u64); Expression::Ptr op = makeDereferenceExpression(addr, u64); insn_to_complete->appendOperand(op, isRead, isWritten, isImplicit); @@ -1627,7 +1627,7 @@ namespace Dyninst Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx)); Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx)); Expression::Ptr highAddr = makeMultiplyExpression(ecx, - Immediate::makeImmediate(Result(u64, 2^32)), u64); + Immediate::makeImmediate(Result(u64, 1LL << 32)), u64); Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64); Expression::Ptr op = makeDereferenceExpression(addr, u64); insn_to_complete->appendOperand(op, isRead, isWritten, isImplicit); From 24389ee42d020721ab6831e1b8de6e44a26c600a Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 10 Aug 2021 00:50:23 -0500 Subject: [PATCH 024/505] fix pessimizing std::move warnings --- common/src/addrtranslate-linux.C | 2 +- common/src/addrtranslate-sysv.C | 2 +- common/src/pathName.C | 2 +- proccontrol/src/linux.C | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common/src/addrtranslate-linux.C b/common/src/addrtranslate-linux.C index 318c814e9f..0750f2b4b1 100644 --- a/common/src/addrtranslate-linux.C +++ b/common/src/addrtranslate-linux.C @@ -189,7 +189,7 @@ string AddressTranslateSysV::getExecName() if (exec_name.empty()) { char name[64]; snprintf(name, 64, "/proc/%d/exe", pid); - exec_name = std::move(resolve_file_path(name)); + exec_name = resolve_file_path(name); } return exec_name; } diff --git a/common/src/addrtranslate-sysv.C b/common/src/addrtranslate-sysv.C index 49e2bb84e2..41db9f2638 100644 --- a/common/src/addrtranslate-sysv.C +++ b/common/src/addrtranslate-sysv.C @@ -866,7 +866,7 @@ FCNode::FCNode(string f, dev_t d, ino_t i, SymbolReaderFactory *factory_) : symreader(NULL), factory(factory_) { - filename = std::move(resolve_file_path(std::move(f))); + filename = resolve_file_path(std::move(f)); } string FCNode::getFilename() { diff --git a/common/src/pathName.C b/common/src/pathName.C index 3942fd54b0..c41bd06f88 100644 --- a/common/src/pathName.C +++ b/common/src/pathName.C @@ -292,7 +292,7 @@ std::string resolve_file_path(std::string path) { // If it has a tilde, expand tilde pathname // This is a no-op on Windows if(path.find("~") != std::string::npos) { - path = std::move(expand_tilde_pathname(path)); + path = expand_tilde_pathname(path); } // Convert to a boost::filesystem::path diff --git a/proccontrol/src/linux.C b/proccontrol/src/linux.C index ac4d169cc4..c51c7e3b1e 100644 --- a/proccontrol/src/linux.C +++ b/proccontrol/src/linux.C @@ -1136,7 +1136,7 @@ bool linux_process::plat_execed() char proc_exec_name[128]; snprintf(proc_exec_name, 128, "/proc/%d/exe", getPid()); - executable = std::move(resolve_file_path(proc_exec_name)); + executable = resolve_file_path(proc_exec_name); return true; } From a033bc19247754aa1ea462c25cc5d89d35dc0497 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Thu, 28 Oct 2021 15:06:18 -0500 Subject: [PATCH 025/505] fix unused const variable warnings --- parseAPI/src/IA_power.C | 1 - 1 file changed, 1 deletion(-) diff --git a/parseAPI/src/IA_power.C b/parseAPI/src/IA_power.C index 4614ead532..db3eed06a3 100644 --- a/parseAPI/src/IA_power.C +++ b/parseAPI/src/IA_power.C @@ -455,7 +455,6 @@ linker_stub_t checkLinkerStub(void *insn_buf, Offset &off) const unsigned int ADDI_R2_R2 = 0x38420000; const unsigned int STD_R2_40R1 = 0xf8410028; const unsigned int LD_R2_40R1 = 0xe8410028; - const unsigned int LD_R2_0R2 = 0xe8420000; const unsigned int LD_R2_0R12 = 0xe84c0000; const unsigned int LD_R11_0R12 = 0xe96c0000; const unsigned int LD_R11_0R2 = 0xe9620000; From 75548f7b157d2e57b97b656b81dac7582d6d3d55 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 28 Oct 2021 16:36:51 -0500 Subject: [PATCH 026/505] Remove usage of arch_ppc and arch_ppc64 (#1129) These were removed by f33ba7b in 2013 and should have been converted to arch_power at that time. Co-authored-by: Tim Haines --- dyninstAPI/src/BPatch_memoryAccessAdapter.C | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dyninstAPI/src/BPatch_memoryAccessAdapter.C b/dyninstAPI/src/BPatch_memoryAccessAdapter.C index 5dcfc47d0a..6450487473 100644 --- a/dyninstAPI/src/BPatch_memoryAccessAdapter.C +++ b/dyninstAPI/src/BPatch_memoryAccessAdapter.C @@ -179,7 +179,7 @@ BPatch_memoryAccess* BPatch_memoryAccessAdapter::convert(Instruction insn, } assert(nac < 3); return bmap; -#elif defined(arch_ppc)||defined(arch_ppc64) +#elif defined arch_power std::vector operands; insn.getOperands(operands); for(std::vector::iterator op = operands.begin(); @@ -268,7 +268,7 @@ void BPatch_memoryAccessAdapter::visit(RegisterAST* r) //fprintf(stderr, "base: %d\n", base.val()); unsigned int converted = base.val() & 0xFFFF; - #if defined(arch_ppc)||defined(arch_ppc64) + #if defined arch_power if((ra == -1) && !setImm) { ra = converted; return; From 917ddc64c44d73db8a0300d5c6581d10a57d5cec Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 28 Oct 2021 17:11:30 -0500 Subject: [PATCH 027/505] Remove common/src/language.h (#1131) This is never used anywhere. We also require a compiler that supports 'typename' implicitly. Co-authored-by: Tim Haines --- common/src/language.h | 60 ------------------------------------------- 1 file changed, 60 deletions(-) delete mode 100644 common/src/language.h diff --git a/common/src/language.h b/common/src/language.h deleted file mode 100644 index be8f04130b..0000000000 --- a/common/src/language.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - - -// $Id: language.h,v - -// Put C++ language specific code in here - -#ifndef __LANGUAGE__ -#define __LANGUAGE__ - -#if ! defined( TYPENAME ) - -#if defined( __GNUC__ ) -# define TYPENAME typename -#elif defined(__SUNPRO_CC) -# define TYPENAME typename -#elif defined (__XLC__) || defined(__xlC__) -#define TYPENAME typename -#elif defined(_MSC_VER) && (_MSC_VER >= 1310) - // Visual Studio .NET or greater -# define TYPENAME typename -#else // other compilers may not support the typename keyword yet -#define TYPENAME -#endif - -#endif - - - -#endif - From 579cce99cfbdf353e530e8dc6c4ef73bd9d9f06c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 29 Oct 2021 12:01:07 -0500 Subject: [PATCH 028/505] Remove xlc macros (#1132) * Remove unused XLC macro in dyntypes.h * Remove XLC check in BPatch_snippet/BPatch_effectiveAddressExpr This was added by c604218d5 in 2004 for compiling dyninst with xlC as a static library for AIX compatibility with DPCL- neither of which is supported by Dyninst now. Co-authored-by: Tim Haines --- common/h/dyntypes.h | 4 ---- dyninstAPI/src/BPatch_snippet.C | 4 ---- 2 files changed, 8 deletions(-) diff --git a/common/h/dyntypes.h b/common/h/dyntypes.h index e3b593f8d1..04d12f8af8 100644 --- a/common/h/dyntypes.h +++ b/common/h/dyntypes.h @@ -47,10 +47,6 @@ #endif #endif -#if defined(_POWER) && !defined(__GNUC__) -#define XLC -#endif - #include #include diff --git a/dyninstAPI/src/BPatch_snippet.C b/dyninstAPI/src/BPatch_snippet.C index 9762705440..dac9e4675e 100644 --- a/dyninstAPI/src/BPatch_snippet.C +++ b/dyninstAPI/src/BPatch_snippet.C @@ -1450,8 +1450,6 @@ BPatch_effectiveAddressExpr::BPatch_effectiveAddressExpr(int _which, int size) { #if defined(i386_unknown_nt4_0) assert(_which >= 0 && _which <= 2); -#elif defined (__XLC__) || defined(__xlC__) - assert(_which >= 0 && _which <= 1); #else assert(_which >= 0 && _which <= (int) BPatch_instruction::nmaxacc_NP); #endif @@ -1468,8 +1466,6 @@ BPatch_bytesAccessedExpr::BPatch_bytesAccessedExpr(int _which) { #if defined(i386_unknown_nt4_0) assert(_which >= 0 && _which <= 2); -#elif defined (__XLC__) || defined(__xlC__) - assert(_which >= 0 && _which <= 1); #else assert(_which >= 0 && _which <= (int)BPatch_instruction::nmaxacc_NP); #endif From 874a73ea462e7e959d97d4dac005179ab328e20c Mon Sep 17 00:00:00 2001 From: Stan Cox Date: Mon, 1 Nov 2021 14:24:07 -0400 Subject: [PATCH 029/505] Don't overflow aarch64 float register vector when setting used regs. (#1127) Do not include the subtype when setting a float register as a used register if the registerSlot vector would be exceeded, e.g. for a value like 0x400 (Q_REG/register 0). --- dyninstAPI/src/inst-aarch64.C | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/dyninstAPI/src/inst-aarch64.C b/dyninstAPI/src/inst-aarch64.C index a699198422..67b1b30c40 100644 --- a/dyninstAPI/src/inst-aarch64.C +++ b/dyninstAPI/src/inst-aarch64.C @@ -551,8 +551,13 @@ bool EmitterAARCH64::clobberAllFuncCall(registerSpace *rs, rs->GPRs()[*itr]->beenUsed = true; std::set *fpRegs = callee->ifunc()->usedFPRs(); - for(std::set::iterator itr = fpRegs->begin(); itr != fpRegs->end(); itr++) - rs->FPRs()[*itr]->beenUsed = true; + for(std::set::iterator itr = fpRegs->begin(); itr != fpRegs->end(); itr++) { + if (*itr <= rs->FPRs().size()) + rs->FPRs()[*itr]->beenUsed = true; + else + // parse_func::calcUsedRegs includes the subtype; we only want the regno + rs->FPRs()[*itr & 0xff]->beenUsed = true; + } } else { for(int idx = 0; idx < rs->numGPRs(); idx++) rs->GPRs()[idx]->beenUsed = true; From f1bcb113f65ec591176aebade781712c3d1235cd Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 2 Nov 2021 13:21:49 -0500 Subject: [PATCH 030/505] Remove support for Cray CNL (#1137) The Compute Node Linux (CNL) was for the old XT/XE platforms that are obsolete now. This should have been removed by e5484368f in 2021. Support for this platform was removed from the test suite by 7e4ab7c12 in 2012. Co-authored-by: Tim Haines --- cmake/cap_arch_def.cmake | 11 ----------- common/CMakeLists.txt | 10 ---------- proccontrol/CMakeLists.txt | 9 --------- symtabAPI/CMakeLists.txt | 3 +-- 4 files changed, 1 insertion(+), 32 deletions(-) diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index 241e68d071..be941f3deb 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -67,17 +67,6 @@ set (CAP_DEFINES ${CAP_DEFINES} ) set (BUG_DEFINES -Dbug_syscall_changepc_rewind -Dbug_force_terminate_failure) -elseif (PLATFORM MATCHES cnl) -set (OS_DEFINES -Dos_linux -Dos_cnl) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_async_events - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - -Dcap_ptrace - ) -set (BUG_DEFINES -Dbug_syscall_changepc_rewind) - elseif (PLATFORM MATCHES freebsd) set (OS_DEFINES -Dos_freebsd) set (CAP_DEFINES ${CAP_DEFINES} diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 2310d2625a..5bde2b9e5c 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -70,16 +70,6 @@ if (PLATFORM MATCHES linux) ) endif() -if (PLATFORM MATCHES cnl) - set (SRC_LIST ${SRC_LIST} - src/linuxKludges.C - src/parseauxv.C - src/addrtranslate-sysv.C - src/addrtranslate-auxv.C - src/addrtranslate-linux.C - ) -endif() - if (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) set (SRC_LIST ${SRC_LIST} src/ntKludges.C diff --git a/proccontrol/CMakeLists.txt b/proccontrol/CMakeLists.txt index 327e1938c2..d0b6ed3e04 100644 --- a/proccontrol/CMakeLists.txt +++ b/proccontrol/CMakeLists.txt @@ -66,15 +66,6 @@ set (SRC_LIST ${SRC_LIST} ../common/src/dthread.C src/loadLibrary/codegen-linux.C ) -elseif (PLATFORM MATCHES cnl) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-stub.C - ) endif() SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index f0d9e11c10..3e07aa3738 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -34,8 +34,7 @@ set (SRC_LIST ) if (PLATFORM MATCHES freebsd OR - PLATFORM MATCHES linux OR - PLATFORM MATCHES cnl) + PLATFORM MATCHES linux) set (SRC_LIST ${SRC_LIST} src/Object-elf.C From 3b920761a672bf0547867282d1d7c5624a087416 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 2 Nov 2021 14:03:05 -0500 Subject: [PATCH 031/505] Unify meaning of 'cap_32_64' macro (#1136) * Unify meaning of 'cap_32_64' macro Currently, this is used in several different ways due to the historical original meaning drifting over the years. It's meaning is now "this host 64-bit platform supports modifying 32-bit binaries". Currently, this is only x86 and PPC32. Although the latter is going away soon due to obsolescence. Co-authored-by: Tim Haines --- cmake/cap_arch_def.cmake | 9 ++++++--- dataflowAPI/src/ABI.C | 10 +++++----- dyninstAPI/src/addressSpace.C | 11 ++--------- dyninstAPI/src/inst-x86.C | 4 ++-- 4 files changed, 15 insertions(+), 19 deletions(-) diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index be941f3deb..83ea52f67d 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -1,5 +1,8 @@ -# The test suite needs this as a list rather than a bunch -# of definitions so that we can append _test to it. +# +# -- Define the capabilities for each supported architecture/platform +# +# cap_32_64 - This host 64-bit platform supports modifying 32-bit binaries +# set (CAP_DEFINES -Dcap_dynamic_heap @@ -53,7 +56,7 @@ elseif (PLATFORM MATCHES ppc64) elseif (PLATFORM MATCHES aarch64) #set (ARCH_DEFINES -Daarch_64 -Darch_64bit) set (ARCH_DEFINES -Darch_aarch64 -Darch_64bit) - set (CAP_DEFINES ${CAP_DEFINES} -Dcap_32_64 -Dcap_registers) + set (CAP_DEFINES ${CAP_DEFINES} -Dcap_registers) endif (PLATFORM MATCHES i386) if (PLATFORM MATCHES linux) diff --git a/dataflowAPI/src/ABI.C b/dataflowAPI/src/ABI.C index 11ebe80528..85d990b44c 100644 --- a/dataflowAPI/src/ABI.C +++ b/dataflowAPI/src/ABI.C @@ -91,8 +91,12 @@ ABI* ABI::getABI(int addr_width){ globalABI64_->index = &machRegIndex_aarch64(); #endif +// We _only_ support instrumenting 32-bit binaries on 64-bit systems +#if !defined arch_64bit || defined cap_32_64 initialize32(); -#if defined(cap_32_64) +#endif + +#ifdef arch_64bit initialize64(); #endif } @@ -553,10 +557,6 @@ void ABI::initialize64(){ //#warning "This is not verified!" #if defined(arch_aarch64) -void ABI::initialize32(){ - return; -} - void ABI::initialize64(){ RegisterMap aarch64Map = machRegIndex_aarch64(); int sz = aarch64Map.size(); diff --git a/dyninstAPI/src/addressSpace.C b/dyninstAPI/src/addressSpace.C index 74feb6edcb..466219a9dc 100644 --- a/dyninstAPI/src/addressSpace.C +++ b/dyninstAPI/src/addressSpace.C @@ -1140,7 +1140,6 @@ bool mapping_sort(const trampTrapMappings::tramp_mapping_t *lhs, return lhs->from_addr < rhs->from_addr; } -#if defined(cap_32_64) void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, unsigned addr_width) { @@ -1149,19 +1148,13 @@ void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, //Currently only support 64-bit mutators with 32-bit mutatees assert(addr_width == 4); assert(sizeof(Address) == 8); +#if defined(cap_32_64) *((uint32_t *) buffer) = (uint32_t) val; return; +#endif } *((unsigned long *) buffer) = val; } -#else -void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, - unsigned) -{ - *((unsigned long *)(void*) buffer) = val; -} -#endif - void trampTrapMappings::writeTrampVariable(const int_variable *var, unsigned long val) diff --git a/dyninstAPI/src/inst-x86.C b/dyninstAPI/src/inst-x86.C index f8bdcf245f..ead580f940 100644 --- a/dyninstAPI/src/inst-x86.C +++ b/dyninstAPI/src/inst-x86.C @@ -197,7 +197,7 @@ void registerSpace::initialize32() { } -#if defined(cap_32_64) +#if defined arch_x86_64 void registerSpace::initialize64() { static bool done = false; if (done) return; @@ -538,7 +538,7 @@ void registerSpace::initialize() initialize32(); -#if defined(cap_32_64) +#if defined arch_x86_64 initialize64(); #endif } From 03e37a9a9e1b4f598f2d075676e00835f2aa76df Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 3 Nov 2021 10:17:35 -0500 Subject: [PATCH 032/505] Update copyright to 2022 (#1141) Co-authored-by: Tim Haines --- COPYRIGHT | 2 +- parseAPI/h/SymLiteCodeSource.h | 2 +- parseAPI/src/CodeSource.C | 2 +- parseAPI/src/SymLiteCodeSource.C | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/COPYRIGHT b/COPYRIGHT index 2ce59090ad..9160abe3e5 100644 --- a/COPYRIGHT +++ b/COPYRIGHT @@ -1,4 +1,4 @@ -Paradyn is Copyright (c) 1996-2021 Barton P. Miller +Paradyn is Copyright (c) 1996-2022 Barton P. Miller Contributions to Paradyn were developed by LLNS and have the following copyright: Copyright (c) 2012-2013, Lawrence Livermore National Security, LLC. Produced at diff --git a/parseAPI/h/SymLiteCodeSource.h b/parseAPI/h/SymLiteCodeSource.h index edcc5dd148..fad01eae29 100644 --- a/parseAPI/h/SymLiteCodeSource.h +++ b/parseAPI/h/SymLiteCodeSource.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * Copyright (c) 1996-2022 Barton P. Miller * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its diff --git a/parseAPI/src/CodeSource.C b/parseAPI/src/CodeSource.C index 8a519f48fa..d46e3b8f1d 100644 --- a/parseAPI/src/CodeSource.C +++ b/parseAPI/src/CodeSource.C @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * Copyright (c) 1996-2022 Barton P. Miller * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its diff --git a/parseAPI/src/SymLiteCodeSource.C b/parseAPI/src/SymLiteCodeSource.C index 9bb02a62de..f826165a1a 100644 --- a/parseAPI/src/SymLiteCodeSource.C +++ b/parseAPI/src/SymLiteCodeSource.C @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * Copyright (c) 1996-2022 Barton P. Miller * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its From e4f98e20fd62a02c2dacdb9b2207bd62c299efb8 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 4 Nov 2021 23:22:15 -0500 Subject: [PATCH 033/505] Implement ppc64 in MachRegister::getROSERegister (#1139) Co-authored-by: Tim Haines --- common/src/dyn_regs.C | 104 +++++++++++++++++++++++++++--------------- 1 file changed, 66 insertions(+), 38 deletions(-) diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index e64a16fb17..ab433db538 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -1069,47 +1069,75 @@ void MachRegister::getROSERegister(int &c, int &n, int &p) } break; case Arch_ppc32: - case Arch_ppc64: // 64-bit not supported in ROSE + { + baseID = reg & 0x0000FFFF; + n = baseID; + switch(category) { - baseID = reg & 0x0000FFFF; - n = baseID; - switch(category) - { - case ppc32::GPR: - c = powerpc_regclass_gpr; - break; - case ppc32::FPR: - case ppc32::FSR: - c = powerpc_regclass_fpr; - break; - case ppc32::SPR: - { - if(baseID < 613) { - c = powerpc_regclass_spr; - } else if(baseID < 621 ) { - c = powerpc_regclass_sr; - } else { - c = powerpc_regclass_cr; - n = 0; - p = baseID - 621; - /* n = baseID - 621; - if(n > 7) { - n = 0; - p = powerpc_condreggranularity_whole; - } else { - p = powerpc_condreggranularity_field; - } - */ - } + case ppc32::GPR: + c = powerpc_regclass_gpr; + break; + case ppc32::FPR: + case ppc32::FSR: + c = powerpc_regclass_fpr; + break; + case ppc32::SPR: + { + if(baseID < 613) { + c = powerpc_regclass_spr; + } else if(baseID < 621 ) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + /* n = baseID - 621; + if(n > 7) { + n = 0; + p = powerpc_condreggranularity_whole; + } else { + p = powerpc_condreggranularity_field; + } + */ } - break; - default: - c = -1; - return; - } - return; + } + break; + default: + c = -1; + return; } - break; + return; + } + break; + case Arch_ppc64: { + baseID = reg & 0x0000FFFF; + n = baseID; + switch (category) { + case ppc64::GPR: + c = powerpc_regclass_gpr; + break; + case ppc64::FPR: + case ppc64::FSR: + c = powerpc_regclass_fpr; + break; + case ppc64::SPR: { + if (baseID < 613) { + c = powerpc_regclass_spr; + } else if (baseID < 621) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + } + } break; + default: + c = -1; + return; + } + return; + } + break; case Arch_aarch64: { p = 0; switch (category) { From 539e0a0934ac6943377d966053bc72d83ac17b0a Mon Sep 17 00:00:00 2001 From: kupsch Date: Sun, 7 Nov 2021 13:41:22 -0600 Subject: [PATCH 034/505] fix statement-like macros (#1143) wrap macro body in 'do {...} while (0)' so they can be used as if they were a statement with a terminating semicolon. changed break to return since it then works in a do/while loop and was semantically the same in all the expansions parenthesized the use of parameters as needed --- dwarf/src/dwarfResult.C | 2 +- dyninstAPI/src/ast.C | 6 +++--- symtabAPI/src/dwarfWalker.C | 12 ++++++------ 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/dwarf/src/dwarfResult.C b/dwarf/src/dwarfResult.C index c840535322..2838c8295f 100644 --- a/dwarf/src/dwarfResult.C +++ b/dwarf/src/dwarfResult.C @@ -43,7 +43,7 @@ using namespace Dyninst; using namespace DwarfDyninst; using namespace std; -#define CHECK_OPER(n) if (operands.size() < n) { error = true; break; } +#define CHECK_OPER(n) do { if (operands.size() < (n)) { error = true; return; } } while (0) void SymbolicDwarfResult::pushReg(MachRegister reg) { dwarf_printf("\t\tPush %s\n", reg.name().c_str()); diff --git a/dyninstAPI/src/ast.C b/dyninstAPI/src/ast.C index 441fd2a4d4..322680b44c 100644 --- a/dyninstAPI/src/ast.C +++ b/dyninstAPI/src/ast.C @@ -777,9 +777,9 @@ bool AstNode::previousComputationValid(Register ®, } // We're going to use this fragment over and over and over... -#define RETURN_KEPT_REG(r) { if (previousComputationValid(r, gen)) { decUseCount(gen); gen.rs()->incRefCount(r); return true;} } -#define ERROR_RETURN { fprintf(stderr, "[%s:%d] ERROR: failure to generate operand\n", __FILE__, __LINE__); return false; } -#define REGISTER_CHECK(r) if (r == REG_NULL) { fprintf(stderr, "[%s: %d] ERROR: returned register invalid\n", __FILE__, __LINE__); return false; } +#define RETURN_KEPT_REG(r) do { if (previousComputationValid(r, gen)) { decUseCount(gen); gen.rs()->incRefCount(r); return true;} } while (0) +#define ERROR_RETURN do { fprintf(stderr, "[%s:%d] ERROR: failure to generate operand\n", __FILE__, __LINE__); return false; } while (0) +#define REGISTER_CHECK(r) do { if ((r) == REG_NULL) { fprintf(stderr, "[%s: %d] ERROR: returned register invalid\n", __FILE__, __LINE__); return false; } } while (0) bool AstNode::initRegisters(codeGen &g) { diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index cbf9324b6a..88426852c9 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -51,33 +51,33 @@ using namespace SymtabAPI; using namespace DwarfDyninst; using namespace std; -#define DWARF_FAIL_RET_VAL(x, v) { \ +#define DWARF_FAIL_RET_VAL(x, v) do { \ int dwarf_fail_ret_val_status = (x); \ if (dwarf_fail_ret_val_status != 0) { \ types_printf("[%s:%d]: libdwarf returned %d, ret false\n", \ FILE__, __LINE__, dwarf_fail_ret_val_status); \ return (v); \ } \ - } + } while (0) #define DWARF_FAIL_RET(x) DWARF_FAIL_RET_VAL(x, false) -#define DWARF_ERROR_RET_VAL(x, v) { \ +#define DWARF_ERROR_RET_VAL(x, v) do { \ int dwarf_error_ret_val_status = (x); \ if (dwarf_error_ret_val_status == 1 /*DW_DLV_ERROR*/) { \ types_printf("[%s:%d]: parsing failure, ret false\n", \ FILE__, __LINE__); \ return (v); \ } \ - } + } while (0) #define DWARF_ERROR_RET(x) DWARF_ERROR_RET_VAL(x, false) -#define DWARF_CHECK_RET_VAL(x, v) { \ +#define DWARF_CHECK_RET_VAL(x, v) do { \ if (x) { \ types_printf("[%s:%d]: parsing failure, ret false\n", \ FILE__, __LINE__); \ return (v); \ } \ - } + } while (0) #define DWARF_CHECK_RET(x) DWARF_CHECK_RET_VAL(x, false) DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf * dbg) : From d7425515bac9f81ffacfd56af3f301999bb83b31 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sun, 7 Nov 2021 13:53:25 -0600 Subject: [PATCH 035/505] Remove ppc32 from builds (#1145) * Remove ppc32 from build system * Remove ppc32 source and header files * Clean up gitignore in parseThat * Remove use of arch_ppc_little_endian * Remove explict use of ppc32_linux macro * Remove implicit use of ppc32 macro There are likely more instances. Co-authored-by: Tim Haines --- cmake/cap_arch_def.cmake | 15 - cmake/platform_unix.cmake | 1 - common/src/util.C | 2 - dyninstAPI/src/Parsing.C | 6 - dyninstAPI/src/image.C | 4 +- dyninstAPI_RT/CMakeLists.txt | 14 +- dyninstAPI_RT/src/RTlinux.c | 2 - .../src/RTstatic_ctors_dtors-ppc32.c | 94 --- dyninstAPI_RT/src/RTthread-powerpc-asm.S | 26 - parseThat/.gitignore | 1 - scripts/dynsysname | 9 - symtabAPI/CMakeLists.txt | 5 - symtabAPI/src/Object-elf.C | 5 - symtabAPI/src/emitElfStatic-ppc32.C | 744 ------------------ symtabAPI/src/relocationEntry-elf-ppc32.C | 143 ---- syscalls/README | 6 +- .../Linux/Arch_ppc32/unistd.h.20130604 | 334 -------- 17 files changed, 5 insertions(+), 1406 deletions(-) delete mode 100644 dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c delete mode 100644 symtabAPI/src/emitElfStatic-ppc32.C delete mode 100644 symtabAPI/src/relocationEntry-elf-ppc32.C delete mode 100644 syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index 83ea52f67d..5778d0a0a2 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -33,12 +33,6 @@ set (CAP_DEFINES ${CAP_DEFINES} -Dcap_stack_mods ) -elseif (PLATFORM MATCHES ppc32) -set (ARCH_DEFINES -Darch_power) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_registers - ) - elseif (PLATFORM MATCHES ppc64) set (ARCH_DEFINES -Darch_power -Darch_64bit) set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -m64") @@ -48,11 +42,6 @@ elseif (PLATFORM MATCHES ppc64) -Dcap_registers -Dcap_toc_64 ) - if (SYSPLATFORM MATCHES ppc64le) - set (CAP_DEFINES ${CAP_DEFINES} - -Darch_ppc_little_endian - ) - endif (SYSPLATFORM MATCHES ppc64le) elseif (PLATFORM MATCHES aarch64) #set (ARCH_DEFINES -Daarch_64 -Darch_64bit) set (ARCH_DEFINES -Darch_aarch64 -Darch_64bit) @@ -99,10 +88,6 @@ set (OLD_DEFINES -Di386_unknown_linux2_0) elseif (PLATFORM STREQUAL x86_64-unknown-linux2.4) set (OLD_DEFINES -Dx86_64_unknown_linux2_4) -elseif (PLATFORM STREQUAL ppc32_linux) -set (OLD_DEFINES -Dppc32_linux) -set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) - elseif (PLATFORM STREQUAL ppc64_linux) set (OLD_DEFINES -Dppc64_linux) set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) diff --git a/cmake/platform_unix.cmake b/cmake/platform_unix.cmake index fa48b98678..7b1bea840c 100644 --- a/cmake/platform_unix.cmake +++ b/cmake/platform_unix.cmake @@ -4,7 +4,6 @@ set (VALID_PLATFORMS amd64-unknown-freebsd7.2 i386-unknown-freebsd7.2 i386-unknown-linux2.4 - ppc32_linux ppc64_linux x86_64-unknown-linux2.4 aarch64-unknown-linux diff --git a/common/src/util.C b/common/src/util.C index 904c5d8424..f24c8a4a51 100644 --- a/common/src/util.C +++ b/common/src/util.C @@ -208,8 +208,6 @@ const char *platform_string() #if defined (os_linux) #if defined (arch_64bit) return "ppc64_linux"; -#else - return "ppc32_linux"; #endif #endif #endif diff --git a/dyninstAPI/src/Parsing.C b/dyninstAPI/src/Parsing.C index c8f43bb552..3471ad34d3 100644 --- a/dyninstAPI/src/Parsing.C +++ b/dyninstAPI/src/Parsing.C @@ -263,12 +263,6 @@ DynParseCallback::patch_nop_jump(Address addr) void DynParseCallback::interproc_cf(Function*f,Block *b,Address /*addr*/,interproc_details*det) { -#if defined(ppc32_linux) - if(det->type == interproc_details::call) { - parse_func * ifunc = static_cast(f); - _img->updatePltFunc(ifunc,det->data.call.target); - } -#endif (void) f; // compiler warning if (det->type == ParseCallback::interproc_details::unresolved) { static_cast(b)->setUnresolvedCF(true); diff --git a/dyninstAPI/src/image.C b/dyninstAPI/src/image.C index 3d108cede0..613f318d6b 100644 --- a/dyninstAPI/src/image.C +++ b/dyninstAPI/src/image.C @@ -172,7 +172,7 @@ extern unsigned enable_pd_sharedobj_debug; int codeBytesSeen = 0; -#if defined(ppc32_linux) || defined(ppc64_linux) +#if defined(ppc64_linux) #include #include @@ -475,7 +475,7 @@ class FindMainVisitor : public ASTVisitor */ int image::findMain() { -#if defined(ppc32_linux) || defined(ppc64_linux) +#if defined(ppc64_linux) using namespace Dyninst::InstructionAPI; // Only look for main in executables, but do allow position-independent diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index 0055e0194b..5d61411a78 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -65,13 +65,6 @@ set (SRC_LIST_x86_64 set (RT_STATIC_ONLY_SRC_LIST_x86_64 src/RTstatic_ctors_dtors-x86.c ) -set (SRC_LIST_ppc32 - src/RTthread-powerpc.c - src/RTthread-powerpc-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_ppc32 - src/RTstatic_ctors_dtors-ppc32.c -) set (SRC_LIST_ppc64 src/RTthread-powerpc.c src/RTthread-powerpc-asm.S @@ -111,16 +104,13 @@ set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SR set (SRC_LIST ${SRC_LIST} ${SRC_LIST_x86_64}) set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_x86_64}) elseif (PLATFORM MATCHES ppc64) -set (SRC_LIST_mabi ${SRC_LIST} ${SRC_LIST_ppc32}) -set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc32}) +set (SRC_LIST_mabi ${SRC_LIST}) +set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST}) set (SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc64}) set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc64}) elseif (PLATFORM MATCHES i386) set (SRC_LIST ${SRC_LIST} ${SRC_LIST_i386}) set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_i386}) -elseif (PLATFORM MATCHES ppc32) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc32}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc32}) elseif (PLATFORM MATCHES aarch64) set (SRC_LIST ${SRC_LIST} ${SRC_LIST_aarch64}) set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_aarch64}) diff --git a/dyninstAPI_RT/src/RTlinux.c b/dyninstAPI_RT/src/RTlinux.c index 44ac47d146..0ddfc12ff6 100644 --- a/dyninstAPI_RT/src/RTlinux.c +++ b/dyninstAPI_RT/src/RTlinux.c @@ -331,8 +331,6 @@ int DYNINST_am_initial_thread( dyntid_t tid ) { #elif defined(arch_power) #if defined(arch_64bit) #define UC_PC(x) x->uc_mcontext.regs->nip - #else // 32-bit - #define UC_PC(x) x->uc_mcontext.uc_regs->gregs[32] #endif // power #elif defined(arch_aarch64) //#warning "UC_PC: in aarch64, pc is not directly accessable." diff --git a/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c b/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c deleted file mode 100644 index 3c3265b832..0000000000 --- a/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if defined(DYNINST_RT_STATIC_LIB) -void (*DYNINSTctors_addr)(void); -void (*DYNINSTdtors_addr)(void); - -#if defined(MUTATEE64) -static const unsigned long long CTOR_LIST_TERM = 0x0000000000000000ULL; -static const unsigned long long CTOR_LIST_START = 0xffffffffffffffffULL; -static const unsigned long long DTOR_LIST_TERM = 0x0000000000000000ULL; -static const unsigned long long DTOR_LIST_START = 0xffffffffffffffffULL; -#else -static const unsigned CTOR_LIST_TERM = 0x00000000; -static const unsigned CTOR_LIST_START = 0xffffffff; -static const unsigned DTOR_LIST_TERM = 0x00000000; -static const unsigned DTOR_LIST_START = 0xffffffff; -#endif - -extern void DYNINSTBaseInit(); - -/* - * When rewritting a static binary, .ctors and .dtors sections of - * instrumentation code needs to be combined with the existing .ctors - * and .dtors sections of the static binary. - * - * The following functions process the .ctors and .dtors sections - * that have been rewritten. The rewriter will relocate the - * address of DYNINSTctors_addr and DYNINSTdtors_addr to point to - * new .ctors and .dtors sections. - */ - -void DYNINSTglobal_ctors_handler() { - void (**ctors_array)(void) = &DYNINSTctors_addr; - - // Find end of function pointer list - void (**tmp_ptr)(void) = ctors_array; - unsigned size = 0; - while( *tmp_ptr != ( (void(*)(void))CTOR_LIST_TERM ) ) { - size++; - tmp_ptr++; - } - - // Constructors are called in the reverse order that they are listed - tmp_ptr = &ctors_array[size-1]; // skip list end - while( *tmp_ptr != ( (void(*)(void))CTOR_LIST_START ) ) { - (*tmp_ptr)(); - tmp_ptr--; - } - - // This ensures that instrumentation cannot execute until all global - // constructors have run - DYNINSTBaseInit(); -} - -void DYNINSTglobal_dtors_handler() { - void (**dtors_array)(void) = &DYNINSTdtors_addr; - - // Destructors are called in the forward order that they are listed - void (**tmp_ptr)(void) = &dtors_array[1]; // skip list start - while( *tmp_ptr != ( (void(*)(void))DTOR_LIST_TERM ) ) { - (*tmp_ptr)(); - tmp_ptr++; - } -} - -#endif diff --git a/dyninstAPI_RT/src/RTthread-powerpc-asm.S b/dyninstAPI_RT/src/RTthread-powerpc-asm.S index fd59bdcd27..818c61a3d0 100644 --- a/dyninstAPI_RT/src/RTthread-powerpc-asm.S +++ b/dyninstAPI_RT/src/RTthread-powerpc-asm.S @@ -1,8 +1,6 @@ .file "RTthread-powerpc-asm.S" .machine "push" -#if defined(arch_ppc_little_endian) .abiversion 2 -#endif #ifndef __clang__ # if defined(arch_64bit) @@ -23,7 +21,6 @@ # /* Return 1 if such an atomic update occurred; */ # /* return 0 otherwise. */ # /* ------------------------------------------- */ -#if defined(arch_ppc_little_endian) .section ".toc", "aw" .section ".text" .align 2 @@ -31,23 +28,6 @@ .globl atomic_set .type atomic_set, @function atomic_set: -#elif defined(arch_64bit) - .globl atomic_set - .section ".opd", "aw" - .align 3 -atomic_set: - .quad .atomic_set, .TOC.@tocbase, 0 - .size atomic_set, 24 - - .previous - .globl .atomic_set - .type .atomic_set, @function -.atomic_set: -#else - .globl atomic_set - .type atomic_set, @function -atomic_set: -#endif addi 4,0,1 # r4 = 1 # Attempt atomic memory swap lwarx 5,0,3 # r5 = *int_ptr (load reserve indexed) @@ -64,13 +44,7 @@ atomic_set_return_0: addi 3,0,0 # function return value = r3 = 0 blr # branch via link register (function return) -#if defined(arch_ppc_little_endian) .size atomic_set, . - atomic_set -#elif defined(arch_64bit) - .size .atomic_set, . - .atomic_set -#else - .size atomic_set, . - atomic_set -#endif .machine "pop" diff --git a/parseThat/.gitignore b/parseThat/.gitignore index 171119f8ae..d67fb0ff91 100644 --- a/parseThat/.gitignore +++ b/parseThat/.gitignore @@ -3,7 +3,6 @@ i386-unknown-freebsd7.2/ i386-unknown-linux2.4/ i386-unknown-vxworks6.x/ ppc32_bgp/ -ppc32_linux/ ppc32-unknown-vxworks6.x/ ppc64_linux/ x86_64-unknown-linux2.4/ diff --git a/scripts/dynsysname b/scripts/dynsysname index dc6692a81a..6906fb224b 100755 --- a/scripts/dynsysname +++ b/scripts/dynsysname @@ -25,12 +25,6 @@ fi if [ ${P/powerpc64/} != ${P} ]; then PLATFORM=ppc64_linux fi -if [ ${P/powerpc-/} != ${P} ]; then -PLATFORM=ppc32_linux -fi -if [ ${P/ppc-/} != ${P} ]; then -PLATFORM=ppc32_linux -fi if [ ${P/aarch64-/} != ${P} ]; then PLATFORM=aarch64-unknown-linux fi @@ -67,9 +61,6 @@ fi if [ ${P/i386/} != ${P} ]; then PLATFORM=i386-unknown-vxworks6.x fi -if [ ${P/powerpc-/} != ${P} ]; then -PLATFORM=ppc32-unknown-vxworks6.x -fi fi echo $PLATFORM diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 3e07aa3738..4ca6896f83 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -57,11 +57,6 @@ set (SRC_LIST ${SRC_LIST} src/emitElfStatic-x86.C src/relocationEntry-elf-x86.C ) -elseif (PLATFORM MATCHES ppc32) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-ppc32.C - src/relocationEntry-elf-ppc32.C - ) elseif (PLATFORM MATCHES ppc64) set (SRC_LIST ${SRC_LIST} src/emitElfStatic-ppc64.C diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 7a52479f7e..1f1f242ce5 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -386,13 +386,8 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, plt_size_ = 0; symtab_addr_ = 0; strtab_addr_ = 0; -#if defined (ppc32_linux) - plt_entry_size_ = 8; - rel_plt_entry_size_ = 8; -#else plt_entry_size_ = 0; rel_plt_entry_size_ = 0; -#endif rel_plt_addr_ = 0; rel_plt_size_ = 0; rel_addr_ = 0; diff --git a/symtabAPI/src/emitElfStatic-ppc32.C b/symtabAPI/src/emitElfStatic-ppc32.C deleted file mode 100644 index e10508b0be..0000000000 --- a/symtabAPI/src/emitElfStatic-ppc32.C +++ /dev/null @@ -1,744 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * holds architecture specific functions for x86 and x86_64 architecture needed for the - * static executable rewriter - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "emitElfStatic.h" -#include "Symtab.h" -#include "Symbol.h" -#include "Archive.h" -#include "Object.h" -#include "Region.h" -#include "debug.h" - -using namespace Dyninst; -using namespace Dyninst::SymtabAPI; - -static const unsigned PPC32_WIDTH = 4; -static const unsigned PPC64_WIDTH = 8; - -static const Elf64_Word X86_HEADER = 0xffffffff; -static const Elf64_Word X86_TRAILER = 0x00000000; -static const Elf64_Xword X86_64_HEADER = 0xffffffffffffffffULL; -static const Elf64_Xword X86_64_TRAILER = 0x0000000000000000ULL; - -unsigned int setBits(unsigned int target, unsigned int pos, unsigned int len, unsigned int value) { - rewrite_printf("setBits target 0x%lx value 0x%lx pos %d len %d \n", target, value, pos, len); - unsigned int mask; - mask = ~(~0 << len); - value = value & mask; - - mask = ~(mask << pos); - value = value << pos; - - target = target & mask; - target = target | value; - rewrite_printf( "setBits target 0x%lx value 0x%lx pos %d len %d \n", target, value, pos, len); - return target; -} - -#if defined(os_freebsd) -#define R_X86_64_JUMP_SLOT R_X86_64_JMP_SLOT -#endif - -// Used in an assert so needs to be a macro -#define UNKNOWN_ADDRESS_WIDTH_ASSERT "An unknown address width was encountered, can't continue" - -/* NOTE: - * As most of these functions are defined per architecture, the description of - * each of these functions is in the emitElfStatic header. Comments describing - * the function interface are explicitly left out. - */ - -/** - * - * Given a relocation, determines if the relocation corresponds to a .ctors or .dtors - * table that requires special consideration. Modifies the passed symbol offset to - * point to the right table, if applicable. - * - * rel The relocation entry to examine - * globalOffset The offset of the linked code (used for symbol offset calculation) - * lmap Holds information about .ctors/.dtors tables - * errMsg Set on error - * symbolOffset Modified by this routine to contain the offset of the table - * - * Returns true, if there are no errors including the case where the relocation - * entry doesn't reference the .ctors/.dtors tables. - */ - -static bool computeCtorDtorAddress(relocationEntry &rel, Offset globalOffset, - LinkMap &lmap, string &errMsg, Offset &symbolOffset) -{ - if( rel.name() == SYMTAB_CTOR_LIST_REL ) { - // This needs to be: (the location of the .ctors table) - if( lmap.newCtorRegions.size() > 0 ) { - symbolOffset = lmap.ctorRegionOffset + globalOffset; - }else if( lmap.originalCtorRegion != NULL ) { - symbolOffset = lmap.originalCtorRegion->getMemOffset(); - }else{ - errMsg = "Failed to locate original .ctors Region -- cannot apply relocation"; - rewrite_printf("Failed to locate original .ctors Region -- cannot apply relocation\n"); - return false; - } - }else if( rel.name() == SYMTAB_DTOR_LIST_REL ) { - // This needs to be: (the location of the .dtors table) - if( lmap.newDtorRegions.size() > 0 ) { - symbolOffset = lmap.dtorRegionOffset + globalOffset; - }else if( lmap.originalDtorRegion != NULL ) { - symbolOffset = lmap.originalDtorRegion->getMemOffset(); - }else{ - errMsg = "Failed to locate original .dtors Region -- cannot apply relocation"; - rewrite_printf("Failed to locate original .dtors Region -- cannot apply relocation\n"); - return false; - } - } - - return true; -} - - -bool emitElfStatic::archSpecificRelocation(Symtab *, Symtab *, char *targetData, relocationEntry &rel, - Offset dest, Offset relOffset, Offset globalOffset, LinkMap &lmap, - string &errMsg) -{ - rewrite_printf(" archSpecificRelocation %s \n", rel.name().c_str()); - if( PPC32_WIDTH == addressWidth_ ) { - int relocation_length = sizeof(Elf32_Word)*8; // in bits - int relocation_pos = 0; // in bits - int branch_pred = -1; - /* - * Referring to the SYSV 386 supplement: - * - * All relocations on x86 are one word32 == Elf32_Word - * - * S = symbolOffset - * A = addend - * P = relOffset - */ - - Offset symbolOffset = rel.getDynSym()->getOffset(); - - Elf32_Word addend; - if( rel.regionType() == Region::RT_REL ) { - memcpy(&addend, &targetData[dest], sizeof(Elf32_Word)); - }else if( rel.regionType() == Region::RT_RELA ) { - addend = rel.addend(); - } - - if(!computeCtorDtorAddress(rel, globalOffset, lmap, errMsg, symbolOffset)) { - return false; - } - - rewrite_printf("relocation for '%s': TYPE = %s(%lu) S = %lx A = %lx P = %lx\n", - rel.name().c_str(), - relocationEntry::relType2Str(rel.getRelType(), addressWidth_), - rel.getRelType(), symbolOffset, addend, relOffset); - - Offset relocation = 0; - map::iterator result; - stringstream tmp; - - switch(rel.getRelType()) { - -/* PowerPC relocations defined by the ABIs */ -case R_PPC_NONE:/* 0 */ - break; -case R_PPC_ADDR32:/* 1 32bit absolute address */ - relocation = symbolOffset + addend; - break; -case R_PPC_ADDR24:/* 2 26bit address, 2 bits ignored. */ - relocation_length = 26; - relocation_pos = 2; - relocation = (symbolOffset + addend) >> 2; - break; -case R_PPC_ADDR16:/* 3 16bit absolute address */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - break; -case R_PPC_ADDR16_LO:/* 4 lower 16bit of absolute address */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = (relocation & 0xffff); - break; -case R_PPC_ADDR16_HI:/* 5 high 16bit of absolute address */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = ((relocation >> 16) & 0xffff); - break; -case R_PPC_ADDR16_HA:/* 6 adjusted high 16bit */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -case R_PPC_ADDR14:/* 7 16bit address, 2 bits ignored */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - break; -case R_PPC_ADDR14_BRTAKEN:/* 8 */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - // bit 10 is set - branch_pred = 1; - break; -case R_PPC_ADDR14_BRNTAKEN:/* 9 */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - // bit 10 is set - branch_pred = 0; - break; -case R_PPC_REL24:/* 10 PC relative 26 bit */ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_REL14:/* 11 PC relative 16 bit */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_REL14_BRTAKEN:/* 12*/ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - branch_pred = 1; - break; -case R_PPC_REL14_BRNTAKEN:/* 13*/ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - branch_pred = 0; - break; -case R_PPC_GOT16:/* 14*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (relocation) >> 16; - relocation_length = 16; - relocation_pos = 16; - break; -case R_PPC_GOT16_LO:/* 15*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (relocation & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_GOT16_HI:/* 16*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = ((relocation >> 16) & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_GOT16_HA:/* 17*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_PLTREL24:/* 18*/ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_COPY:/* 19*/ - break; -case R_PPC_GLOB_DAT:/* 20*/ - relocation = symbolOffset + addend; - break; -case R_PPC_JMP_SLOT:/* 21*/ - break; -case R_PPC_RELATIVE:/* 22*/ - tmp << "ERROR: encountered relocation type(" << rel.getRelType() << - ") that is meant for use during dynamic linking"; - errMsg = tmp.str(); - return false; -case R_PPC_LOCAL24PC:/* 23*/ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_UADDR32:/* 24*/ - relocation = symbolOffset + addend ; - break; -case R_PPC_UADDR16:/* 25*/ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - break; -case R_PPC_REL32:/* 26*/ - relocation = symbolOffset + addend - relOffset; - break; -case R_PPC_PLT32:/* 27*/ - relocation = symbolOffset + addend; - break; -case R_PPC_PLTREL32:/* 28*/ - relocation = symbolOffset + addend - relOffset; - break; -case R_PPC_PLT16_LO:/* 29*/ - relocation = symbolOffset + addend; - relocation = (relocation & 0xffff); - break; -case R_PPC_PLT16_HI:/* 30*/ - relocation = symbolOffset + addend; - relocation = ((relocation >> 16) & 0xffff); - break; -case R_PPC_PLT16_HA:/* 31*/ - relocation = symbolOffset + addend; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -case R_PPC_SDAREL16:/* 32*/ -case R_PPC_SECTOFF:/* 33*/ -case R_PPC_SECTOFF_LO:/* 34*/ -case R_PPC_SECTOFF_HI:/* 35*/ -case R_PPC_SECTOFF_HA:/* 36*/ - tmp << "Relocation type " << rel.getRelType() - << " currently unimplemented"; - errMsg = tmp.str(); - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - return false; - -/* PowerPC relocations defined for the TLS access ABI. */ -case R_PPC_TLS:/* 67 none (sym+add)@tls */ -case R_PPC_DTPMOD32:/* 68 word32 (sym+add)@dtpmod */ -case R_PPC_TPREL16:/* 69 half16* (sym+add)@tprel */ -case R_PPC_TPREL16_LO:/* 70 half16 (sym+add)@tprel@l */ -case R_PPC_TPREL16_HI:/* 71 half16 (sym+add)@tprel@h */ -case R_PPC_TPREL16_HA:/* 72 half16 (sym+add)@tprel@ha */ -case R_PPC_TPREL32:/* 73 word32 (sym+add)@tprel */ -case R_PPC_DTPREL16:/* 74 half16* (sym+add)@dtprel */ -case R_PPC_DTPREL16_LO:/* 75 half16 (sym+add)@dtprel@l */ -case R_PPC_DTPREL16_HI:/* 76 half16 (sym+add)@dtprel@h */ -case R_PPC_DTPREL16_HA:/* 77 half16 (sym+add)@dtprel@ha */ -case R_PPC_DTPREL32:/* 78 word32 (sym+add)@dtprel */ -case R_PPC_GOT_TLSGD16:/* 79 half16* (sym+add)@got@tlsgd */ -case R_PPC_GOT_TLSGD16_LO:/* 80 half16 (sym+add)@got@tlsgd@l */ -case R_PPC_GOT_TLSGD16_HI:/* 81 half16 (sym+add)@got@tlsgd@h */ -case R_PPC_GOT_TLSGD16_HA:/* 82 half16 (sym+add)@got@tlsgd@ha */ -case R_PPC_GOT_TLSLD16:/* 83 half16* (sym+add)@got@tlsld */ -case R_PPC_GOT_TLSLD16_LO:/* 84 half16 (sym+add)@got@tlsld@l */ -case R_PPC_GOT_TLSLD16_HI:/* 85 half16 (sym+add)@got@tlsld@h */ -case R_PPC_GOT_TLSLD16_HA:/* 86 half16 (sym+add)@got@tlsld@ha */ -case R_PPC_GOT_TPREL16:/* 87 half16* (sym+add)@got@tprel */ -case R_PPC_GOT_TPREL16_LO:/* 88 half16 (sym+add)@got@tprel@l */ -case R_PPC_GOT_TPREL16_HI:/* 89 half16 (sym+add)@got@tprel@h */ -case R_PPC_GOT_TPREL16_HA:/* 90 half16 (sym+add)@got@tprel@ha */ -case R_PPC_GOT_DTPREL16:/* 91 half16* (sym+add)@got@dtprel */ -case R_PPC_GOT_DTPREL16_LO:/* 92 half16* (sym+add)@got@dtprel@l */ -case R_PPC_GOT_DTPREL16_HI:/* 93 half16* (sym+add)@got@dtprel@h */ -case R_PPC_GOT_DTPREL16_HA:/* 94 half16* (sym+add)@got@dtprel@ha */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - break; - -/* GNU relocs used in PIC code sequences. */ -/* NOTE: The following relocations are not defined in some elf.h - Hence, using numbers instead of name */ -case 249: /*R_PPC_REL16: 249 word32 (sym-.) */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - break; -case 250: /*R_PPC_REL16_LO: 250 half16 (sym-.)@l */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = (relocation & 0xffff); - break; -case 251: /*R_PPC_REL16_HI: 251 half16 (sym-.)@h */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = ((relocation >> 16) & 0xffff); - break; -case 252: /*R_PPC_REL16_HA: 252 half16 (sym-.)@ha */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -/* This is a phony reloc to handle any old fashioned TOC16 references - that may still be in object files. */ -case 255: /*R_PPC_TOC16: 255*/ - break; - -default: - tmp << "Relocation type " << rel.getRelType() - << " currently unimplemented"; - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - errMsg = tmp.str(); - return false; - } - - rewrite_printf(" relocation = 0x%lx @ 0x%lx target data 0x%lx %lx %lx %lx \n", relocation, relOffset, targetData[dest], targetData[dest+1], targetData[dest+2], targetData[dest+3]); - if (rel.getRelType() == R_PPC_REL24) { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, relocation_pos, relocation_length, relocation); - memcpy(&targetData[dest], &target, sizeof(Elf32_Word)); - } else { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, relocation_pos, relocation_length, relocation); - memcpy(&td[dest/4], &target, sizeof(Elf32_Word)); -// memcpy(&targetData[dest], r+2, relocation_size); - rewrite_printf(" relocation = 0x%lx @ 0x%lx target data 0x%lx %lx %lx %lx \n", relocation, relOffset, targetData[dest], targetData[dest+1], targetData[dest+2], targetData[dest+3]); - } - if (branch_pred >= 0) { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, 10, 1, branch_pred); - memcpy(&td[dest/4], &target, sizeof(Elf32_Word)); - } - - } else{ - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - return true; -} - -bool emitElfStatic::checkSpecialCaseSymbols(Symtab *, Symbol *) { - return true; -} - -/* The TLS implementation on ppc is Variant 1 */ - -Offset emitElfStatic::layoutTLSImage(Offset globalOffset, Region *dataTLS, Region *bssTLS, LinkMap &lmap) { - return tlsLayoutVariant1(globalOffset, dataTLS, bssTLS, lmap); -} - -Offset emitElfStatic::adjustTLSOffset(Offset curOffset, Offset tlsSize) { - return curOffset; -} - -char emitElfStatic::getPaddingValue(Region::RegionType rtype) { - // TODO: if this matters, we can noop-pad by returning an unsigned - // instead of a char... - return 0x0; -} - -void emitElfStatic::cleanupTLSRegionOffsets(map ®ionAllocs, - Region *dataTLS, Region *bssTLS) -{ - tlsCleanupVariant2(regionAllocs, dataTLS, bssTLS); -} - -static const string CTOR_NAME(".ctors"); -static const string DTOR_NAME(".dtors"); -Offset emitElfStatic::layoutNewCtorRegion(LinkMap &lmap) { - /* - * .ctors sections are processed in reverse order on Linux x86. New .ctors - * sections need to be placed before the original .ctors section - */ - - Offset retOffset = lmap.ctorRegionOffset; - retOffset += addressWidth_; - - pair::iterator, bool> result; - - for(auto reg_it = lmap.newCtorRegions.begin(); reg_it != lmap.newCtorRegions.end(); ++reg_it) { - result = lmap.regionAllocs.insert(make_pair(*reg_it, make_pair(0, retOffset))); - - // If the map already contains this Region, this is a logic error - if( !result.second ) { - return ~0UL; - } - - retOffset += (*reg_it)->getDiskSize(); - } - - if( lmap.originalCtorRegion != NULL ) { - // Account for original .ctors section (minus the header and trailer) - retOffset += lmap.originalCtorRegion->getDiskSize() - addressWidth_ - addressWidth_; - } - retOffset += addressWidth_; - - return retOffset; - - return 0; -} - -bool emitElfStatic::createNewCtorRegion(LinkMap &lmap) { - char *targetData = lmap.allocatedData; - - if( PPC32_WIDTH != addressWidth_ && PPC64_WIDTH != addressWidth_ ) { - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - unsigned trailerSize, headerSize; - - /* Give the new Region a header and trailer */ - Offset headerOffset = lmap.ctorRegionOffset; - Offset trailerOffset; - if( PPC32_WIDTH == addressWidth_ ) { - memcpy(&targetData[headerOffset], &X86_HEADER, sizeof(X86_HEADER)); - trailerOffset = lmap.ctorRegionOffset + lmap.ctorSize - sizeof(X86_TRAILER); - memcpy(&targetData[trailerOffset], &X86_TRAILER, sizeof(X86_TRAILER)); - headerSize = sizeof(X86_HEADER); - trailerSize = sizeof(X86_TRAILER); - }else{ - memcpy(&targetData[headerOffset], &X86_64_HEADER, sizeof(X86_64_HEADER)); - trailerOffset = lmap.ctorRegionOffset + lmap.ctorSize - sizeof(X86_64_TRAILER); - memcpy(&targetData[trailerOffset], &X86_64_TRAILER, sizeof(X86_64_TRAILER)); - headerSize = sizeof(X86_64_HEADER); - trailerSize = sizeof(X86_64_TRAILER); - } - - if( lmap.originalCtorRegion != NULL ) { - /* Determine where the original .ctors section should be placed */ - Offset originalOffset = lmap.ctorRegionOffset + lmap.ctorSize - - trailerSize - (lmap.originalCtorRegion->getDiskSize() - headerSize - trailerSize); - - /* Copy the original .ctors section w/o the header and trailer */ - char *rawRegionData = reinterpret_cast(lmap.originalCtorRegion->getPtrToRawData()); - memcpy(&targetData[originalOffset], &rawRegionData[headerSize], - lmap.originalCtorRegion->getDiskSize() - headerSize - trailerSize); - } - - return true; -} - - -Offset emitElfStatic::layoutNewDtorRegion(LinkMap &lmap) { - /* - * .dtors sections are processed in forward order on Linux x86. So new - * .dtors sections need to be placed after the original .dtors section - */ - - Offset retOffset = lmap.dtorRegionOffset; - retOffset += addressWidth_; - - pair::iterator, bool> result; - if( lmap.originalDtorRegion != NULL ) { - // Account for the original .dtors section (minus the header and trailer) - retOffset += lmap.originalDtorRegion->getDiskSize() - addressWidth_ - addressWidth_; - } - - for(auto reg_it = lmap.newDtorRegions.begin(); reg_it != lmap.newDtorRegions.end(); ++reg_it) { - result = lmap.regionAllocs.insert(make_pair(*reg_it, make_pair(0, retOffset))); - - // If the map already contains this Region, this is a logic error - if( !result.second ) { - return ~0UL; - } - - retOffset += (*reg_it)->getDiskSize(); - } - - retOffset += addressWidth_; - return retOffset; - - return 0; -} - -bool emitElfStatic::createNewDtorRegion(LinkMap &lmap) { - char *targetData = lmap.allocatedData; - - if( PPC32_WIDTH != addressWidth_ && PPC64_WIDTH != addressWidth_ ) { - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - unsigned headerSize, trailerSize; - - /* Give the new Region a header and trailer */ - Offset headerOffset = lmap.dtorRegionOffset; - Offset trailerOffset; - if( PPC32_WIDTH == addressWidth_ ) { - memcpy(&targetData[headerOffset], &X86_HEADER, sizeof(X86_HEADER)); - trailerOffset = lmap.dtorRegionOffset + lmap.dtorSize - sizeof(X86_TRAILER); - memcpy(&targetData[trailerOffset], &X86_TRAILER, sizeof(X86_TRAILER)); - headerSize = sizeof(X86_HEADER); - trailerSize = sizeof(X86_TRAILER); - }else{ - memcpy(&targetData[headerOffset], &X86_64_HEADER, sizeof(X86_64_HEADER)); - trailerOffset = lmap.dtorRegionOffset + lmap.dtorSize - sizeof(X86_64_TRAILER); - memcpy(&targetData[trailerOffset], &X86_64_TRAILER, sizeof(X86_64_TRAILER)); - headerSize = sizeof(X86_64_HEADER); - trailerSize = sizeof(X86_64_TRAILER); - } - - if( lmap.originalDtorRegion != NULL ) { - /* Determine where the original .dtors section should be placed */ - Offset originalOffset = lmap.dtorRegionOffset + headerSize; - - /* Copy the original .dtors section w/o header and trailer */ - char *rawRegionData = reinterpret_cast(lmap.originalDtorRegion->getPtrToRawData()); - memcpy(&targetData[originalOffset], &rawRegionData[headerSize], - lmap.originalDtorRegion->getDiskSize() - headerSize - trailerSize); - } - - return true; - -} - -bool emitElfStatic::isConstructorRegion(Region *reg) { - return ( CTOR_NAME.compare(reg->getRegionName()) == 0 ); - -} - -bool emitElfStatic::isDestructorRegion(Region *reg) { - return ( DTOR_NAME.compare(reg->getRegionName()) == 0 ); -} - -bool emitElfStatic::isGOTRegion(Region *) { - return false; -} - -bool emitElfStatic::isGOTRelocation(unsigned long relType) { - if( PPC32_WIDTH == addressWidth_ ) { - switch(relType) { - case R_PPC_GOT16: - case R_PPC_GOT16_LO: - case R_PPC_GOT16_HI: - case R_PPC_GOT16_HA: - case R_PPC_GOT_TPREL16: - case R_PPC_TLS: - return true; - break; - default: - return false; - break; - } - } else{ - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - return false; -} - -Offset emitElfStatic::getGOTSize(Symtab *, LinkMap &, Offset &) { - return 0; -} - -Offset emitElfStatic::getGOTAlign(LinkMap &) { - return 0; -} - -void emitElfStatic::buildGOT(Symtab *, LinkMap &) { -} - -void emitElfStatic::getExcludedSymbolNames(set &) { -} - -Offset emitElfStatic::allocStubRegions(LinkMap &lmap, Offset) { - // Size 0 - return lmap.stubRegionOffset; -} - -bool emitElfStatic::updateTOC(Symtab *, LinkMap &, Offset) { - return true; -} - - -bool emitElfUtils::updateRelocation(Symtab *obj, relocationEntry &rel, int library_adjust) { - // Currently, only verified on x86 and x86_64 -- this may work on other architectures - Region *targetRegion = obj->findEnclosingRegion(rel.rel_addr()); - if( NULL == targetRegion ) { - rewrite_printf("Failed to find enclosing Region for relocation"); - return false; - } - - unsigned addressWidth = obj->getAddressWidth(); - if( addressWidth == 8 ) { - switch(rel.getRelType()) { - case R_PPC64_IRELATIVE: - case R_PPC64_RELATIVE: - rel.setAddend(rel.addend() + library_adjust); - break; -/* case R_PPC64_JMP_SLOT: - * For PowerPC ABI V2, .plt is a nobit section. - * We do not need to adjust the relocation entry. - */ - default: - //fprintf(stderr, "Unimplemented relType for architecture: %d\n", rel.getRelType()); - //assert(0); - break; - } - } - - // XXX The GOT also holds a pointer to the DYNAMIC segment -- this is currently not - // updated. However, this appears to be unneeded for regular shared libraries. - - // From the SYS V ABI x86 supplement - // "The table's entry zero is reserved to hold the address of the dynamic structure, - // referenced with the symbol _DYNAMIC. This allows a program, such as the - // dynamic linker, to find its own dynamic structure without having yet processed - // its relocation entries. This is especially important for the dynamic linker, because - // it must initialize itself without relying on other programs to relocate its memory - // image." - - // In order to implement this, would have determine the final address of a new .dynamic - // section before outputting the patched GOT data -- this will require some refactoring. - - //rewrite_printf("WARNING: updateRelocation is not implemented on this architecture\n"); - //(void) obj; (void) rel; (void) library_adjust; //silence warnings - - return true; -} - diff --git a/symtabAPI/src/relocationEntry-elf-ppc32.C b/symtabAPI/src/relocationEntry-elf-ppc32.C deleted file mode 100644 index 7cee2b36c4..0000000000 --- a/symtabAPI/src/relocationEntry-elf-ppc32.C +++ /dev/null @@ -1,143 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Functions of the relocationEntry class specific to PPC ELF */ -#include "Symtab.h" -#include "annotations.h" -#include - -const char* relocationEntry::relType2Str(unsigned long r, unsigned /*addressWidth*/) { - switch(r) { - CASE_RETURN_STR(R_PPC_NONE); - CASE_RETURN_STR(R_PPC_ADDR32); - CASE_RETURN_STR(R_PPC_ADDR24); - CASE_RETURN_STR(R_PPC_ADDR16); - CASE_RETURN_STR(R_PPC_ADDR16_LO); - CASE_RETURN_STR(R_PPC_ADDR16_HI); - CASE_RETURN_STR(R_PPC_ADDR16_HA); - CASE_RETURN_STR(R_PPC_ADDR14); - CASE_RETURN_STR(R_PPC_ADDR14_BRTAKEN); - CASE_RETURN_STR(R_PPC_ADDR14_BRNTAKEN); - CASE_RETURN_STR(R_PPC_REL24); - CASE_RETURN_STR(R_PPC_REL14); - CASE_RETURN_STR(R_PPC_REL14_BRTAKEN); - CASE_RETURN_STR(R_PPC_REL14_BRNTAKEN); - CASE_RETURN_STR(R_PPC_GOT16); - CASE_RETURN_STR(R_PPC_GOT16_LO); - CASE_RETURN_STR(R_PPC_GOT16_HI); - CASE_RETURN_STR(R_PPC_GOT16_HA); - CASE_RETURN_STR(R_PPC_PLTREL24); - CASE_RETURN_STR(R_PPC_COPY); - CASE_RETURN_STR(R_PPC_GLOB_DAT); - CASE_RETURN_STR(R_PPC_JMP_SLOT); - CASE_RETURN_STR(R_PPC_RELATIVE); - CASE_RETURN_STR(R_PPC_LOCAL24PC); - CASE_RETURN_STR(R_PPC_UADDR32); - CASE_RETURN_STR(R_PPC_UADDR16); - CASE_RETURN_STR(R_PPC_REL32); - CASE_RETURN_STR(R_PPC_PLT32); - CASE_RETURN_STR(R_PPC_PLTREL32); - CASE_RETURN_STR(R_PPC_PLT16_LO); - CASE_RETURN_STR(R_PPC_PLT16_HI); - CASE_RETURN_STR(R_PPC_PLT16_HA); - CASE_RETURN_STR(R_PPC_SDAREL16); - CASE_RETURN_STR(R_PPC_SECTOFF); - CASE_RETURN_STR(R_PPC_SECTOFF_LO); - CASE_RETURN_STR(R_PPC_SECTOFF_HI); - CASE_RETURN_STR(R_PPC_SECTOFF_HA); - CASE_RETURN_STR(R_PPC_TLS); - CASE_RETURN_STR(R_PPC_DTPMOD32); - CASE_RETURN_STR(R_PPC_TPREL16); - CASE_RETURN_STR(R_PPC_TPREL16_LO); - CASE_RETURN_STR(R_PPC_TPREL16_HI); - CASE_RETURN_STR(R_PPC_TPREL16_HA); - CASE_RETURN_STR(R_PPC_TPREL32); - CASE_RETURN_STR(R_PPC_DTPREL16); - CASE_RETURN_STR(R_PPC_DTPREL16_LO); - CASE_RETURN_STR(R_PPC_DTPREL16_HI); - CASE_RETURN_STR(R_PPC_DTPREL16_HA); - CASE_RETURN_STR(R_PPC_DTPREL32); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_LO); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_HI); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_HA); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_LO); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_HI); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_HA); - CASE_RETURN_STR(R_PPC_GOT_TPREL16); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_LO); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_HI); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_HA); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_LO); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_HI); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_HA); -#if defined(R_PPC_NUM) - CASE_RETURN_STR(R_PPC_NUM); -#endif - CASE_RETURN_STR(R_PPC_EMB_NADDR32); - CASE_RETURN_STR(R_PPC_EMB_NADDR16); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_LO); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_HI); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_HA); - CASE_RETURN_STR(R_PPC_EMB_SDAI16); - CASE_RETURN_STR(R_PPC_EMB_SDA2I16); - CASE_RETURN_STR(R_PPC_EMB_SDA2REL); - CASE_RETURN_STR(R_PPC_EMB_SDA21); - CASE_RETURN_STR(R_PPC_EMB_MRKREF); - CASE_RETURN_STR(R_PPC_EMB_RELSEC16); - CASE_RETURN_STR(R_PPC_EMB_RELST_LO); - CASE_RETURN_STR(R_PPC_EMB_RELST_HI); - CASE_RETURN_STR(R_PPC_EMB_RELST_HA); - CASE_RETURN_STR(R_PPC_EMB_BIT_FLD); - CASE_RETURN_STR(R_PPC_EMB_RELSDA); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_LO); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_HI); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_HA); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_LO); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_HI); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_HA); -#ifdef R_PPC_REL16 - // Older versions of elf.h may not have these defined. - CASE_RETURN_STR(R_PPC_REL16); - CASE_RETURN_STR(R_PPC_REL16_LO); - CASE_RETURN_STR(R_PPC_REL16_HI); - CASE_RETURN_STR(R_PPC_REL16_HA); -#endif - CASE_RETURN_STR(R_PPC_TOC16); - default: - return "?"; - } -} - -SYMTAB_EXPORT unsigned long relocationEntry::getGlobalRelType(unsigned /*addressWidth*/, Symbol *) { - return R_PPC_GLOB_DAT; -} diff --git a/syscalls/README b/syscalls/README index c4e033b093..39f16970c7 100644 --- a/syscalls/README +++ b/syscalls/README @@ -1,5 +1 @@ -System header files (unistd*.h) should be placed in Platform-specific files. - -NOTE: unistd.h from Linux/ppc contains both 32- and 64-bit syscall numbers. -This file has been copied to the Arch_ppc32 and Arch_ppc64 directories and -manually edited to reflect architecture-specific system call information. +System header files (unistd*.h) should be placed in Platform-specific files. \ No newline at end of file diff --git a/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 b/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 deleted file mode 100644 index a11a6ad5a0..0000000000 --- a/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 +++ /dev/null @@ -1,334 +0,0 @@ -#ifndef _ASM_POWERPC_UNISTD_H_ -#define _ASM_POWERPC_UNISTD_H_ - -/* - * This file contains the system call numbers. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 -#define __NR_query_module 166 -#define __NR_poll 167 -#define __NR_nfsservctl 168 -#define __NR_setresgid 169 -#define __NR_getresgid 170 -#define __NR_prctl 171 -#define __NR_rt_sigreturn 172 -#define __NR_rt_sigaction 173 -#define __NR_rt_sigprocmask 174 -#define __NR_rt_sigpending 175 -#define __NR_rt_sigtimedwait 176 -#define __NR_rt_sigqueueinfo 177 -#define __NR_rt_sigsuspend 178 -#define __NR_pread64 179 -#define __NR_pwrite64 180 -#define __NR_chown 181 -#define __NR_getcwd 182 -#define __NR_capget 183 -#define __NR_capset 184 -#define __NR_sigaltstack 185 -#define __NR_sendfile 186 -#define __NR_getpmsg 187 /* some people actually want streams */ -#define __NR_putpmsg 188 /* some people actually want streams */ -#define __NR_vfork 189 -#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */ -#define __NR_readahead 191 -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_pciconfig_read 198 -#define __NR_pciconfig_write 199 -#define __NR_pciconfig_iobase 200 -#define __NR_multiplexer 201 -#define __NR_getdents64 202 -#define __NR_pivot_root 203 -#define __NR_fcntl64 204 -#define __NR_madvise 205 -#define __NR_mincore 206 -#define __NR_gettid 207 -#define __NR_tkill 208 -#define __NR_setxattr 209 -#define __NR_lsetxattr 210 -#define __NR_fsetxattr 211 -#define __NR_getxattr 212 -#define __NR_lgetxattr 213 -#define __NR_fgetxattr 214 -#define __NR_listxattr 215 -#define __NR_llistxattr 216 -#define __NR_flistxattr 217 -#define __NR_removexattr 218 -#define __NR_lremovexattr 219 -#define __NR_fremovexattr 220 -#define __NR_futex 221 -#define __NR_sched_setaffinity 222 -#define __NR_sched_getaffinity 223 -/* 224 currently unused */ -#define __NR_tuxcall 225 -#define __NR_sendfile64 226 -#define __NR_io_setup 227 -#define __NR_io_destroy 228 -#define __NR_io_getevents 229 -#define __NR_io_submit 230 -#define __NR_io_cancel 231 -#define __NR_set_tid_address 232 -#define __NR_fadvise64 233 -#define __NR_exit_group 234 -#define __NR_lookup_dcookie 235 -#define __NR_epoll_create 236 -#define __NR_epoll_ctl 237 -#define __NR_epoll_wait 238 -#define __NR_remap_file_pages 239 -#define __NR_timer_create 240 -#define __NR_timer_settime 241 -#define __NR_timer_gettime 242 -#define __NR_timer_getoverrun 243 -#define __NR_timer_delete 244 -#define __NR_clock_settime 245 -#define __NR_clock_gettime 246 -#define __NR_clock_getres 247 -#define __NR_clock_nanosleep 248 -#define __NR_swapcontext 249 -#define __NR_tgkill 250 -#define __NR_utimes 251 -#define __NR_statfs64 252 -#define __NR_fstatfs64 253 -#define __NR_fadvise64_64 254 -#define __NR_rtas 255 -#define __NR_sys_debug_setcontext 256 -/* Number 257 is reserved for vserver */ -#define __NR_migrate_pages 258 -#define __NR_mbind 259 -#define __NR_get_mempolicy 260 -#define __NR_set_mempolicy 261 -#define __NR_mq_open 262 -#define __NR_mq_unlink 263 -#define __NR_mq_timedsend 264 -#define __NR_mq_timedreceive 265 -#define __NR_mq_notify 266 -#define __NR_mq_getsetattr 267 -#define __NR_kexec_load 268 -#define __NR_add_key 269 -#define __NR_request_key 270 -#define __NR_keyctl 271 -#define __NR_waitid 272 -#define __NR_ioprio_set 273 -#define __NR_ioprio_get 274 -#define __NR_inotify_init 275 -#define __NR_inotify_add_watch 276 -#define __NR_inotify_rm_watch 277 -#define __NR_spu_run 278 -#define __NR_spu_create 279 -#define __NR_pselect6 280 -#define __NR_ppoll 281 -#define __NR_unshare 282 -#define __NR_splice 283 -#define __NR_tee 284 -#define __NR_vmsplice 285 -#define __NR_openat 286 -#define __NR_mkdirat 287 -#define __NR_mknodat 288 -#define __NR_fchownat 289 -#define __NR_futimesat 290 -#define __NR_fstatat64 291 -#define __NR_unlinkat 292 -#define __NR_renameat 293 -#define __NR_linkat 294 -#define __NR_symlinkat 295 -#define __NR_readlinkat 296 -#define __NR_fchmodat 297 -#define __NR_faccessat 298 -#define __NR_get_robust_list 299 -#define __NR_set_robust_list 300 -#define __NR_move_pages 301 -#define __NR_getcpu 302 -#define __NR_epoll_pwait 303 -#define __NR_utimensat 304 -#define __NR_signalfd 305 -#define __NR_timerfd_create 306 -#define __NR_eventfd 307 -#define __NR_sync_file_range2 308 -#define __NR_fallocate 309 -#define __NR_subpage_prot 310 -#define __NR_timerfd_settime 311 -#define __NR_timerfd_gettime 312 -#define __NR_signalfd4 313 -#define __NR_eventfd2 314 -#define __NR_epoll_create1 315 -#define __NR_dup3 316 -#define __NR_pipe2 317 -#define __NR_inotify_init1 318 - - -#endif /* _ASM_POWERPC_UNISTD_H_ */ From 0b9df83c99cf900cbb5bceae6d683b1b33b9b724 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sun, 7 Nov 2021 17:42:16 -0600 Subject: [PATCH 036/505] Remove memory emulation (#1146) This was disabled by 89919d982 in 2012. Co-authored-by: Tim Haines --- cmake/cap_arch_def.cmake | 1 - dyninstAPI/CMakeLists.txt | 3 - dyninstAPI/src/BPatch_process.C | 6 - dyninstAPI/src/MemoryEmulator/memEmulator.C | 544 ------------ dyninstAPI/src/MemoryEmulator/memEmulator.h | 116 --- .../src/MemoryEmulator/memEmulatorStub.h | 60 -- .../MemoryEmulator/memEmulatorTransformer.C | 214 ----- .../MemoryEmulator/memEmulatorTransformer.h | 87 -- .../src/MemoryEmulator/memEmulatorWidget.C | 800 ------------------ .../src/MemoryEmulator/memEmulatorWidget.h | 185 ---- .../Relocation/Transformers/Movement-adhoc.h | 2 +- .../Transformers/Movement-analysis.h | 2 +- .../src/Relocation/Widgets/CFWidget-aarch64.C | 13 - .../src/Relocation/Widgets/CFWidget-ppc.C | 15 - .../src/Relocation/Widgets/CFWidget-x86.C | 114 --- dyninstAPI/src/Relocation/Widgets/CFWidget.C | 15 +- dyninstAPI/src/Relocation/Widgets/CFWidget.h | 6 - dyninstAPI/src/addressSpace.C | 64 -- dyninstAPI/src/addressSpace.h | 14 - dyninstAPI/src/dynProcess.C | 7 - dyninstAPI/src/function.C | 1 - dyninstAPI/src/hybridCallbacks.C | 8 - dyninstAPI/src/hybridInstrumentation.C | 81 +- dyninstAPI/src/hybridOverwrites.C | 4 - dyninstAPI/src/mapped_object.C | 43 - dyninstAPI/src/pcEventHandler.C | 11 - dyninstAPI/src/pdwinnt.C | 24 - dyninstAPI_RT/CMakeLists.txt | 1 - dyninstAPI_RT/h/dyninstAPI_RT.h | 2 - dyninstAPI_RT/src/RTcommon.c | 2 - dyninstAPI_RT/src/RTmemEmulator.c | 170 ---- parseAPI/src/StackTamperVisitor.h | 2 +- 32 files changed, 6 insertions(+), 2611 deletions(-) delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulator.C delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulator.h delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulatorStub.h delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C delete mode 100644 dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h delete mode 100644 dyninstAPI_RT/src/RTmemEmulator.c diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index 5778d0a0a2..91fa984f55 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -76,7 +76,6 @@ set (BUG_DEFINES -Dbug_freebsd_missing_sigstop elseif (PLATFORM STREQUAL i386-unknown-nt4.0) set (OS_DEFINES -Dos_windows) set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_mem_emulation -Dcap_mutatee_traps ) endif (PLATFORM MATCHES linux) diff --git a/dyninstAPI/CMakeLists.txt b/dyninstAPI/CMakeLists.txt index 1b89f71d8b..518e6aacc9 100644 --- a/dyninstAPI/CMakeLists.txt +++ b/dyninstAPI/CMakeLists.txt @@ -177,9 +177,6 @@ elseif(PLATFORM MATCHES windows OR PLATFORM MATCHES nt) src/inst-winnt.C src/pdwinnt.C src/syscall-nt.C - src/MemoryEmulator/memEmulator.C - src/MemoryEmulator/memEmulatorTransformer.C - src/MemoryEmulator/memEmulatorWidget.C src/Relocation/DynAddrSpace.C src/Relocation/DynCFGMaker.C src/Relocation/DynInstrumenter.C diff --git a/dyninstAPI/src/BPatch_process.C b/dyninstAPI/src/BPatch_process.C index b331fc65a5..2085a51984 100644 --- a/dyninstAPI/src/BPatch_process.C +++ b/dyninstAPI/src/BPatch_process.C @@ -57,7 +57,6 @@ #include "parseAPI/h/CFG.h" #include "ast.h" #include "debug.h" -#include "MemoryEmulator/memEmulator.h" #include #include "PatchMgr.h" @@ -1453,11 +1452,6 @@ unsigned char * BPatch_process::makeShadowPage(Dyninst::Address pageAddr) pageAddr = (pageAddr / pagesize) * pagesize; Address shadowAddr = pageAddr; - if (llproc->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, shadowAddr) = llproc->getMemEm()->translate(pageAddr); - assert(valid); - } unsigned char* buf = (unsigned char*) ::malloc(pagesize); llproc->readDataSpace((void*)shadowAddr, pagesize, buf, true); diff --git a/dyninstAPI/src/MemoryEmulator/memEmulator.C b/dyninstAPI/src/MemoryEmulator/memEmulator.C deleted file mode 100644 index 15ddfd9440..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulator.C +++ /dev/null @@ -1,544 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "parseAPI/h/CodeObject.h" -#include "dyninstAPI/src/addressSpace.h" -#include "memEmulator.h" -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/src/image.h" -#include "symtabAPI/h/Symtab.h" -#include "symtabAPI/h/Region.h" -#include "dyninstAPI/src/dynProcess.h" -#include "dyninstAPI/src/function.h" -#include "dyninstAPI/src/debug.h" - -using namespace Dyninst; -using namespace SymtabAPI; - -bool MemoryEmulator::findMutateeTable() { - if (mutateeBase_ != 0) return true; - - std::vector memoryMapperTable; - if (!aS_->findVarsByAll("RTmemoryMapper", memoryMapperTable)) { - return false; - } - - if (memoryMapperTable.size() > 1) { - // ??? - return false; - } - mutateeBase_ = memoryMapperTable[0]->getAddress(); - return true; -} - -void MemoryEmulator::update() { - if (!findMutateeTable()) return; - - // 1) Create shadow copies for any MappedObject we - // have modified. - // 2) Update the runtime's MemoryMapper structure - // to correspond to this. - - // First step: nonblocking synchro. - int guardValue; - aS_->readDataSpace((void *)mutateeBase_, - sizeof(int), - &guardValue, - false); - guardValue++; - aS_->writeDataSpace((void *)mutateeBase_, - sizeof(int), - &guardValue); - - sensitivity_cerr << "UpdateMemEmulator: writing guard value " << guardValue << endl; - // 64->32 bit is annoying... - if (addrWidth() == 4) { - struct MemoryMapper32 newMapper; - - aS_->readDataSpace((void *)mutateeBase_, - sizeof(newMapper), - &newMapper, - false); - - // First step: - newMapper.guard1 = guardValue; - newMapper.guard2 = guardValue; - newMapper.size = memoryMap_.size(); - sensitivity_cerr << "\t new values: " << newMapper.guard1 << "/" << newMapper.guard2 << "/" << newMapper.size << endl; - std::vector elements; - memoryMap_.elements(elements); - for (unsigned i = 0; i < elements.size(); ++i) { - Address base = elements[i].first.first; - - newMapper.elements[i].lo = base; - newMapper.elements[i].hi = elements[i].first.second; - assert(newMapper.elements[i].hi > newMapper.elements[i].lo); - newMapper.elements[i].shift = elements[i].second; - } - aS_->writeDataSpace((void *)mutateeBase_, - sizeof(newMapper), - &newMapper); - - } - else { - // TODO copy - //assert(0); - } -} - -void MemoryEmulator::addAllocatedRegion(Address start, unsigned size) { - addRegion(start, size, -1); -} - -void MemoryEmulator::addRegion(mapped_object *obj) { - if (aS_->runtime_lib.find(obj) != aS_->runtime_lib.end()) - { - // Runtime library, skip - return; - } - // Add each code region - std::vector codeRegions; - obj->parse_img()->getObject()->getCodeRegions(codeRegions); - - for (unsigned i = 0; i < codeRegions.size(); ++i) { - Region *reg = codeRegions[i]; - - addRegion(reg, obj->codeBase(), 0, 0); - } -} - -void MemoryEmulator::removeRegion(mapped_object *obj) { - sensitivity_cerr << "Removing region " << obj->fileName() << endl; - sensitivity_cerr << "\t Before: " << endl; - debug(); - // Remove each code region - std::vector codeRegions; - obj->parse_img()->getObject()->getCodeRegions(codeRegions); - - for (unsigned i = 0; i < codeRegions.size(); ++i) { - Region *reg = codeRegions[i]; - - removeRegion(reg, obj->codeBase()); - } - sensitivity_cerr << "\t After: " << endl; - debug(); -} - -void MemoryEmulator::addRegion(Region *reg, Address base, Address, Address) { - - if (addedRegions_.find(reg) != addedRegions_.end()) return; - - PCProcess *proc = dynamic_cast(aS_); - char *buffer = (char *)malloc(reg->getMemSize()); - if (proc) { - if (!proc->readDataSpace((void*)(base + reg->getMemOffset()), - reg->getMemSize(), buffer, false)) { - assert(0); - } - } else { - memset(buffer, 0, reg->getMemSize()); - memcpy(buffer, reg->getPtrToRawData(), reg->getDiskSize()); - } - - unsigned long allocSize = reg->getMemSize(); - allocSize += 0x1000; - - Address mutateeBase = aS_->inferiorMalloc(allocSize); - assert(mutateeBase); - - // "Upcast" it to align with a page boundary - Kevin's request - if (proc) { - mutateeBase += proc->getMemoryPageSize(); - mutateeBase -= mutateeBase % proc->getMemoryPageSize(); - } - - aS_->writeDataSpace((void *)mutateeBase, - reg->getMemSize(), - (void *)buffer); - if (aS_->proc() && BPatch_defensiveMode == aS_->proc()->getHybridMode()) { - using namespace SymtabAPI; - PCProcess::PCMemPerm memPerm_; - Region::perm_t reg_rights = reg->getRegionPermissions(); - switch (reg_rights) { - case Region::RP_R: - memPerm_.setR(); // PAGE_READONLY; - break; - case Region::RP_RW: - memPerm_.setR().setW(); // PAGE_READWRITE; - break; - case Region::RP_RX: - memPerm_.setR().setX(); // PAGE_EXECUTE_READ; - break; - case Region::RP_RWX: - memPerm_.setR().setW().setX(); // PAGE_EXECUTE_READWRITE; - break; - default: - assert(0); - } - - PCProcess *proc = aS_->proc(); - assert(proc); - proc->stopProcess(); - proc->changeMemoryProtections(mutateeBase, reg->getMemSize(), memPerm_, false); - } - - Address regionBase = base + reg->getMemOffset(); - - addRegion(regionBase, - reg->getMemSize(), - mutateeBase - regionBase); - - - addedRegions_[reg] = std::make_pair(base + reg->getMemOffset(), mutateeBase); - free(buffer); -} - -void MemoryEmulator::removeRegion(Region *reg, Address base) { - - //cerr << "\t\t Region " << i << ": " << hex - //<< codeRegions[i]->getMemOffset() + obj->codeBase() << " -> " - //<< codeRegions[i]->getMemOffset() + codeRegions[i]->getMemSize() + obj->codeBase() << endl; - - RegionMap::iterator iter = addedRegions_.find(reg); - if (iter == addedRegions_.end()) return; - - // First, nuke our track of the springboards - springboards_.erase(reg); - - // Second, nuke it from the list of regions to copy on a sync - addedRegions_.erase(reg); - - // Deallocate the shadow pages in the mutatee - // -- this is TODO; we mangle the allocation base and therefore can't - // really call inferiorfree on it. - - // Remove the region from the translation map - removeRegion(base + reg->getMemOffset(), reg->getMemSize()); -} - -void MemoryEmulator::addRegion(Address start, unsigned size, Address shift) { - if (size == 0) return; - //debug(); - //cerr << endl; - Address end = start + size; - assert(end > start); - - // Okay. For efficiency, we want to merge this if possible with an existing - // range. We do this because our allocation tends to be contiguous. - // Two options: we're immediately above an existing range or we're immediately - // below. Check both. - - - Address lb, ub; - unsigned long val; - if (memoryMap_.find(start, lb, ub, val)) { - // This is possibly very bad. - if (start != ub) { - if ((start == lb) && - (end == ub) && - (val == shift)) { - return; - } - // Yeah, data inconsistency == bad - assert(0); - } - if (val == shift) { - // Accumulate - memoryMap_.remove(lb); - memoryMap_.insert(lb, end, shift); - return; - } - else { - memoryMap_.insert(start, end, shift); - } - } - else if (memoryMap_.find(end, lb, ub, val)) { - // See the above - if (end != ub) { - fprintf(stderr, "ERROR: adding range 0x%lx -> 0x%lx (0x%lx), found range 0x%lx -> 0x%lx (0x%lx)\n", - start, end, shift, lb, ub, val); - - assert(0); - } - if (val == shift) { - memoryMap_.remove(lb); - memoryMap_.insert(start, ub, shift); - } - else { - memoryMap_.insert(start, end, shift); - } - } - else { - memoryMap_.insert(start, end, shift); - } - - if (shift != (unsigned long) -1) { - reverseMemoryMap_.insert(start + shift, end + shift, shift); - } - //debug(); - return; -} - -void MemoryEmulator::removeRegion(Address addr, unsigned size) { - Address lb = 0, ub = 0; - unsigned long shiftVal; - - cerr << "MemoryEmulator: removing region " << hex << addr << " : " << size << dec << endl; - - //debug(); - //cerr << endl; - - Address lowLB = 0, lowUB = 0, hiLB = 0, hiUB = 0; - - // We are guaranteed to be either our own allocated range or - // coalesced with another range. - if (!memoryMap_.find(addr, lb, ub, shiftVal)) { - return; - } - - if ((lb != 0) && (lb < addr)) { - lowLB = lb; - lowUB = addr; - } - if ((ub != 0) && (ub > (addr + size))) { - hiLB = (addr + size); - hiUB = ub; - } - memoryMap_.remove(lb); - if (lowLB || lowUB) { - memoryMap_.insert(lowLB, lowUB, shiftVal); - } - if (hiLB || hiUB) { - memoryMap_.insert(hiLB, hiUB, shiftVal); - } - - reverseMemoryMap_.remove(addr + shiftVal); - //debug(); -} - -unsigned MemoryEmulator::addrWidth() { - return aS_->getAddressWidth(); -} - -std::pair MemoryEmulator::translate(Address orig) { - // Mimic the translation performed in the RT library - Address lb, ub; - unsigned long val; - if (!memoryMap_.find(orig, lb, ub, val)) { - return std::make_pair(false, 0); - } - if (val == (unsigned long) -1) { - return std::make_pair(true, orig); - } - return std::make_pair(true, orig + val); -} - -std::pair MemoryEmulator::translateBackwards(Address addr) { - // Mimic the translation performed in the RT library - Address lb, ub; - unsigned long val; - if (!reverseMemoryMap_.find(addr, lb, ub, val)) { - return std::make_pair(false, 0); - } - if (val == (unsigned long) -1) { - return std::make_pair(true, addr); - } - return std::make_pair(true, addr - val); -} - -void MemoryEmulator::synchShadowOrig(bool toOrig) -{ - - if (toOrig) { - malware_cerr << "Syncing shadow to orig" << endl; - } - else { - malware_cerr << "Syncing orig to shadow" << endl; - } - - using namespace SymtabAPI; - - for (RegionMap::iterator iter = addedRegions_.begin(); - iter != addedRegions_.end(); ++iter) { - Region * reg = iter->first; - - // We copy "source" (where we're copying from) and "target" (where we're - // copying to). We then select snippets of target (where springboards reside) - // and copy them into source, and then write source into target. - - unsigned char *source = (unsigned char*) malloc(reg->getMemSize()); - unsigned char *target = (unsigned char *) malloc(reg->getMemSize()); - - Address from = 0; - Address to = 0; - if (toOrig) { - from = iter->second.second; - to = iter->second.first; - } else { - from = iter->second.first; - to = iter->second.second; - } - - if (!aS_->readDataSpace((void *)from, - reg->getMemSize(), - source, - false)) - { - assert(0); - } - if (!aS_->readDataSpace((void *)to, - reg->getMemSize(), - target, - false)) - { - assert(0); - } - - std::map::const_iterator sit = springboards_[reg].begin(); - for (; sit != springboards_[reg].end(); sit++) { - - Address fromLB = (Address) target + sit->first; - Address toLB = (Address) source + sit->first; - memcpy((void *)toLB, (void *)fromLB, sit->second); - } - - if (!aS_->writeDataSpace((void *)to, - reg->getMemSize(), - source)) - { - assert(0); - } - free(source); - free(target); - - } - -} - - -void MemoryEmulator::addSpringboard(Region *reg, Address offset, int size) -{ - // Look up whether there is a previous springboard that overlaps with us; - // clearly, it's getting removed. - - std::map >::iterator s_iter = springboards_.find(reg); - if (s_iter == springboards_.end()) { - springboards_[reg][offset] = size; - return; - } - std::map &smap = s_iter->second; - - springboard_cerr << "Inserting SB [" << hex << offset << "," << offset + size << "]" << dec << endl; - - std::map::iterator iter = smap.find(offset); - if (iter == smap.end()) { - smap[offset] = size; - } - else if (size > iter->second) { - smap[offset] = size; - } - // Otherwise keep the current value - springboard_cerr << "\t New value: " << hex << offset << " -> " << smap[offset] + offset << dec << endl; -} - -void MemoryEmulator::removeSpringboards(func_instance * func) -{ - malware_cerr << "untracking springboards from deadfunc " << hex << func->addr() << dec << endl; - - const PatchFunction::Blockset & blocks = func->blocks(); - PatchFunction::Blockset::const_iterator bit = blocks.begin(); - for (; bit != blocks.end(); bit++) { - removeSpringboards(SCAST_BI(*bit)); - } -} - -void MemoryEmulator::removeSpringboards(const block_instance *bbi) -{ - malware_cerr << " untracking springboards from deadblock [" << hex - << bbi->start() << " " << bbi->end() << ")" << dec <llb()->region())->symRegion(); - springboards_[reg].erase(bbi->llb()->start() - reg->getMemOffset()); - if (springboards_[reg].empty()) springboards_.erase(reg); -} - -void MemoryEmulator::debug() const { - if (!dyn_debug_sensitivity) { - return; - } - std::vector elements; - memoryMap_.elements(elements); - cerr << "\t Forward map: " << endl; - for (std::vector::iterator iter = elements.begin(); iter != elements.end(); ++iter) - { - cerr << "\t\t " << hex << "[" << iter->first.first << "," << iter->first.second << "]: " << iter->second << dec << endl; -#if 0 // debug output - if (iter->first.first == 0x40d000) { - Address val; - Address addr = (iter->second + 0x40d84b); - assert(sizeof(Address) == aS_->getAddressWidth()); - Address width = aS_->getAddressWidth(); - for (Address idx=0; idx < 0x40; idx+=width) { - aS_->readDataSpace((void*)(addr+idx), width, &val, true); - cerr << hex << " " << 0x40d84b + idx << "[" << addr+idx << "]: "; - fprintf(stderr,"%2x",((unsigned char*)&val)[3]); - fprintf(stderr,"%2x",((unsigned char*)&val)[2]); - fprintf(stderr,"%2x",((unsigned char*)&val)[1]); - fprintf(stderr,"%2x\n",((unsigned char*)&val)[0]); - } - } -#endif - } - elements.clear(); - cerr << "\t Backwards map: " << endl; - reverseMemoryMap_.elements(elements); - for (std::vector::iterator iter = elements.begin(); iter != elements.end(); ++iter) - { - cerr << "\t\t " << hex << "[" << iter->first.first << "," << iter->first.second << "]: " << iter->second << dec << endl; - } - elements.clear(); - -} - -void MemoryEmulator::addPOPAD(Address addr) -{ - emulatedPOPADs_.insert(addr); -} - -bool MemoryEmulator::isEmulPOPAD(Address addr) -{ - Address orig = -1; - std::vector dontcare1; - baseTramp *dontcare2; - if (!aS_->getAddrInfo(addr, orig, dontcare1, dontcare2)) { - assert(0); - } - return emulatedPOPADs_.end() != emulatedPOPADs_.find(orig); -} diff --git a/dyninstAPI/src/MemoryEmulator/memEmulator.h b/dyninstAPI/src/MemoryEmulator/memEmulator.h deleted file mode 100644 index 422c9162ff..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulator.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(cap_mem_emulation) -#include "memEmulatorStub.h" -#else - - - -#if !defined(_MEMORY_EMULATOR_H_) -#define _MEMORY_EMULATOR_H_ - -#include "common/src/IntervalTree.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" - -class AddressSpace; -class mapped_object; -class int_variable; - -namespace Dyninst { - namespace SymtabAPI { - class Region; - }; - -class MemoryEmulator { - public: - MemoryEmulator(AddressSpace *addrSpace) - : aS_(addrSpace), mutateeBase_(0) {}; - ~MemoryEmulator() {}; - - void addAllocatedRegion(Address start, unsigned size); - void addRegion(mapped_object *obj); - void addRegion(SymtabAPI::Region *reg, Address base, Address bufferStart, Address bufferEnd); - void update(); - - void removeRegion(mapped_object *obj); - void removeRegion(SymtabAPI::Region *reg, Address base); - void removeRegion(Address start, unsigned size); - - void reprocess(mapped_object *obj); - - std::pair translate(Address addr); - std::pair translateBackwards(Address addr); - - const std::map & getSpringboards(SymtabAPI::Region*) const; - void removeSpringboards(func_instance* deadfunc); - void removeSpringboards(const block_instance* deadBBI); - void addSpringboard(SymtabAPI::Region*, - Address offset,/*from start of region*/ - int size); - void synchShadowOrig(bool toOrig); - - void addPOPAD(Address addr); - bool isEmulPOPAD(Address addr); - - static const int STACK_SHIFT_VAL=256; - - void debug() const; - - private: - void addRegion(Address start, unsigned size, Address newBase); - - - bool findMutateeTable(); - unsigned addrWidth(); - - AddressSpace *aS_; - - // Track what the address space looks like for defensive mode. - typedef IntervalTree MemoryMapTree; - MemoryMapTree memoryMap_; - MemoryMapTree reverseMemoryMap_; - - Address mutateeBase_; - - std::map > springboards_; - - // First address: original base in memory. Second address: shadow base. - typedef std::map > RegionMap; - RegionMap addedRegions_; - - std::map saved; - std::set
emulatedPOPADs_; -}; -}; - -#endif -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorStub.h b/dyninstAPI/src/MemoryEmulator/memEmulatorStub.h deleted file mode 100644 index 242dc03c6d..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorStub.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#if !defined(MEM_EMULATOR_STUB) -#define MEM_EMULATOR_STUB - -#if defined(cap_mem_emulation) -#error -#endif - -class mapped_object; - -namespace Dyninst { -class MemoryEmulator { - public: - MemoryEmulator(AddressSpace *) {} - void addSpringboard(SymtabAPI::Region *, Address, int) {} - void removeSpringboards(func_instance*) {} - void removeSpringboards(const block_instance*) {} - void addAllocatedRegion(Address, unsigned) {} - void addRegion(mapped_object *) {} - void removeRegion(Address, unsigned) {} - void removeRegion(mapped_object *) {} - void update() {} - void synchShadowOrig(bool) {} - std::pair translate(Address) { return std::make_pair(false, 0); } - std::pair translateBackwards(Address) { return std::make_pair(false, 0); } - static const int STACK_SHIFT_VAL = 0; - void debug() {} - -}; -} - -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C b/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C deleted file mode 100644 index ef056dcdbc..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C +++ /dev/null @@ -1,214 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - - -#include "dyninstAPI/src/Relocation/Transformers/Transformer.h" -#include "memEmulatorTransformer.h" -#include "dyninstAPI/src/debug.h" -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/Relocation/Widgets/InsnWidget.h" -#include "memEmulatorWidget.h" -#include "dyninstAPI/src/instPoint.h" // Memory insn modelling requirement. -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/h/BPatch_enums.h" -#include -#include "dyninstAPI/src/Relocation/CFG/RelocBlock.h" - -using namespace std; -using namespace Dyninst; -using namespace Relocation; -using namespace InstructionAPI; - - -// Replace all memory accesses to a non-statically-determinable -// location with an emulation sequence -bool MemEmulatorTransformer::process(RelocBlock *rblock, RelocGraph *rgraph) -{ - if (!(rblock->block())) return true; - - // AssignmentConverter is written in terms of parse_func, - // so translate - func_instance *func = rblock->func(); - - WidgetList &elements = rblock->elements(); - - for (WidgetList::iterator e_iter = elements.begin(); - e_iter != elements.end(); ++e_iter) { - // If we're not an instruction then skip... - InsnWidget::Ptr reloc = boost::dynamic_pointer_cast(*e_iter); - if (!reloc) continue; - - relocation_cerr << "Memory emulation considering addr " << hex << reloc->addr() << dec << endl; - - if (BPatch_defensiveMode != func->obj()->hybridMode() || !isSensitive(reloc, func, rblock->block())) { - relocation_cerr << "\t Not sensitive, skipping" << endl; - continue; - } - - if (!canRewriteMemInsn(reloc, func)) { - malware_cerr << "\tUnable to rewrite memory access at "<< hex << reloc->addr() <<": " << reloc->format() << dec << endl; - continue; - } - - Widget::Ptr replacement = createReplacement(reloc, func, rblock->block()); - if (!replacement) return false; - - (*e_iter).swap(replacement); - } - return true; -} - -bool MemEmulatorTransformer::canRewriteMemInsn(InsnWidget::Ptr reloc, - func_instance *func) { - // Let's see if this is an instruction we can rewrite; - // otherwise complain but let it through (for testing purposes) - if (override(reloc)) - return true; - - codeGen tmpGen(1024); - tmpGen.setAddrSpace(func->proc()); // needed by insn::generateMem - - instruction ugly_insn(reloc->insn()->ptr()); - if (!insnCodeGen::generateMem(tmpGen, - ugly_insn, - 0, - 0, - 0, - Null_Register)) { - return false; - } - return true; -} - -bool MemEmulatorTransformer::override(InsnWidget::Ptr reloc) { - unsigned char *buf = (unsigned char *)reloc->insn()->ptr(); - if ((unsigned char) 0xa0 <= buf[0] && - buf[0] <= (unsigned char) 0xa3) { - // Read/write with addr specified in an operand - return true; - } - const InstructionAPI::Instruction::Ptr &insn = reloc->insn(); - - const InstructionAPI::Operation &op = insn->getOperation(); - - switch(op.getID()) { - case e_scasb: - case e_scasd: - case e_scasw: - case e_lodsb: - case e_lodsd: - case e_lodsw: - case e_movsb: - case e_movsd: - case e_movsw: - case e_stosb: - case e_stosd: - case e_stosw: - case e_cmpsb: - case e_cmpsd: - case e_cmpsw: - case e_insb: - case e_insd: - case e_insw: - case e_outsb: - case e_outsd: - case e_outsw: - case e_popad: - return true; - default: - break; - } - return false; -} - -Widget::Ptr MemEmulatorTransformer::createReplacement(InsnWidget::Ptr reloc, - func_instance *func, - block_instance *block) { - // MemEmulators want instPoints. How unreasonable. - instPoint *point = instPoint::preInsn(func, block, reloc->addr(), reloc->insn(), true); - if (!point) return Widget::Ptr(); - - // Replace this instruction with a MemEmulator - Widget::Ptr memE = MemEmulator::create(reloc->insn(), - reloc->addr(), - point); - - return memE; -} - -bool MemEmulatorTransformer::isSensitive(InsnWidget::Ptr reloc, - func_instance *func, - block_instance *block) { - - parse_func *ifunc = func->ifunc(); - Address image_addr = func->addrToOffset(reloc->addr()); - - std::vector assignments; - aConverter.convert(reloc->insn(), - image_addr, - ifunc, - block->llb(), - assignments); - - for (std::vector::const_iterator a_iter = assignments.begin(); - a_iter != assignments.end(); ++a_iter) { - - const std::vector &ins = (*a_iter)->inputs(); - for (std::vector::const_iterator i = ins.begin(); - i != ins.end(); ++i) { - //relocation_cerr << "\t\t Input: " << i->format() << endl; - if (i->contains(Absloc::Heap)) { - return true; - } - if (i->absloc().type() == Absloc::Heap) { - return true; - } - } - // Writes too - //relocation_cerr << "\t\t Output: " << (*a_iter)->out().format() << endl; - if ((*a_iter)->out().contains(Absloc::Heap)) { - return true; - } - if ((*a_iter)->out().absloc().type() == Absloc::Heap) { - return true; - } - } - - return false; -} - -#if 0 -void MemEmulatorTransformer::createTranslator(Register r) { - Widget::Ptr translator = MemEmulatorTranslator::create(r); - RelocBlock::Ptr newRelocBlock = RelocBlock::create(translator); - translators_[r] = newRelocBlock; -}; -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h b/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h deleted file mode 100644 index 1e65f8ee94..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(cap_mem_emulation) -#error -#endif - -#if !defined(_R_T_EMULATE_MEMORY_H_) -#define _R_T_EMULATE_MEMORY_H_ - -#include "dyninstAPI/src/Relocation/Transformers/Transformer.h" -#include "dyninstAPI/src/Relocation/Transformers/Modification.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis -#include "dataflowAPI/h/AbslocInterface.h" // And more of the same - -class func_instance; - -namespace Dyninst { -namespace Relocation { - -class InsnWidget; - -class MemEmulatorTransformer : public Transformer { - typedef boost::shared_ptr InsnWidgetPtr; - - public: - typedef std::map TranslatorMap; - - virtual bool process(RelocBlock *, RelocGraph *); - - MemEmulatorTransformer() : - aConverter(false, false) {}; - - virtual ~MemEmulatorTransformer() {}; - - private: - - WidgetPtr createReplacement(InsnWidgetPtr reloc, - func_instance *func, block_instance *); - - bool canRewriteMemInsn(InsnWidgetPtr reloc, - func_instance *func); - - bool isSensitive(InsnWidgetPtr reloc, - func_instance *func, - block_instance *block); - - void createTranslator(Register r); - - bool override(InsnWidgetPtr reloc); - - TranslatorMap translators_; - - AssignmentConverter aConverter; - -}; -}; -}; - -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C b/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C deleted file mode 100644 index ab0173a561..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C +++ /dev/null @@ -1,800 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/Relocation/CFG/RelocTarget.h" -#include "dyninstAPI/src/Relocation/Widgets/CFWidget.h" // CFPatch - -// For our horribly horked memory effective address system -// Which I'm not fixing here. -#include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#include "dyninstAPI/h/BPatch_addressSpace.h" // bpatch_address... you get the picture -#include "dyninstAPI/h/BPatch_point.h" -// Memory hackitude -#include "dyninstAPI/src/emit-x86.h" -#include "dyninstAPI/src/inst-x86.h" - -#include "instructionAPI/h/Instruction.h" -#include "dyninstAPI/src/addressSpace.h" -#include "dyninstAPI/src/debug.h" -#include "dyninstAPI/src/registerSpace.h" -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/src/Relocation/CodeBuffer.h" -#include "common/src/arch-x86.h" - -#include "memEmulatorWidget.h" - -#include "dyninstAPI/src/RegisterConversion.h" - -#include "boost/tuple/tuple.hpp" -#include "memEmulator.h" - - -using namespace Dyninst; -using namespace Relocation; -using namespace InstructionAPI; - - -MemEmulator::Ptr MemEmulator::create(Instruction::Ptr insn, - Address addr, - instPoint *point) { - MemEmulator::Ptr ptr = MemEmulator::Ptr(new MemEmulator(insn, addr, point)); - return ptr; -} - -const int ESI_SHIFT_REG = REGNUM_EBP; -const int EDI_SHIFT_REG = REGNUM_EBX; - -bool MemEmulator::initialize(const codeGen &templ, const RelocBlock *t) { - // Number chosen arbitrarily - scratch.allocate(128); - scratch.applyTemplate(templ); - - block = t->block(); - - effAddr = Null_Register; - stackOffset = 0; - effAddrSaveOffset = 0; - usesESI = false; - usesEDI = false; - debug = false; - - return true; -} - -/* Block comment ho! - * - * - * We're trying to "emulate" the memory operation. That is, we want to redirect it - * to (or from) a shadow of original memory. In general, this is simple, using the following - * code fragment: - * - * -- EAX if it isn't read by the instruction; else ECX; else EDX. - * -- so we don't stomp on any data the program stores under the stack. - * -- eax, ecx, edx; we save all three since we don't trust liveness. - * -- see the above comment - * -- LEA so we don't harm registers - * -- EAX, and debugging arguments - * -- leaves new pointer in EAX - * - * - * - * - * - * -- via a mov instruction - * - * Now, that's the overview. But this is x86, and things get tricky. We handle the following special cases: - * 1) Push/pop - * 2) Write to (ESP) - * 3) a1-a3 implicit use of EAX - * 4) scas/ins/outs/cmps/stos/movs/lods implicit use of ESI/EDI - * - * 1) Push/pop. I believe we can structure the common code to leave ESP untouched at the memory operation time, - * which means this case is trivially solved. However, we need to be sure to restore effAddr from the right place. - * 2) Write to (ESP). See case 1) - * 3) a1-a3 implicit use of EAX. These are of the form mov eax, [mem] or mov [mem], eax; thus, we _skip_ all of - * the above complexity and just statically translate [mem]. - * 4) Implicit use of ESI/EDI (either or both). First, we need to keep two effective address registers, and we - * need to call translate twice (possibly). Second, these operations modify ESI/EDI, and we want to emulate - * that modification as well. So we do the following: - * 1) shiftESI := translate_shift(ESI) - return is the amount that esi needs to be _shifted_ to be translated. - * 2) shiftEDI := translate_shift(EDI) - * 3) ESI += shiftESI - * 4) EDI += shiftEDI - * 5) Emulate instruction - * 6) ESI -= shiftESI (note: we can't use an LEA for this, thus we sub and have to save flags) - * 7) EDI -= shiftEDI (see above) - */ - -bool MemEmulator::generate(const codeGen &templ, - const RelocBlock *t, - CodeBuffer &buffer) -{ - if (!initialize(templ, t)) return false; - - if (generateViaOverride(buffer)) - return true; - if (generateViaModRM(buffer)) - return true; - - cerr << "Error: failed to emulate memory operation @ " << hex << addr() << dec << ", " << insn()->format() << endl; - unsigned char *tmp = (unsigned char *)insn()->ptr(); - cerr << hex << "\t raw: "; - for (unsigned i = 0; i < insn()->size(); ++i) { - cerr << tmp[i]; - } - cerr << dec << endl; - assert(0); - return false; -} - -bool MemEmulator::generateViaOverride(CodeBuffer &buffer) -{ - // Watch for a0/a1/a2/a3 moves - unsigned char *buf = (unsigned char *)insn_->ptr(); - if ((unsigned char) 0xa0 <= buf[0] && - buf[0] <= (unsigned char) 0xa3) { - if (!generateEAXMove(buf[0], buffer)) - assert(0); - return true; - } - - const InstructionAPI::Operation &op = insn_->getOperation(); - switch(op.getID()) { - case e_scasb: - case e_scasd: - case e_scasw: - case e_lodsb: - case e_lodsd: - case e_lodsw: - case e_stosb: - case e_stosd: - case e_stosw: - case e_movsb: - case e_movsd: - case e_movsw: - case e_cmpsb: - case e_cmpsd: - case e_cmpsw: - case e_insb: - case e_insd: - case e_insw: - case e_outsb: - case e_outsd: - case e_outsw: - if (!generateESI_EDI(buffer)) { - assert(0); - } - return true; - break; - case e_popad: - if (!generatePOPAD(buffer)) { - assert(0); - } - return true; - break; - default: - break; - } - return false; -} - -bool MemEmulator::generateEAXMove(unsigned char opcode, - CodeBuffer &buffer) -{ - // mov [offset], eax - // We hates them. - - Address origTarget; - switch(opcode) { - case 0xa0: - case 0xa1: { - // read from memory - std::set reads; - insn_->getMemoryReadOperands(reads); - assert(reads.size() == 1); - Result res = (*(reads.begin()))->eval(); - assert(res.defined); - origTarget = res.convert
(); - break; - } - case 0xa2: - case 0xa3: { - // write - std::set writes; - insn_->getMemoryWriteOperands(writes); - assert(writes.size() == 1); - Result res = (*(writes.begin()))->eval(); - assert(res.defined); - origTarget = res.convert
(); - break; - } - default: - assert(0); - break; - } - // Map it to the new location - bool valid; Address target; - boost::tie(valid, target) = scratch.addrSpace()->getMemEm()->translate(origTarget); - if (!valid) target = origTarget; - //cerr << "Handling mov EAX, [offset]: opcode " << hex << opcode << ", orig dest " << origTarget << " and translated " << target << dec << endl; - // And emit the insn - assert(insn_->size() == 5); - GET_PTR(buf, scratch); - *buf = (char) opcode; buf++; - int *tmp = (int *)buf; - *tmp = target; tmp++; - buf = (codeBuf_t *)tmp; - SET_PTR(buf, scratch); - buffer.addPIC(scratch, tracker()); - return true; -} - -bool MemEmulator::generateViaModRM(CodeBuffer &buffer) { - // We need a BPatch_something to do the memory handling. If that's - // not present, assume we don't need to emulate this piece of - // memory. - if (!scratch.addrSpace()->up_ptr()) { - buffer.addPIC(insn_->ptr(), insn_->size(), tracker()); - assert(0); - return true; - } - - insertDebugMarker(); - - // Choose a register to hold the effective address - if (!generateModRMInitialize()) return false; - insertDebugMarker(); - // Shift the stack, save registers, calculate original effective address - if (!generateTranslatorSetup()) return false; - copyScratchToCodeBuffer(buffer); - - // Make the call to the translation function - if (!generateTranslatorCall(buffer)) return false; - // Teardown the call saves - insertDebugMarker(); - if (!generateTranslatorTeardown()) return false; - insertDebugMarker(); - - copyScratchToCodeBuffer(buffer); - - return true; -} - -void MemEmulator::insertDebugMarker() { - if (debug || (dyn_debug_trap /*&& addr() > 0xab000 && addr() <0xad000*/)) - scratch.fill(1, codeGen::cgTrap); -} - -bool MemEmulator::generateModRMInitialize() { - // Placeholder for good code design... - - return true; -} - -bool MemEmulator::generateTranslatorSetup() { - // Our job: - // Shift the stack down - // Decide who will hold the effective address - // Save caller-save registers - // Calculate the original effective address - // Save flags - - if (!shiftStack()) return false; - if (!determineEffAddr()) return false; - if (!saveRegisters()) return false; - if (!calculateEffAddr()) return false; - if (!saveFlags()) return false; - - return true; -} - -bool MemEmulator::generateTranslatorCall(CodeBuffer &buffer) { - - // This is easy. We don't know where we are, - // so we have to use the patch mechanic, but that's - // not too bad. - // We also set up the arguments in the patch code so that we - // have access to the current address (for debugging purposes) - - Address target = getTranslatorAddr(false); - if (!target) return false; - buffer.addPatch(new MemEmulatorPatch(effAddr, effAddr, addr_, target), tracker()); - return true; -} - -bool MemEmulator::generateTranslatorTeardown() { - // Restore flags - // Restore registers (except effAddr) - // Shift stack back up - // Emulate memory operation - // Restore effAddr - insertDebugMarker(); - if (!restoreFlags()) return false; - insertDebugMarker(); - if (!restoreRegisters()) return false; - insertDebugMarker(); - if (!restoreStack()) return false; - insertDebugMarker(); - if (!emulateOriginalInstruction()) return false; - if (!restoreEffectiveAddr()) return false; - - return true; -} - -bool MemEmulator::shiftStack() { - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, -1*MemoryEmulator::STACK_SHIFT_VAL, RealRegister(REGNUM_ESP), scratch); - stackOffset -= MemoryEmulator::STACK_SHIFT_VAL; - return true; -} - -bool MemEmulator::determineEffAddr() { - // We want to use whichever register isn't used by the instruction. - // Technically, _written_ by the instruction. As that would be silly. - - // Theory: we can always use either ECX or EDX, as they're getting saved - // anyway. - - // We can use a register if it's only used for a memory operand. We cannot use - // it if it's directly used, either mov [ptr], reg or mov reg, [ptr]. - // Technically, we could do mov reg, [ptr] so long as we don't restore reg. - // I'm not too worried, though. - - static RegisterAST::Ptr ecx = RegisterAST::Ptr(new RegisterAST(x86::ecx)); - static RegisterAST::Ptr edx = RegisterAST::Ptr(new RegisterAST(x86::edx)); - - bool useECX = true; - bool useEDX = true; - std::vector operands; - insn_->getOperands(operands); - for (unsigned i = 0; i < operands.size(); ++i) { - if (operands[i].readsMemory()) continue; - if (operands[i].writesMemory()) continue; - if (operands[i].isRead(ecx) || operands[i].isWritten(ecx)) useECX = false; - if (operands[i].isRead(edx) || operands[i].isWritten(edx)) useEDX = false; - } - - if (useECX) { - effAddr = REGNUM_ECX; - } - if (useEDX) { - effAddr = REGNUM_EDX; - } - - block->obj()->addEmulInsn(addr(),effAddr); - - return (useECX || useEDX); -} - -bool MemEmulator::saveRegisters() { - // Theoretically we could use liveness to determine - // whether to save a register or not. - // We want to save the effAddr register _first_ to make - // our lives easier. - if (effAddr == REGNUM_ECX) { - push(REGNUM_ECX); - effAddrSaveOffset = stackOffset; - push(REGNUM_EDX); - } - else { - push(REGNUM_EDX); - effAddrSaveOffset = stackOffset; - push(REGNUM_ECX); - } - push(REGNUM_EAX); - - return true; -} - - -bool MemEmulator::calculateEffAddr() { - // Luckily, we have code to do this already. - assert(scratch.addrSpace()); - BPatch_addressSpace *bproc = (BPatch_addressSpace *)scratch.addrSpace()->up_ptr(); - assert(bproc); - - assert(point_); - BPatch_point *bpoint = bproc->findOrCreateBPPoint(NULL, point_, BPatch_locInstruction); - if (bpoint == NULL) { - fprintf(stderr, "ERROR: Unable to find BPatch point for internal point %p/0x%lx\n", - point_, addr_); - return false; - } - const BPatch_memoryAccess *ma = bpoint->getMemoryAccess(); - - const BPatch_addrSpec_NP *start = ma->getStartAddr(0); // Guessing on 0, here... - - // Now that we've done all the background work, we can emit an LEA to grab the - // effective address. - // The stackOffset parameter is a magic "if you used ESP, be sure to take into - // account the fact we movled it". - emitASload(start, effAddr, stackOffset, scratch, true); - - return true; -} - -bool MemEmulator::saveFlags() { - // nice thing is, eax is already saved at this point. So our live, it be easy. - emitSimpleInsn(0x9f, scratch); - emitSaveO(scratch); - - push(REGNUM_EAX); - return true; -} - -bool MemEmulator::restoreFlags() { - pop(REGNUM_EAX); - - emitRestoreO(scratch); - emitSimpleInsn(0x9E, scratch); - - return true; -} - -bool MemEmulator::restoreRegisters() { - // Order needs to match that in saveRegisters - // Also, don't restore over effAddr. Yet. - pop(REGNUM_EAX); - if (effAddr == REGNUM_ECX) - pop(REGNUM_EDX); - else - pop(REGNUM_ECX); - return true; -} - -bool MemEmulator::restoreStack() { - // We track stack depth in the stackOffset - // parameter... - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, -1*stackOffset, RealRegister(REGNUM_ESP), scratch); - stackOffset = 0; - return true; -} - -using namespace NS_x86; - -bool MemEmulator::emulateOriginalInstruction() { - NS_x86::instruction ugly_insn(insn_->ptr()); - - if (!insnCodeGen::generateMem(scratch, - ugly_insn, - 0, // ignored - 0, // ignored - effAddr, - Null_Register)) - return false; - - // Do we mess with the stack pointer? - if (insn_->getOperation().getID() == e_push) { - stackOffset -= 4; - } - if (insn_->getOperation().getID() == e_pop) { - stackOffset += 4; - } - - return true; -} - -bool MemEmulator::restoreEffectiveAddr() { - // We want to pull it out of wherever it is on the stack - // We could LEA esp down, pop, and back up. But really. - // Instead, use a mov. - int restoreOffset = (effAddrSaveOffset - stackOffset); - - ::emitMovRMToReg(RealRegister(effAddr), RealRegister(REGNUM_ESP), restoreOffset, scratch); - return true; -} - -bool MemEmulator::copyScratchToCodeBuffer(CodeBuffer &buffer) { - // Copy it in and re-initialize the scratch buffer to hold more - // goodies. - if (scratch.used() == 0) return true; - - buffer.addPIC(scratch, tracker()); - - scratch.allocate(128); - return true; -} - -TrackerElement *MemEmulator::tracker() const { - EmulatorTracker *e = new EmulatorTracker(addr_, block, point_->func()); - return e; -} - -bool MemEmulator::push(Register reg) { - ::emitPush(RealRegister(reg), scratch); - stackOffset -= 4; - return true; -} - -bool MemEmulator::pop(Register reg) { - ::emitPop(RealRegister(reg), scratch); - stackOffset += 4; - return true; -} - -// wrap whole thing in check that esp is outside of the stack segment? -bool MemEmulator::generatePOPAD(CodeBuffer &buffer) { - point_->func()->proc()->getMemEm()->addPOPAD(addr()); - scratch.fill(1, codeGen::cgTrap); - buffer.addPIC(scratch, tracker()); - return true; -} - -/* Block quote redux! - * - * We need to: - * 1) Determine if we use ESI, EDI, or both; - * 2) Shift the stack - * 3) Retain a register (ECX) for the "shift" involved in translating ESI - * (that is, tESI = ESI + ECX) - * 4) Do the same for EDI/EDX - * 5) Save caller-saved registers - * 6) Save the flags - * 7) If using ESI, ECX := shift(ESI) - * 8) If using ESI, ESI += ECX - * 9) If using EDI, EDX := shift(EDI) - * 10) If using EDI, EDI += EDX - * 11) Restore flags and EAX. The "EAX" is very important. - * 12) Run the instruction - * 13) Save EAX and flags (again) - * 14) If using ESI, ESI -= ECX - * 15) If using EDI, EDI -= EDX - * 16) Restore EAX and flags - * 17) Restore the stack. - */ - -bool MemEmulator::generateESI_EDI(CodeBuffer &buffer) { - if (!determineESI_EDIUse()) return false; - - insertDebugMarker(); - - if (!shiftStack()) return false; - - if (!saveRegistersESI_EDI()) return false; - - if (!saveFlags()) return false; - - copyScratchToCodeBuffer(buffer); - - if (usesESI && !generateESIShift(buffer)) return false; - if (usesEDI && !generateEDIShift(buffer)) return false; - - if (!saveShiftsAndRestoreRegs()) return false; - - insertDebugMarker(); - if (!emulateOriginalESI_EDI()) return false; - if (!emulateESI_EDIValues()) return false; - if (!restoreAllRegistersESI_EDI()) return false; - if (!restoreStack()) return false; - assert(stackOffset == 0); - insertDebugMarker(); - - copyScratchToCodeBuffer(buffer); - - return true; -} - - -bool MemEmulator::determineESI_EDIUse() { - const InstructionAPI::Operation &op = insn_->getOperation(); - - switch(op.getID()) { - case e_insb: - case e_insd: - case e_insw: - usesEDI = true; - break; - case e_movsb: - case e_movsd: - case e_movsw: - usesESI = true; - usesEDI = true; - break; - case e_outsb: - case e_outsd: - case e_outsw: - usesESI = true; - break; - case e_lodsb: - case e_lodsd: - case e_lodsw: - usesESI = true; - break; - case e_stosb: - case e_stosd: - case e_stosw: - usesEDI = true; - break; - case e_cmpsb: - case e_cmpsw: - case e_cmpsd: - usesESI = true; - usesEDI = true; - break; - case e_scasb: - case e_scasd: - case e_scasw: - usesEDI = true; - break; - default: - assert(0); - break; - } - return true; -} - -bool MemEmulator::saveRegistersESI_EDI() { - // Always save EAX, but save it last - // so that it's easy to access. - - // We use EBX/EBP to hold shift values so that we can restore EA/C/DX pre-instruction - - push(REGNUM_EBX); - push(REGNUM_EBP); - - push(REGNUM_EDX); - push(REGNUM_ECX); - push(REGNUM_EAX); - return true; -} - -bool MemEmulator::generateESIShift(CodeBuffer &buffer) { - Address destination = getTranslatorAddr(true); - if (!destination) return false; - buffer.addPatch(new MemEmulatorPatch(REGNUM_ESI, ESI_SHIFT_REG, addr_, destination), tracker()); - - // Also, set up ESI to have the right value - ::emitLEA(RealRegister(REGNUM_ESI), RealRegister(ESI_SHIFT_REG), 0, 0, RealRegister(REGNUM_ESI), scratch); - copyScratchToCodeBuffer(buffer); - - return true; -} - -bool MemEmulator::generateEDIShift(CodeBuffer &buffer) { - Address destination = getTranslatorAddr(true); - if (!destination) return false; - buffer.addPatch(new MemEmulatorPatch(REGNUM_EDI, EDI_SHIFT_REG, addr_, destination), tracker()); - - ::emitLEA(RealRegister(REGNUM_EDI), RealRegister(EDI_SHIFT_REG), 0, 0, RealRegister(REGNUM_EDI), scratch); - - copyScratchToCodeBuffer(buffer); - - return true; -} - -bool MemEmulator::saveShiftsAndRestoreRegs() { - // Several instructions implicitly use EAX, and the REP prefix can use ECX. - - // Currently the stack looks like this: - // - // EBX - // EBP - // EDX - // ECX - // EAX - // Flags - - // We want it to look like this: - // - // EBX - // EBP - - if (!restoreFlags()) return false; - pop(REGNUM_EAX); - pop(REGNUM_ECX); - pop(REGNUM_EDX); - - return true; -} - -bool MemEmulator::emulateOriginalESI_EDI() { - scratch.copy(insn_->ptr(), insn_->size()); - return true; -} - -bool MemEmulator::emulateESI_EDIValues() { - // We need to: - // EDI -= EDX - // ESI -= ECX - // And "subtract" means "save the flags" - // ... which in turn means "save eax, fool" - push(REGNUM_EAX); - saveFlags(); - - if (usesESI) ::emitSubRegReg(RealRegister(REGNUM_ESI), RealRegister(ESI_SHIFT_REG), scratch); - if (usesEDI) ::emitSubRegReg(RealRegister(REGNUM_EDI), RealRegister(EDI_SHIFT_REG), scratch); - - restoreFlags(); - pop(REGNUM_EAX); - return true; -} - -bool MemEmulator::restoreAllRegistersESI_EDI() { - - pop(REGNUM_EBP); - pop(REGNUM_EBX); - return true; -} - -string MemEmulator::format() const { - stringstream ret; - ret << "MemE(" << insn_->format() - << "," << std::hex << addr_ << std::dec - << ")"; - - return ret.str(); -} - -Address MemEmulator::getTranslatorAddr(bool wantShift) { - if (wantShift) { - // Function lookup time - func_instance *func = scratch.addrSpace()->findOnlyOneFunction("RTtranslateMemoryShift"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - if (!func) return 0; - // assert(func); - return func->addr(); - } - else { - // Function lookup time - func_instance *func = scratch.addrSpace()->findOnlyOneFunction("RTtranslateMemory"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - if (!func) return 0; - // assert(func); - return func->addr(); - } -} - -bool MemEmulatorPatch::apply(codeGen &gen, - CodeBuffer *) { - relocation_cerr << "MemEmulatorPatch::apply @ " << hex << gen.currAddr() << dec << endl; - relocation_cerr << "\tSource reg " << source_ << endl; - assert(!gen.bt()); - - // Two debugging assists - ::emitPushImm(gen.currAddr(), gen); - ::emitPushImm(orig_, gen); - // And our argument - ::emitPush(RealRegister(source_), gen); - - // Step 2: call the translator - Address src = gen.currAddr() + 5; - relocation_cerr << "\tCall " << hex << dest_ << ", offset " << dest_ - src << dec << endl; - assert(dest_); - emitCallRel32(dest_ - src, gen); - if (target_ != REGNUM_EAX) - { - ::emitMovRegToReg(RealRegister(target_), RealRegister(REGNUM_EAX), gen); - } - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, 12, RealRegister(REGNUM_ESP), gen); - - return true; -} - diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h b/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h deleted file mode 100644 index 853b3e05b6..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(cap_mem_emulation) -#error -#endif - - -#if !defined (_R_E_MEM_EMULATOR_H_) -#define _R_E_MEM_EMULATOR_H_ - -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/codegen.h" -#include -class registerSlot; - - -namespace Dyninst { -namespace Relocation { - -class MemEmulatorTranslator; - -class MemEmulator : public Widget { - friend class MemEmulatorTranslator; - typedef std::map TranslatorMap; - public: - typedef boost::shared_ptr Ptr; - - static Ptr create(InstructionAPI::Instruction::Ptr insn, - Address addr, - instPoint *point); - - virtual bool generate(const codeGen &, const RelocBlock *, CodeBuffer &); - - virtual ~MemEmulator() {}; - virtual std::string format() const; - - virtual Address addr() const { return addr_; } - virtual unsigned size() const { return insn_->size(); } - virtual InstructionAPI::Instruction::Ptr insn() const { return insn_; } - - private: - MemEmulator(InstructionAPI::Instruction::Ptr insn, - Address addr, - instPoint *point) - : insn_(insn), - addr_(addr), - point_(point) - {}; - - // Set up the codeGen structures we use to hold code. - bool initialize(const codeGen &templ, const RelocBlock *); - - // Handle a0-a3 implicit EAX uses, or ESI/EDI instructions - bool generateViaOverride(CodeBuffer &buffer); - - // Handle generic MOD/RM using instructions - bool generateViaModRM(CodeBuffer &buffer); - - // Handle a0-a3 implicit EAX moves - bool generateEAXMove(unsigned char opcode, CodeBuffer &buffer); - - // Handle ESI/EDI instructions - bool generateESI_EDI(CodeBuffer &buffer); - - // Handle POPAD instructions - bool generatePOPAD(CodeBuffer &buffer); - - // Drop in a trap for later debugging assistance - void insertDebugMarker(); - - // Initialize mod/rm specific data - bool generateModRMInitialize(); - // Create the pre-call handling for MOD/RM instructions - bool generateTranslatorSetup(); - // Create the call to the translator function - bool generateTranslatorCall(CodeBuffer &buffer); - // Create the teardown code - bool generateTranslatorTeardown(); - - // Move the stack down by a known amount - bool shiftStack(); - // Determine which register we can use for the effective address - bool determineEffAddr(); - // Save eax/ecx/edx - bool saveRegisters(); - // Run the effective address calculation before we modify anything (except the stack pointer, sigh) - bool calculateEffAddr(); - // Save the flags - bool saveFlags(); - - // Restore flags after the call - bool restoreFlags(); - // Restore caller-saved registers (except effAddr) - bool restoreRegisters(); - // Restore the stack - bool restoreStack(); - // Emulate the original instruction using effAddr instead of the original expression - bool emulateOriginalInstruction(); - // And restore the effective address register - bool restoreEffectiveAddr(); - - // ESI/EDI implicit shtuff - bool determineESI_EDIUse(); - bool saveRegistersESI_EDI(); // Almost, but not quite the same as saveRegisters. Yuck. - bool generateESIShift(CodeBuffer &buffer); - bool generateEDIShift(CodeBuffer &buffer); - bool saveShiftsAndRestoreRegs(); - bool emulateOriginalESI_EDI(); - bool emulateESI_EDIValues(); - bool restoreAllRegistersESI_EDI(); - - // Copy code into the CodeBuffer (and reset the scratch codegen) - bool copyScratchToCodeBuffer(CodeBuffer &); - TrackerElement *tracker() const; - bool push(Register); - bool pop(Register); - Address getTranslatorAddr(bool wantShiftFunc); - - - /// Members - Register effAddr; - int stackOffset; - int effAddrSaveOffset; - block_instance *block; - - bool usesESI; - bool usesEDI; - - codeGen scratch; - bool debug; - - InstructionAPI::Instruction::Ptr insn_; - Address addr_; - instPoint *point_; -}; - -struct MemEmulatorPatch : public Patch { - // Put in a call to the RTtranslateMemory - // function - MemEmulatorPatch(Register s, - Register t, - Address o, - Address d) - : source_(s), target_(t), orig_(o), dest_(d) {}; - virtual bool apply(codeGen &gen, CodeBuffer *buf); - virtual unsigned estimate(codeGen &) { return 7; }; - virtual ~MemEmulatorPatch() {}; - - Register source_; - Register target_; - Address orig_; - Address dest_; -}; - -}; -}; -#endif diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h index d5b6ddb988..1670545ec3 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h +++ b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h @@ -35,7 +35,7 @@ class AddressSpace; #include "Transformer.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dyninstAPI/src/function.h" diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h index add95fdaa7..d57fc3fa4d 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h +++ b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h @@ -34,7 +34,7 @@ #include "Transformer.h" #include "dyninstAPI/src/LinearVariable.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/AbslocInterface.h" // And more of the same #include "common/h/Graph.h" // PC-sensitive transformer diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C index 5de3d558cd..ba0fee07ec 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C @@ -219,16 +219,3 @@ bool CFPatch::handleTOCUpdate(codeGen &gen) { } */ -bool CFWidget::generateAddressTranslator(CodeBuffer &/*buffer*/, - const codeGen &/*templ*/, - Register &/*reg*/, - const RelocBlock */*trace*/) { -#if !defined(cap_mem_emulation) - return true; -#else - assert(0); - return false; -#endif - -} - diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C index b9bab37c04..cba4cde2c3 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C @@ -283,18 +283,3 @@ bool CFPatch::handleTOCUpdate(codeGen &gen) { return false; } } - -bool CFWidget::generateAddressTranslator(CodeBuffer & /*buffer*/, - const codeGen & /*templ*/, - Register & /*reg*/, - const RelocBlock * /*trace*/) -{ -#if !defined(cap_mem_emulation) - return true; -#else - assert(0); - return false; -#endif - -} - diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C index 0cb91f46ec..caec2b5504 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C @@ -46,10 +46,6 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#if defined(cap_mem_emulation) -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#endif - using namespace Dyninst; using namespace Relocation; using namespace InstructionAPI; @@ -293,113 +289,3 @@ bool CFPatch::applyPLT(codeGen &gen, CodeBuffer *) { return true; } - -#if !defined(cap_mem_emulation) -bool CFWidget::generateAddressTranslator(CodeBuffer &,const codeGen &,Register &,const RelocBlock *) { - return true; -} -#else -bool CFWidget::generateAddressTranslator(CodeBuffer &buffer, - const codeGen &templ, - Register ®, - const RelocBlock *trace) -{ - if (!templ.addrSpace()->isMemoryEmulated() || - BPatch_defensiveMode != trace->block()->obj()->hybridMode()) - return true; - - if (insn_->getOperation().getID() == e_ret_near || - insn_->getOperation().getID() == e_ret_far) { - // Oops! - return true; - } - if (!insn_->readsMemory()) { - return true; - } - - BPatch_memoryAccessAdapter converter; - BPatch_memoryAccess *acc = converter.convert(insn_, addr_, false); - if (!acc) { - reg = Null_Register; - return true; - } - - codeGen patch(128); - patch.applyTemplate(templ); - - // TODO: we probably want this in a form that doesn't stomp the stack... - // But we can probably get away with this for now. Check that. - - // step 1: create space on the stack. - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // step 2: save registers that will be affected by the call - ::emitPush(RealRegister(REGNUM_ECX), patch); - ::emitPush(RealRegister(REGNUM_EDX), patch); - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // Step 3: LEA this sucker into ECX. - const BPatch_addrSpec_NP *start = acc->getStartAddr(0); - if (start->getReg(0) == REGNUM_ESP || - start->getReg(1) == REGNUM_ESP) { - cerr << "ERROR: CF insn that uses the stack pointer! " << insn_->format() << endl; - } - - int stackShift = -16; - // If we are a call _instruction_ but isCall is false, then we've got an extra word - // on the stack from an emulated return address - if (!isCall_ && insn_->getCategory() == c_CallInsn) stackShift -= 4; - - emitASload(start, REGNUM_ECX, stackShift, patch, true); - - // Step 4: save flags post-LEA - emitSimpleInsn(0x9f, patch); - emitSaveO(patch); - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // This might look a lot like a memEmulatorWidget. That's, well, because it - // is. - buffer.addPIC(patch, tracker(trace)); - - // Where are we going? - func_instance *func = templ.addrSpace()->findOnlyOneFunction("RTtranslateMemory"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - assert(func); - - // Now we start stealing from memEmulatorWidget. We need to call our translation function, - // which means a non-PIC patch to the CodeBuffer. I don't feel like rewriting everything, - // so there we go. - buffer.addPatch(new MemEmulatorPatch(REGNUM_ECX, REGNUM_ECX, addr_, func->addr()), - tracker(trace)); - patch.setIndex(0); - - // Restore flags - ::emitPop(RealRegister(REGNUM_EAX), patch); - emitRestoreO(patch); - emitSimpleInsn(0x9E, patch); - ::emitPop(RealRegister(REGNUM_EAX), patch); - ::emitPop(RealRegister(REGNUM_EDX), patch); - - // ECX now holds the pointer to the destination... - // Dereference - ::emitMovRMToReg(RealRegister(REGNUM_ECX), - RealRegister(REGNUM_ECX), - 0, - patch); - - // ECX now holds the _actual_ destination, so move it on to the stack. - // We've got ECX saved - ::emitMovRegToRM(RealRegister(REGNUM_ESP), - 1*4, - RealRegister(REGNUM_ECX), - patch); - ::emitPop(RealRegister(REGNUM_ECX), patch); - // And tell our people to use the top of the stack - // for their work. - // TODO: trust liveness and leave this in a register. - - buffer.addPIC(patch, tracker(trace)); - reg = REGNUM_ESP; - return true; -} -#endif diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget.C b/dyninstAPI/src/Relocation/Widgets/CFWidget.C index e1b2e6e1ca..8c6b8efccc 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget.C @@ -38,14 +38,6 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/src/debug.h" -#if defined(cap_mem_emulation) -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#include "dyninstAPI/src/BPatch_memoryAccessAdapter.h" -#include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#include "dyninstAPI/src/registerSpace.h" -#endif - #include "../dyninstAPI/src/debug.h" #include "../CodeTracker.h" @@ -133,7 +125,7 @@ CFWidget::CFWidget(InstructionAPI::Instruction insn, Address addr) : } -bool CFWidget::generate(const codeGen &templ, +bool CFWidget::generate(const codeGen &, const RelocBlock *trace, CodeBuffer &buffer) { @@ -269,10 +261,7 @@ bool CFWidget::generate(const codeGen &templ, } case Indirect: { Register reg = Null_Register; /* = originalRegister... */ - // Originally for use in helping with jump tables, I'm taking - // this for the memory emulation effort. Huzzah! - if (!generateAddressTranslator(buffer, templ, reg, trace)) - return false; + // If this is an indirect tail call, we still treat it // as an indirect call if (isCall_ || trace->block()->llb()->isIndirectTailCallBlock()) { diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget.h b/dyninstAPI/src/Relocation/Widgets/CFWidget.h index e9a4cd714a..d903a1f143 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget.h @@ -187,12 +187,6 @@ class CFWidget : public Widget { InstructionAPI::Instruction insn, const RelocBlock *trace, Address origAddr); - - bool generateAddressTranslator(CodeBuffer &buffer, - const codeGen &templ, - Register ®, - const RelocBlock *trace); - }; struct CFPatch : public Patch { diff --git a/dyninstAPI/src/addressSpace.C b/dyninstAPI/src/addressSpace.C index 466219a9dc..022d8c2308 100644 --- a/dyninstAPI/src/addressSpace.C +++ b/dyninstAPI/src/addressSpace.C @@ -50,7 +50,6 @@ #include "Relocation/Transformers/Include.h" #include "Relocation/CodeTracker.h" -#include "MemoryEmulator/memEmulator.h" #include "parseAPI/h/CodeObject.h" #include @@ -89,20 +88,8 @@ AddressSpace::AddressSpace () : up_ptr_(NULL), costAddr_(0), installedSpringboards_(new Relocation::InstalledSpringboards()), - memEmulator_(NULL), - emulateMem_(false), - emulatePC_(false), delayRelocation_(false) { -#if 0 - // Disabled for now; used by defensive mode - if ( getenv("DYNINST_EMULATE_MEMORY") ) { - printf("emulating memory & pc\n"); - memEmulator_ = new MemoryEmulator(this); - emulateMem_ = true; - emulatePC_ = true; - } -#endif // Historically, we only use SIGTRAP as the signal for tramopline. // However, SIGTRAP is always intercepted by GDB, causing it is // almost impossible to debug through signal trampolines. @@ -116,8 +103,6 @@ AddressSpace::AddressSpace () : } AddressSpace::~AddressSpace() { - if (memEmulator_) - delete memEmulator_; if (mgr_) static_cast(mgr_->as())->removeAddrSpace(this); @@ -235,10 +220,6 @@ void AddressSpace::copyAddressSpace(AddressSpace *parent) { func_instance *to = findFunction(SCAST_FI(iter->second.first)->ifunc()); fwm[from] = std::make_pair(to, iter->second.second); } - - if (memEmulator_) assert(0 && "FIXME!"); - emulateMem_ = parent->emulateMem_; - emulatePC_ = parent->emulatePC_; } void AddressSpace::deleteAddressSpace() { @@ -271,9 +252,6 @@ void AddressSpace::deleteAddressSpace() { // up_ptr_ is untouched costAddr_ = 0; - - if (memEmulator_) delete memEmulator_; - memEmulator_ = NULL; } @@ -396,10 +374,6 @@ void AddressSpace::addHeap(heapItem *h) { std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), ptr_fun(heapItemLessByAddr)); heap_.totalFreeMemAvailable += h2->length; - - if (h->dynamic) { - addAllocatedRegion(h->addr, h->length); - } } void AddressSpace::initializeHeap() { @@ -1711,8 +1685,6 @@ bool AddressSpace::relocate() { modFuncs = actualModFuncs; } - addModifiedRegion(iter->first); - Address middle = (iter->first->codeAbs() + (iter->first->imageSize() / 2)); if (!relocateInt(iter->second.begin(), iter->second.end(), middle)) { @@ -1724,7 +1696,6 @@ bool AddressSpace::relocate() { - updateMemEmulator(); modifiedFunctions_.clear(); @@ -1876,13 +1847,6 @@ bool AddressSpace::transform(CodeMover::Ptr cm) { cm->transform(pc); } -#if defined(cap_mem_emulation) - if (emulateMem_) { - MemEmulatorTransformer m; - cm->transform(m); - } -#endif - // Add instrumentation relocation_cerr << "Inst transformer" << endl; Instrumenter i; @@ -1996,17 +1960,6 @@ bool AddressSpace::patchCode(CodeMover::Ptr cm, // HACK: code modification will make this happen... return false; } - - mapped_object *obj = findObject(iter->startAddr()); - if (obj && runtime_lib.end() == runtime_lib.find(obj)) { - Address objBase = obj->codeBase(); - SymtabAPI::Region * reg = obj->parse_img()->getObject()-> - findEnclosingRegion(iter->startAddr() - objBase); - if (memEmulator_) - memEmulator_->addSpringboard(reg, - iter->startAddr() - objBase - reg->getMemOffset(), - iter->used()); - } } return true; @@ -2156,23 +2109,6 @@ void AddressSpace::addInstrumentationInstance(baseTramp *bt, instrumentationInstances_[bt].insert(a); } -void AddressSpace::addAllocatedRegion(Address start, unsigned size) { - if (memEmulator_) memEmulator_->addAllocatedRegion(start, size); -} - -void AddressSpace::addModifiedRegion(mapped_object *obj) { - if (memEmulator_) memEmulator_->addRegion(obj); - return; -} - -void AddressSpace::updateMemEmulator() { - if (memEmulator_) memEmulator_->update(); -} - -MemoryEmulator * AddressSpace::getMemEm() { - return memEmulator_; -} - void updateSrcListAndVisited(ParseAPI::Edge* e, std::list& srcList, std::set& visited) diff --git a/dyninstAPI/src/addressSpace.h b/dyninstAPI/src/addressSpace.h index f00e04a4ef..e0639dfa4f 100644 --- a/dyninstAPI/src/addressSpace.h +++ b/dyninstAPI/src/addressSpace.h @@ -88,7 +88,6 @@ class trampTrapMappings; class baseTramp; namespace Dyninst { - class MemoryEmulator; namespace InstructionAPI { class Instruction; @@ -485,11 +484,6 @@ class AddressSpace : public InstructionSource { void addModifiedFunction(func_instance *func); void addModifiedBlock(block_instance *block); - void updateMemEmulator(); - bool isMemoryEmulated() { return emulateMem_; } - bool emulatingPC() { return emulatePC_; } - MemoryEmulator *getMemEm(); - bool delayRelocation() const; protected: @@ -552,14 +546,6 @@ class AddressSpace : public InstructionSource { // FuncModMap functionReplacements_; // FuncModMap functionWraps_; - void addAllocatedRegion(Address start, unsigned size); - void addModifiedRegion(mapped_object *obj); - - MemoryEmulator *memEmulator_; - - bool emulateMem_; - bool emulatePC_; - bool delayRelocation_; std::map wrappedFunctionWorklist_; diff --git a/dyninstAPI/src/dynProcess.C b/dyninstAPI/src/dynProcess.C index 31a77cb3a0..ddef4e343b 100644 --- a/dyninstAPI/src/dynProcess.C +++ b/dyninstAPI/src/dynProcess.C @@ -46,7 +46,6 @@ #include "common/src/pathName.h" #include "PCErrors.h" -#include "MemoryEmulator/memEmulator.h" #include #include "symtabAPI/h/SymtabReader.h" @@ -2203,12 +2202,6 @@ bool PCProcess::getOverwrittenBlocks // 1. Read the modified page in from memory Address readAddr = curPageAddr; - if (isMemoryEmulated()) { - bool valid = false; - boost::tie(valid,readAddr) = getMemEm()->translate(curPageAddr); - cerr << "\t\t Reading from shadow page " << hex << readAddr << " instead of original " << curPageAddr << endl; - assert(valid); - } readTextSpace((void*)readAddr, MEM_PAGE_SIZE, memVersion); // 2. build overwritten region list by comparing shadow, memory diff --git a/dyninstAPI/src/function.C b/dyninstAPI/src/function.C index d9bc6e92a3..7ca018b1df 100644 --- a/dyninstAPI/src/function.C +++ b/dyninstAPI/src/function.C @@ -38,7 +38,6 @@ #include "mapped_object.h" #include "mapped_module.h" #include "InstructionDecoder.h" -#include "MemoryEmulator/memEmulator.h" #include "Relocation/Transformers/Movement-analysis.h" #include "PatchMgr.h" // Scope diff --git a/dyninstAPI/src/hybridCallbacks.C b/dyninstAPI/src/hybridCallbacks.C index cda52f88ed..74b0d27ecf 100644 --- a/dyninstAPI/src/hybridCallbacks.C +++ b/dyninstAPI/src/hybridCallbacks.C @@ -37,7 +37,6 @@ #include "instPoint.h" #include "function.h" #include "dynProcess.h" -#include "MemoryEmulator/memEmulator.h" #include "PatchModifier.h" #include "BPatch_image.h" #include "mapped_object.h" @@ -56,11 +55,6 @@ void HybridAnalysis::synchShadowOrigCB(BPatch_point *point, bool toOrig) mal_printf("in synch callback for point 0x%lx toOrig=%d\n", (Address)point->getAddress(), (int) (long) toOrig); - - proc()->lowlevel_process()->getMemEm()->synchShadowOrig - ((bool) toOrig); - - std::vector *mods = proc()->getImage()->getModules(); // fix up page rights so that the program can proceed @@ -369,8 +363,6 @@ void HybridAnalysis::virtualFreeCB(BPatch_point *, void *t) { if (!bpfunc) continue; PatchAPI::PatchModifier::remove(bpfunc->lowlevel_func()); } - - proc()->lowlevel_process()->getMemEm()->removeRegion(virtualFreeAddr_, virtualFreeSize_); // And nuke the RT cache proc()->lowlevel_process()->proc()->flushAddressCache_RT(virtualFreeAddr_, virtualFreeSize_); diff --git a/dyninstAPI/src/hybridInstrumentation.C b/dyninstAPI/src/hybridInstrumentation.C index 446ac589ce..19a8d39494 100644 --- a/dyninstAPI/src/hybridInstrumentation.C +++ b/dyninstAPI/src/hybridInstrumentation.C @@ -41,7 +41,6 @@ #include "debug.h" #include "dynProcess.h" #include "mapped_object.h" -#include "MemoryEmulator/memEmulator.h" #include "mapped_module.h" #include #include @@ -153,44 +152,6 @@ bool HybridAnalysis::init() proc()->finalizeInsertionSet(false); // Done instrumenting VirtualFree - - if (proc()->lowlevel_process()->isMemoryEmulated()) { - // read in the list of whitelisted Windows API functions (those that - // don't use pointers) so we save time by not to synchronizing around - // them - char *dyn_root = getenv("DYNINST_ROOT"); - if (!dyn_root) { - fprintf(stderr, "ERROR: DYNINST_ROOT environment variable was not " - "declared, couldn't find the list of non-pointer Windows API " - "functions, will synchronize memory at all inter-library calls" - " %s[%d]\n",FILE__,__LINE__); - } - else { - string fname = string(dyn_root) + "\\dyninst\\dyninstAPI\\nosynchfuncs.txt"; - ifstream nsf_file(fname.c_str()); - if ( ! nsf_file.is_open() ) { - fprintf(stderr, "ERROR: failed to open file %s, which should " - "contain the list of non-pointer Windows API functions, " - "will synchronize memory at all inter-library calls " - "%s[%d]\n",fname.c_str(),FILE__,__LINE__); - } - else { - std::string curfunc; - while (nsf_file.good()) { - getline(nsf_file, curfunc); - skipShadowFuncs_.insert(curfunc); - } - } - } - skipShadowFuncs_.insert("GetCurrentProcessId"); - skipShadowFuncs_.insert("VirtualAlloc"); - skipShadowFuncs_.insert("VirtualFree"); - skipShadowFuncs_.insert("GetCurrentThreadId"); - skipShadowFuncs_.insert("GetLocalTime"); - skipShadowFuncs_.insert("LocalAlloc"); - skipShadowFuncs_.insert("TlsAlloc"); - skipShadowFuncs_.insert("TlsSetValue"); - } #endif //mal_printf(" pre-inst "); proc()->printKTimer(); @@ -362,12 +323,6 @@ bool HybridAnalysis::instrumentFunction(BPatch_function *func, assert(proc()); assert(proc()->lowlevel_process()); - if (proc()->lowlevel_process()->isMemoryEmulated() && - BPatch_defensiveMode == func->lowlevel_func()->obj()->hybridMode()) - { // we have to relocate all functions to emulate their memory accesses - proc()->lowlevel_process()->addModifiedFunction(func->lowlevel_func()); - } - if (instrumentedFuncs->end() == instrumentedFuncs->find(func)) { (*instrumentedFuncs)[func] = new std::map(); @@ -634,7 +589,7 @@ bool HybridAnalysis::instrumentFunction(BPatch_function *func, } // close insertion set - if (proc()->lowlevel_process()->isMemoryEmulated() || pointCount) { + if (pointCount) { mal_printf("instrumented %d points in function at %p\n", pointCount, func->getBaseAddr()); if (useInsertionSet) { @@ -682,40 +637,6 @@ void HybridAnalysis::removeInstrumentation(BPatch_function *func, // 1. Remove elements from instrumentedFuncs if (instrumentedFuncs->end() != instrumentedFuncs->find(func)) { - if (proc()->lowlevel_process()->isMemoryEmulated()) { - map::iterator - pit = (*instrumentedFuncs)[func]->begin(); - for (; pit != (*instrumentedFuncs)[func]->end(); pit++) { - if (synchMap_pre_.end() != synchMap_pre_.find(pit->first)) - { - SynchHandle *shandle = synchMap_pre_[pit->first]; - // Note: the points in this snippet handle may have been deleted, and thus - // should not be dereferenced; use them only as key values in maps. - - synchMap_pre_.erase(shandle->prePt_); - /* - // Don't remove an instrumentation point that we haven't specifically found; - // it might be in a different function. - synchMap_post_.erase(shandle->postPt_); - */ - delete shandle; - } - else if (synchMap_post_.end() != synchMap_post_.find(pit->first)) - { - SynchHandle *shandle = synchMap_post_[pit->first]; - // Note: the points in this snippet handle may have been deleted, and thus - // should not be dereferenced; use them only as key values in maps. - - /* - // Do not remove an instrumentation point that we haven't specifically found; - // it might be in a different function. - synchMap_pre_.erase(shandle->prePt_); - */ - synchMap_post_.erase(shandle->postPt_); - delete shandle; - } - } - } (*instrumentedFuncs)[func]->clear(); delete (*instrumentedFuncs)[func]; instrumentedFuncs->erase(func); diff --git a/dyninstAPI/src/hybridOverwrites.C b/dyninstAPI/src/hybridOverwrites.C index 45cd5070f5..e670053028 100644 --- a/dyninstAPI/src/hybridOverwrites.C +++ b/dyninstAPI/src/hybridOverwrites.C @@ -46,7 +46,6 @@ #include "instPoint.h" #include "mapped_object.h" #include "mapped_module.h" -#include "MemoryEmulator/memEmulator.h" using namespace Dyninst; @@ -1321,9 +1320,6 @@ void HybridAnalysisOW::overwriteAnalysis(BPatch_point *point, void *loopID_) proc()->finalizeInsertionSet(false); proc()->protectAnalyzedCode(); malware_cerr << "overWriteAnalysis returns" << endl; - - proc()->lowlevel_process()->getMemEm()->debug(); - } #endif diff --git a/dyninstAPI/src/mapped_object.C b/dyninstAPI/src/mapped_object.C index b6d99e8826..ad6acf2529 100644 --- a/dyninstAPI/src/mapped_object.C +++ b/dyninstAPI/src/mapped_object.C @@ -46,7 +46,6 @@ #include "InstructionDecoder.h" #include "Parsing.h" #include "instPoint.h" -#include "MemoryEmulator/memEmulator.h" #include #include "BPatch_image.h" #include "PatchCFG.h" @@ -1327,11 +1326,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) // 1. copy memory into regBuf Address readAddr = regStart + codeBase(); - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace((void*)readAddr, copySize, regBuf, @@ -1344,8 +1338,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) mal_printf("EXTEND_CB: copied to [%lx %lx)\n", codeBase()+regStart, codeBase()+regStart+copySize); - if ( ! proc()->isMemoryEmulated() ) { - // 2. copy code bytes back into the regBuf to wipe out instrumentation // and set regBuf to be the data for the region @@ -1378,7 +1370,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) } mal_printf("Expand region: %lx blocks copied back into mapped file\n", analyzedBlocks.size()); - } if (reg->isDirty()) { // if isDirty is true, the pointer was created via malloc @@ -1410,7 +1401,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) // 2. copy overwritten regions into the mapped objects void mapped_object::updateCodeBytes(const list > &owRanges) { - bool memEmulation = proc()->isMemoryEmulated(); // 1. use other update functions to update non-code areas of mapped files, // expanding them if we wrote in un-initialized memory using namespace SymtabAPI; @@ -1447,11 +1437,6 @@ void mapped_object::updateCodeBytes(const list > &owRanges for(rIter = owRanges.begin(); rIter != owRanges.end(); rIter++) { Address readAddr = rIter->first; - if (memEmulation) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } Region *reg = parse_img()->getObject()->findEnclosingRegion ( (*rIter).first - baseAddress ); @@ -1518,11 +1503,6 @@ void mapped_object::updateCodeBytes(SymtabAPI::Region * symReg) if (prevEndAddr < curB->start()) { // update the mapped file Address readAddr = prevEndAddr + base; - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace( (void*)readAddr, curB->start() - prevEndAddr, @@ -1550,11 +1530,6 @@ void mapped_object::updateCodeBytes(SymtabAPI::Region * symReg) // (will read in whole region if there are no ranges in the region) if (prevEndAddr < regStart + symReg->getDiskSize()) { Address readAddr = prevEndAddr + base; - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace( (void*)readAddr, regStart + symReg->getDiskSize() - prevEndAddr, @@ -1632,12 +1607,6 @@ bool mapped_object::isUpdateNeeded(Address entry) ? comparison_size : page_size; regBuf = malloc(comparison_size); Address readAddr = entry; - if (proc()->isMemoryEmulated()) { - bool valid = false; - Address translated = 0; - boost::tie(valid, translated) = proc()->getMemEm()->translate(readAddr); - if (valid) readAddr = translated; - } // mal_printf("%s[%d] Comparing %lx bytes starting at %lx\n", // FILE__,__LINE__,comparison_size,entry); @@ -1682,11 +1651,6 @@ bool mapped_object::isExpansionNeeded(Address entry) // see if the first few bytes have been updated Address compareStart = base + reg->getMemOffset() + reg->getDiskSize(); - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, compareStart) = proc()->getMemEm()->translate(compareStart); - assert(valid); - } unsigned compareSize = InstructionAPI::InstructionDecoder::maxInstructionLength; Address uninitSize = reg->getMemSize() - reg->getDiskSize(); @@ -1772,10 +1736,6 @@ bool mapped_object::updateCodeBytesIfNeeded(Address entry) } void mapped_object::remove(func_instance *func) { - - if (as()->isMemoryEmulated()) { - as()->getMemEm()->removeSpringboards(func); - } // clear out module- and BPatch-level data structures BPatch_addressSpace* bpAS = (BPatch_addressSpace*)proc()->up_ptr(); @@ -1842,9 +1802,6 @@ void mapped_object::remove(instPoint *point) // does not delete void mapped_object::destroy(PatchAPI::PatchBlock *b) { calleeNames_.erase(SCAST_BI(b)); - if (as()->isMemoryEmulated()) { - as()->getMemEm()->removeSpringboards(SCAST_BI(b)); - } } // does not delete diff --git a/dyninstAPI/src/pcEventHandler.C b/dyninstAPI/src/pcEventHandler.C index e97662d91f..43690abda1 100644 --- a/dyninstAPI/src/pcEventHandler.C +++ b/dyninstAPI/src/pcEventHandler.C @@ -36,7 +36,6 @@ #include "registerSpace.h" #include "RegisterConversion.h" #include "function.h" -#include "MemoryEmulator/memEmulator.h" #include "dynThread.h" #include "Mailbox.h" @@ -460,16 +459,6 @@ bool PCEventHandler::handleSignal(EventSignal::const_ptr ev, PCProcess *evProc) Address addr = ev->getAddress(); mapped_object* obj = evProc->findObject(addr); - // retry finding object by its original address. - if (obj == NULL && evProc->isMemoryEmulated()) { - std::pair trans = - evProc->getMemEm()->translateBackwards(addr); - if (trans.first) { - addr = trans.second; - obj = evProc->findObject(addr); - } - } - // change permissions if we can find this originally writable region if (obj != NULL) { SymtabAPI::Region* reg = diff --git a/dyninstAPI/src/pdwinnt.C b/dyninstAPI/src/pdwinnt.C index 5eee0bb55e..13e520070d 100644 --- a/dyninstAPI/src/pdwinnt.C +++ b/dyninstAPI/src/pdwinnt.C @@ -46,7 +46,6 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/src/registerSpace.h" #include "image.h" -#include "MemoryEmulator/memEmulator.h" #include #include "dyninstAPI/src/ast.h" @@ -174,29 +173,6 @@ void PCProcess::changeMemoryProtections(Address addr, size_t size, rights, oldRights)) { mal_printf("ERROR: failed to set access rights " "for page %lx, %s[%d]\n", addr, FILE__, __LINE__); - } else if (isMemoryEmulated() && setShadow) { - Address shadowAddr = 0; - PCMemPerm shadowRights; - bool valid = false; - boost::tie(valid, shadowAddr) = getMemEm()->translate(idx); - if (!valid) { - mal_printf("WARNING: set access rights on page %lx that has " - "no shadow %s[%d]\n",addr,FILE__,__LINE__); - } else { - if(!pcProc_->setMemoryAccessRights(shadowAddr, pageSize, - rights, shadowRights)) { - mal_printf("ERROR: failed to set access rights " - "for page %lx, %s[%d]\n", - shadowAddr, FILE__, __LINE__); - } - - if (shadowRights != oldRights) { - mal_printf("WARNING: shadow page[%lx] rights %s did not " - "match orig-page [%lx] rights %s\n", - shadowAddr, shadowRights.getPermName().c_str(), - addr, oldRights.getPermName().c_str()); - } - } } } } diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index 5d61411a78..983a5ab8da 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -14,7 +14,6 @@ include_directories ( set (SRC_LIST src/RTcommon.c - src/RTmemEmulator.c ) if (PLATFORM MATCHES freebsd) diff --git a/dyninstAPI_RT/h/dyninstAPI_RT.h b/dyninstAPI_RT/h/dyninstAPI_RT.h index 0c14df3c92..f5f8cda93e 100644 --- a/dyninstAPI_RT/h/dyninstAPI_RT.h +++ b/dyninstAPI_RT/h/dyninstAPI_RT.h @@ -244,7 +244,5 @@ struct MemoryMapper64 { DLLEXPORT extern struct MemoryMapper RTmemoryMapper; -extern int RTuntranslatedEntryCounter; - #include "dyninstRTExport.h" #endif /* _DYNINSTAPI_RT_H */ diff --git a/dyninstAPI_RT/src/RTcommon.c b/dyninstAPI_RT/src/RTcommon.c index 7454d5821f..14695126cb 100644 --- a/dyninstAPI_RT/src/RTcommon.c +++ b/dyninstAPI_RT/src/RTcommon.c @@ -171,8 +171,6 @@ void DYNINSTBaseInit() #endif DYNINST_unlock_tramp_guard(); DYNINSThasInitialized = 1; - - RTuntranslatedEntryCounter = 0; } /** diff --git a/dyninstAPI_RT/src/RTmemEmulator.c b/dyninstAPI_RT/src/RTmemEmulator.c deleted file mode 100644 index 8699fad15b..0000000000 --- a/dyninstAPI_RT/src/RTmemEmulator.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "dyninstAPI_RT/h/dyninstAPI_RT.h" -#include "dyninstAPI_RT/src/RTcommon.h" -#include -#include -#include -#include - -#if defined (__GNUC__) -#include -#define FAST_CALL __attribute__((fastcall)) -#elif defined (os_windows) -#define FAST_CALL __fastcall -#endif - -/* Code to assist in remapping memory operations that were affected - * by our instrumentation */ - -extern void DYNINST_stopThread(void *, void *, void *, void *); - -#if _MSC_VER -struct MemoryMapper RTmemoryMapper = {0, 0, 0, 0 }; -#else -struct MemoryMapper RTmemoryMapper = {0, 0, 0, 0, {{0}} }; -#endif -extern FILE *stOut; - -//#define DEBUG_MEM_EM - -unsigned long RTtranslateMemory(unsigned long input, unsigned long origAddr, unsigned long currAddr) { - /* Standard nonblocking synchronization construct */ - int index; - int min; - int max; - volatile int guard2; - (void)origAddr; /* unused parameter */ - (void)currAddr; /* unused parameter */ - - do { - guard2 = RTmemoryMapper.guard2; - min = 0; - max = (RTmemoryMapper.size - 1); - do { - index = min + ((max - min) / 2); - if (input >= RTmemoryMapper.elements[index].lo) { - /* Either correct or too low */ - if (input < RTmemoryMapper.elements[index].hi) { - break; - } - else { - min = index + 1; - } - } - else { - /* Too high */ - max = index - 1; - } - } while (min <= max); - } while (guard2 != RTmemoryMapper.guard1); - - if (min <= max) { - if (RTmemoryMapper.elements[index].shift == -1) { - return 0; - } - else { - return input + RTmemoryMapper.elements[index].shift; - } - } - else { - return input; - } - return 0; -} - -unsigned long RTtranslateMemoryShift(unsigned long input, unsigned long origAddr, unsigned long currAddr) { - /* Standard nonblocking synchronization construct */ - int index; - int min; - int max; - volatile int guard2; - (void)origAddr; /* unused parameter */ - (void)currAddr; /* unused parameter */ - - do { - guard2 = RTmemoryMapper.guard2; - min = 0; - max = (RTmemoryMapper.size - 1); - do { - index = min + ((max - min) / 2); - if (input >= RTmemoryMapper.elements[index].lo) { - /* Either correct or too low */ - if (input < RTmemoryMapper.elements[index].hi) { - break; - } - else { - min = index + 1; - } - } - else { - /* Too high */ - max = index - 1; - } - } while (min <= max); - } while (guard2 != RTmemoryMapper.guard1); - - if (min <= max) { - if (RTmemoryMapper.elements[index].shift == -1) { - fflush(stOut); - return -1 * input; - } - else { - return RTmemoryMapper.elements[index].shift; - } - } - else { - return 0; - } - return 0; -} - -int RTuntranslatedEntryCounter; -extern void DYNINST_stopThread (void * pointAddr, void *callBackID, void *flags, void *calculation); - -void RThandleShadow(void *direction, void *pointAddr, void *callbackID, void *flags, void *calculation) { - (void)calculation; /* unused parameter */ - if ((int)((long) direction) == 1) { - if (RTuntranslatedEntryCounter == 0) { - // Entering a system call... - DYNINST_stopThread(pointAddr, callbackID, flags, (void *)1); - } - RTuntranslatedEntryCounter++; - } - else { - if (RTuntranslatedEntryCounter > 0) { - RTuntranslatedEntryCounter--; - } - if (RTuntranslatedEntryCounter == 0) { - DYNINST_stopThread(pointAddr, callbackID, flags, (void *)0); - } - } -} diff --git a/parseAPI/src/StackTamperVisitor.h b/parseAPI/src/StackTamperVisitor.h index b30c374161..4bcb563175 100644 --- a/parseAPI/src/StackTamperVisitor.h +++ b/parseAPI/src/StackTamperVisitor.h @@ -35,7 +35,7 @@ #include #include -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/AbslocInterface.h" // And more of the same #include "dataflowAPI/h/SymEval.h" // Variable class #include "common/h/DynAST.h" From 780d7d1246c405f51a58c8945b3dd25876d73e74 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 9 Nov 2021 21:48:09 -0600 Subject: [PATCH 037/505] Remove PCProcess::getDeadCode This was disabled by ab24c9bf0 in 2012. Because it was replaced with an 'assert(0)', it's safe to say no one has used it since it was disabled. --- dyninstAPI/src/BPatch_process.C | 2 - dyninstAPI/src/dynProcess.C | 179 -------------------------------- dyninstAPI/src/dynProcess.h | 7 -- 3 files changed, 188 deletions(-) diff --git a/dyninstAPI/src/BPatch_process.C b/dyninstAPI/src/BPatch_process.C index 2085a51984..cad51d86c0 100644 --- a/dyninstAPI/src/BPatch_process.C +++ b/dyninstAPI/src/BPatch_process.C @@ -1501,12 +1501,10 @@ void BPatch_process::overwriteAnalysisUpdate /*2. remove dead code from the analysis */ - // identify the dead code (see getDeadCode for its parameter definitions) std::set delBlocks; std::map > elimMap; std::list deadFuncs; std::map newFuncEntries; - llproc->getDeadCode(owBBIs,delBlocks,elimMap,deadFuncs,newFuncEntries); // remove instrumentation from affected funcs beginInsertionSet(); diff --git a/dyninstAPI/src/dynProcess.C b/dyninstAPI/src/dynProcess.C index ddef4e343b..a34026dda1 100644 --- a/dyninstAPI/src/dynProcess.C +++ b/dyninstAPI/src/dynProcess.C @@ -2276,185 +2276,6 @@ void PCProcess::updateCodeBytes assert(objRanges.size() <= 1); //o/w analysis code may not be prepared for other cases } -#if 0 -static void otherFuncBlocks(func_instance *func, - const set &blks, - set &otherBlks) -{ - const func_instance::BlockSet &allBlocks = - func->blocks(); - for (func_instance::BlockSet::const_iterator bit = - allBlocks.begin(); - bit != allBlocks.end(); - bit++) - { - if (blks.end() == blks.find((*bit))) { - otherBlks.insert((*bit)); - } - } -} -#endif - -/* Summary - * Given a list of overwritten blocks, find blocks that are unreachable, - * functions that have been overwritten at their entry points and can go away, - * and new function entry for functions that are being overwritten while still - * executing - * - * variables - * f: the overwritten function - * ow: the set of overwritten blocks - * ex: the set of blocks that are executing on the call stack that were not overwritten - * - * primitives - * R(b,s): yields set of reachable blocks for collection of blocks b, starting - * at seed blocks s. - * B(f): the blocks pertaining to function f - * EP(f): the entry point of function f - * F(b): functions containing block b - * - * calculations - * Elim(f): the set of blocks to eliminate from function f. - * Elim(f) = B(f) - R( B(f)-ow , EP(f) ) - * New(f): new function entry candidates for f's surviving blocks. - * If EB(f) not in ow(f), empty set - * Else, all blocks b such that ( b in ex AND e in Elim(f) ) - * Eliminate New(f) elements that have ancestors in New(f) - * Del(f): A block can be deleted altogether if - * forall f in F(b): B(F) - R( B(f) - ow , New(f) U (EP(f) \ ow(f)) U (ex(f) intersect Elim(f)) ), - * b is not in the resulting set. In other words, b is not - * reachable from non-overwritten blocks in the functions in - * which it appears, seeded at new entry points and original - * non-overwritten entry points to the function, and at f's - * executing blocks if these will be deleted from the - * function (they constitute an entry point into the function - * even if they've been overwritten). - * DeadF: the set of functions that have no executing blocks - * and were overwritten in their entry blocks - * EP(f) in ow(f) AND ex(f) is empty - */ -bool PCProcess::getDeadCode -( const std::list & /*owBlocks*/, // input - std::set & /*delBlocks*/, //output: Del(for all f) - std::map > & /*elimMap*/, //output: elimF - std::list & /*deadFuncs*/, //output: DeadF - std::map & /*newFuncEntries*/) //output: newF -{ - assert(0 && "TODO"); - return false; -#if 0 - // do a stackwalk to see which functions are currently executing - std::vector > stacks; - std::vector
pcs; - if (!walkStacks(stacks)) { - inst_printf("%s[%d]: walkStacks failed\n", FILE__, __LINE__); - return false; - } - for (unsigned i = 0; i < stacks.size(); ++i) { - std::vector &stack = stacks[i]; - for (unsigned int j = 0; j < stack.size(); ++j) { - Address origPC = 0; - vector dontcare1; - baseTramp *dontcare2 = NULL; - getAddrInfo(stack[j].getPC(), origPC, dontcare1, dontcare2); - pcs.push_back( origPC ); - } - } - - // group blocks by function - std::map > deadMap; - std::set deadEntryFuncs; - std::set
owBlockAddrs; - for (list::const_iterator bIter=owBlocks.begin(); - bIter != owBlocks.end(); - bIter++) - { - deadMap[(*bIter)->func()].insert(*bIter); - owBlockAddrs.insert((*bIter)->start()); - if ((*bIter)->llb() == (*bIter)->func()->ifunc()->entry()) { - deadEntryFuncs.insert((*bIter)->func()); - } - } - - // for each modified function, calculate ex, ElimF, NewF, DelF - for (map >::iterator fit = deadMap.begin(); - fit != deadMap.end(); - fit++) - { - - // calculate ex(f) - set execBlocks; - for (unsigned pidx=0; pidx < pcs.size(); pidx++) { - std::set candidateBlocks; - fit->first->findBlocksByAddr(pcs[pidx], candidateBlocks); - for (std::set::iterator cb_iter = candidateBlocks.begin(); - cb_iter != candidateBlocks.end(); ++cb_iter) { - block_instance *exB = *cb_iter; - if (exB && owBlockAddrs.end() == owBlockAddrs.find( - exB->start())) - { - execBlocks.insert(exB); - } - } - } - - // calculate DeadF: EP(f) in ow and EP(f) not in ex - if ( 0 == execBlocks.size() ) { - set::iterator eb = fit->second.find( - fit->first->entryBlock()); - if (eb != fit->second.end()) { - deadFuncs.push_back(fit->first); - continue;// treated specially, don't need elimF, NewF or DelF - } - } - - // calculate elimF - set keepF; - list seedBs; - seedBs.push_back(fit->first->entryBlock()); - fit->first->getReachableBlocks(fit->second, seedBs, keepF); - otherFuncBlocks(fit->first, keepF, elimMap[fit->first]); - - // calculate NewF - if (deadEntryFuncs.end() != deadEntryFuncs.find(fit->first)) { - for (set::iterator bit = execBlocks.begin(); - bit != execBlocks.end(); - bit++) - { - if (elimMap[fit->first].end() != - elimMap[fit->first].find(*bit)) - { - newFuncEntries[fit->first] = *bit; - break; // just need one candidate - } - } - } - - // calculate Del(f) - seedBs.clear(); - if (deadEntryFuncs.end() == deadEntryFuncs.find(fit->first)) { - seedBs.push_back(fit->first->entryBlock()); - } - else if (newFuncEntries.end() != newFuncEntries.find(fit->first)) { - seedBs.push_back(newFuncEntries[fit->first]); - } - for (set::iterator xit = execBlocks.begin(); - xit != execBlocks.end(); - xit++) - { - if (elimMap[fit->first].end() != elimMap[fit->first].find(*xit)) { - seedBs.push_back(*xit); - } - } - keepF.clear(); - fit->first->getReachableBlocks(fit->second, seedBs, keepF); - otherFuncBlocks(fit->first, keepF, delBlocks); - - } - - return true; -#endif -} // will flush addresses of all addresses in the specified range, if the // range is null, flush all addresses from the cache. Also flush diff --git a/dyninstAPI/src/dynProcess.h b/dyninstAPI/src/dynProcess.h index 34585aae6b..ecd07c3ac3 100644 --- a/dyninstAPI/src/dynProcess.h +++ b/dyninstAPI/src/dynProcess.h @@ -232,13 +232,6 @@ class PCProcess : public AddressSpace { std::list >& overwrittenRegions,//output std::list &writtenBBIs);//output - bool getDeadCode - ( const std::list &owBlocks, // input - std::set &delBlocks, //output: Del(for all f) - std::map > &elimMap, //output: elimF - std::list &deadFuncs, //output: DeadF - std::map &newFuncEntries); //output: newF - // synch modified mapped objects with current memory contents mapped_object *createObjectNoFile(Address addr); void updateCodeBytes( const std::list > &owRegions); From b054059fc4b51e496f76db61af077d7e0dc45c74 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 9 Nov 2021 21:50:29 -0600 Subject: [PATCH 038/505] Remove thread registration functions from PCProcess These were disabled in 2015 by 0e791cce8. --- dyninstAPI/src/dynProcess.C | 106 ------------------------------------ 1 file changed, 106 deletions(-) diff --git a/dyninstAPI/src/dynProcess.C b/dyninstAPI/src/dynProcess.C index a34026dda1..36879e3919 100644 --- a/dyninstAPI/src/dynProcess.C +++ b/dyninstAPI/src/dynProcess.C @@ -1364,112 +1364,6 @@ bool PCProcess::removeThread(dynthread_t tid) { } extern Address getVarAddr(PCProcess *proc, std::string str); -#if 0 -bool PCProcess::registerThread(PCThread *thread) { - - Address tid = (Address) thread->getTid(); - Address index = thread->getIndex(); - - Address tmp = 0; - unsigned ptrsize = getAddressWidth(); - - if (tid == (Address) -1) return true; - if (index == (Address) -1) return true; - - if (!initializeRegisterThread()) { - startup_printf("%s[%d]: initializeRegisterThread failed\n", - FILE__, __LINE__); - - return false; - } - // Must match the "hash" algorithm used in the RT lib - int working = (tid % thread_hash_size); - while(1) { - tmp = 0; - if (!readDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &tmp, false)) { - startup_printf("%s[%d]: Failed to read index slot, base 0x%lx, active 0x%lx\n", FILE__, __LINE__, - thread_hash_indices, thread_hash_indices + (working * ptrsize)); - return false; - } - startup_printf("%s[%d]: value of tid in slot %p is 0x%lx\n", - FILE__, __LINE__, thread_hash_indices + (working * ptrsize), tmp); - if (ptrsize == 4 && tmp == 0xffffffff) { - int index_int = (int) index; - int tid_int = (int) tid; - startup_printf("%s[%d]: writing %d to %p and 0x%x to %p\n", - FILE__, __LINE__, index_int, thread_hash_indices + (working * ptrsize), - tid_int, thread_hash_tids + (working * ptrsize)); - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &index_int); - writeDataWord(( void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tid_int); - break; - } - else if (ptrsize == 8 && tmp == (Address)-1) { - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &index); - writeDataWord(( void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tid); - break; - } - working++; - if (working == thread_hash_size) working = 0; - if (working == (int) (tid % thread_hash_size)) { - startup_printf("%s[%d]: Failed to find empty tid slot\n", FILE__, __LINE__); - return false; - } - } - return true; -} -bool PCProcess::unregisterThread(PCThread *thread) { - return true; - Address tid = (Address) thread->getTid(); - Address index = thread->getIndex(); - Address tmp = 0; - - unsigned ptrsize = getAddressWidth(); - if (tid == (Address) -1) return true; - if (index == (Address) -1) return true; - - initializeRegisterThread(); - - // Must match the "hash" algorithm used in the RT lib - int working = tid % thread_hash_size; - while(1) { - tmp = 0; - if (!readDataWord((void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tmp, false)) return false; - if (tmp == tid) { - // Zero it out - tmp = (Address) -1; - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &tmp); - break; - } - working++; - if (working == thread_hash_size) working = 0; - if (working == (int) (tid % thread_hash_size)) return false; - } - return true; -} - -bool PCProcess::initializeRegisterThread() { -// if (thread_hash_tids) return true; - - unsigned ptrsize = getAddressWidth(); - - Address tidPtr = getVarAddr(this, "DYNINST_thread_hash_tids"); - if (!tidPtr) return false; - Address indexPtr = getVarAddr(this, "DYNINST_thread_hash_indices"); - if (!indexPtr) return false; - Address sizePtr = getVarAddr(this, "DYNINST_thread_hash_size"); - if (!sizePtr) return false; - - if (!readDataWord((const void *)tidPtr, ptrsize, &thread_hash_tids, false)) return false; - - if (!readDataWord((const void *)indexPtr, ptrsize, &thread_hash_indices, false)) return false; - - if (!readDataWord((const void *)sizePtr, sizeof(int), &thread_hash_size, false)) return false; - - return true; -} -#endif - - void PCProcess::addThread(PCThread *thread) { pair::iterator, bool> result; result = threadsByTid_.insert(make_pair(thread->getTid(), thread)); From ed7cba87686cd6e3bec30e68129630bfe71cb9bc Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 9 Nov 2021 21:51:53 -0600 Subject: [PATCH 039/505] Remove unregisterTrapMapping from PCProcess This was disabled in 2013 by fce999f48. --- dyninstAPI/src/dynProcess.h | 1 - 1 file changed, 1 deletion(-) diff --git a/dyninstAPI/src/dynProcess.h b/dyninstAPI/src/dynProcess.h index ecd07c3ac3..fba8e1bd78 100644 --- a/dyninstAPI/src/dynProcess.h +++ b/dyninstAPI/src/dynProcess.h @@ -282,7 +282,6 @@ class PCProcess : public AddressSpace { virtual bool multithread_capable(bool ignoreIfMtNotSet = false); // platform-specific virtual bool multithread_ready(bool ignoreIfMtNotSet = false); virtual bool needsPIC(); - //virtual bool unregisterTrapMapping(Address from); virtual void addTrap(Address from, Address to, codeGen &gen); virtual void removeTrap(Address from); From 6eb87220db3ab02f3ced5a6748a13222cc449b37 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 10 Nov 2021 13:04:42 -0600 Subject: [PATCH 040/505] Remove AddressSpace::causeTemplateInstantiations (#1149) This was removed by 47c4dfe96 in 2010. Co-authored-by: Tim Haines --- dyninstAPI/src/addressSpace.C | 3 --- dyninstAPI/src/addressSpace.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/dyninstAPI/src/addressSpace.C b/dyninstAPI/src/addressSpace.C index 022d8c2308..3b4cf9eba7 100644 --- a/dyninstAPI/src/addressSpace.C +++ b/dyninstAPI/src/addressSpace.C @@ -1965,9 +1965,6 @@ bool AddressSpace::patchCode(CodeMover::Ptr cm, return true; } -void AddressSpace::causeTemplateInstantiations() { -} - void AddressSpace::getRelocAddrs(Address orig, block_instance *block, func_instance *func, diff --git a/dyninstAPI/src/addressSpace.h b/dyninstAPI/src/addressSpace.h index e0639dfa4f..6a79d2a36e 100644 --- a/dyninstAPI/src/addressSpace.h +++ b/dyninstAPI/src/addressSpace.h @@ -463,8 +463,6 @@ class AddressSpace : public InstructionSource { RelocInfo &relocInfo); // defensive mode code // - void causeTemplateInstantiations(); - // Debugging method bool inEmulatedCode(Address addr); From e672765f31dfaf5bcfa69ab4b7681de8657daf47 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 10 Nov 2021 21:00:37 -0600 Subject: [PATCH 041/505] Improve docs for lookup functions in CodeObject (#1147) Add wording to improve clarity about when a CodeRegion is strictly needed when using the lookup functions. Co-authored-by: Tim Haines --- parseAPI/doc/API/CodeObject.tex | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/parseAPI/doc/API/CodeObject.tex b/parseAPI/doc/API/CodeObject.tex index 52325cfa54..a1bda62143 100644 --- a/parseAPI/doc/API/CodeObject.tex +++ b/parseAPI/doc/API/CodeObject.tex @@ -92,6 +92,15 @@ \subsection{Class CodeObject} \end{apient} \apidesc{Speculatively parse the indicated region of the binary using the specified technique to find likely function entry points, enabled on the x86 and x86-64 platforms.} +\fbox{\begin{minipage}[t]{1\columnwidth}% +\begin{center}{\textbf{A note on using the lookup functions}}\end{center}\\ +When parsing binary objects such as .o files and static libraries which may have multiple +\texttt{CodeRegion} objects that overlap in the address space, the \texttt{CodeRegion} argument +\textit{must} be passed. For executable binaries and shared libraries that are fully linked, there +is no ambiguity, and {\scshape null} can be passed. The only exception is \texttt{findFuncsByBlock} +which always requires a valid \texttt{CodeRegion}.% +\end{minipage}} + \begin{apient} Function * findFuncByEntry(CodeRegion * cr, Address entry) From 98248b4deef459f8f890f35ab5f97ab938451ba4 Mon Sep 17 00:00:00 2001 From: John M Mellor-Crummey Date: Sun, 11 Jul 2021 22:16:26 -0500 Subject: [PATCH 042/505] first draft of support for nvidia enhanced line maps --- symtabAPI/src/Object-elf.C | 155 ++++++++++++++++++++++++++++++++----- 1 file changed, 136 insertions(+), 19 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 1f1f242ce5..e41ff640f9 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -47,6 +47,8 @@ #include "dwarfWalker.h" +#include "Object-elf.h" + using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace Dyninst::DwarfDyninst; @@ -3357,7 +3359,9 @@ class open_statement { end_addr = noAddress(); line_number = 0; column_number = 0; - } + context = 0; + funcname_offset = 0; + }; bool sameFileLineColumn(const open_statement &rhs) { return ((string_table_index == rhs.string_table_index) && (line_number == rhs.line_number) && @@ -3369,12 +3373,31 @@ class open_statement { end_addr = rhs.end_addr; line_number = rhs.line_number; column_number = rhs.column_number; - } + context = rhs.context; + funcname_offset = rhs.funcname_offset; + }; friend std::ostream& operator<<(std::ostream& os, const open_statement& st) { - os << hex << st.start_addr << " " << st.end_addr << " line:" - << dec << st.line_number << " file:" << st.string_table_index << " col:" << st.column_number << std::endl; + st.dump(os, 0, true); return os; + }; + const char * str(Region *r, unsigned int offset) const { + return ((char *) r->getPtrToRawData()) + offset; + }; + void dump(std::ostream& os, Region *debug_str, bool addrRange) const { + // unsigned int o = 0x2868; + // unsigned int o = 0x2868 + 0x500; + unsigned int o = 0x2868 + 0x700; + if (addrRange) os << "[" << hex << start_addr - o << ", " << end_addr - o << "]"; + else os << "inlined at"; + os << " file:" << string_table_index; + os << " line:" << dec << line_number; + os << " col:" << column_number; + if (context) { + os << " context " << context; + os << " function name " << str(debug_str, funcname_offset); + } + os << std::endl; } public: Dwarf_Word string_table_index; @@ -3382,6 +3405,8 @@ class open_statement { Dwarf_Addr end_addr; int line_number; int column_number; + unsigned int context; + unsigned int funcname_offset; }; @@ -3564,8 +3589,46 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) } -LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) +void +dumpLineContext +( + Region *debug_str, + open_statement &saved_statement, + vector &inline_context ) { + cout << "--" << endl; + saved_statement.dump(cout, debug_str, true); + if (inline_context.size()) { + for (unsigned int i = inline_context.size(); i > 0; i--) { + inline_context[i -1].dump(cout, debug_str, false); + } + } +} + +bool +replaceInlineContext +( + vector &inline_context, + open_statement &saved_statement +) { + if (saved_statement.context) { + for (unsigned int i = 0; i < inline_context.size(); i++) { + if (inline_context[i].context == saved_statement.context) { + inline_context.erase(inline_context.begin() + i, inline_context.end()); + return true; + } + } + } + return false; +} + + +LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) +{ + Region *debug_str; + std::string debug_str_secname = ".debug_str"; + bool has_debug_str = associated_symtab->findRegion(debug_str, debug_str_secname); + if (li_for_object) { // The line information for this object has been parsed. return li_for_object; @@ -3626,9 +3689,11 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) Offset baseAddr = getBaseAddress(); - /* Iterate over this CU's source lines. */ - open_statement current_line; + /* Iterate over this object's source lines. */ + open_statement saved_statement; open_statement current_statement; + + vector inline_context; for(size_t i = 0; i < lineCount; i++ ) { auto line = dwarf_onesrcline(lineBuffer, i); @@ -3698,21 +3763,73 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) cout << "dwarf_linebeginstatement failed" << endl; continue; } - if (current_line.uninitialized()) { - current_line = current_statement; + + status = dwarf_linecontext(line, ¤t_statement.context); + if(status != 0) { + cout << "dwarf_linecontext failed" << endl; + continue; + } + + status = dwarf_linefunctionname(line, ¤t_statement.funcname_offset); + if(status != 0) { + cout << "dwarf_linefunctionname failed" << endl; + continue; + } + + if (saved_statement.uninitialized()) { + saved_statement = current_statement; } else { - current_line.end_addr = current_statement.start_addr; - if (!current_line.sameFileLineColumn(current_statement) || - isEndOfSequence) { - li_for_object->addLine((unsigned int)(current_line.string_table_index), - (unsigned int)(current_line.line_number), - (unsigned int)(current_line.column_number), - current_line.start_addr, current_line.end_addr); - current_line = current_statement; - } + bool pushed = false; + saved_statement.end_addr = current_statement.start_addr; + // need to be comparing saved with prev not current with saved + if (1 || current_statement.context != saved_statement.context) { + // if (current_statement.context) { + if (saved_statement.context || current_statement.context) { + // if current_statement has a non-zero context, then saved_statement + // is part of the inlined_at context for the saved_statement. there + // are two cases to consider: + // 1) if the context of saved_statement is the same as the context of + // a statement that is already part of the inlined context, then update + // the matching item in the inlined context with saved_statement and + // remove any nested items. + // 2) if saved_statement.context doesn't match anything already in the + // inlined context, add it to the end. + + bool replaced = replaceInlineContext(inline_context, saved_statement); + + if (current_statement.start_addr != saved_statement.start_addr) + dumpLineContext(debug_str, saved_statement, inline_context); + + // if (!replaced) inline_context.push_back(saved_statement); + inline_context.push_back(saved_statement); + + pushed = true; + } + } + if ((!saved_statement.sameFileLineColumn(current_statement) || + isEndOfSequence)) { + // if we didn't add saved_statement to the inlined context, then + // the context for the saved_statement needs to be emitted. + if (!pushed) { + dumpLineContext(debug_str, saved_statement, inline_context); + } + + li_for_object->addLine((unsigned int)(saved_statement.string_table_index), + (unsigned int)(saved_statement.line_number), + (unsigned int)(saved_statement.column_number), + saved_statement.start_addr, saved_statement.end_addr); + + // a statement with context 0 clears all inlined context. remove all + // inlined context entries in the vector. + if (current_statement.context == 0) { + inline_context.resize(0); + } + + saved_statement = current_statement; + } } if (isEndOfSequence) { - current_line.reset(); + saved_statement.reset(); } } } From dc45b755e00867ebe3fef4c22bab3c470b6adacf Mon Sep 17 00:00:00 2001 From: John M Mellor-Crummey Date: Mon, 12 Jul 2021 10:54:15 -0500 Subject: [PATCH 043/505] cleaning up code for ingesting nvidia extended linemaps --- symtabAPI/src/Object-elf.C | 155 ++++++++++++++++++++----------------- 1 file changed, 86 insertions(+), 69 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index e41ff640f9..36952f6089 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3385,19 +3385,20 @@ class open_statement { return ((char *) r->getPtrToRawData()) + offset; }; void dump(std::ostream& os, Region *debug_str, bool addrRange) const { - // unsigned int o = 0x2868; - // unsigned int o = 0x2868 + 0x500; - unsigned int o = 0x2868 + 0x700; - if (addrRange) os << "[" << hex << start_addr - o << ", " << end_addr - o << "]"; - else os << "inlined at"; - os << " file:" << string_table_index; - os << " line:" << dec << line_number; - os << " col:" << column_number; - if (context) { - os << " context " << context; - os << " function name " << str(debug_str, funcname_offset); - } - os << std::endl; + // to facilitate comparison with nvdisasm output, where each function starts at 0, + // set o to an offset that makes a function of interest report addresses that + // match its unrelocated offsets reported by nvdisasm + unsigned int o = 0; + if (addrRange) os << "[" << hex << start_addr - o << ", " << end_addr - o << "]"; + else os << " inlined at"; + os << " file:" << string_table_index; + os << " line:" << dec << line_number; + os << " col:" << column_number; + if (context) { + os << " context " << context; + os << " function name " << str(debug_str, funcname_offset); + } + os << std::endl; } public: Dwarf_Word string_table_index; @@ -3590,12 +3591,13 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) void -dumpLineContext +dumpLineWithInlineContext ( Region *debug_str, - open_statement &saved_statement, - vector &inline_context ) { - cout << "--" << endl; + open_statement &saved_statement, + vector &inline_context +) +{ saved_statement.dump(cout, debug_str, true); if (inline_context.size()) { for (unsigned int i = inline_context.size(); i > 0; i--) { @@ -3604,22 +3606,50 @@ dumpLineContext } } -bool -replaceInlineContext + +void +recordLine +( + LineInformation *li_for_object, + Region *debug_str, + open_statement &saved_statement, + vector &inline_context +) +{ + // record line map entry + li_for_object->addLine((unsigned int)(saved_statement.string_table_index), + (unsigned int)(saved_statement.line_number), + (unsigned int)(saved_statement.column_number), + saved_statement.start_addr, saved_statement.end_addr); + + // record inline context, if any + if (inline_context.size()) { + for (unsigned int i = inline_context.size(); i > 0; i--) { + // record inline context for inline_context[i -1] + } + } + + dumpLineWithInlineContext(debug_str, saved_statement, inline_context); +} + + +void +deleteAnyMatchingInlinedContext ( vector &inline_context, open_statement &saved_statement -) +) { - if (saved_statement.context) { + unsigned int c = saved_statement.context; + if (c) { for (unsigned int i = 0; i < inline_context.size(); i++) { - if (inline_context[i].context == saved_statement.context) { + if (inline_context[i].context == c) { + // delete the entry matching c and any nexted entries inline_context.erase(inline_context.begin() + i, inline_context.end()); - return true; + return; } } } - return false; } @@ -3633,8 +3663,8 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // The line information for this object has been parsed. return li_for_object; } - li_for_object = new LineInformation(); - li_for_object->setStrings(strings_); + li_for_object = new LineInformation(); + li_for_object->setStrings(strings); /* Initialize libdwarf. */ Dwarf **dbg_ptr = dwarf->type_dbg(); if (!dbg_ptr) return li_for_object; @@ -3696,7 +3726,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) vector inline_context; for(size_t i = 0; i < lineCount; i++ ) { - auto line = dwarf_onesrcline(lineBuffer, i); + auto line = dwarf_onesrcline(lineBuffer, i); /* Acquire the line number, address, source, and end of sequence flag. */ status = dwarf_lineno(line, ¤t_statement.line_number); @@ -3723,7 +3753,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) if (result) current_statement.start_addr = new_lineAddr; } - + //status = dwarf_line_srcfileno(line, ¤t_statement.string_table_index); const char * file_name = dwarf_linesrc(line, NULL, NULL); if ( !file_name ) { @@ -3736,9 +3766,9 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) int index = -1; for(size_t idx = offset; idx < strings->size(); ++idx) { - if((*strings)[idx].str==file_name_str) - { - index = idx; + if((*strings)[idx].str==file_name_str) + { + index = idx; break; } } @@ -3781,47 +3811,34 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) } else { bool pushed = false; saved_statement.end_addr = current_statement.start_addr; - // need to be comparing saved with prev not current with saved - if (1 || current_statement.context != saved_statement.context) { - // if (current_statement.context) { - if (saved_statement.context || current_statement.context) { - // if current_statement has a non-zero context, then saved_statement - // is part of the inlined_at context for the saved_statement. there - // are two cases to consider: - // 1) if the context of saved_statement is the same as the context of - // a statement that is already part of the inlined context, then update - // the matching item in the inlined context with saved_statement and - // remove any nested items. - // 2) if saved_statement.context doesn't match anything already in the - // inlined context, add it to the end. - - bool replaced = replaceInlineContext(inline_context, saved_statement); - - if (current_statement.start_addr != saved_statement.start_addr) - dumpLineContext(debug_str, saved_statement, inline_context); - - // if (!replaced) inline_context.push_back(saved_statement); - inline_context.push_back(saved_statement); - - pushed = true; - } - } + if (saved_statement.context || current_statement.context) { + // if saved_statement.context is non-zero, we need to remove any previously + // recorded inlined context that matches saved_statement.context or is + // nexted inside the matching context + deleteAnyMatchingInlinedContext(inline_context, saved_statement); + + // record saved_statement and its inlining context if any addresses fall + // between saved_statement and current_statement. + if (current_statement.start_addr != saved_statement.start_addr) + recordLine (li_for_object, debug_str, saved_statement, inline_context); + + // record saved_statement as inlined context for current_statement` + inline_context.push_back(saved_statement); + + pushed = true; + } if ((!saved_statement.sameFileLineColumn(current_statement) || isEndOfSequence)) { - // if we didn't add saved_statement to the inlined context, then - // the context for the saved_statement needs to be emitted. - if (!pushed) { - dumpLineContext(debug_str, saved_statement, inline_context); - } - li_for_object->addLine((unsigned int)(saved_statement.string_table_index), - (unsigned int)(saved_statement.line_number), - (unsigned int)(saved_statement.column_number), - saved_statement.start_addr, saved_statement.end_addr); + if (!pushed) { + // we didn't add saved_statement to the inlined context of current_statement, + // so a line map entry for saved_statement needs to be recorded + recordLine (li_for_object, debug_str, saved_statement, inline_context); + } - // a statement with context 0 clears all inlined context. remove all - // inlined context entries in the vector. if (current_statement.context == 0) { + // a line map statement with context 0 clears all inlined context. + // remove all inlined context entries in the vector. inline_context.resize(0); } @@ -3831,7 +3848,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) if (isEndOfSequence) { saved_statement.reset(); } - } + } } return li_for_object; } @@ -3913,7 +3930,7 @@ bool Object::convertDebugOffset(Offset off, Offset &new_off) int hi = DebugSectionMap.size(); if (hi == 0) { - // DebugSectionMap is empty; handle this case separately + // DebugSectionMap is empty; handle this case separately DbgSectionMapSorted = true; return true; } From 0f9750a9e4b03b958b1fa76516aec1432a0a7739 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 20 Jul 2021 10:48:18 -0500 Subject: [PATCH 044/505] Start to construct inlining call chains using Nvidia's extended line map --- symtabAPI/h/Function.h | 1 + symtabAPI/h/Symtab.h | 1 + symtabAPI/src/Object-elf.C | 153 +++++++++++++++++----------------- symtabAPI/src/Object-elf.h | 84 +++++++++++++++++++ symtabAPI/src/Symtab-lookup.C | 10 +-- 5 files changed, 167 insertions(+), 82 deletions(-) diff --git a/symtabAPI/h/Function.h b/symtabAPI/h/Function.h index 231db3ea23..037382966c 100644 --- a/symtabAPI/h/Function.h +++ b/symtabAPI/h/Function.h @@ -192,6 +192,7 @@ class SYMTAB_EXPORT InlinedFunction : public FunctionBase { friend class Symtab; friend class DwarfWalker; + friend class Object; protected: InlinedFunction(FunctionBase *parent); ~InlinedFunction(); diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 84788b3e28..71e3a338c9 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -105,6 +105,7 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, friend class emitWin; friend class Aggregate; friend class relocationEntry; + friend class Object; public: diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 36952f6089..36d1472374 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -2484,7 +2484,8 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), EEL(false), did_open(false), obj_type_(obj_Unknown), DbgSectionMapSorted(false), - soname_(NULL) + soname_(NULL), + containingFunc(nullptr) { li_for_object = NULL; @@ -3346,71 +3347,6 @@ const char *Object::interpreter_name() const { return interpreter_name_; } -class open_statement { - public: - open_statement() { reset(); } - Dwarf_Addr noAddress() { return (Dwarf_Addr) ~0; } - bool uninitialized() { - return start_addr == noAddress(); - } - void reset() { - string_table_index = -1; - start_addr = noAddress(); - end_addr = noAddress(); - line_number = 0; - column_number = 0; - context = 0; - funcname_offset = 0; - }; - bool sameFileLineColumn(const open_statement &rhs) { - return ((string_table_index == rhs.string_table_index) && - (line_number == rhs.line_number) && - (column_number == rhs.column_number)); - } - void operator=(const open_statement &rhs) { - string_table_index = rhs.string_table_index; - start_addr = rhs.start_addr; - end_addr = rhs.end_addr; - line_number = rhs.line_number; - column_number = rhs.column_number; - context = rhs.context; - funcname_offset = rhs.funcname_offset; - }; - friend std::ostream& operator<<(std::ostream& os, const open_statement& st) - { - st.dump(os, 0, true); - return os; - }; - const char * str(Region *r, unsigned int offset) const { - return ((char *) r->getPtrToRawData()) + offset; - }; - void dump(std::ostream& os, Region *debug_str, bool addrRange) const { - // to facilitate comparison with nvdisasm output, where each function starts at 0, - // set o to an offset that makes a function of interest report addresses that - // match its unrelocated offsets reported by nvdisasm - unsigned int o = 0; - if (addrRange) os << "[" << hex << start_addr - o << ", " << end_addr - o << "]"; - else os << " inlined at"; - os << " file:" << string_table_index; - os << " line:" << dec << line_number; - os << " col:" << column_number; - if (context) { - os << " context " << context; - os << " function name " << str(debug_str, funcname_offset); - } - os << std::endl; - } - public: - Dwarf_Word string_table_index; - Dwarf_Addr start_addr; - Dwarf_Addr end_addr; - int line_number; - int column_number; - unsigned int context; - unsigned int funcname_offset; -}; - - void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) { /* Acquire this CU's source lines. */ @@ -3608,28 +3544,91 @@ dumpLineWithInlineContext void -recordLine +Object::recordLine ( LineInformation *li_for_object, Region *debug_str, open_statement &saved_statement, - vector &inline_context + vector &inline_context, + Symtab* associated_symtab ) -{ +{ // record line map entry li_for_object->addLine((unsigned int)(saved_statement.string_table_index), (unsigned int)(saved_statement.line_number), (unsigned int)(saved_statement.column_number), - saved_statement.start_addr, saved_statement.end_addr); - + saved_statement.start_addr, saved_statement.end_addr); // record inline context, if any if (inline_context.size()) { - for (unsigned int i = inline_context.size(); i > 0; i--) { - // record inline context for inline_context[i -1] + + // We only do a lookup when the current function does not contain the current range + if (containingFunc == nullptr || + containingFunc->getOffset() >= saved_statement.start_addr || + containingFunc->getOffset() + containingFunc->getSize() < saved_statement.start_addr) { + + associated_symtab->getContainingFunction(saved_statement.start_addr, containingFunc); + if (containingFunc == nullptr) { + fprintf(stderr, "Cannot find function contains range [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); + assert(0); + } + } + + FunctionBase* cur = static_cast(containingFunc); + FunctionBase* outer_most = cur; + StringTablePtr strings(li_for_object->getStrings()); + const char* func_name_table = static_cast(debug_str->getPtrToRawData()); + + // Record all inline call sites + for (unsigned int i = 0; i < inline_context.size() - 1; ++i) { + cur = recordAnInlinedFunction( + inline_context[i], + inline_context[i + 1], + strings, + cur, + func_name_table, + saved_statement.start_addr, + saved_statement.end_addr); } + recordAnInlinedFunction( + *(inline_context.rbegin()), + saved_statement, + strings, + cur, + func_name_table, + saved_statement.start_addr, + saved_statement.end_addr); + + associated_symtab->addFunctionRange(outer_most, 0); } - dumpLineWithInlineContext(debug_str, saved_statement, inline_context); + //dumpLineWithInlineContext(debug_str, saved_statement, inline_context); +} + +InlinedFunction* Object::recordAnInlinedFunction( + open_statement& caller, + open_statement& callee, + StringTablePtr strings, + FunctionBase *parent, + const char* func_name_table, + Dwarf_Addr start, + Dwarf_Addr end +) { + InlinedFunction *ifunc = new InlinedFunction(parent); + + // Use the filename and line number from the caller + const string& src_file = (*strings)[caller.string_table_index].str; + ifunc->callsite_file_number = strings->project<0>(strings->get<1>().insert(StringTableEntry(src_file,"")).first) - strings->begin(); + ifunc->callsite_line = caller.line_number; + + // Use the function name from the callee + const char* func_name_ptr = func_name_table + callee.funcname_offset; + ifunc->addMangledName(func_name_ptr, true, true); + + ifunc->ranges.emplace_back(FuncRange(start, end - start, ifunc)); + + fprintf(stderr, "%p %p [%lx, %lx)", ifunc, parent, start, end); + fprintf(stderr, " func name %s, line number %d, file name %s, func name index %lx\n", func_name_ptr, ifunc->callsite_line, src_file.c_str(), caller.string_table_index); + return ifunc; } @@ -3803,7 +3802,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) status = dwarf_linefunctionname(line, ¤t_statement.funcname_offset); if(status != 0) { cout << "dwarf_linefunctionname failed" << endl; - continue; + continue; } if (saved_statement.uninitialized()) { @@ -3820,7 +3819,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // record saved_statement and its inlining context if any addresses fall // between saved_statement and current_statement. if (current_statement.start_addr != saved_statement.start_addr) - recordLine (li_for_object, debug_str, saved_statement, inline_context); + recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); // record saved_statement as inlined context for current_statement` inline_context.push_back(saved_statement); @@ -3833,7 +3832,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) if (!pushed) { // we didn't add saved_statement to the inlined context of current_statement, // so a line map entry for saved_statement needs to be recorded - recordLine (li_for_object, debug_str, saved_statement, inline_context); + recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); } if (current_statement.context == 0) { diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index 8a8dbf3511..a2255419e8 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -77,6 +77,73 @@ class pdElfShdr; class Symtab; class Region; class Object; +class InlinedFunction; + +class open_statement { + public: + open_statement() { reset(); }; + Dwarf_Addr noAddress() { return (Dwarf_Addr) ~0; } + bool uninitialized() { + return start_addr == noAddress(); + }; + void reset() { + string_table_index = -1; + start_addr = noAddress(); + end_addr = noAddress(); + line_number = 0; + column_number = 0; + context = 0; + funcname_offset = 0; + }; + bool sameFileLineColumn(const open_statement &rhs) { + return ((string_table_index == rhs.string_table_index) && + (line_number == rhs.line_number) && + (column_number == rhs.column_number)); + }; + void operator=(const open_statement &rhs) { + string_table_index = rhs.string_table_index; + start_addr = rhs.start_addr; + end_addr = rhs.end_addr; + line_number = rhs.line_number; + column_number = rhs.column_number; + context = rhs.context; + funcname_offset = rhs.funcname_offset; + }; + friend std::ostream& operator<<(std::ostream& os, const open_statement& st) + { + st.dump(os, 0, true); + return os; + }; + const char * str(Region *r, unsigned int offset) const { + return ((char *) r->getPtrToRawData()) + offset; + }; + void dump(std::ostream& os, Region *debug_str, bool addrRange) const { + // to facilitate comparison with nvdisasm output, where each function starts at 0, + // set o to an offset that makes a function of interest report addresses that + // match its unrelocated offsets reported by nvdisasm + unsigned int o = 0; + if (addrRange) os << "[" << std::hex << start_addr - o << ", " << end_addr - o << "]"; + else os << " inlined at"; + os << " file:" << string_table_index; + os << " line:" << std::dec << line_number; + os << " col:" << column_number; + if (context) { + os << " context " << context; + os << " function name " << str(debug_str, funcname_offset); + os << " function name offset " << std::hex << funcname_offset << std::dec; + } + os << std::endl; + } + public: + Dwarf_Word string_table_index; + Dwarf_Addr start_addr; + Dwarf_Addr end_addr; + int line_number; + int column_number; + unsigned int context; + unsigned int funcname_offset; +}; + class Object : public AObject { @@ -349,6 +416,22 @@ class Object : public AObject private: void parseLineInfoForCU(Module::DebugInfoT cuDIE, LineInformation* li); + void recordLine( + LineInformation *li_for_object, + Region *debug_str, + open_statement &saved_statement, + std::vector &inline_context, + Symtab* associated_symtab + ); + InlinedFunction* recordAnInlinedFunction( + open_statement&, + open_statement&, + StringTablePtr, + FunctionBase*, + const char*, + Dwarf_Addr, + Dwarf_Addr + ); LineInformation* li_for_object; LineInformation* parseLineInfoForObject(StringTablePtr strings); @@ -422,6 +505,7 @@ class Object : public AObject std::vector > new_dynamic_entries; private: const char* soname_; + Function* containingFunc; }; diff --git a/symtabAPI/src/Symtab-lookup.C b/symtabAPI/src/Symtab-lookup.C index 0f5d88c3db..8545baf14f 100644 --- a/symtabAPI/src/Symtab-lookup.C +++ b/symtabAPI/src/Symtab-lookup.C @@ -722,13 +722,13 @@ bool Symtab::addFunctionRange(FunctionBase *func, Dyninst::Offset next_start) for (FuncRangeCollection::iterator i = ranges.begin(); i != ranges.end(); i++) { FuncRange &range = *i; if (range.low() == sym_low && range.high() == sym_high) - found_sym_range = true; + found_sym_range = true; func_lookup->insert(&range); } //Add symbol range to func_lookup, if present and not already added if (!found_sym_range && sym_low && sym_high) { - FuncRange *frange = new FuncRange(sym_low, sym_high - sym_low, func); + FuncRange *frange = new FuncRange(sym_low, sym_high - sym_low, func); func_lookup->insert(frange); } @@ -825,7 +825,7 @@ bool Symtab::getContainingFunction(Offset offset, Function* &func) } bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) -{ +{ if (!func_lookup) parseFunctionRanges(); assert(func_lookup); @@ -851,7 +851,7 @@ bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) // Therefore, here we heuristicaly prefer the deeper call chain // to reflect inlining information. int maxDepth = 0; - for (auto range : ranges) { + for (auto range : ranges) { FunctionBase *cur_func = range->container; int depth = 0; while (cur_func) { @@ -862,7 +862,7 @@ bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) maxDepth = depth; func = range->container; } - } + } return true; } From 818d3c6441865bc2cc7b79ea15df7ec3fb3e9faf Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 27 Jul 2021 11:23:42 -0500 Subject: [PATCH 045/505] Inline context from nvidia extended line map identifies an inlined call path --- symtabAPI/src/Object-elf.C | 24 +++++++++++++----------- symtabAPI/src/Object-elf.h | 3 +++ 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 36d1472374..d563b6a4cb 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3601,7 +3601,7 @@ Object::recordLine associated_symtab->addFunctionRange(outer_most, 0); } - //dumpLineWithInlineContext(debug_str, saved_statement, inline_context); + dumpLineWithInlineContext(debug_str, saved_statement, inline_context); } InlinedFunction* Object::recordAnInlinedFunction( @@ -3626,27 +3626,28 @@ InlinedFunction* Object::recordAnInlinedFunction( ifunc->ranges.emplace_back(FuncRange(start, end - start, ifunc)); - fprintf(stderr, "%p %p [%lx, %lx)", ifunc, parent, start, end); - fprintf(stderr, " func name %s, line number %d, file name %s, func name index %lx\n", func_name_ptr, ifunc->callsite_line, src_file.c_str(), caller.string_table_index); + //fprintf(stderr, "%p %p [%lx, %lx)", ifunc, parent, start, end); + //fprintf(stderr, " func name %s, line number %d, file name %s, func name index %lx\n", func_name_ptr, ifunc->callsite_line, src_file.c_str(), caller.string_table_index); return ifunc; } void -deleteAnyMatchingInlinedContext +Object::lookupInlinedContext ( vector &inline_context, open_statement &saved_statement ) { + // If we encounter an unseen inline context, + // the current inlining call path is stored with the inline context id. + // Otherwise, we replace current context with the stored one unsigned int c = saved_statement.context; if (c) { - for (unsigned int i = 0; i < inline_context.size(); i++) { - if (inline_context[i].context == c) { - // delete the entry matching c and any nexted entries - inline_context.erase(inline_context.begin() + i, inline_context.end()); - return; - } + if (contextMap.find(c) == contextMap.end()) { + contextMap[c] = inline_context; + } else { + inline_context = contextMap[c]; } } } @@ -3814,7 +3815,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // if saved_statement.context is non-zero, we need to remove any previously // recorded inlined context that matches saved_statement.context or is // nexted inside the matching context - deleteAnyMatchingInlinedContext(inline_context, saved_statement); + lookupInlinedContext(inline_context, saved_statement); // record saved_statement and its inlining context if any addresses fall // between saved_statement and current_statement. @@ -3846,6 +3847,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) } if (isEndOfSequence) { saved_statement.reset(); + contextMap.clear(); } } } diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index a2255419e8..d7cc038021 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -432,6 +432,8 @@ class Object : public AObject Dwarf_Addr, Dwarf_Addr ); + + void lookupInlinedContext( std::vector &, open_statement &); LineInformation* li_for_object; LineInformation* parseLineInfoForObject(StringTablePtr strings); @@ -506,6 +508,7 @@ class Object : public AObject private: const char* soname_; Function* containingFunc; + std::unordered_map > contextMap; }; From 490c093550eb5722b43ce430f1ed42975aa01586 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Thu, 19 Aug 2021 20:57:13 -0500 Subject: [PATCH 046/505] 1. Handle unrelocated line map entries for CUBIN 2. Remove redundant addFunctionRange call to improve performance 3. Add some debug logging --- symtabAPI/src/Object-elf.C | 116 ++++++++++++++++++++----------------- 1 file changed, 64 insertions(+), 52 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index d563b6a4cb..6d8d229d1e 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3552,7 +3552,8 @@ Object::recordLine vector &inline_context, Symtab* associated_symtab ) -{ +{ + lineinfo_printf("Object::recordLine for [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); // record line map entry li_for_object->addLine((unsigned int)(saved_statement.string_table_index), (unsigned int)(saved_statement.line_number), @@ -3565,11 +3566,14 @@ Object::recordLine if (containingFunc == nullptr || containingFunc->getOffset() >= saved_statement.start_addr || containingFunc->getOffset() + containingFunc->getSize() < saved_statement.start_addr) { - + if (containingFunc != nullptr) { + associated_symtab->addFunctionRange(containingFunc, 0); + } + associated_symtab->getContainingFunction(saved_statement.start_addr, containingFunc); if (containingFunc == nullptr) { - fprintf(stderr, "Cannot find function contains range [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); - assert(0); + lineinfo_printf("Cannot find function contains range [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); + return; } } @@ -3597,11 +3601,11 @@ Object::recordLine func_name_table, saved_statement.start_addr, saved_statement.end_addr); - - associated_symtab->addFunctionRange(outer_most, 0); } - dumpLineWithInlineContext(debug_str, saved_statement, inline_context); + if (common_debug_lineinfo) { + dumpLineWithInlineContext(debug_str, saved_statement, inline_context); + } } InlinedFunction* Object::recordAnInlinedFunction( @@ -3625,9 +3629,6 @@ InlinedFunction* Object::recordAnInlinedFunction( ifunc->addMangledName(func_name_ptr, true, true); ifunc->ranges.emplace_back(FuncRange(start, end - start, ifunc)); - - //fprintf(stderr, "%p %p [%lx, %lx)", ifunc, parent, start, end); - //fprintf(stderr, " func name %s, line number %d, file name %s, func name index %lx\n", func_name_ptr, ifunc->callsite_line, src_file.c_str(), caller.string_table_index); return ifunc; } @@ -3724,6 +3725,11 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) open_statement current_statement; vector inline_context; + // The line map may contain un-relocated entries, + // which often corresponds to dead code. + // If we find line map entries with zero address, + // we ignore them until the end of sequence + bool isZeroAddress = false; for(size_t i = 0; i < lineCount; i++ ) { auto line = dwarf_onesrcline(lineBuffer, i); @@ -3744,6 +3750,10 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) cout << "dwarf_lineaddr failed" << endl; continue; } + if (current_statement.start_addr == 0) { + isZeroAddress = true; + containingFunc = nullptr; + } current_statement.start_addr += baseAddr; @@ -3804,51 +3814,53 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) if(status != 0) { cout << "dwarf_linefunctionname failed" << endl; continue; - } + } - if (saved_statement.uninitialized()) { - saved_statement = current_statement; - } else { - bool pushed = false; - saved_statement.end_addr = current_statement.start_addr; - if (saved_statement.context || current_statement.context) { - // if saved_statement.context is non-zero, we need to remove any previously - // recorded inlined context that matches saved_statement.context or is - // nexted inside the matching context - lookupInlinedContext(inline_context, saved_statement); - - // record saved_statement and its inlining context if any addresses fall - // between saved_statement and current_statement. - if (current_statement.start_addr != saved_statement.start_addr) - recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); - - // record saved_statement as inlined context for current_statement` - inline_context.push_back(saved_statement); - - pushed = true; - } - if ((!saved_statement.sameFileLineColumn(current_statement) || - isEndOfSequence)) { - - if (!pushed) { - // we didn't add saved_statement to the inlined context of current_statement, - // so a line map entry for saved_statement needs to be recorded - recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); - } + if (!isZeroAddress && saved_statement.uninitialized()) { + saved_statement = current_statement; + } else if (!isZeroAddress) { + bool pushed = false; + saved_statement.end_addr = current_statement.start_addr; + if (saved_statement.context || current_statement.context) { + // if saved_statement.context is non-zero, we need to remove any previously + // recorded inlined context that matches saved_statement.context or is + // nexted inside the matching context + lookupInlinedContext(inline_context, saved_statement); + + // record saved_statement and its inlining context if any addresses fall + // between saved_statement and current_statement. + if (current_statement.start_addr != saved_statement.start_addr) + recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); + + // record saved_statement as inlined context for current_statement` + inline_context.push_back(saved_statement); + pushed = true; + } + if ((!saved_statement.sameFileLineColumn(current_statement) || isEndOfSequence)) { - if (current_statement.context == 0) { - // a line map statement with context 0 clears all inlined context. - // remove all inlined context entries in the vector. - inline_context.resize(0); - } + if (!pushed) { + // we didn't add saved_statement to the inlined context of current_statement, + // so a line map entry for saved_statement needs to be recorded + recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); + } - saved_statement = current_statement; - } - } - if (isEndOfSequence) { - saved_statement.reset(); - contextMap.clear(); - } + if (current_statement.context == 0) { + // a line map statement with context 0 clears all inlined context. + // remove all inlined context entries in the vector. + inline_context.resize(0); + } + + saved_statement = current_statement; + } + } + if (isEndOfSequence) { + isZeroAddress = false; + saved_statement.reset(); + contextMap.clear(); + if (containingFunc != nullptr) { + associated_symtab->addFunctionRange(containingFunc, 0); + } + } } } return li_for_object; From 7c571dbda212615b42d896d1b080a1669d6a1291 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 24 Aug 2021 14:06:46 -0500 Subject: [PATCH 047/505] Fix compilation warning and add cmake option ENABLE_NVIDIA_EXT_LINE_MAP --- cmake/options.cmake | 1 + symtabAPI/CMakeLists.txt | 2 ++ symtabAPI/src/Object-elf.C | 40 ++++++++++++++++++++------------------ symtabAPI/src/Object-elf.h | 18 ++++++++--------- 4 files changed, 32 insertions(+), 29 deletions(-) diff --git a/cmake/options.cmake b/cmake/options.cmake index 1f46d90df2..081025e798 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -16,6 +16,7 @@ option(BUILD_DOCS "Build manuals from LaTeX sources" ON) option (ENABLE_LTO "Enable Link-Time Optimization" OFF) option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) +option(ENABLE_NVIDIA_EXT_LINE_MAP "Enable debuginfod support" OFF) # Some global on/off switches if (LIGHTWEIGHT_SYMTAB) diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 4ca6896f83..1a15d9ff56 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -102,6 +102,8 @@ endif() dyninst_library(symtabAPI ${DEPS}) +target_compile_definitions(symtabAPI PRIVATE $<$:ENABLE_NVIDIA_EXT_LINE_MAP>) + if(TARGET ElfUtils) add_dependencies(symtabAPI ElfUtils) endif() diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 6d8d229d1e..a0ff8d6b7d 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3546,11 +3546,9 @@ dumpLineWithInlineContext void Object::recordLine ( - LineInformation *li_for_object, Region *debug_str, open_statement &saved_statement, - vector &inline_context, - Symtab* associated_symtab + vector &inline_context ) { lineinfo_printf("Object::recordLine for [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); @@ -3560,7 +3558,7 @@ Object::recordLine (unsigned int)(saved_statement.column_number), saved_statement.start_addr, saved_statement.end_addr); // record inline context, if any - if (inline_context.size()) { + if (debug_str != nullptr && inline_context.size()) { // We only do a lookup when the current function does not contain the current range if (containingFunc == nullptr || @@ -3578,7 +3576,6 @@ Object::recordLine } FunctionBase* cur = static_cast(containingFunc); - FunctionBase* outer_most = cur; StringTablePtr strings(li_for_object->getStrings()); const char* func_name_table = static_cast(debug_str->getPtrToRawData()); @@ -3656,9 +3653,9 @@ Object::lookupInlinedContext LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) { - Region *debug_str; + Region *debug_str = nullptr; std::string debug_str_secname = ".debug_str"; - bool has_debug_str = associated_symtab->findRegion(debug_str, debug_str_secname); + associated_symtab->findRegion(debug_str, debug_str_secname); if (li_for_object) { // The line information for this object has been parsed. @@ -3686,7 +3683,6 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) &files, &fileCount, &lineBuffer, &lineCount)) == 0) { - StringTablePtr strings(li_for_object->getStrings()); boost::unique_lock l(strings->lock); size_t offset = strings->size(); @@ -3804,17 +3800,23 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) continue; } - status = dwarf_linecontext(line, ¤t_statement.context); - if(status != 0) { - cout << "dwarf_linecontext failed" << endl; - continue; - } +#if defined (ENABLE_NVIDIA_EXT_LINE_MAP) + // Only attempt to parse inlining context and inline function name + // when there is a .debug_str section. + if (debug_str != nullptr) { + status = dwarf_linecontext(line, ¤t_statement.context); + if(status != 0) { + cout << "dwarf_linecontext failed" << endl; + continue; + } - status = dwarf_linefunctionname(line, ¤t_statement.funcname_offset); - if(status != 0) { - cout << "dwarf_linefunctionname failed" << endl; - continue; + status = dwarf_linefunctionname(line, ¤t_statement.funcname_offset); + if(status != 0) { + cout << "dwarf_linefunctionname failed" << endl; + continue; + } } +#endif if (!isZeroAddress && saved_statement.uninitialized()) { saved_statement = current_statement; @@ -3830,7 +3832,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // record saved_statement and its inlining context if any addresses fall // between saved_statement and current_statement. if (current_statement.start_addr != saved_statement.start_addr) - recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); + recordLine (debug_str, saved_statement, inline_context); // record saved_statement as inlined context for current_statement` inline_context.push_back(saved_statement); @@ -3841,7 +3843,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) if (!pushed) { // we didn't add saved_statement to the inlined context of current_statement, // so a line map entry for saved_statement needs to be recorded - recordLine (li_for_object, debug_str, saved_statement, inline_context, associated_symtab); + recordLine (debug_str, saved_statement, inline_context); } if (current_statement.context == 0) { diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index d7cc038021..f92a83f351 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -81,11 +81,11 @@ class InlinedFunction; class open_statement { public: - open_statement() { reset(); }; + open_statement() { reset(); } Dwarf_Addr noAddress() { return (Dwarf_Addr) ~0; } bool uninitialized() { return start_addr == noAddress(); - }; + } void reset() { string_table_index = -1; start_addr = noAddress(); @@ -94,12 +94,12 @@ class open_statement { column_number = 0; context = 0; funcname_offset = 0; - }; + } bool sameFileLineColumn(const open_statement &rhs) { return ((string_table_index == rhs.string_table_index) && (line_number == rhs.line_number) && (column_number == rhs.column_number)); - }; + } void operator=(const open_statement &rhs) { string_table_index = rhs.string_table_index; start_addr = rhs.start_addr; @@ -108,15 +108,15 @@ class open_statement { column_number = rhs.column_number; context = rhs.context; funcname_offset = rhs.funcname_offset; - }; + } friend std::ostream& operator<<(std::ostream& os, const open_statement& st) { st.dump(os, 0, true); return os; - }; + } const char * str(Region *r, unsigned int offset) const { return ((char *) r->getPtrToRawData()) + offset; - }; + } void dump(std::ostream& os, Region *debug_str, bool addrRange) const { // to facilitate comparison with nvdisasm output, where each function starts at 0, // set o to an offset that makes a function of interest report addresses that @@ -417,11 +417,9 @@ class Object : public AObject private: void parseLineInfoForCU(Module::DebugInfoT cuDIE, LineInformation* li); void recordLine( - LineInformation *li_for_object, Region *debug_str, open_statement &saved_statement, - std::vector &inline_context, - Symtab* associated_symtab + std::vector &inline_context ); InlinedFunction* recordAnInlinedFunction( open_statement&, From 5378d240934e8f70043ecd33291d9c825be8a461 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Thu, 26 Aug 2021 10:51:00 -0500 Subject: [PATCH 048/505] Add compile-time checking to see if elfutils support nvidia extended line map when the user have specified ENABLE_NVIDIA_EXT_LINE_MAP --- symtabAPI/src/Object-elf.C | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index a0ff8d6b7d..59a5b97447 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -49,6 +49,8 @@ #include "Object-elf.h" +#include "elfutils/version.h" + using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace Dyninst::DwarfDyninst; @@ -3799,8 +3801,13 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) cout << "dwarf_linebeginstatement failed" << endl; continue; } - +// ENABLE_NVIDIA_EXT_LINE_MAP is defined if the Dyninst +// user wants to have nvidia ex line map support #if defined (ENABLE_NVIDIA_EXT_LINE_MAP) + +// NVIDIA_LINEMAP_INLINING_EXTENSIONS is defined if +// the underlying elfutils supports nvidia ex line map +#if defined (NVIDIA_LINEMAP_INLINING_EXTENSIONS) // Only attempt to parse inlining context and inline function name // when there is a .debug_str section. if (debug_str != nullptr) { @@ -3816,7 +3823,11 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) continue; } } -#endif +#else + #error The specified elfutils is not capable of handling nvidia extended line map. Please reconfigure elfutils with "--enable-nvidia-linemap" +#endif // NVIDIA_LINEMAP_INLINING_EXTENSIONS + +#endif // ENABLE_NVIDIA_EXT_LINE_MAP if (!isZeroAddress && saved_statement.uninitialized()) { saved_statement = current_statement; From 2543b18e509bd725cdc8e66f7338f1656ca5094e Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Sat, 6 Nov 2021 15:43:17 -0500 Subject: [PATCH 049/505] Adjust interface changes in elfutils regarding NVIDIA extended line map --- symtabAPI/src/Object-elf.C | 34 ++++++++++------------------------ symtabAPI/src/Object-elf.h | 26 +++++++++++--------------- 2 files changed, 21 insertions(+), 39 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 59a5b97447..f7dc7cfb77 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3531,15 +3531,14 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) void dumpLineWithInlineContext ( - Region *debug_str, open_statement &saved_statement, vector &inline_context ) { - saved_statement.dump(cout, debug_str, true); + saved_statement.dump(cout, true); if (inline_context.size()) { for (unsigned int i = inline_context.size(); i > 0; i--) { - inline_context[i -1].dump(cout, debug_str, false); + inline_context[i -1].dump(cout, false); } } } @@ -3579,7 +3578,6 @@ Object::recordLine FunctionBase* cur = static_cast(containingFunc); StringTablePtr strings(li_for_object->getStrings()); - const char* func_name_table = static_cast(debug_str->getPtrToRawData()); // Record all inline call sites for (unsigned int i = 0; i < inline_context.size() - 1; ++i) { @@ -3588,7 +3586,6 @@ Object::recordLine inline_context[i + 1], strings, cur, - func_name_table, saved_statement.start_addr, saved_statement.end_addr); } @@ -3597,13 +3594,12 @@ Object::recordLine saved_statement, strings, cur, - func_name_table, saved_statement.start_addr, saved_statement.end_addr); } if (common_debug_lineinfo) { - dumpLineWithInlineContext(debug_str, saved_statement, inline_context); + dumpLineWithInlineContext(saved_statement, inline_context); } } @@ -3612,7 +3608,6 @@ InlinedFunction* Object::recordAnInlinedFunction( open_statement& callee, StringTablePtr strings, FunctionBase *parent, - const char* func_name_table, Dwarf_Addr start, Dwarf_Addr end ) { @@ -3624,9 +3619,9 @@ InlinedFunction* Object::recordAnInlinedFunction( ifunc->callsite_line = caller.line_number; // Use the function name from the callee - const char* func_name_ptr = func_name_table + callee.funcname_offset; - ifunc->addMangledName(func_name_ptr, true, true); - + if (callee.funcname != nullptr) { + ifunc->addMangledName(callee.funcname, true, true); + } ifunc->ranges.emplace_back(FuncRange(start, end - start, ifunc)); return ifunc; } @@ -3642,8 +3637,8 @@ Object::lookupInlinedContext // If we encounter an unseen inline context, // the current inlining call path is stored with the inline context id. // Otherwise, we replace current context with the stored one - unsigned int c = saved_statement.context; - if (c) { + void* c = (void*)saved_statement.context; + if (c != nullptr) { if (contextMap.find(c) == contextMap.end()) { contextMap[c] = inline_context; } else { @@ -3811,17 +3806,8 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // Only attempt to parse inlining context and inline function name // when there is a .debug_str section. if (debug_str != nullptr) { - status = dwarf_linecontext(line, ¤t_statement.context); - if(status != 0) { - cout << "dwarf_linecontext failed" << endl; - continue; - } - - status = dwarf_linefunctionname(line, ¤t_statement.funcname_offset); - if(status != 0) { - cout << "dwarf_linefunctionname failed" << endl; - continue; - } + current_statement.context = dwarf_linecontext(lineBuffer, line); + current_statement.funcname = dwarf_linefunctionname(dbg, line); } #else #error The specified elfutils is not capable of handling nvidia extended line map. Please reconfigure elfutils with "--enable-nvidia-linemap" diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index f92a83f351..69b9fa8596 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -92,8 +92,8 @@ class open_statement { end_addr = noAddress(); line_number = 0; column_number = 0; - context = 0; - funcname_offset = 0; + context = nullptr; + funcname = nullptr; } bool sameFileLineColumn(const open_statement &rhs) { return ((string_table_index == rhs.string_table_index) && @@ -107,17 +107,15 @@ class open_statement { line_number = rhs.line_number; column_number = rhs.column_number; context = rhs.context; - funcname_offset = rhs.funcname_offset; + funcname = rhs.funcname; } friend std::ostream& operator<<(std::ostream& os, const open_statement& st) { - st.dump(os, 0, true); + st.dump(os, true); return os; } - const char * str(Region *r, unsigned int offset) const { - return ((char *) r->getPtrToRawData()) + offset; - } - void dump(std::ostream& os, Region *debug_str, bool addrRange) const { + + void dump(std::ostream& os, bool addrRange) const { // to facilitate comparison with nvdisasm output, where each function starts at 0, // set o to an offset that makes a function of interest report addresses that // match its unrelocated offsets reported by nvdisasm @@ -127,10 +125,9 @@ class open_statement { os << " file:" << string_table_index; os << " line:" << std::dec << line_number; os << " col:" << column_number; - if (context) { + if (context != nullptr) { os << " context " << context; - os << " function name " << str(debug_str, funcname_offset); - os << " function name offset " << std::hex << funcname_offset << std::dec; + os << " function name " << funcname; } os << std::endl; } @@ -140,8 +137,8 @@ class open_statement { Dwarf_Addr end_addr; int line_number; int column_number; - unsigned int context; - unsigned int funcname_offset; + Dwarf_Line* context; + const char* funcname; }; @@ -426,7 +423,6 @@ class Object : public AObject open_statement&, StringTablePtr, FunctionBase*, - const char*, Dwarf_Addr, Dwarf_Addr ); @@ -506,7 +502,7 @@ class Object : public AObject private: const char* soname_; Function* containingFunc; - std::unordered_map > contextMap; + std::unordered_map > contextMap; }; From 07fbe1167780f64ea09e09f44b9a7b96c0370f04 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Wed, 10 Nov 2021 15:55:58 -0600 Subject: [PATCH 050/505] Add CMake test to check if libdw supports NVIDIA extended line map --- cmake/ElfUtils.cmake | 10 ++++++++++ cmake/options.cmake | 2 +- symtabAPI/src/Object-elf.C | 8 -------- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/cmake/ElfUtils.cmake b/cmake/ElfUtils.cmake index ec895c3a7a..975e361e04 100644 --- a/cmake/ElfUtils.cmake +++ b/cmake/ElfUtils.cmake @@ -166,3 +166,13 @@ include_directories(${ElfUtils_INCLUDE_DIRS}) message(STATUS "ElfUtils includes: ${ElfUtils_INCLUDE_DIRS}") message(STATUS "ElfUtils library dirs: ${ElfUtils_LIBRARY_DIRS}") message(STATUS "ElfUtils libraries: ${ElfUtils_LIBRARIES}") + +include(CheckSymbolExists) +if(ENABLE_NVIDIA_EXT_LINE_MAP) + set(CMAKE_REQUIRED_INCLUDES ${ElfUtils_INCLUDE_DIRS}) + set(CMAKE_REQUIRED_LIBRARIES ${ElfUtils_LIBRARIES}) + check_symbol_exists(dwarf_linecontext elfutils/libdw.h _has_exmap) + if(NOT _has_exmap) + message(FATAL_ERROR "ElfUtils does not support NVIDIA line maps") + endif() +endif() diff --git a/cmake/options.cmake b/cmake/options.cmake index 081025e798..67e9636a95 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -16,7 +16,7 @@ option(BUILD_DOCS "Build manuals from LaTeX sources" ON) option (ENABLE_LTO "Enable Link-Time Optimization" OFF) option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) -option(ENABLE_NVIDIA_EXT_LINE_MAP "Enable debuginfod support" OFF) +option(ENABLE_NVIDIA_EXT_LINE_MAP "Enable support for NVIDIA extended line map" OFF) # Some global on/off switches if (LIGHTWEIGHT_SYMTAB) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index f7dc7cfb77..e15e0a8715 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -49,8 +49,6 @@ #include "Object-elf.h" -#include "elfutils/version.h" - using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace Dyninst::DwarfDyninst; @@ -3800,18 +3798,12 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) // user wants to have nvidia ex line map support #if defined (ENABLE_NVIDIA_EXT_LINE_MAP) -// NVIDIA_LINEMAP_INLINING_EXTENSIONS is defined if -// the underlying elfutils supports nvidia ex line map -#if defined (NVIDIA_LINEMAP_INLINING_EXTENSIONS) // Only attempt to parse inlining context and inline function name // when there is a .debug_str section. if (debug_str != nullptr) { current_statement.context = dwarf_linecontext(lineBuffer, line); current_statement.funcname = dwarf_linefunctionname(dbg, line); } -#else - #error The specified elfutils is not capable of handling nvidia extended line map. Please reconfigure elfutils with "--enable-nvidia-linemap" -#endif // NVIDIA_LINEMAP_INLINING_EXTENSIONS #endif // ENABLE_NVIDIA_EXT_LINE_MAP From 154dde783dbadd502c25b451e10eecdc3b6c732b Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 11 Nov 2021 14:38:48 -0600 Subject: [PATCH 051/505] Documentation update for 12.0.0 release (#1151) Co-authored-by: Tim Haines --- CHANGELOG.md | 157 ++++++++++++++++++++++++++ cmake/shared.cmake | 4 +- common/doc/manual_frontpage.tex | 4 +- dataflowAPI/doc/dataflowAPI.pdf | Bin 349746 -> 349805 bytes dynC_API/doc/dynC_API.pdf | Bin 298452 -> 298512 bytes dyninstAPI/doc/dyninstAPI.docx | Bin 150585 -> 151312 bytes dyninstAPI/doc/dyninstAPI.pdf | Bin 409142 -> 409466 bytes instructionAPI/doc/instructionAPI.pdf | Bin 563367 -> 563428 bytes parseAPI/doc/parseAPI.pdf | Bin 401523 -> 404138 bytes patchAPI/doc/patchAPI.pdf | Bin 614110 -> 614185 bytes proccontrol/doc/proccontrol.docx | Bin 163615 -> 105765 bytes proccontrol/doc/proccontrol.pdf | Bin 854102 -> 355537 bytes stackwalk/doc/stackwalk.pdf | Bin 318531 -> 318588 bytes symtabAPI/doc/symtabAPI.pdf | Bin 452050 -> 457426 bytes 14 files changed, 161 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3809907c4c..84423abe4d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,162 @@ # Change Log +## [12.0.0](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-11) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.1...v12.0.0) + +**GPU Support** + +- Add CMake test to check if libdw supports NVIDIA extended line map +- Adjust interface changes in elfutils regarding NVIDIA extended line map +- Add compile-time checking to see if elfutils support nvidia extended line map when the user have specified ENABLE_NVIDIA_EXT_LINE_MAP +- Fix compilation warning and add cmake option ENABLE_NVIDIA_EXT_LINE_MAP +- 1. Handle unrelocated line map entries for CUBIN 2. Remove redundant addFunctionRange call to improve performance 3. Add some debug logging +- Inline context from nvidia extended line map identifies an inlined call path +- Start to construct inlining call chains using Nvidia's extended line map +- cleaning up code for ingesting nvidia extended linemaps +- first draft of support for nvidia enhanced line maps + +**Enhancements** + +- Load callee's address when the callee and caller are in the same module ([1056](https://github.com/dyninst/dyninst/issues/1056)) +- Give global annotation objects internal linkage and file scope +- Summit fixes ([1108](https://github.com/dyninst/dyninst/issues/1108)) +- Add x86 xsavec instruction ([1074](https://github.com/dyninst/dyninst/issues/1074)) +- Convert TRAMP_\*_OFFSET macros to functions ([1073](https://github.com/dyninst/dyninst/issues/1073)) +- Add x86_64 xrstor instruction ([1070](https://github.com/dyninst/dyninst/issues/1070)) +- Fix insertion operators in BPatch and Symtab ([1069](https://github.com/dyninst/dyninst/issues/1069)) +- Add DWARF4 base type entry encodings to symtabAPI::typeScalar ([1059](https://github.com/dyninst/dyninst/issues/1059)) +- Add xsave instruction ([1055](https://github.com/dyninst/dyninst/issues/1055)) +- Cleanup orphaned code ([1064](https://github.com/dyninst/dyninst/issues/1064)) + +**ABI Breakages** +- Remove AddressSpace::causeTemplateInstantiations ([1149](https://github.com/dyninst/dyninst/issues/1149)) +- Remove unregisterTrapMapping from PCProcess +- Remove thread registration functions from PCProcess +- Remove PCProcess::getDeadCode +- Remove memory emulation ([1146](https://github.com/dyninst/dyninst/issues/1146)) +- Remove unused generateSimple ([1122](https://github.com/dyninst/dyninst/issues/1122)) +- Remove unused variables from Symtab +- Remove special Fortran debug handling +- Remove stabs from symbol demangling +- Remove stabs from BPatch +- Remove stabs from SymtabAPI +- Remove Module::getAllVariables ([1066](https://github.com/dyninst/dyninst/issues/1066)) + +**Documentation** + +- Improve docs for lookup functions in CodeObject ([1147](https://github.com/dyninst/dyninst/issues/1147)) +- Update copyright to 2022 ([1141](https://github.com/dyninst/dyninst/issues/1141)) +- Remove stabs from documentation ([1120](https://github.com/dyninst/dyninst/issues/1120)) + +**Build Changes** +- Remove ppc32 from builds ([1145](https://github.com/dyninst/dyninst/issues/1145)) +- Unify meaning of 'cap_32_64' macro ([1136](https://github.com/dyninst/dyninst/issues/1136)) +- Remove support for Cray CNL ([1137](https://github.com/dyninst/dyninst/issues/1137)) +- Remove xlc macros ([1132](https://github.com/dyninst/dyninst/issues/1132)) +- Remove common/src/language.h ([1131](https://github.com/dyninst/dyninst/issues/1131)) +- Remove usage of arch_ppc and arch_ppc64 ([1129](https://github.com/dyninst/dyninst/issues/1129)) +- Remove usage of x86_64_cnl ([1130](https://github.com/dyninst/dyninst/issues/1130)) +- Remove DynC tests ([1126](https://github.com/dyninst/dyninst/issues/1126)) +- Remove NO_INITIALIZER_LIST_SUPPORT ([1125](https://github.com/dyninst/dyninst/issues/1125)) +- Turn on STERILE_BUILD by default ([1118](https://github.com/dyninst/dyninst/issues/1118)) +- update minimum boost version to 1.70.0 ([1117](https://github.com/dyninst/dyninst/issues/1117)) +- Remove boost_system linking ([1112](https://github.com/dyninst/dyninst/issues/1112)) +- Enforce detection of libiberty ([1099](https://github.com/dyninst/dyninst/issues/1099)) +- fix compiler warnings to work with clang ([1092](https://github.com/dyninst/dyninst/issues/1092)) +- update optimization (-Og) and debug flags (-g3) ([1084](https://github.com/dyninst/dyninst/issues/1084)) +- use the C11 standard for C code in Dyninst ([1086](https://github.com/dyninst/dyninst/issues/1086)) +- Make Dyninst buildable with Clang ([1021](https://github.com/dyninst/dyninst/issues/1021)) +- Remove valueAdded subdirectory completely ([1065](https://github.com/dyninst/dyninst/issues/1065)) +- Remove valueAdded subdirectory ([1063](https://github.com/dyninst/dyninst/issues/1063)) + +**Bug Fixes** +- fix statement-like macros ([1143](https://github.com/dyninst/dyninst/issues/1143)) +- Don't overflow aarch64 float register vector when setting used regs. ([1127](https://github.com/dyninst/dyninst/issues/1127)) +- fix unused const variable warnings +- fix pessimizing std::move warnings +- fix xor operator used as power operator +- fix misleading indentation warning +- fix uninitialized this and variable warnings +- fix float to double promotion warning +- fix unused const variable warnings +- Fix possible buffer overflow in BPatch::processCreate +- Fix uninitialized variable use in DispatcherARM64::iproc_init +- remove executable flag from .dyninst_heap section ([1096](https://github.com/dyninst/dyninst/issues/1096)) +- fix broken cast of a char literal to pointer ([1090](https://github.com/dyninst/dyninst/issues/1090)) +- fix possibly uninitialized variables ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix possible null 'this' pointer dereference ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- prevent maybe uninitialized warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- adjust large frame threshold for specific sources ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix deprecated implicit assignment operator ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix buffer overflow ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix duplicate branch condition by removing branch ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix out of bounds array access ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix potentially uninitialized variable warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- use unused variable to correct code ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove unused variables ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix broken bool expression that was always true ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing initializer braces ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make constructor public so class is usable ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove ';' after in-class method definitions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate logical op warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make implicit double promotions explicit ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- annotate malloc-like functions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make method noexcept, so noexcept expr can be true ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing default to switch statement ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix int to void\* cast if sizeof(int) ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix unused vars/params/funcs on aarch64 ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix ambiguous type name warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove always true || sub-expression ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix possible sprintf buffer overflow ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- delete unnecessary ambiguous forward class decl ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make destructor virtual if a virtual method exist ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument signedness match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add compiler annotation to printf-like functions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix var-tracking-assignments warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove assert(this) as 'this' should never be null ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove obvious null pointer dereference ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix for C++20 removal of std::allocator methods ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make cmp function object operator() a const func ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make Boost and TBB include dirs be system includes ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix shadow variable warning, has other brokenness ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix duplicate branch warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate switch case fall through warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- explicit base class initialization in constructor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove default argument from lambda ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove non-C++ compound literal ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- do not compile empty compilation units ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix deprecated implicit copy constructor if dtor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing copy assignment ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix illegal in C empty brace initialization ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- disable flexible array member warning in C++ ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix discard qualifiers: make char\* -> const char\* ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix non-standard use of \_\_VA_ARGS\_\_ ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove excess semicolons as reported by -pedantic ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix overflow warning for 0x90 assigned to a char ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix illegal function pointer to void\* compare ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove use of GNU binary operator ?: ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove non-C++ variable length arrays ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix shadow identifier warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- enable more warnings and test compiler support ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- miscellaneous compiler warning cleanups ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate switch case fall through warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add header with compiler annotation macros ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing break statements ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- compute num array elements instead of fixed values ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove dynamic_ and dynamic() from fileDescriptor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove emptyString static members ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- delete unnecessary .DS_Store file ([1082](https://github.com/dyninst/dyninst/issues/1082)) + + ## [11.0.1](https://github.com/dyninst/dyninst/tree/v11.0.1) (2021-06-14) [Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.0...v11.0.1) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 77ef83499a..38b21b3ea0 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,6 +1,6 @@ -set (DYNINST_MAJOR_VERSION 11) +set (DYNINST_MAJOR_VERSION 12) set (DYNINST_MINOR_VERSION 0) -set (DYNINST_PATCH_VERSION 1) +set (DYNINST_PATCH_VERSION 0) set (SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") set (LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") diff --git a/common/doc/manual_frontpage.tex b/common/doc/manual_frontpage.tex index e61d3c6246..60796bf0f6 100644 --- a/common/doc/manual_frontpage.tex +++ b/common/doc/manual_frontpage.tex @@ -42,9 +42,9 @@ % }; \node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$) - {\fontsize{24}{32}\selectfont 11.0 Release}; + {\fontsize{24}{32}\selectfont 12.0 Release}; \node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$) - {\fontsize{24}{32}\selectfont April 2021}; + {\fontsize{24}{32}\selectfont November 2021}; % Contact information % \matrix (UWaddress) [% diff --git a/dataflowAPI/doc/dataflowAPI.pdf b/dataflowAPI/doc/dataflowAPI.pdf index fce535adb41e080348f42331f03bcaa819101a8b..8f613b960252a3d8b6cf2573eae31507f40d9f7a 100644 GIT binary patch delta 18076 zcmZU4bBy4<6ZhJ-ackT5t!>*jzsp&v(TI1RQ}MG1b^FW{Q_sWWflav9O6c!7OO@cSD|L zvDM19ZN0rQSf`L21D;n;PEIcyuZ3W(i4ihNY8=%ttLR_YM2;?i8$szk3VLB6ZJ3Ef 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zZ9fC)J=xV=8sA6GJdFRG^(nO#>m==q4wvjkryK{~dK6s$f5JxVv^C_QW zLEW~o9ol@t|EYoFMz{m&Xj1<>zX@Du9p9zvHfeR;!4gzw;4iB_tIxBa)p>wu9QT^% z_{B1S&{DKE5;WFhQlKn#NV6D%uLRhlC^l)0i{-set`aiM``9Ng79>INpxc%<28dOK zh4Jg2+bTv)uI5+6$VIo!T$C_274y5Vm^O7Dp@mFrhCC@mX#_C4F z<)m0o2RgH#gfx3mY#uZlXqffUc*HAC#-$NdP)Zkex=9Hf2`mKQipHlmuuSg`+%OCL}x1T#f}>y``8IcqRz@lhxFGcAsI=F3zas z)IV4(ITkq*>>Tbwqj-y{|2%5yBas^n=bi1C9|(>Z`%Es3ne>?M5%Nqug*5=xg^Moy z+*vxH%^8b91MEgE&WS91*O@#IX+gOgkn~+9So7~2v}Qo#KE3=60w0czn}eAhhMZhn IQ3B?F0h3;b3;+NC From 4f6f1a21abc14820ea1a752856d6f20bf0a0694b Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sat, 13 Nov 2021 14:59:08 -0600 Subject: [PATCH 052/505] Add conflict with CMake 3.19.0 (#1153) There is a bug in 3.19.0 that treats .S files like C-language files. Co-authored-by: Tim Haines --- CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7f394dcb8e..994d3e35ba 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,10 @@ cmake_minimum_required (VERSION 3.4.0) + +# There is a bug in 3.19.0 that causes .S files to be treated like C files +if(CMAKE_VERSION VERSION_EQUAL "3.19.0") + message(FATAL_ERROR "Dyninst cannot use CMake version 3.19.0") +endif() + project (Dyninst) set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}) From 71027cb36e9deb4291f316fb0a4c897ff2e321dd Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 17 Nov 2021 18:51:26 -0600 Subject: [PATCH 053/505] DwarfWalker: clean up interfaces for findDieName and findName (#1154) findDieName always returned 'true', so any checks for its return value were meaningless. It was also not clear that 'findName' would modify its argument. The new interface removes that surprise by making the name the return value. Co-authored-by: Tim Haines --- symtabAPI/src/Object-elf.C | 11 ++---- symtabAPI/src/dwarfWalker.C | 68 +++++++++++++++---------------------- symtabAPI/src/dwarfWalker.h | 4 +-- 3 files changed, 33 insertions(+), 50 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index e15e0a8715..020356f9fe 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -2243,10 +2243,7 @@ bool Object::dwarf_parse_aranges(Dwarf *dbg, std::set &/*dies_seen*/) auto off_die = dwarf_dieoffset(&cu_die); //if (dies_seen.find(off_die) != dies_seen.end()) continue; - std::string modname; - if (!DwarfWalker::findDieName(cu_die, modname)) { - modname = associated_symtab->file(); // default module - } + std::string modname = DwarfWalker::die_name(cu_die); Offset actual_start, actual_end; convertDebugOffset(start, actual_start); @@ -2301,10 +2298,8 @@ bool Object::fix_global_symbol_modules_static_dwarf() { for (size_t i = 0; i < dies.size(); i++) { Dwarf_Die cu_die = dies[i]; - std::string modname; - if (!DwarfWalker::findDieName(cu_die, modname)) { - modname = associated_symtab->file(); // default module - } + std::string modname = DwarfWalker::die_name(cu_die); + if(modname=="") { auto off_die = dwarf_dieoffset(&cu_die); diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 88426852c9..7fb678598a 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -232,8 +232,7 @@ bool DwarfWalker::parseModule(Dwarf_Die moduleDIE, Module *&fixUnknownMod) { return false; /* Extract the name of this module. */ - std::string moduleName; - if (!findDieName(moduleDIE, moduleName)) return false; + std::string moduleName = die_name(moduleDIE); // DIEs without name or named will be associated to // the default module (whose name is ELF filename) @@ -819,8 +818,7 @@ bool DwarfWalker::parseLexicalBlock() { bool DwarfWalker::parseCommonBlock() { dwarf_printf("(0x%lx) Parsing common block\n", id()); - std::string commonBlockName; - if (!findDieName(entry(), commonBlockName)) return false; + std::string commonBlockName = die_name(entry()); Symbol* commonBlockVar = findSymbolForCommonBlock(commonBlockName); if(!commonBlockVar) { @@ -878,9 +876,7 @@ bool DwarfWalker::parseVariable() { if (!handleSpecification(hasSpecification)) return false; - if (!findName(curName())) - return false; - + curName() = std::move(die_name()); removeFortranUnderscore(curName()); /* We'll start with the location, since that's most likely to @@ -1040,7 +1036,7 @@ bool DwarfWalker::parseFormalParam() { return false; } - if (!findName(curName())) return false; + curName() = std::move(die_name()); /* We can't do anything with anonymous parameters. */ if (!nameDefined()) { dwarf_printf("(0x%lx) No name associated with formal, returning\n", id()); @@ -1085,7 +1081,7 @@ bool DwarfWalker::parseBaseType() { if(!tc()) return false; dwarf_printf("(0x%lx) parseBaseType entry\n", id()); - if (!findName(curName())) return false; + curName() = std::move(die_name()); if (!nameDefined()) { dwarf_printf("(0x%lx) No name for type, returning early\n", id()); return true; @@ -1169,7 +1165,7 @@ bool DwarfWalker::parseTypedef() { boost::shared_ptr referencedType; if (!findType(referencedType, true)) return false; - if (!findName(curName())) return false; + curName() = std::move(die_name()); if (!nameDefined()) { if (!fixName(curName(), referencedType)) return false; } @@ -1201,7 +1197,7 @@ bool DwarfWalker::parseArray() { if (!findType(elementType, false)) return false; if (!elementType) return false; - if (!findName(curName())) return false; + curName() = std::move(die_name()); // curName may get overridden by the subrange parsing code. // TODO: make this part of the context stack. @@ -1262,7 +1258,7 @@ bool DwarfWalker::parseSubrange() { bool DwarfWalker::parseEnum() { if(!tc()) return false; dwarf_printf("(0x%lx) parseEnum entry\n", id()); - if (!findName(curName())) return false; + curName() = std::move(die_name()); //setEnum(tc()->addOrUpdateType( Type::make_shared( type_id(), "enum " + curName()))); setEnum(tc()->addOrUpdateType( Type::make_shared( type_id(), curName()))); return true; @@ -1301,7 +1297,7 @@ bool DwarfWalker::parseStructUnionClass() { return false; } - if (!findName(curName())) return false; + curName() = std::move(die_name()); dwarf_printf("(0x%lx) Struct/Union/Class name from dwarf: %s\n", id(), curName().c_str()); if (!nameDefined()) { @@ -1372,8 +1368,7 @@ bool DwarfWalker::parseStructUnionClass() { bool DwarfWalker::parseEnumEntry() { dwarf_printf("(0x%lx) parseEnumEntry entry\n", id()); - std::string name; - if (!findName(name)) return false; + std::string name = die_name(); long value = 0; bool valid; @@ -1391,7 +1386,7 @@ bool DwarfWalker::parseMember() { if (!findType(memberType, false)) return false; if (!memberType) return false; - if (!findName(curName())) return false; + curName() = std::move(die_name()); long value; bool hasValue; @@ -1447,7 +1442,7 @@ bool DwarfWalker::parseConstPackedVolatile() { boost::shared_ptr type = NULL; if (!findType(type, true)) return false; - if (!findName(curName())) return false; + curName() = std::move(die_name()); if (!nameDefined()) { dwarf_printf("(0x%lx) parseConstPackedVolatile fixName\n", id()); if (!fixName(curName(), type)) return false; @@ -1467,11 +1462,7 @@ bool DwarfWalker::parseTypeReferences() { return false; } - if (!findName(curName())) - { - dwarf_printf("(0x%lx) name not found\n", id()); - return false; - } + curName() = std::move(die_name()); Dwarf_Die e = entry(); boost::shared_ptr indirectType; @@ -1576,22 +1567,21 @@ bool DwarfWalker::handleSpecification(bool &hasSpec) { return true; } -bool DwarfWalker::findDieName(Dwarf_Die die, std::string &name) +std::string DwarfWalker::die_name(Dwarf_Die die) { - auto cname = dwarf_diename(&die); - if (cname == 0) { - name = std::string(); - return true; - } + auto name = dwarf_diename(&die); - name = cname; - return true; + // You cannot construct a std::string from a null pointer + if (name) { + return name; + } + return {}; } -bool DwarfWalker::findName(std::string &name) { - if (!findDieName(specEntry(), name)) return false; +std::string DwarfWalker::die_name() { + auto name = die_name(specEntry()); dwarf_printf("(0x%lx) Found name %s.\n", id(), name.c_str()); - return true; + return name; } @@ -1617,7 +1607,8 @@ bool DwarfWalker::findFuncName() { dwarf_printf("(0x%lx) DW_AT_linkage_name name not found\n", id()); setMangledName(false); - return findDieName(entry(), curName()); + curName() = std::move(die_name(entry())); + return true; } std::vector& DwarfParseActions::getFramePtrRefForInit() @@ -2265,10 +2256,7 @@ bool DwarfWalker::parseSubrangeAUX(Dwarf_Die entry, } /* end if we found an upper bound or count. */ /* Construct the range type. */ - if (!findName(curName())) { - dwarf_printf("cannot find subrange name %s\n", curName().c_str()); - return false; - } + curName() = std::move(die_name()); if (!nameDefined()) { curName() = "{anonymousRange}"; } @@ -2403,8 +2391,8 @@ bool DwarfWalker::decipherBound(Dwarf_Attribute boundAttribute, bool /*is_info*/ if(!ret_p) return false; /* Does it have a name? */ - if (findDieName(boundEntry, boundString) - && !boundString.empty()) + boundString = std::move(die_name(boundEntry)); + if (!boundString.empty()) return true; /* Does it describe a nameless constant? */ diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 5dd6663c67..c8c74dbfad 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -344,9 +344,9 @@ class DwarfWalker : public DwarfParseActions { bool &hasLineNumber, std::string &filename); public: - static bool findDieName(Dwarf_Die die, std::string &); + static std::string die_name(Dwarf_Die die); private: - bool findName(std::string &); + std::string die_name(); void removeFortranUnderscore(std::string &); bool findSize(unsigned &size); bool findVisibility(visibility_t &visibility); From 29bcc7b203293627bf627a815f5caa6af4202c32 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sat, 20 Nov 2021 11:24:06 -0600 Subject: [PATCH 054/505] Add readable name for Symtab::typeRef (#1157) Arguably, this is completely arbitrary as it could have been spelled 'ref', 'reference', etc. Using the language symbol also allows users to reconstruct source-level syntax more directly. Co-authored-by: Tim Haines --- symtabAPI/src/dwarfWalker.C | 3 +++ 1 file changed, 3 insertions(+) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 7fb678598a..1cea4a47a7 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -1480,6 +1480,9 @@ bool DwarfWalker::parseTypeReferences() { offset(), indirectType->getSize(), (void*)tc(), mod()->fullName().c_str()); break; case DW_TAG_reference_type: + if(!nameDefined()){ + curName() = "&"; + } indirectType = tc()->addOrUpdateType(Type::make_shared( type_id(), typePointedTo, curName())); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p\n", id(), From 094c567a61cb637338aeeff136cdcff115448040 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 22 Nov 2021 13:29:53 -0600 Subject: [PATCH 055/505] Refactor dwarfWalker::findConst (#1160) This function always returns 'true' and few callsites checked the bool out variable. Using an optional here makes everything simpler. Logging has been substantially improved for better tracing. --- symtabAPI/src/dwarfWalker.C | 48 ++++++++++++++++--------------------- symtabAPI/src/dwarfWalker.h | 3 ++- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 1cea4a47a7..a0c5b14996 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -1370,11 +1370,10 @@ bool DwarfWalker::parseEnumEntry() { std::string name = die_name(); - long value = 0; - bool valid; - if (!findValue(value, valid)) return false; + auto value = findConstValue(); + if(!value) { return false; } - curEnum()->asEnumType().addConstant(name, value); + curEnum()->asEnumType().addConstant(name, *value); return true; } @@ -1388,10 +1387,7 @@ bool DwarfWalker::parseMember() { curName() = std::move(die_name()); - long value; - bool hasValue; - if (!findValue(value, hasValue)) return false; - if (hasValue) { + if (findConstValue()) { if(!nameDefined()) return false; dwarf_printf("(0x%lx) member is a named constant, forwarding to parseConstant\n", id()); return parseConstant(); @@ -1695,15 +1691,8 @@ bool DwarfWalker::isStaticStructMember(std::vector &locs, bool // if parsing a struct-member which is not a regular member (i.e. not with an offset) if (curEnclosure()->getDataClass() == dataStructure && locs.size() == 0) { - long value; - bool hasValue; - if (!findValue(value, hasValue)) return false; - - // and, if it is not a constant, then it must be a static field member - if (!hasValue) { - isStatic = true; - return true; - } + // and it is not a constant, then it must be a static field member + isStatic = !findConstValue(); } return true; @@ -2133,24 +2122,29 @@ bool DwarfWalker::findVisibility(visibility_t &visibility) { return true; } -bool DwarfWalker::findValue(long &value, bool &valid) { - Dwarf_Attribute valueAttr; +boost::optional DwarfWalker::findConstValue() { + dwarf_printf("(0x%lx) findConstValue entry\n", id()); + + Dwarf_Attribute valueAttr{}; Dwarf_Die e = entry(); - auto status = dwarf_attr(&e, DW_AT_const_value, & valueAttr); - if (status == 0) { - valid = false; - return true; + // This also applies to constexpr objects (i.e., DW_AT_const_expr) + if(!dwarf_attr(&e, DW_AT_const_value, & valueAttr)) { + dwarf_printf("No const value found\n"); + return {}; } Dwarf_Sword enumValue; + if(dwarf_formsdata(&valueAttr, &enumValue) != 0) { + dwarf_printf("ERROR: dwarf_formsdata error for entry %p\n", static_cast(&e)); + return {}; + } - DWARF_FAIL_RET(dwarf_formsdata(&valueAttr, &enumValue)); + dwarf_printf("Found value '%ld'\n", static_cast(enumValue)); - value = enumValue; - valid = true; + dwarf_printf("(0x%lx) end findConstValue\n", id()); - return true; + return enumValue; } bool DwarfWalker::fixBitFields(std::vector &locs, diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index c8c74dbfad..545fa9b0b3 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -18,6 +18,7 @@ #include "Object.h" #include #include +#include #include //Concurrent Hash Map @@ -350,7 +351,7 @@ class DwarfWalker : public DwarfParseActions { void removeFortranUnderscore(std::string &); bool findSize(unsigned &size); bool findVisibility(visibility_t &visibility); - bool findValue(long &value, bool &valid); + boost::optional findConstValue(); bool fixName(std::string &name, boost::shared_ptr type); bool fixBitFields(std::vector &locs, long &size); From 1912be31c72961de2f53f6baa094d8f67245322c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 23 Nov 2021 13:09:53 -0600 Subject: [PATCH 056/505] Increase minimum elfutils version to 0.186 (#1161) This is needed to parse NVIDIA's extended line map information. HPCToolkit makes extensive use of this functionality. --- cmake/ElfUtils.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/ElfUtils.cmake b/cmake/ElfUtils.cmake index 975e361e04..de17e2b991 100644 --- a/cmake/ElfUtils.cmake +++ b/cmake/ElfUtils.cmake @@ -37,8 +37,8 @@ if(NOT UNIX) endif() # Minimum acceptable version of elfutils -# NB: We need >=0.178 because libdw isn't thread-safe before then -set(_min_version 0.178) +# NB: We need >=0.186 because of NVIDIA line map extensions +set(_min_version 0.186) set(ElfUtils_MIN_VERSION ${_min_version} CACHE STRING "Minimum acceptable elfutils version") From e6b188351481b354d6ea4c8b4aaaeb2bfababb32 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 23 Nov 2021 13:44:39 -0600 Subject: [PATCH 057/505] Remove NVIDIA external line map configure check (#1162) Now that we require elfutils >= 0.186, this is no longer needed. --- cmake/ElfUtils.cmake | 10 ---------- cmake/options.cmake | 1 - symtabAPI/CMakeLists.txt | 2 -- symtabAPI/src/Object-elf.C | 5 ----- 4 files changed, 18 deletions(-) diff --git a/cmake/ElfUtils.cmake b/cmake/ElfUtils.cmake index de17e2b991..7eeb3f1b84 100644 --- a/cmake/ElfUtils.cmake +++ b/cmake/ElfUtils.cmake @@ -166,13 +166,3 @@ include_directories(${ElfUtils_INCLUDE_DIRS}) message(STATUS "ElfUtils includes: ${ElfUtils_INCLUDE_DIRS}") message(STATUS "ElfUtils library dirs: ${ElfUtils_LIBRARY_DIRS}") message(STATUS "ElfUtils libraries: ${ElfUtils_LIBRARIES}") - -include(CheckSymbolExists) -if(ENABLE_NVIDIA_EXT_LINE_MAP) - set(CMAKE_REQUIRED_INCLUDES ${ElfUtils_INCLUDE_DIRS}) - set(CMAKE_REQUIRED_LIBRARIES ${ElfUtils_LIBRARIES}) - check_symbol_exists(dwarf_linecontext elfutils/libdw.h _has_exmap) - if(NOT _has_exmap) - message(FATAL_ERROR "ElfUtils does not support NVIDIA line maps") - endif() -endif() diff --git a/cmake/options.cmake b/cmake/options.cmake index 67e9636a95..1f46d90df2 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -16,7 +16,6 @@ option(BUILD_DOCS "Build manuals from LaTeX sources" ON) option (ENABLE_LTO "Enable Link-Time Optimization" OFF) option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) -option(ENABLE_NVIDIA_EXT_LINE_MAP "Enable support for NVIDIA extended line map" OFF) # Some global on/off switches if (LIGHTWEIGHT_SYMTAB) diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 1a15d9ff56..4ca6896f83 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -102,8 +102,6 @@ endif() dyninst_library(symtabAPI ${DEPS}) -target_compile_definitions(symtabAPI PRIVATE $<$:ENABLE_NVIDIA_EXT_LINE_MAP>) - if(TARGET ElfUtils) add_dependencies(symtabAPI ElfUtils) endif() diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 020356f9fe..9c14f9a29a 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3789,9 +3789,6 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) cout << "dwarf_linebeginstatement failed" << endl; continue; } -// ENABLE_NVIDIA_EXT_LINE_MAP is defined if the Dyninst -// user wants to have nvidia ex line map support -#if defined (ENABLE_NVIDIA_EXT_LINE_MAP) // Only attempt to parse inlining context and inline function name // when there is a .debug_str section. @@ -3800,8 +3797,6 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) current_statement.funcname = dwarf_linefunctionname(dbg, line); } -#endif // ENABLE_NVIDIA_EXT_LINE_MAP - if (!isZeroAddress && saved_statement.uninitialized()) { saved_statement = current_statement; } else if (!isZeroAddress) { From 91ede1ff4309c3ebb5518d0a8d43befd3eb5ceae Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 23 Nov 2021 15:46:24 -0600 Subject: [PATCH 058/505] Documentation updates for 12.0.1 release --- CHANGELOG.md | 15 +++++++++++++++ cmake/shared.cmake | 2 +- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 84423abe4d..7857fb5a3e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,20 @@ # Change Log +## [12.0.1](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-23) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.0...v12.0.1) + +**Build Changes** + +- Remove NVIDIA external line map configure check ([1162](https://github.com/dyninst/dyninst/issues/1162)) +- Increase minimum elfutils version to 0.186 ([1161](https://github.com/dyninst/dyninst/issues/1161)) +- Add conflict with CMake 3.19.0 ([1153](https://github.com/dyninst/dyninst/issues/1153)) + +**Enhancements** + +- Refactor dwarfWalker::findConst ([1160](https://github.com/dyninst/dyninst/issues/1160)) +- Add readable name for Symtab::typeRef ([1157](https://github.com/dyninst/dyninst/issues/1157)) +- DwarfWalker: clean up interfaces for findDieName and findName ([1154](https://github.com/dyninst/dyninst/issues/1154)) + ## [12.0.0](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-11) [Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.1...v12.0.0) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 38b21b3ea0..0c3f6afcd1 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,6 +1,6 @@ set (DYNINST_MAJOR_VERSION 12) set (DYNINST_MINOR_VERSION 0) -set (DYNINST_PATCH_VERSION 0) +set (DYNINST_PATCH_VERSION 1) set (SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") set (LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") From 94252b8ce87293da4b10d0cee550e7ad0507a3ae Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sun, 28 Nov 2021 17:44:35 -0600 Subject: [PATCH 059/505] Clean up memoryTracker usage in binaryEdit (#877) * Store memoryTracker_ as a value instead of pointer This provides cleaner semantics for its usage and ensures that the it's default-constructed correctly. * Code cleanup * Give codeRange a virtual destructor This will ensure that memoryTracker objects removed from a codeTree will correctly get destroyed. * Simplify inferiorFree * Free any remaining memoryTrackers on destruction --- dyninstAPI/src/binaryEdit.C | 60 +++++++++++++++---------------------- dyninstAPI/src/binaryEdit.h | 2 +- dyninstAPI/src/codeRange.h | 2 ++ 3 files changed, 27 insertions(+), 37 deletions(-) diff --git a/dyninstAPI/src/binaryEdit.C b/dyninstAPI/src/binaryEdit.C index 7973419e50..55f8b28a4f 100644 --- a/dyninstAPI/src/binaryEdit.C +++ b/dyninstAPI/src/binaryEdit.C @@ -60,7 +60,7 @@ bool BinaryEdit::readTextSpace(const void *inOther, // Look up this address in the code range tree of memory codeRange *range = NULL; - if (!memoryTracker_->find(addr, range)) + if (!memoryTracker_.find(addr, range)) return false; assert(addr >= range->get_address()); @@ -86,7 +86,7 @@ bool BinaryEdit::writeTextSpace(void *inOther, while (to_do) { // Look up this address in the code range tree of memory codeRange *range = NULL; - if (!memoryTracker_->find(addr, range)) { + if (!memoryTracker_.find(addr, range)) { return false; } @@ -197,10 +197,7 @@ Address BinaryEdit::inferiorMalloc(unsigned size, if (ret) { memoryTracker *newTracker = new memoryTracker(ret, size); newTracker->alloced = true; - if (!memoryTracker_) - memoryTracker_ = new codeRangeTree(); - memoryTracker_->insert(newTracker); - + memoryTracker_.insert(newTracker); break; } } @@ -212,17 +209,11 @@ void BinaryEdit::inferiorFree(Address item) { inferiorFreeInternal(item); - codeRange *obj; - if(!memoryTracker_->find(item, obj)) - { - // Warn the user? - return; - } - - - delete obj; - - memoryTracker_->remove(item); + codeRange *obj{}; + if(memoryTracker_.find(item, obj)) delete obj; + + // Remove it from the tree + memoryTracker_.remove(item); } bool BinaryEdit::inferiorRealloc(Address item, unsigned newsize) @@ -234,17 +225,17 @@ bool BinaryEdit::inferiorRealloc(Address item, unsigned newsize) maxAllocedAddr(); codeRange *obj; - result = memoryTracker_->find(item, obj); + result = memoryTracker_.find(item, obj); assert(result); - memoryTracker_->remove(item); + memoryTracker_.remove(item); memoryTracker *mem_track = dynamic_cast(obj); assert(mem_track); mem_track->realloc(newsize); - memoryTracker_->insert(obj); + memoryTracker_.insert(obj); return true; } @@ -276,7 +267,7 @@ BinaryEdit::BinaryEdit() : highWaterMark_(0), lowWaterMark_(0), isDirty_(false), - memoryTracker_(NULL), + memoryTracker_{}, mobj(NULL), multithread_capable_(false), writing_(false) @@ -294,7 +285,12 @@ BinaryEdit::~BinaryEdit() for(auto *rel : dependentRelocations) { delete rel; } - delete memoryTracker_; + + std::vector x; + memoryTracker_.elements(x); + for(auto const *c : x) { + delete c; + } } BinaryEdit *BinaryEdit::openFile(const std::string &file, @@ -528,7 +524,7 @@ bool BinaryEdit::writeFile(const std::string &newFileName) // Now, we need to copy in the memory of the new segments for (unsigned i = 0; i < oldSegs.size(); i++) { codeRange *segRange = NULL; - if (!memoryTracker_->find(oldSegs[i]->getMemOffset(), segRange)) { + if (!memoryTracker_.find(oldSegs[i]->getMemOffset(), segRange)) { #if 0 // Looks like BSS if (newSegs[i].name == ".bss") @@ -556,7 +552,7 @@ bool BinaryEdit::writeFile(const std::string &newFileName) void *newSectionPtr = calloc(highWaterMark_ - lowWaterMark_, 1); std::vector writes; - memoryTracker_->elements(writes); + memoryTracker_.elements(writes); for (unsigned i = 0; i < writes.size(); i++) { assert(newSectionPtr); @@ -747,24 +743,16 @@ bool BinaryEdit::createMemoryBackingStore(mapped_object *obj) { symObj->getAllRegions(regs); for (unsigned i = 0; i < regs.size(); i++) { - memoryTracker *newTracker = NULL; if (regs[i]->getRegionType() == Region::RT_BSS || (regs[i]->getMemSize() == 0)) { continue; } - else { - newTracker = new memoryTracker(regs[i]->getMemOffset(), - regs[i]->getMemSize(), - regs[i]->getPtrToRawData()); - - } + auto *newTracker = new memoryTracker(regs[i]->getMemOffset(), + regs[i]->getMemSize(), + regs[i]->getPtrToRawData()); newTracker->alloced = false; - if (!memoryTracker_) - memoryTracker_ = new codeRangeTree(); - memoryTracker_->insert(newTracker); + memoryTracker_.insert(newTracker); } - - return true; } diff --git a/dyninstAPI/src/binaryEdit.h b/dyninstAPI/src/binaryEdit.h index 28d7e2d7a5..c9d3d9e2dc 100644 --- a/dyninstAPI/src/binaryEdit.h +++ b/dyninstAPI/src/binaryEdit.h @@ -211,7 +211,7 @@ class BinaryEdit : public AddressSpace { /* Function specific to rewritting static binaries */ bool doStaticBinarySpecialCases(); - codeRangeTree* memoryTracker_; + codeRangeTree memoryTracker_; mapped_object * addSharedObject(const std::string *fullPath); diff --git a/dyninstAPI/src/codeRange.h b/dyninstAPI/src/codeRange.h index 47a7ead81b..31d60105d8 100644 --- a/dyninstAPI/src/codeRange.h +++ b/dyninstAPI/src/codeRange.h @@ -102,6 +102,8 @@ class codeRange : public patchTarget { void print_range(Address addr = 0); friend ostream &operator<<(ostream &s, const codeRange &c); + + virtual ~codeRange() = default; }; class codeRangeTree { From f6d12af97ed8a3a5167d7950564b0ba5ec92d5c1 Mon Sep 17 00:00:00 2001 From: "Jonathan R. Madsen" Date: Fri, 7 Jan 2022 12:48:48 -0600 Subject: [PATCH 060/505] Remove erroneous use of realloc in symtabAPI/Type-mem.h (#1170) --- symtabAPI/src/Type-mem.h | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/symtabAPI/src/Type-mem.h b/symtabAPI/src/Type-mem.h index 356664982c..325c9721b9 100644 --- a/symtabAPI/src/Type-mem.h +++ b/symtabAPI/src/Type-mem.h @@ -41,16 +41,12 @@ using namespace SymtabAPI; template T *upgradePlaceholder(Type *placeholder, T *new_type) { - assert(sizeof(T) <= Type::max_size); - - void* mem = realloc((void *) placeholder, sizeof(T)); - assert(mem == (void *) placeholder); - memset(mem, 0, sizeof(T)); - - T *ret = new(mem) T(); - assert(mem == (void *) ret); - *ret = *new_type; - return ret; + assert(sizeof(T) <= Type::max_size); + memset(static_cast(placeholder), 0, Type::max_size); + T* ret = new(placeholder) T{}; + assert(static_cast(placeholder) == static_cast(ret)); + *ret = *new_type; + return ret; } template From 1cfbe939a7c26041f7718233b6a47509c96a8ef8 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Tue, 11 Jan 2022 22:29:09 -0700 Subject: [PATCH 061/505] Adding first stage of automated docker build (#1180) * adding first stage of automated docker build this first workflow include a base container with ubuntu 20.04 and a set of dependencies chosen by Tim. The base container will be set (after this PR) as a scheduled, nightly build, and we do this so testing each day can simply pull it, re-add the new source code and testsuite, and quickly compile again (on the order of 3.5 minutes vs. 1 hour+ for the entire container build. This update will happen in two stages - this first to deploy the base container, and a follow up to add automated testing using it. Currently this does not upload test results to Tims server, and this is only because I want to talk to him about it first and then test the workflow before PR here. Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/base-containers.yaml | 80 +++++++++++ CHANGELOG.md | 1 + README.md | 8 ++ docker/Dockerfile | 125 +++++++++++++++++ docker/README.md | 179 +++++++++++++++++++++++++ docker/build.sh | 38 ++++++ 6 files changed, 431 insertions(+) create mode 100644 .github/workflows/base-containers.yaml create mode 100644 docker/Dockerfile create mode 100644 docker/README.md create mode 100644 docker/build.sh diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml new file mode 100644 index 0000000000..efbcfd2363 --- /dev/null +++ b/.github/workflows/base-containers.yaml @@ -0,0 +1,80 @@ +name: Build Deploy Containers + +on: + + # Always have a base image ready to go - this is a nightly build + schedule: + - cron: 0 3 * * * + + # On pull request we test updates to images + pull_request: [] + + # On push to main we build and deploy images + push: + branches: + - main + +jobs: + build: + permissions: + packages: write + strategy: + fail-fast: false + matrix: + + # Note: this can be extended in two ways + # 1. Add more configurations to the matrix, either like this or flattening + # 2. Generate matrix programatically and pipe in (recommended) + # perl is 5.30.0 provided by 20.04 container base + ubuntu: ["20.04"] + boost: ["1.73.0"] + elfutils: ["0.186"] + libiberty: ["2.33.1"] + inteltbb: ["2020.2"] + + runs-on: ubuntu-latest + name: Build + steps: + - name: Checkout + uses: actions/checkout@v2 + + - name: Make Space For Build + run: | + sudo rm -rf /usr/share/dotnet + sudo rm -rf /opt/ghc + + - name: Set Organization Name + if: (github.event_name != 'schedule') + env: + org: ${{ github.event.repository.owner.login }} + run: echo "org=${org}" >> ${GITHUB_ENV} + + - name: Set Organization Name + if: (github.event_name == 'schedule') + run: echo "org=dyninst" >> ${GITHUB_ENV} + + - name: Pull Layers for "Cache" + run: docker pull ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest || echo "No cache available" + + - name: Build Dyninst Base Container + run: | + cd docker/ + docker build --build-arg ubuntu_version=${{ matrix.ubuntu }} \ + --build-arg BOOST_VERSION=${{ matrix.boost }} \ + --build-arg ELFUTILS_VERSION=${{ matrix.elfutils }} \ + --build-arg LIBIBERTY_VERSION=${{ matrix.libiberty }} \ + --build-arg INTELTBB_VERSION=${{ matrix.inteltbb }} \ + -f Dockerfile \ + -t ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest ../ + + - name: GHCR Login + if: (github.event_name != 'pull_request') + uses: docker/login-action@v1 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Deploy + if: (github.event_name != 'pull_request') + run: docker push ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest diff --git a/CHANGELOG.md b/CHANGELOG.md index 7857fb5a3e..5003fd307b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -14,6 +14,7 @@ - Refactor dwarfWalker::findConst ([1160](https://github.com/dyninst/dyninst/issues/1160)) - Add readable name for Symtab::typeRef ([1157](https://github.com/dyninst/dyninst/issues/1157)) - DwarfWalker: clean up interfaces for findDieName and findName ([1154](https://github.com/dyninst/dyninst/issues/1154)) +- Added automated docker build for development and testing ## [12.0.0](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-11) [Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.1...v12.0.0) diff --git a/README.md b/README.md index e33974941b..dc8f82095f 100644 --- a/README.md +++ b/README.md @@ -15,6 +15,14 @@ ## Build DyninstAPI and its subcomponents +### Docker Containers + +Containers are provided that can be used for Dyninst development (e.g., make changes to Dyninst and quickly rebuild it) +or for development of your own tools (e.g., have a container ready to go with Dyninst). Links will be added +here when the containers are pushed to the Dyninst associated package registries. Instructions for usage +and building locally are provided in the [docker](docker) directory. + + ### Install with Spack ```spack install dyninst``` diff --git a/docker/Dockerfile b/docker/Dockerfile new file mode 100644 index 0000000000..4e26864a15 --- /dev/null +++ b/docker/Dockerfile @@ -0,0 +1,125 @@ +ARG ubuntu_version=20.04 +FROM ubuntu:${ubuntu_version} + +# Build the Dockerfile in this directory, context one level up +# docker build -t dyninst -f Dockerfile ../ + +LABEL maintainer="@hainest,@vsoch" + +ENV DEBIAN_FRONTEND=noninteractive +ENV TZ=America/Los_Angeles + +# We can use build args to populate the specific versions of dependencies (with defaults here) +ARG BOOST_VERSION=1.73.0 +ARG ELFUTILS_VERSION=0.186 +ARG LIBIBERTY_VERSION=2.33.1 +ARG INTELTBB_VERSION=2020.2 +ARG PERL_VERSION=5.32.1 + +# Sort of separate from dyninst (but used to build/test) +ARG CMAKE_VERSION=3.21.2 +ENV CMAKE_VERSION=${CMAKE_VERSION} + +# Set the branch name for spack to use (should be master even for PR) +ARG DYNINST_BRANCH=master +ENV DYNINST_BRANCH=${DYNINST_BRANCH} + +# Note that perl 5.30.0 is provided by ubuntu + +# Args need to be passed into envars to be used in RUN +ENV BOOST_VERSION=${BOOST_VERSION} +ENV ELFUTILS_VERSION=${ELFUTILS_VERSION} +ENV LIBIBERTY_VERSION=${LIBIBERTY_VERSION} +ENV INTELTBB_VERSION=${INTELTBB_VERSION} +ENV PERL_VERSION=${PERL_VERSION} + +RUN apt-get -qq update && \ + apt-get -qq install -fy tzdata && \ + apt-get -qq install -y --no-install-recommends \ + build-essential \ + bzip2 \ + ca-certificates \ + curl \ + dh-autoreconf \ + git \ + gnupg2 \ + lcov \ + libssl-dev \ + ninja-build \ + pkg-config \ + python-dev \ + python3-pip \ + sudo \ + valgrind \ + vim \ + wget \ + xsltproc + +# Install Clingo for Spack +RUN python3 -m pip install --upgrade pip && \ + python3 -m pip install clingo && \ + dpkg-reconfigure tzdata + +# Update gcc to 11.1.1 (otherwise we'd have 9.3.0) +RUN apt-get install -y software-properties-common && \ + add-apt-repository 'deb http://mirrors.kernel.org/ubuntu hirsute main universe' && \ + apt-get update && \ + apt-get install -y gcc-11 g++-11 && \ + update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 70 --slave /usr/bin/g++ g++ /usr/bin/g++-9 --slave /usr/bin/gcov gcov /usr/bin/gcov-9 --slave /usr/bin/gcc-ar gcc-ar /usr/bin/gcc-ar-9 --slave /usr/bin/gcc-ranlib gcc-ranlib /usr/bin/gcc-ranlib-9 && \ + update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-11 110 --slave /usr/bin/g++ g++ /usr/bin/g++-11 --slave /usr/bin/gcov gcov /usr/bin/gcov-11 --slave /usr/bin/gcc-ar gcc-ar /usr/bin/gcc-ar-11 --slave /usr/bin/gcc-ranlib gcc-ranlib /usr/bin/gcc-ranlib-11; + +# Install spack +WORKDIR /opt +RUN git clone --depth 1 https://github.com/spack/spack +ENV PATH=/opt/spack/bin:$PATH + +# Use the autamus build cache for faster install +# Note that autamus currently uses 18.04 +RUN python3 -m pip install botocore boto3 && \ + spack mirror add autamus s3://autamus-cache && \ + curl http://s3.amazonaws.com/autamus-cache/build_cache/_pgp/FFEB24B0A9D81F6D5597F9900B59588C86C41BE7.pub > key.pub && \ + spack gpg trust key.pub + +# Find packages already installed on system, e.g. autoconf +RUN spack external find && \ + spack config add 'packages:all:target:[x86_64]' && \ + # Install a new CMake (Tim originally wanted 3.17.1 but spack doesn't have it) + spack install cmake@${CMAKE_VERSION} perl + +# Add cmake to a view +RUN spack view --dependencies no symlink --ignore-conflicts /opt/view cmake@${CMAKE_VERSION} perl +ENV PATH=/opt/view/bin:$PATH + +RUN spack external find cmake && \ + spack config add 'packages:cmake:buildable:False' + +# Add Dyninst source code here (e.g., from PR or master) +WORKDIR /code +COPY . /code + +# Add test code to base container so we can build tests here +RUN git clone https://github.com/dyninst/testsuite /opt/testsuite + +# Install Dyninst to its own view +WORKDIR /opt/dyninst-env +RUN . /opt/spack/share/spack/setup-env.sh && \ + spack env create -d . && \ + echo " concretization: together" >> spack.yaml && \ + spack env activate . && \ + + # This adds metadata for dyninst to spack.yaml + spack develop --path /code dyninst@${DYNINST_BRANCH} && \ + + # ...but we need spack add to add to the install list! + spack add dyninst@${DYNINST_BRANCH} && \ + + # Add our hard coded versions here. + spack add boost@${BOOST_VERSION} && \ + spack add elfutils@${ELFUTILS_VERSION} && \ + spack add libiberty@${LIBIBERTY_VERSION} && \ + spack add intel-tbb@${INTELTBB_VERSION} && \ + spack install --reuse + +# Build tests (but don't run) +COPY ./docker/build.sh build.sh +RUN /bin/bash build.sh diff --git a/docker/README.md b/docker/README.md new file mode 100644 index 0000000000..e1c06734c6 --- /dev/null +++ b/docker/README.md @@ -0,0 +1,179 @@ +# Dyninst Containers + +This is a testing set of Dockerfile for building a Dyninst base container. + +## Strategy + +For development, we want to be able to: + + 1. Pull a container with dyninst ready to go (for development or dyninst or another library) + 2. Quickly update with our own source code without needing to build everything. + +And for testing, we want to be able to: + + 1. Have a set of base containers that make dependency preparation minimal + 2. Use those base containers to quickly test a PR's dyninst and report results + +To do this we will have two workflows: + +### Base Containers + +The [base-containers.yaml](../.github/workflows/base-containers.yaml) workflow will build updated base +containers nightly or at an appropriate frequency. Right now we are providing one container build with a reasonable set of dependencies +and dyninst, and this is done by way of installing via spack, and setting versions +in an environment via build args. The current workflow, although there is just one container, +done by using a matrix so in the future when additional build configurations are added, +we can just extend the matrix. When this time comes, we can have a simple script (e.g., Python) +that generates this same matrix, and then pipes it into the GitHub workflow to still use as +build args in the Dockerfile. It's setup right now to still use this build arg -> environment -> matrix +strategy so the transition is easier. + +### Test Container + +This will be added via a second PR here! This second Dockerfile starts with a base container (ready to go with +dependencies) and then adds Dyninst to it, updates with the changes, and then run tests. It should +be fairly speedy given that the base containers are pre-built. + +**to be added** + +## Usage + +While most of this is done via recipes in CI, here is how to interact with the repository locally. + +### Build + +A [Dockerfile](Dockerfile) is provided that makes it easy to bring up a development environment. + +```bash +$ docker build -t dyninst -f Dockerfile ../ +``` + +### Develop + +You can then shell inside to interact with dyninst - there will be a spack environment +directory right in the root where you shell in: + +```bash +$ docker run -it dyninst bash +``` +```bash +# ls +spack.lock spack.yaml +``` + +This lock and spack yaml defines a spack envirironment, which is generated during the container build. If we inspect closer, we would see: + +```yaml +# This is a Spack Environment file. +# +# It describes a set of packages to be installed, along with +# configuration settings. +spack: + # add package specs to the `specs` list + specs: [boost@1.73.0, elfutils@0.186, libiberty@2.33.1, intel-tbb@2020.2, perl@5.32.1] + view: true + concretization: together + develop: + dyninst: + path: /code + spec: dyninst@master +``` + +Which includes a set of depdencies and versions we want to build. If you are just running a container as a developer, you are ready to go, +because you can find all the dyninst libraries in the spack enviroment: + +```bash +.spack-env/view/lib/libdynC_API.so +.spack-env/view/lib/libdynC_API.so.11.0 +.spack-env/view/lib/libdynC_API.so.11.0.1 +.spack-env/view/lib/libdynDwarf.so +.spack-env/view/lib/libdynDwarf.so.11.0 +.spack-env/view/lib/libdynDwarf.so.11.0.1 +.spack-env/view/lib/libdynElf.so +.spack-env/view/lib/libdynElf.so.11.0 +.spack-env/view/lib/libdynElf.so.11.0.1 +.spack-env/view/lib/libdyninstAPI.so +.spack-env/view/lib/libdyninstAPI.so.11.0 +.spack-env/view/lib/libdyninstAPI.so.11.0.1 +.spack-env/view/lib/libdyninstAPI_RT.a +.spack-env/view/lib/libdyninstAPI_RT.so +.spack-env/view/lib/libdyninstAPI_RT.so.11.0 +.spack-env/view/lib/libdyninstAPI_RT.so.11.0.1 +``` +Which you can then activate + +```bash +$ . /opt/spack/share/spack/setup-env.sh +$ spack env activate . +``` + +And here is an example of what activation does to the `LD_LIBRARY_PATH`: + +```bash +# env | grep LD_LIBRARY_PATH +LD_LIBRARY_PATH=/opt/dyninst-env/.spack-env/view/lib64:/opt/dyninst-env/.spack-env/view/lib:/opt/view/lib:/opt/view/lib64 +``` +You could then make any changes to the source code at `/code` (even if you've bound from your local machine to open with your editor of choice) and then run spack install again to rebuild (without needing to rebuild dependencies!) + +```bash +$ spack install --reuse +``` + +Note that we've added "reuse" to tell spack to be as flexible as it can to reuse what it has. +And that's it! For a more interactive development environment, you can bind the present working directory with the +Dyninst source code bound to `/code` instead: + +```bash +$ docker run -it -v $PWD:/code dyninst +``` + +If you do the same steps as above, you'll be in the activated environment: + +```bash +$ . /opt/spack/share/spack/setup-env.sh +$ spack env activate . +``` + +And again navigate to the bound source code - this time the files are on your local machine, so you can edit +them locally and build in the container! + +```bash +# This is bound to your host - edit files there +$ cd /code +``` + +And then again do: + +```bash +$ spack install --reuse +``` + +Finally, if you just want a container for development with Dyninst ready to go, you +can use [ghcr.io/autamus/dyninst](https://github.com/orgs/autamus/packages/container/package/dyninst) +(view the page there for tags available). New tags are automatically detected when there is +a release to the repository here, and the container built and deployed. You can find the libraries +under the root `/opt/view` (and then lib, bin, share, etc.) + +```bash +# ls /opt/view/lib/libd* +libdw-0.185.so libdynC_API.so libdynDwarf.so.11.0 libdynElf.so.11.0.1 libdyninstAPI_RT.a +libdw.a libdynC_API.so.11.0 libdynDwarf.so.11.0.1 libdyninstAPI.so libdyninstAPI_RT.so +libdw.so libdynC_API.so.11.0.1 libdynElf.so libdyninstAPI.so.11.0 libdyninstAPI_RT.so.11.0 +libdw.so.1 libdynDwarf.so libdynElf.so.11.0 libdyninstAPI.so.11.0.1 libdyninstAPI_RT.so.11.0.1 +root@89e4fbb001b5:/# ls /opt/view/lib/libsym* +libsymLite.so libsymLite.so.11.0 libsymLite.so.11.0.1 libsymtabAPI.so libsymtabAPI.so.11.0 libsymtabAPI.so.11.0.1 +``` + +## Test + +**Note will be added in followup PR** + +To build the test container, you'll want to use [Dockerfile.test](Dockerfile.test). If you want to use +the base dyninst container from GitHub packages, leave out build args (it will default to this). Otherwise, if you want to use a container you just built, specify that as the build arg `dyninst_base`: + +```bash +$ docker build -f Dockerfile.test --build-arg dyninst_base=dyninst -t dyninst-test ../ +``` + +The tests are added and run during build, so if they fail inside the container, the container build will fail +(and trigger any CI building it to fail). diff --git a/docker/build.sh b/docker/build.sh new file mode 100644 index 0000000000..4d86095e55 --- /dev/null +++ b/docker/build.sh @@ -0,0 +1,38 @@ +#!/bin/bash +set -euo pipefail + +# This script builds dyninst and the test suite (but does not run tests) + +printf "⭐️ Setting up spack environment for Dyninst\n" +. /opt/spack/share/spack/setup-env.sh +spack env activate . +mkdir -p build/dyninst + +# 1. Build Dyninst +printf "⭐️ Preparing to build Dyninst\n" +echo "::group::build dyninst" +cd build/dyninst +cmake -H/code -B. -DCMAKE_INSTALL_PREFIX=. > >(tee config.out) 2> >(tee config.err >&2) +make VERBOSE=1 -j2 > >(tee build.out) 2> >(tee build.err >&2) +make install VERBOSE=1 -j2 > >(tee build-install.out) 2> >(tee build-install.err >&2) +echo "::endgroup::" + +# 2. Update the test suite +printf "⭐️ Updating the testsuite\n" +echo "::group::update testsuite" +cd /opt/testsuite +git pull origin master +cd - +echo "::endgroup::" + +# 3. Build the test suite +printf "⭐️ Preparing to build the testsuite\n" +echo "::group::build tests" +cd /opt/dyninst-env/ +mkdir -p build/testsuite/tests +cd build/testsuite + +cmake -H/opt/testsuite -B. -DCMAKE_INSTALL_PREFIX=$PWD/tests -DDyninst_DIR=/opt/dyninst-env/build/dyninst/lib/cmake/Dyninst > >(tee config.out) 2> >(tee config.err >&2) +make VERBOSE=1 -j2 > >(tee build.out) 2> >(tee build.err >&2) +make install VERBOSE=1 -j2 > >(tee build-install.out) 2> >(tee build-install.err >&2) +echo "::endgroup::" From 67c2ec44cd28596c14a93e5eb8718692e43089b4 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Tue, 11 Jan 2022 22:39:13 -0700 Subject: [PATCH 062/505] fixing workflow trigger (#1182) we do not need the build on PR, but we do need on merge into MASTER not MAIN Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/base-containers.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml index efbcfd2363..07c40716c3 100644 --- a/.github/workflows/base-containers.yaml +++ b/.github/workflows/base-containers.yaml @@ -5,14 +5,11 @@ on: # Always have a base image ready to go - this is a nightly build schedule: - cron: 0 3 * * * - - # On pull request we test updates to images - pull_request: [] # On push to main we build and deploy images push: branches: - - main + - master jobs: build: From 8ff2424c9f687dbf5f309a76087d0c9822c335f9 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Wed, 12 Jan 2022 12:36:55 -0700 Subject: [PATCH 063/505] adding dyninst release trigger (#1181) to release a tagged (versioned) container on publication of a release we just need to add the release -> published trigger, derive the tag from the GITHUB_REF environment variable, and then tag and push the container Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/base-containers.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml index 07c40716c3..1fb33bc023 100644 --- a/.github/workflows/base-containers.yaml +++ b/.github/workflows/base-containers.yaml @@ -5,7 +5,11 @@ on: # Always have a base image ready to go - this is a nightly build schedule: - cron: 0 3 * * * - + + # Publish packages on release + release: + types: [published] + # On push to main we build and deploy images push: branches: @@ -72,6 +76,14 @@ jobs: username: ${{ github.actor }} password: ${{ secrets.GITHUB_TOKEN }} + - name: Tag and Push Release Image + if: (github.event_name == 'release') + run: | + tag=${GITHUB_REF#refs/tags/} + echo "Tagging and releasing ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag}" + docker tag ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag} + docker push ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag} + - name: Deploy if: (github.event_name != 'pull_request') run: docker push ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest From 23416d71782f2b281d77ad9f11693b47522138ed Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Wed, 12 Jan 2022 12:50:12 -0700 Subject: [PATCH 064/505] start of work to add automated testing to dyninst! (#1183) start of work to add automated testing to dyninst! Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/test-dyninst.yaml | 39 +++++++++++++++++++++++++++++ docker/Dockerfile.test | 17 +++++++++++++ docker/README.md | 21 ++++++++++------ docker/test.sh | 19 ++++++++++++++ 4 files changed, 88 insertions(+), 8 deletions(-) create mode 100644 .github/workflows/test-dyninst.yaml create mode 100644 docker/Dockerfile.test create mode 100755 docker/test.sh diff --git a/.github/workflows/test-dyninst.yaml b/.github/workflows/test-dyninst.yaml new file mode 100644 index 0000000000..664a6e9021 --- /dev/null +++ b/.github/workflows/test-dyninst.yaml @@ -0,0 +1,39 @@ +name: Test Dyninst + +on: + pull_request: [] + push: + branches: + - master + +jobs: + build: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + + # Testing containers named by ubuntu version for now + ubuntu: ["20.04"] + + runs-on: ubuntu-latest + name: Build + steps: + - name: Checkout + uses: actions/checkout@v2 + + - name: Make Space For Build + run: | + sudo rm -rf /usr/share/dotnet + sudo rm -rf /opt/ghc + + - name: Set Organization Name for Packages Registry + env: + org: ${{ github.event.repository.owner.login }} + run: echo "org=${org}" >> $GITHUB_ENV + + - name: Build Test Container + run: | + cd docker/ + docker build -f Dockerfile.test --build-arg dyninst_base=ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest -t dyninst-test ../ diff --git a/docker/Dockerfile.test b/docker/Dockerfile.test new file mode 100644 index 0000000000..fb1ed8c763 --- /dev/null +++ b/docker/Dockerfile.test @@ -0,0 +1,17 @@ +ARG dyninst_base=ghcr.io/dyninst/dyninst-ubuntu-20.04:latest +FROM ${dyninst_base} + +# docker build --build-arg dyninst_base=ghcr.io/dyninst/dyninst-ubuntu-20.04:latest -f Dockerfile.test -t dyninst-test ../ + +# Add updated Dyninst code +COPY . /code + +# Add testing and build script to run +COPY ./docker/build.sh /opt/dyninst-env/build.sh +COPY ./docker/test.sh /opt/dyninst-env/test.sh + +# Previous WORKDIR, just to be careful - reinstall dyninst if needed +# Thenbuild and run the test suite +WORKDIR /opt/dyninst-env +RUN /bin/bash build.sh && \ + /bin/bash test.sh diff --git a/docker/README.md b/docker/README.md index e1c06734c6..c241f94253 100644 --- a/docker/README.md +++ b/docker/README.md @@ -30,11 +30,11 @@ strategy so the transition is easier. ### Test Container -This will be added via a second PR here! This second Dockerfile starts with a base container (ready to go with -dependencies) and then adds Dyninst to it, updates with the changes, and then run tests. It should -be fairly speedy given that the base containers are pre-built. - -**to be added** +The [test-dyninst.yaml](../.github/workflows/test-dyninst.yaml) workflow +has it's own Dockerfile, [Dockerfile.test](docker/Dockerfile.test) that starts with a base container (ready to go with +dependencies, Dyninst compiler, and the testsuite compiler) and then adds Dyninst +and an updated testsuite to it, compiles changes, and then runs tests. Given that the base +containers are pre-built, the entire workflow takes only a few minutes. ## Usage @@ -166,10 +166,15 @@ libsymLite.so libsymLite.so.11.0 libsymLite.so.11.0.1 libsymta ## Test -**Note will be added in followup PR** +To build the test container, you'll want to use [Dockerfile.test](docker/Dockerfile.test). If you want to use +the base dyninst container from GitHub packages, leave out build args (it will default to this). + +```bash +$ cd docker/ +$ docker build -f Dockerfile.test -t dyninst-test ../ +``` -To build the test container, you'll want to use [Dockerfile.test](Dockerfile.test). If you want to use -the base dyninst container from GitHub packages, leave out build args (it will default to this). Otherwise, if you want to use a container you just built, specify that as the build arg `dyninst_base`: +Otherwise, if you want to use a container you just built, specify that as the build arg `dyninst_base`: ```bash $ docker build -f Dockerfile.test --build-arg dyninst_base=dyninst -t dyninst-test ../ diff --git a/docker/test.sh b/docker/test.sh new file mode 100755 index 0000000000..072cc69960 --- /dev/null +++ b/docker/test.sh @@ -0,0 +1,19 @@ +#!/bin/bash +set -euo pipefail + +printf "⭐️ Setting up spack environment for Dyninst\n" +. /opt/spack/share/spack/setup-env.sh +spack env activate . + +# 3. Run the tests +printf "⭐️ Running tests...\n" +cd /opt/dyninst-env/build/testsuite +export DYNINSTAPI_RT_LIB=/opt/dyninst-env/build/dyninst/lib/libdyninstAPI_RT.so +export OMP_NUM_THREADS=2 +export LD_LIBRARY_PATH=/opt/dyninst-env/build/dyninst/lib:$PWD:$LD_LIBRARY_PATH +./runTests -64 -all -log test.log -j1 > >(tee stdout.log) 2> >(tee stderr.log >&2) + +# TODO will update here to upload given merge to master +# Run the build script to collect and process the logs then upload them +# cd /opt/dyninst-env && \ +# perl /opt/testsuite/scripts/build/build.pl --hostname=ci-github --quiet --restart=build --no-run-tests --upload --auth-token=xxxxxxxxxxxxxxxxxxx From 273803a4c643ed3506f9a69c6ec71d5ab337489c Mon Sep 17 00:00:00 2001 From: Stan Cox Date: Wed, 12 Jan 2022 21:00:50 -0500 Subject: [PATCH 065/505] Remove interposed definition of _r_debug (#1176) Previously there was a dynamic relocation against _r_debug in the loader which picked up the interposed definition, but glibc now uses a direct internal hidden symbol reference and thus no longer updates the interposed object. --- dyninstAPI_RT/src/RTlinux.c | 1 - 1 file changed, 1 deletion(-) diff --git a/dyninstAPI_RT/src/RTlinux.c b/dyninstAPI_RT/src/RTlinux.c index 0ddfc12ff6..0ca7a41d43 100644 --- a/dyninstAPI_RT/src/RTlinux.c +++ b/dyninstAPI_RT/src/RTlinux.c @@ -404,7 +404,6 @@ void dyninstTrapHandler(int sig, siginfo_t *sg, ucontext_t *context) #if defined(cap_binary_rewriter) extern struct r_debug _r_debug; -DLLEXPORT struct r_debug _r_debug __attribute__ ((weak)); /* Verify that the r_debug variable is visible */ void r_debugCheck() { assert(_r_debug.r_map); } From f01e178a2c17c3aef7e260462226620759be660b Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Wed, 12 Jan 2022 21:28:29 -0600 Subject: [PATCH 066/505] ELF+DWARF: always parse first entry in source file table (#1184) rocm-4.5 starts to emit AMD GPU binaries with DWARF 5. I noticed missing source line information for these binaries. The root cause is that dyninst assumes that source file table entry 0 represents "unknown file". This no longer seems to be true in DWARF 5, where entry 0 can represents a real application source file. --- symtabAPI/src/Object-elf.C | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 9c14f9a29a..b3e76d3f47 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3388,12 +3388,9 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) return s_name; }; - // dwarf_line_srcfileno == 0 means unknown; 1...n means files[0...n-1] - // so we ensure that we're adding a block of unknown, 1...n to the string table - // and that offset + dwarf_line_srcfileno points to the correct string using namespace boost::filesystem; strings->emplace_back("",""); - for(size_t i = 1; i < filecount; i++) + for(size_t i = 0; i < filecount; i++) { auto filename = dwarf_filesrc(files, i, nullptr, nullptr); if(!filename) continue; @@ -3676,12 +3673,9 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) boost::unique_lock l(strings->lock); size_t offset = strings->size(); - // dwarf_line_srcfileno == 0 means unknown; 1...n means files[0...n-1] - // so we ensure that we're adding a block of unknown, 1...n to the string table - // and that offset + dwarf_line_srcfileno points to the correct string using namespace boost::filesystem; strings->emplace_back("",""); - for(size_t i = 1; i < fileCount; i++) + for(size_t i = 0; i < fileCount; i++) { auto filename = dwarf_filesrc(files, i, nullptr, nullptr); if(!filename) continue; From 5c01c39956034ce57f92d9327fac18b843d27a7a Mon Sep 17 00:00:00 2001 From: Jonathon Anderson <17242663+blue42u@users.noreply.github.com> Date: Fri, 4 Feb 2022 13:57:51 -0600 Subject: [PATCH 067/505] ParseAPI: Speed up the case where a function is called from many locations (#1190) In some binaries a single function has many callers, so copying out the source edges for the entry Block takes a while and causes significant contention on the Block's lock. The case in Parser::finalize where this becomes a hotspot likely does not need to read every edge, so this commit inlines those cases into methods on Block instead. --- parseAPI/h/CFG.h | 13 ++++--------- parseAPI/src/Block.C | 23 +++++++++++++++++++++++ parseAPI/src/Parser.C | 17 ++--------------- 3 files changed, 29 insertions(+), 24 deletions(-) diff --git a/parseAPI/h/CFG.h b/parseAPI/h/CFG.h index f2ea37463c..d78fe31ef8 100644 --- a/parseAPI/h/CFG.h +++ b/parseAPI/h/CFG.h @@ -254,7 +254,6 @@ class PARSER_EXPORT Block : Address end, Address last, Function* f = NULL); virtual ~Block(); - boost::recursive_mutex& lockable() { return boost::lockable_adapter::lockable(); } inline Address start() const { return _start; } inline Address end() const { return _end; } @@ -271,15 +270,11 @@ class PARSER_EXPORT Block : /* Edge access */ const edgelist & sources() const { return _srclist; } const edgelist & targets() const { return _trglist; } - void copy_sources(edgelist & src) { - boost::lock_guard g(*this); - src = _srclist; - } - void copy_targets(edgelist & trg) { - boost::lock_guard g(*this); - trg = _trglist; - } + void copy_sources(edgelist & src) const; + void copy_targets(edgelist & trg) const; + bool hasCallSource() const; + Edge* getOnlyIncomingEdge() const; bool consistent(Address addr, Address & prev_insn); int containingFuncs() const; diff --git a/parseAPI/src/Block.C b/parseAPI/src/Block.C index 2e819dcbb9..2269b4607b 100644 --- a/parseAPI/src/Block.C +++ b/parseAPI/src/Block.C @@ -356,3 +356,26 @@ void Block::moveTargetEdges(Block* B) { } trgs.clear(); } + +void Block::copy_sources(edgelist & src) const { + boost::lock_guard g(lockable()); + src = _srclist; +} + +void Block::copy_targets(edgelist & trg) const { + boost::lock_guard g(lockable()); + trg = _trglist; +} + +bool Block::hasCallSource() const { + boost::lock_guard g(lockable()); + for (auto e: _srclist) + if (e->type() == CALL) + return true; + return false; +} + +Edge* Block::getOnlyIncomingEdge() const { + boost::lock_guard g(lockable()); + return _srclist.size() == 1 ? *_srclist.begin() : nullptr; +} diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index 37276bd47b..a1654672a2 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -852,14 +852,7 @@ Parser::finalize(Function *f) Block* trg_block = e->trg(); - bool trg_has_call_edge = false; - Block::edgelist sources; - trg_block->copy_sources(sources); - for (auto e2: sources) - if (e2->type() == CALL) { - trg_has_call_edge = true; - break; - } + bool trg_has_call_edge = trg_block->hasCallSource(); // Rule 1: // If an edge is currently not a tail call, but the edge target has a CALL incoming edge, @@ -900,13 +893,7 @@ Parser::finalize(Function *f) // Rule 3: // If an edge is currently a tail call, but the edge target has only the current edge as incoming edges, // we treat this as not tail call. - bool only_incoming = true; - for (auto e2: sources) - if (e2 != e) { - only_incoming = false; - break; - } - if (only_incoming) { + if (trg_block->getOnlyIncomingEdge() == e) { e->_type._interproc = false; parsing_printf("from %lx to %lx, marked as not tail call (single entry), re-finalize\n", b->last(), e->trg()->start()); return false; From 3489263edbb3f8a4b10f35b8104cefbfab08a9f0 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Fri, 4 Feb 2022 13:04:29 -0700 Subject: [PATCH 068/505] Dockerfile: use explicit packages for 'spack external find' (#1195) currently gettext in ubuntu 20.04 is being added as an external dependency (just added about 24 hours ago) and it is breaking the build. This change will test removing from the OS (probably not recommended but okay in the context of the Dyninst image) Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/base-containers.yaml | 2 +- docker/Dockerfile | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml index 1fb33bc023..74522bbf18 100644 --- a/.github/workflows/base-containers.yaml +++ b/.github/workflows/base-containers.yaml @@ -9,7 +9,7 @@ on: # Publish packages on release release: types: [published] - + # On push to main we build and deploy images push: branches: diff --git a/docker/Dockerfile b/docker/Dockerfile index 4e26864a15..36ff99d7ba 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -67,7 +67,7 @@ RUN apt-get install -y software-properties-common && \ apt-get install -y gcc-11 g++-11 && \ update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 70 --slave /usr/bin/g++ g++ /usr/bin/g++-9 --slave /usr/bin/gcov gcov /usr/bin/gcov-9 --slave /usr/bin/gcc-ar gcc-ar /usr/bin/gcc-ar-9 --slave /usr/bin/gcc-ranlib gcc-ranlib /usr/bin/gcc-ranlib-9 && \ update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-11 110 --slave /usr/bin/g++ g++ /usr/bin/g++-11 --slave /usr/bin/gcov gcov /usr/bin/gcov-11 --slave /usr/bin/gcc-ar gcc-ar /usr/bin/gcc-ar-11 --slave /usr/bin/gcc-ranlib gcc-ranlib /usr/bin/gcc-ranlib-11; - + # Install spack WORKDIR /opt RUN git clone --depth 1 https://github.com/spack/spack @@ -81,7 +81,7 @@ RUN python3 -m pip install botocore boto3 && \ spack gpg trust key.pub # Find packages already installed on system, e.g. autoconf -RUN spack external find && \ +RUN spack external find gcc@11.0.1 autoconf bzip2 git tar xz perl && \ spack config add 'packages:all:target:[x86_64]' && \ # Install a new CMake (Tim originally wanted 3.17.1 but spack doesn't have it) spack install cmake@${CMAKE_VERSION} perl From 458d04f1130d7a678a80dec68bf6141f5b761d49 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 4 Feb 2022 14:06:30 -0600 Subject: [PATCH 069/505] Symtab::module documentation cleanup (#1189) * Remove docs for hasLineInformation This was removed by 0dee1c8 in 2016 * Remove getAllVariables This was by b3ad134 in 2021. It was removed there because this function was never implemented. Co-authored-by: Tim Haines --- symtabAPI/doc/API/Symtab/Module.tex | 9 --------- 1 file changed, 9 deletions(-) diff --git a/symtabAPI/doc/API/Symtab/Module.tex b/symtabAPI/doc/API/Symtab/Module.tex index 30424305ca..5036ac942f 100644 --- a/symtabAPI/doc/API/Symtab/Module.tex +++ b/symtabAPI/doc/API/Symtab/Module.tex @@ -28,7 +28,6 @@ \subsection{Class Module}\label{Module} language & supportedLanguages & The source language used by the Module. \\ addr & Offset & Offset of the start of the module, as reported by the symbol table, assuming contiguous modules. \\ exec & Symtab * & Symtab object that contains the module. \\ -hasLineInformation & bool & True if the module has line information. \\ \bottomrule \end{tabular} @@ -99,14 +98,6 @@ \subsubsection{Function, Variable, Symbol lookup} \code{false}. The error value is set to \code{No\_Such\_Variable}. } -\begin{apient} -bool getAllVariables(vector &ret) -\end{apient} -\apidesc{ -This method returns all variables in the object file. Returns \code{true} on success -and \code{false} if there are no modules. The error value is set to \code{No\_Such\_Variable}. -} - \begin{apient} bool getAllSymbols(vector &ret) \end{apient} From 2c94ce001356b55d6c83c2265b905de4f1e86a51 Mon Sep 17 00:00:00 2001 From: Stan Cox Date: Fri, 4 Feb 2022 15:35:36 -0500 Subject: [PATCH 070/505] glibc r_debug extensions to support multiple namespaces (#1175) * Remove interposed definition of _r_debug Previously there was a dynamic relocation against _r_debug in the loader which picked up the interposed definition, but glibc now uses a direct internal hidden symbol reference and thus no longer updates the interposed object. * Update the elf _DYNAMIC symbol When the symbol table is created in emitElf::createSymbolTables, also update the elf _DYNAMIC symbol to reflect the new address of the .dynamic section. --- symtabAPI/src/emitElf.C | 42 +++++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/symtabAPI/src/emitElf.C b/symtabAPI/src/emitElf.C index 139504181d..6e8a0014da 100644 --- a/symtabAPI/src/emitElf.C +++ b/symtabAPI/src/emitElf.C @@ -342,7 +342,7 @@ bool emitElf::createElfSymbol(Symbol *symbol, unsigned strIndex, vecto else { if (vers) { // There should only be one version string by this time - //If the verison name already exists then add the same version number to the version symbol table + //If the version name already exists then add the same version number to the version symbol table //Else give a new number and add it to the mapping. if (versionNames.find((*vers)[0]) == versionNames.end()) { mpos += sprintf(mpos, " new version name: %s\n", (*vers)[0].c_str()); @@ -694,7 +694,7 @@ bool emitElf::driver(std::string fName) { } // Change offsets of sections based on the newly added sections if (movePHdrsFirst) { - /* This special case is specific to FreeBSD but there is no hurt in + /* This special case is specific to FreeBSD but there is no harm in * handling it on other platforms. * * This is necessary because the INTERP header must be located within in @@ -1105,7 +1105,7 @@ void emitElf::fixPhdrs(unsigned &extraAlignSize) { return; //We made a new section to contain the program headers--keeps - // libelf from overwriting the program headers data when outputing + // libelf from overwriting the program headers data when outputting // sections. Fill in the new section's data with what we just wrote. Elf_Data *data = elf_newdata(phdrs_scn); size_t total_size = (size_t) newEhdr->e_phnum * (size_t) newEhdr->e_phentsize; @@ -1135,7 +1135,7 @@ void emitElf::fixPhdrs(unsigned &extraAlignSize) { template void emitElf::updateDynamic(unsigned tag, Elf_Addr val) { if (isStaticBinary) return; - // This is for REL/RELA if it doesnt already exist in the original binary; + // This is for REL/RELA if it doesn't already exist in the original binary; if(dynamicSecData.find(tag) != dynamicSecData.end()) dynamicSecData[tag][0]->d_tag = tag; else return; @@ -1277,7 +1277,7 @@ bool emitElf::createLoadableSections(Elf_Shdr *&shdr, unsigned &extraA } else if (!firstNewLoadSec || !newSecs[i]->getDiskOffset()) { newshdr->sh_offset = shdr->sh_offset + shdr->sh_size; } else { - // The offset can be computed by determing the difference from + // The offset can be computed by determining the difference from // the first new loadable section newshdr->sh_offset = firstNewLoadSec->sh_offset + library_adjust + (newSecs[i]->getDiskOffset() - firstNewLoadSec->sh_addr); @@ -1632,7 +1632,7 @@ bool emitElf::createNonLoadableSections(Elf_Shdr *&shdr) { /* Regenerates the .symtab, .strtab sections from the symbols * Add new .dynsym, .dynstr sections for the newly added dynamic symbols - * Method - For every symbol call createElfSymbol to get a Elf_Sym corresposnding + * Method - For every symbol call createElfSymbol to get a Elf_Sym corresponding * to a Symbol object. Accumulate all and their names to form the sections * and add them to the list of new sections */ @@ -1718,7 +1718,7 @@ bool emitElf::createSymbolTables(set &allSymbols) { + errMsg; Symtab::setSymtabError(Emit_Error); symtab_log_perror(linkStaticError.c_str()); - fprintf(stderr, "##### %s\n", linkStaticError.c_str()); + fprintf(stderr, "##### %s\n", linkStaticError.c_str()); return false; } @@ -1755,7 +1755,7 @@ bool emitElf::createSymbolTables(set &allSymbols) { } } - // sort allSymbols in a way that every symmbol with index -1 are in order of offset + // sort allSymbols in a way that every symbol with index -1 are in order of offset std::sort(allDynSymbols.begin(), allDynSymbols.end(), sortByOffsetNewIndices()); int max_index = -1; @@ -1990,6 +1990,32 @@ bool emitElf::createSymbolTables(set &allSymbols) { if (!obj->getAllNewRegions(newSecs)) log_elferror(err_func_, "No new sections to add"); + unsigned int prev_size = 0; + unsigned long sec_addr = 0; + for (unsigned long nsi = 0; nsi < newSecs.size(); nsi++) { + // Update the _DYNAMIC symbol; described in the elf standard as: + // The program header table will have an element of type PT_DYNAMIC. + // This "segment" contains the .dynamic section. A special symbol, + // _DYNAMIC, labels the section + if (newSecs[nsi]->getDiskOffset()) + sec_addr = newSecs[nsi]->getDiskOffset() + library_adjust; + else + sec_addr += prev_size; + prev_size = newSecs[nsi]->getDiskSize(); + if (".dynamic" == newSecs[nsi]->getRegionName()) { + // Found the .dynamic section + for (unsigned long symi = 0; symi < symbolStrs.size(); symi++) + if ("_DYNAMIC" == symbolStrs[symi]) { + // Found the _DYNAMIC symbol + rewrite_printf("update _DYNAMIC symbol from %#lx to %#lx\n", + (unsigned long) syms[symi].st_value, (unsigned long) sec_addr); + syms[symi].st_value = sec_addr; + break; + } + break; + } + } + return true; } From 8afa925fd7b421ce6eb9ad3734d00c6907c8c610 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 25 Jan 2022 20:34:23 -0600 Subject: [PATCH 071/505] Remove dead code Object::elf_vaddr_to_ptr (#1192) --- symtabAPI/src/Object-elf.C | 14 -------------- symtabAPI/src/Object-elf.h | 3 +-- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index b3e76d3f47..4aec0f8ad5 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -2429,20 +2429,6 @@ void Object::find_code_and_data(Elf_X &elf, //if (addressWidth_nbytes == 8) bperr( ">>> 64-bit find_code_and_data() successful\n"); } -const char *Object::elf_vaddr_to_ptr(Offset vaddr) const { - const char *ret = NULL; - unsigned code_size_ = code_len_; - unsigned data_size_ = data_len_; - - if (vaddr >= code_off_ && vaddr < code_off_ + code_size_) { - ret = ((char *) code_ptr_) + (vaddr - code_off_); - } else if (vaddr >= data_off_ && vaddr < data_off_ + data_size_) { - ret = ((char *) data_ptr_) + (vaddr - data_off_); - } - - return ret; -} - Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), bool alloc_syms, Symtab *st) : AObject(mf_, err_func, st), diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index 69b9fa8596..0f29ec1a3a 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -156,8 +156,7 @@ class Object : public AObject virtual ~Object(); bool emitDriver(std::string fName, std::set &allSymbols, unsigned flag); - - const char *elf_vaddr_to_ptr(Offset vaddr) const; + bool hasDwarfInfo() const { return dwarvenDebugInfo; } std::string getFileName() const; void getModuleLanguageInfo(dyn_hash_map *mod_langs); From fd8744ee667874c6780f4f3a4ce9297d0f8388bd Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 25 Jan 2022 20:44:17 -0600 Subject: [PATCH 072/505] Remove dead code and variables related to Symtab::data_ptr_ and Symtab::code_ptr_ (#1192) --- symtabAPI/h/Symtab.h | 2 -- symtabAPI/src/Symtab.C | 18 ------------------ 2 files changed, 20 deletions(-) diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 71e3a338c9..4a06cadad8 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -508,8 +508,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, Offset main_call_addr_; // address of call to main() unsigned address_width_; - char *code_ptr_; - char *data_ptr_; std::string interpreter_name_; Offset entry_address_; Offset base_address_; diff --git a/symtabAPI/src/Symtab.C b/symtabAPI/src/Symtab.C index 24f52a7c88..2308b5276e 100644 --- a/symtabAPI/src/Symtab.C +++ b/symtabAPI/src/Symtab.C @@ -313,7 +313,6 @@ SYMTAB_EXPORT Symtab::Symtab(MappedFile *mf_) : is_a_out(false), main_call_addr_(0), address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), entry_address_(0), base_address_(0), load_address_(0), object_type_(obj_Unknown), is_eel_(false), no_of_sections(0), @@ -343,7 +342,6 @@ SYMTAB_EXPORT Symtab::Symtab() : is_a_out(false), main_call_addr_(0), address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), entry_address_(0), base_address_(0), load_address_(0), object_type_(obj_Unknown), is_eel_(false), no_of_sections(0), @@ -426,17 +424,6 @@ SYMTAB_EXPORT void Symtab::fixup_code_and_data(Offset newImageOffset, // Should we update the underlying Object? } -/* -SYMTAB_EXPORT char* Symtab::image_ptr () const -{ - return code_ptr_; -} - -SYMTAB_EXPORT char* Symtab::data_ptr () const -{ - return data_ptr_; -} -*/ SYMTAB_EXPORT const char* Symtab::getInterpreterName() const { if (interpreter_name_.length()) @@ -1069,7 +1056,6 @@ Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : is_a_out(false), main_call_addr_(0), address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), entry_address_(0), base_address_(0), load_address_(0), object_type_(obj_Unknown), is_eel_(false), no_of_sections(0), @@ -1139,7 +1125,6 @@ Symtab::Symtab(unsigned char *mem_image, size_t image_size, is_a_out(false), main_call_addr_(0), address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), entry_address_(0), base_address_(0), load_address_(0), object_type_(obj_Unknown), is_eel_(false), no_of_sections(0), @@ -1318,8 +1303,6 @@ bool Symtab::extractInfo(Object *linkedFile) /* insert error check here. check if parsed */ address_width_ = linkedFile->getAddressWidth(); is_a_out = linkedFile->is_aout(); - code_ptr_ = linkedFile->code_ptr(); - data_ptr_ = linkedFile->data_ptr(); if (linkedFile->interpreter_name()) interpreter_name_ = std::string(linkedFile->interpreter_name()); @@ -1419,7 +1402,6 @@ Symtab::Symtab(const Symtab& obj) : is_a_out(obj.is_a_out), main_call_addr_(obj.main_call_addr_), address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), entry_address_(0), base_address_(0), load_address_(0), object_type_(obj_Unknown), is_eel_(false), defaultNamespacePrefix(obj.defaultNamespacePrefix), From 645e38a33fa5a86153bd08d923355f432289f7d5 Mon Sep 17 00:00:00 2001 From: Xiaozhu Meng Date: Tue, 25 Jan 2022 20:30:53 -0600 Subject: [PATCH 073/505] Allow zero-length ELF program headers (#1192) CUDA-11.6 binaries do not have program headers, which causes ELF parsing to stop early and miss line info --- symtabAPI/src/Object-elf.C | 6 ------ 1 file changed, 6 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 4aec0f8ad5..d70477d7d5 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -1489,12 +1489,6 @@ void Object::load_object(bool alloc_syms) { // find code and data segments.... find_code_and_data(*elfHdr, txtaddr, dataddr); - if (elfHdr->e_type() != ET_REL) { - if (!code_ptr_ || !code_len_) { - //bpfatal( "no text segment\n"); - goto cleanup; - } - } get_valid_memory_areas(*elfHdr); #if (defined(os_linux) || defined(os_freebsd)) From 7c8d841b1321eefa8349423356b1f884cb3e60c1 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 4 Feb 2022 19:08:30 -0600 Subject: [PATCH 074/505] Additional cleanup of memory emulation for hybrid analysis (#1172) * Remove vestiges of runtime functions * Remove translation for emulation shadow pages Co-authored-by: Tim Haines --- dyninstAPI/src/IAPI_to_AST.C | 9 +-------- dyninstAPI_RT/h/dyninstRTExport.h | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/dyninstAPI/src/IAPI_to_AST.C b/dyninstAPI/src/IAPI_to_AST.C index a27909a396..15e6b89270 100644 --- a/dyninstAPI/src/IAPI_to_AST.C +++ b/dyninstAPI/src/IAPI_to_AST.C @@ -69,14 +69,7 @@ void ASTFactory::visit(Dereference* ) { AstNodePtr effaddr = m_stack.back(); m_stack.pop_back(); - // We need to translate the addr to handle emulation shadow pages - // before we dereference - std::vector args; - args.push_back(effaddr); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *) 0xdeadbeef)); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *) 0xcafebabe)); - AstNodePtr funcCall = AstNode::funcCallNode("RTtranslateMemory", args); - m_stack.push_back(AstNode::operandNode(AstNode::DataIndir, funcCall)); + m_stack.push_back(AstNode::operandNode(AstNode::DataIndir, effaddr)); } void ASTFactory::visit(Immediate* i) diff --git a/dyninstAPI_RT/h/dyninstRTExport.h b/dyninstAPI_RT/h/dyninstRTExport.h index ed9f9c3016..526298c54d 100644 --- a/dyninstAPI_RT/h/dyninstRTExport.h +++ b/dyninstAPI_RT/h/dyninstRTExport.h @@ -102,9 +102,6 @@ DLLEXPORT void DYNINSTinit(); DLLEXPORT void DYNINST_snippetBreakpoint(); DLLEXPORT void DYNINST_stopThread(void *, void *, void *, void *); DLLEXPORT void DYNINST_stopInterProc(void *, void *, void *, void *, void *, void *); -DLLEXPORT void RThandleShadow(void *, void *, void *, void *, void *); -DLLEXPORT unsigned long RTtranslateMemory(unsigned long, unsigned long, unsigned long); -DLLEXPORT unsigned long RTtranslateMemoryShift(unsigned long, unsigned long, unsigned long); DLLEXPORT void *DYNINSTos_malloc(size_t, void *, void *); DLLEXPORT int DYNINSTloadLibrary(char *); From b8fed71b204e98b016dc751f2273da5fa2d5967f Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 9 Feb 2022 10:41:16 -0600 Subject: [PATCH 075/505] fix building of symlite (#1197) - add missing pure virtual functions isReadOnly - fix isCode and isData methods to use program header permissions instead of just returning true - fix printf compiler warning - disable parseThat if using symlite as it is not compatible - remove #include from proccontrol/src/linux.h on aarch64 if SYMLITE is configured as it is incompatible with --- CMakeLists.txt | 6 ++++-- parseAPI/h/SymLiteCodeSource.h | 8 +++++--- parseAPI/src/SymLiteCodeSource.C | 28 +++++++++++++++++++++++++--- proccontrol/src/linux.C | 2 ++ 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 994d3e35ba..a4c6d7d76e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -92,7 +92,6 @@ if(NOT ${PLATFORM} MATCHES nt) add_subdirectory (elf) add_subdirectory (dwarf) add_subdirectory (symlite) - add_subdirectory (parseThat) endif() add_subdirectory (instructionAPI) add_subdirectory (symtabAPI) @@ -104,6 +103,7 @@ add_subdirectory (patchAPI) if(${SYMREADER} MATCHES symtabAPI) add_subdirectory (dyninstAPI) add_subdirectory (dynC_API) + add_subdirectory (parseThat) endif() if(BUILD_RTLIB) @@ -143,7 +143,9 @@ if(BUILD_RTLIB) if(TARGET TBB) add_dependencies(DyninstRT TBB) endif() - add_dependencies(dyninstAPI DyninstRT) + if(TARGET dyninstAPI) + add_dependencies(dyninstAPI DyninstRT) + endif() if(TARGET dyninstAPI-static) add_dependencies(dyninstAPI-static DyninstRT) endif() diff --git a/parseAPI/h/SymLiteCodeSource.h b/parseAPI/h/SymLiteCodeSource.h index fad01eae29..054dd1f378 100644 --- a/parseAPI/h/SymLiteCodeSource.h +++ b/parseAPI/h/SymLiteCodeSource.h @@ -65,9 +65,10 @@ class SymReaderCodeRegion : public CodeRegion { PARSER_EXPORT bool isValidAddress(const Address) const; PARSER_EXPORT void* getPtrToInstruction(const Address) const; PARSER_EXPORT void* getPtrToData(const Address) const; - PARSER_EXPORT unsigned int getAddressWidth() const; - PARSER_EXPORT bool isCode(const Address) const; - PARSER_EXPORT bool isData(const Address) const; + PARSER_EXPORT unsigned int getAddressWidth() const override; + PARSER_EXPORT bool isCode(const Address) const override; + PARSER_EXPORT bool isData(const Address) const override; + PARSER_EXPORT bool isReadOnly(const Address) const override; PARSER_EXPORT Address offset() const; PARSER_EXPORT Address length() const; PARSER_EXPORT Architecture getArch() const; @@ -109,6 +110,7 @@ class SymReaderCodeSource : public CodeSource { PARSER_EXPORT unsigned int getAddressWidth() const; PARSER_EXPORT bool isCode(const Address) const; PARSER_EXPORT bool isData(const Address) const; + PARSER_EXPORT bool isReadOnly(const Address) const; PARSER_EXPORT Address offset() const; PARSER_EXPORT Address length() const; PARSER_EXPORT Architecture getArch() const; diff --git a/parseAPI/src/SymLiteCodeSource.C b/parseAPI/src/SymLiteCodeSource.C index f826165a1a..8b9475870c 100644 --- a/parseAPI/src/SymLiteCodeSource.C +++ b/parseAPI/src/SymLiteCodeSource.C @@ -148,7 +148,7 @@ bool SymReaderCodeRegion::isCode(const Address addr) const { if(!contains(addr)) return false; - return true; + return _region->perms & PF_X; /* // XXX this is the predicate from SymReader::isCode(a) + @@ -163,7 +163,7 @@ bool SymReaderCodeRegion::isData(const Address addr) const { if(!contains(addr)) return false; - return true; + return !(_region->perms & PF_X); /* @@ -174,6 +174,16 @@ SymReaderCodeRegion::isData(const Address addr) const */ } +bool +SymReaderCodeRegion::isReadOnly(const Address addr) const +{ + if (!contains(addr)) { + return false; + } + + return !(_region->perms & PF_W); +} + Address SymReaderCodeRegion::offset() const { @@ -400,7 +410,7 @@ inline void SymReaderCodeSource::overlapping_warn(const char * file, unsigned line) const { if(regionsOverlap()) { - fprintf(stderr,"Invocation of routine at %s:%d is ambiguous for " + fprintf(stderr,"Invocation of routine at %s:%u is ambiguous for " "binaries with overlapping code regions\n", file,line); } @@ -484,6 +494,18 @@ SymReaderCodeSource::isData(const Address addr) const return false; } +bool +SymReaderCodeSource::isReadOnly(const Address addr) const +{ + overlapping_warn(FILE__,__LINE__); + + CodeRegion * cr = lookup_region(addr); + if(cr) + return cr->isReadOnly(addr); + else + return false; +} + Address SymReaderCodeSource::offset() const { diff --git a/proccontrol/src/linux.C b/proccontrol/src/linux.C index c51c7e3b1e..5e46507acf 100644 --- a/proccontrol/src/linux.C +++ b/proccontrol/src/linux.C @@ -75,8 +75,10 @@ #include #include #include +#if !defined(WITH_SYMLITE) #include #endif +#endif // Before glibc-2.7, sys/ptrace.h lacked PTRACE_O_* and PTRACE_EVENT_*, so we // need them from linux/ptrace.h. (Conditionally, as later glibc conflicts.) From a85835269188c24a5c27a50bbd06751c1badc3d7 Mon Sep 17 00:00:00 2001 From: bbiiggppiigg Date: Wed, 23 Feb 2022 09:16:55 -0600 Subject: [PATCH 076/505] Add Support for AMDGPU CDNA2 Architectures based on XML ISA spec (#1107) Add Initial Support for cdna based on the lastest version of XML file ( 20210720 ) Added new register names based on the latest xml-isa drop Decoder implementation updated based on the latest xml-isa drop renumbered registers to make low registers have the same value as full register (or its super set) add larger memoery types for representing consecutive registers used as a single operand Modify the format function to output multiple registers as a single operand correctly, handling for certain registers are still being worked on split register-vector into multiple registers --- common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h | 617 ++ common/h/amdgpu_cdna2_op_table.h | 1135 ++ common/h/amdgpu_cdna2_sys_regs.h | 1563 +++ common/h/amdgpu_cdna_op_table.h | 1152 ++ common/h/amdgpu_cdna_sys_regs.h | 1563 +++ common/h/amdgpu_op_table.h | 783 +- common/h/dyn_regs.h | 3954 +++---- common/h/entryIDs.h | 2 + common/src/dyn_regs.C | 452 +- dwarf/src/dwarfHandle.C | 6 +- elf/src/Elf_X.C | 6 +- instructionAPI/CMakeLists.txt | 5 +- instructionAPI/h/Instruction.h | 2 + instructionAPI/h/Operation_impl.h | 3 + instructionAPI/h/Result.h | 1095 +- .../cdna2/InstructionDecoder-amdgpu-cdna2.C | 310 + .../cdna2/InstructionDecoder-amdgpu-cdna2.h | 317 + .../AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C | 2195 ++++ .../AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h | 378 + .../AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h | 30 + .../src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h | 1135 ++ .../AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C | 2879 +++++ .../src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h | 617 ++ .../src/AMDGPU/cdna2/decodeOperands.C | 6648 +++++++++++ .../src/AMDGPU/cdna2/decodeOperands.h | 41 + .../src/AMDGPU/cdna2/finalizeOperands.C | 9860 +++++++++++++++++ .../vega}/InstructionDecoder-amdgpu-vega.C | 17 +- .../vega}/InstructionDecoder-amdgpu-vega.h | 8 +- .../vega/amdgpu_vega_decoder_impl.C} | 64 +- .../vega/amdgpu_vega_decoder_impl.h} | 0 .../src/AMDGPU/vega/amdgpu_vega_insn_entry.h | 24 + .../vega/amdgpu_vega_opcode_tables.C} | 128 +- instructionAPI/src/Instruction.C | 1077 +- instructionAPI/src/InstructionCategories.C | 1 + instructionAPI/src/InstructionDecoderImpl.C | 5 +- instructionAPI/src/Operand.C | 195 +- instructionAPI/src/Operation.C | 924 +- instructionAPI/src/Register.C | 34 +- instructionAPI/src/amdgpu_branchinsn_table.h | 16 + instructionAPI/src/amdgpu_insn_entry.h | 24 - parseAPI/src/IA_IAPI.C | 31 +- parseAPI/src/IA_amdgpu.C | 3 +- parseAPI/src/SymbolicExpression.C | 2 +- proccontrol/src/process.C | 3 +- 44 files changed, 35037 insertions(+), 4267 deletions(-) create mode 100644 common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h create mode 100644 common/h/amdgpu_cdna2_op_table.h create mode 100644 common/h/amdgpu_cdna2_sys_regs.h create mode 100644 common/h/amdgpu_cdna_op_table.h create mode 100644 common/h/amdgpu_cdna_sys_regs.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C create mode 100644 instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C create mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/decodeOperands.C create mode 100644 instructionAPI/src/AMDGPU/cdna2/decodeOperands.h create mode 100644 instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C rename instructionAPI/src/{ => AMDGPU/vega}/InstructionDecoder-amdgpu-vega.C (98%) rename instructionAPI/src/{ => AMDGPU/vega}/InstructionDecoder-amdgpu-vega.h (98%) rename instructionAPI/src/{amdgpu_decoder_impl_vega.C => AMDGPU/vega/amdgpu_vega_decoder_impl.C} (84%) rename instructionAPI/src/{amdgpu_decoder_impl_vega.h => AMDGPU/vega/amdgpu_vega_decoder_impl.h} (100%) create mode 100644 instructionAPI/src/AMDGPU/vega/amdgpu_vega_insn_entry.h rename instructionAPI/src/{amdgpu_opcode_tables.C => AMDGPU/vega/amdgpu_vega_opcode_tables.C} (96%) delete mode 100644 instructionAPI/src/amdgpu_insn_entry.h diff --git a/common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h b/common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h new file mode 100644 index 0000000000..8515f8630b --- /dev/null +++ b/common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h @@ -0,0 +1,617 @@ +#ifndef DYNINST_AMDGPU_CDNA2_SYS_REGS_H +#define DYNINST_AMDGPU_CDNA2_SYS_REGS_H +DEF_REGISTER(s0, Arch_amdgpu_cdna2| SGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(s1, Arch_amdgpu_cdna2| SGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(s2, Arch_amdgpu_cdna2| SGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(s3, Arch_amdgpu_cdna2| SGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(s4, Arch_amdgpu_cdna2| SGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(s5, Arch_amdgpu_cdna2| SGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(s6, Arch_amdgpu_cdna2| SGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(s7, Arch_amdgpu_cdna2| SGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(s8, Arch_amdgpu_cdna2| SGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(s9, Arch_amdgpu_cdna2| SGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(s10, Arch_amdgpu_cdna2| SGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(s11, Arch_amdgpu_cdna2| SGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(s12, Arch_amdgpu_cdna2| SGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(s13, Arch_amdgpu_cdna2| SGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(s14, Arch_amdgpu_cdna2| SGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(s15, Arch_amdgpu_cdna2| SGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(s16, Arch_amdgpu_cdna2| SGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(s17, Arch_amdgpu_cdna2| SGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(s18, Arch_amdgpu_cdna2| SGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(s19, Arch_amdgpu_cdna2| SGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(s20, Arch_amdgpu_cdna2| SGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(s21, Arch_amdgpu_cdna2| SGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(s22, Arch_amdgpu_cdna2| SGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(s23, Arch_amdgpu_cdna2| SGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(s24, Arch_amdgpu_cdna2| SGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(s25, Arch_amdgpu_cdna2| SGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(s26, Arch_amdgpu_cdna2| SGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(s27, Arch_amdgpu_cdna2| SGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(s28, Arch_amdgpu_cdna2| SGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(s29, Arch_amdgpu_cdna2| SGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(s30, Arch_amdgpu_cdna2| SGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(s31, Arch_amdgpu_cdna2| SGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(s32, Arch_amdgpu_cdna2| SGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(s33, Arch_amdgpu_cdna2| SGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(s34, Arch_amdgpu_cdna2| SGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(s35, Arch_amdgpu_cdna2| SGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(s36, Arch_amdgpu_cdna2| SGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(s37, Arch_amdgpu_cdna2| SGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(s38, Arch_amdgpu_cdna2| SGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(s39, Arch_amdgpu_cdna2| SGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(s40, Arch_amdgpu_cdna2| SGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(s41, Arch_amdgpu_cdna2| SGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(s42, Arch_amdgpu_cdna2| SGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(s43, Arch_amdgpu_cdna2| SGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(s44, Arch_amdgpu_cdna2| SGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(s45, Arch_amdgpu_cdna2| SGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(s46, Arch_amdgpu_cdna2| SGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(s47, Arch_amdgpu_cdna2| SGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(s48, Arch_amdgpu_cdna2| SGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(s49, Arch_amdgpu_cdna2| SGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(s50, Arch_amdgpu_cdna2| SGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(s51, Arch_amdgpu_cdna2| SGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(s52, Arch_amdgpu_cdna2| SGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(s53, Arch_amdgpu_cdna2| SGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(s54, Arch_amdgpu_cdna2| SGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(s55, Arch_amdgpu_cdna2| SGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(s56, Arch_amdgpu_cdna2| SGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(s57, Arch_amdgpu_cdna2| SGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(s58, Arch_amdgpu_cdna2| SGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(s59, Arch_amdgpu_cdna2| SGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(s60, Arch_amdgpu_cdna2| SGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(s61, Arch_amdgpu_cdna2| SGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(s62, Arch_amdgpu_cdna2| SGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(s63, Arch_amdgpu_cdna2| SGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(s64, Arch_amdgpu_cdna2| SGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(s65, Arch_amdgpu_cdna2| SGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(s66, Arch_amdgpu_cdna2| SGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(s67, Arch_amdgpu_cdna2| SGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(s68, Arch_amdgpu_cdna2| SGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(s69, Arch_amdgpu_cdna2| SGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(s70, Arch_amdgpu_cdna2| SGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(s71, Arch_amdgpu_cdna2| SGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(s72, Arch_amdgpu_cdna2| SGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(s73, Arch_amdgpu_cdna2| SGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(s74, Arch_amdgpu_cdna2| SGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(s75, Arch_amdgpu_cdna2| SGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(s76, Arch_amdgpu_cdna2| SGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(s77, Arch_amdgpu_cdna2| SGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(s78, Arch_amdgpu_cdna2| SGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(s79, Arch_amdgpu_cdna2| SGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(s80, Arch_amdgpu_cdna2| SGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(s81, Arch_amdgpu_cdna2| SGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(s82, Arch_amdgpu_cdna2| SGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(s83, Arch_amdgpu_cdna2| SGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(s84, Arch_amdgpu_cdna2| SGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(s85, Arch_amdgpu_cdna2| SGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(s86, Arch_amdgpu_cdna2| SGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(s87, Arch_amdgpu_cdna2| SGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(s88, Arch_amdgpu_cdna2| SGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(s89, Arch_amdgpu_cdna2| SGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(s90, Arch_amdgpu_cdna2| SGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(s91, Arch_amdgpu_cdna2| SGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(s92, Arch_amdgpu_cdna2| SGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(s93, Arch_amdgpu_cdna2| SGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(s94, Arch_amdgpu_cdna2| SGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(s95, Arch_amdgpu_cdna2| SGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(s96, Arch_amdgpu_cdna2| SGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(s97, Arch_amdgpu_cdna2| SGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(s98, Arch_amdgpu_cdna2| SGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(s99, Arch_amdgpu_cdna2| SGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(s100, Arch_amdgpu_cdna2| SGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(s101, Arch_amdgpu_cdna2| SGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(v0, Arch_amdgpu_cdna2| VGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(v1, Arch_amdgpu_cdna2| VGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(v2, Arch_amdgpu_cdna2| VGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(v3, Arch_amdgpu_cdna2| VGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(v4, Arch_amdgpu_cdna2| VGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(v5, Arch_amdgpu_cdna2| VGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(v6, Arch_amdgpu_cdna2| VGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(v7, Arch_amdgpu_cdna2| VGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(v8, Arch_amdgpu_cdna2| VGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(v9, Arch_amdgpu_cdna2| VGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(v10, Arch_amdgpu_cdna2| VGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(v11, Arch_amdgpu_cdna2| VGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(v12, Arch_amdgpu_cdna2| VGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(v13, Arch_amdgpu_cdna2| VGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(v14, Arch_amdgpu_cdna2| VGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(v15, Arch_amdgpu_cdna2| VGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(v16, Arch_amdgpu_cdna2| VGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(v17, Arch_amdgpu_cdna2| VGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(v18, Arch_amdgpu_cdna2| VGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(v19, Arch_amdgpu_cdna2| VGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(v20, Arch_amdgpu_cdna2| VGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(v21, Arch_amdgpu_cdna2| VGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(v22, Arch_amdgpu_cdna2| VGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(v23, Arch_amdgpu_cdna2| VGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(v24, Arch_amdgpu_cdna2| VGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(v25, Arch_amdgpu_cdna2| VGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(v26, Arch_amdgpu_cdna2| VGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(v27, Arch_amdgpu_cdna2| VGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(v28, Arch_amdgpu_cdna2| VGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(v29, Arch_amdgpu_cdna2| VGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(v30, Arch_amdgpu_cdna2| VGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(v31, Arch_amdgpu_cdna2| VGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(v32, Arch_amdgpu_cdna2| VGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(v33, Arch_amdgpu_cdna2| VGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(v34, Arch_amdgpu_cdna2| VGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(v35, Arch_amdgpu_cdna2| VGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(v36, Arch_amdgpu_cdna2| VGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(v37, Arch_amdgpu_cdna2| VGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(v38, Arch_amdgpu_cdna2| VGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(v39, Arch_amdgpu_cdna2| VGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(v40, Arch_amdgpu_cdna2| VGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(v41, Arch_amdgpu_cdna2| VGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(v42, Arch_amdgpu_cdna2| VGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(v43, Arch_amdgpu_cdna2| VGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(v44, Arch_amdgpu_cdna2| VGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(v45, Arch_amdgpu_cdna2| VGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(v46, Arch_amdgpu_cdna2| VGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(v47, Arch_amdgpu_cdna2| VGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(v48, Arch_amdgpu_cdna2| VGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(v49, Arch_amdgpu_cdna2| VGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(v50, Arch_amdgpu_cdna2| VGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(v51, Arch_amdgpu_cdna2| VGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(v52, Arch_amdgpu_cdna2| VGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(v53, Arch_amdgpu_cdna2| VGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(v54, Arch_amdgpu_cdna2| VGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(v55, Arch_amdgpu_cdna2| VGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(v56, Arch_amdgpu_cdna2| VGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(v57, Arch_amdgpu_cdna2| VGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(v58, Arch_amdgpu_cdna2| VGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(v59, Arch_amdgpu_cdna2| VGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(v60, Arch_amdgpu_cdna2| VGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(v61, Arch_amdgpu_cdna2| VGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(v62, Arch_amdgpu_cdna2| VGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(v63, Arch_amdgpu_cdna2| VGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(v64, Arch_amdgpu_cdna2| VGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(v65, Arch_amdgpu_cdna2| VGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(v66, Arch_amdgpu_cdna2| VGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(v67, Arch_amdgpu_cdna2| VGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(v68, Arch_amdgpu_cdna2| VGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(v69, Arch_amdgpu_cdna2| VGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(v70, Arch_amdgpu_cdna2| VGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(v71, Arch_amdgpu_cdna2| VGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(v72, Arch_amdgpu_cdna2| VGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(v73, Arch_amdgpu_cdna2| VGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(v74, Arch_amdgpu_cdna2| VGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(v75, Arch_amdgpu_cdna2| VGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(v76, Arch_amdgpu_cdna2| VGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(v77, Arch_amdgpu_cdna2| VGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(v78, Arch_amdgpu_cdna2| VGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(v79, Arch_amdgpu_cdna2| VGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(v80, Arch_amdgpu_cdna2| VGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(v81, Arch_amdgpu_cdna2| VGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(v82, Arch_amdgpu_cdna2| VGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(v83, Arch_amdgpu_cdna2| VGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(v84, Arch_amdgpu_cdna2| VGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(v85, Arch_amdgpu_cdna2| VGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(v86, Arch_amdgpu_cdna2| VGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(v87, Arch_amdgpu_cdna2| VGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(v88, Arch_amdgpu_cdna2| VGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(v89, Arch_amdgpu_cdna2| VGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(v90, Arch_amdgpu_cdna2| VGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(v91, Arch_amdgpu_cdna2| VGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(v92, Arch_amdgpu_cdna2| VGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(v93, Arch_amdgpu_cdna2| VGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(v94, Arch_amdgpu_cdna2| VGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(v95, Arch_amdgpu_cdna2| VGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(v96, Arch_amdgpu_cdna2| VGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(v97, Arch_amdgpu_cdna2| VGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(v98, Arch_amdgpu_cdna2| VGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(v99, Arch_amdgpu_cdna2| VGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(v100, Arch_amdgpu_cdna2| VGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(v101, Arch_amdgpu_cdna2| VGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(v102, Arch_amdgpu_cdna2| VGPR | BITS_32 | 102 , "amdgpu_cdna2"); +DEF_REGISTER(v103, Arch_amdgpu_cdna2| VGPR | BITS_32 | 103 , "amdgpu_cdna2"); +DEF_REGISTER(v104, Arch_amdgpu_cdna2| VGPR | BITS_32 | 104 , "amdgpu_cdna2"); +DEF_REGISTER(v105, Arch_amdgpu_cdna2| VGPR | BITS_32 | 105 , "amdgpu_cdna2"); +DEF_REGISTER(v106, Arch_amdgpu_cdna2| VGPR | BITS_32 | 106 , "amdgpu_cdna2"); +DEF_REGISTER(v107, Arch_amdgpu_cdna2| VGPR | BITS_32 | 107 , "amdgpu_cdna2"); +DEF_REGISTER(v108, Arch_amdgpu_cdna2| VGPR | BITS_32 | 108 , "amdgpu_cdna2"); +DEF_REGISTER(v109, Arch_amdgpu_cdna2| VGPR | BITS_32 | 109 , "amdgpu_cdna2"); +DEF_REGISTER(v110, Arch_amdgpu_cdna2| VGPR | BITS_32 | 110 , "amdgpu_cdna2"); +DEF_REGISTER(v111, Arch_amdgpu_cdna2| VGPR | BITS_32 | 111 , "amdgpu_cdna2"); +DEF_REGISTER(v112, Arch_amdgpu_cdna2| VGPR | BITS_32 | 112 , "amdgpu_cdna2"); +DEF_REGISTER(v113, Arch_amdgpu_cdna2| VGPR | BITS_32 | 113 , "amdgpu_cdna2"); +DEF_REGISTER(v114, Arch_amdgpu_cdna2| VGPR | BITS_32 | 114 , "amdgpu_cdna2"); +DEF_REGISTER(v115, Arch_amdgpu_cdna2| VGPR | BITS_32 | 115 , "amdgpu_cdna2"); +DEF_REGISTER(v116, Arch_amdgpu_cdna2| VGPR | BITS_32 | 116 , "amdgpu_cdna2"); +DEF_REGISTER(v117, Arch_amdgpu_cdna2| VGPR | BITS_32 | 117 , "amdgpu_cdna2"); +DEF_REGISTER(v118, Arch_amdgpu_cdna2| VGPR | BITS_32 | 118 , "amdgpu_cdna2"); +DEF_REGISTER(v119, Arch_amdgpu_cdna2| VGPR | BITS_32 | 119 , "amdgpu_cdna2"); +DEF_REGISTER(v120, Arch_amdgpu_cdna2| VGPR | BITS_32 | 120 , "amdgpu_cdna2"); +DEF_REGISTER(v121, Arch_amdgpu_cdna2| VGPR | BITS_32 | 121 , "amdgpu_cdna2"); +DEF_REGISTER(v122, Arch_amdgpu_cdna2| VGPR | BITS_32 | 122 , "amdgpu_cdna2"); +DEF_REGISTER(v123, Arch_amdgpu_cdna2| VGPR | BITS_32 | 123 , "amdgpu_cdna2"); +DEF_REGISTER(v124, Arch_amdgpu_cdna2| VGPR | BITS_32 | 124 , "amdgpu_cdna2"); +DEF_REGISTER(v125, Arch_amdgpu_cdna2| VGPR | BITS_32 | 125 , "amdgpu_cdna2"); +DEF_REGISTER(v126, Arch_amdgpu_cdna2| VGPR | BITS_32 | 126 , "amdgpu_cdna2"); +DEF_REGISTER(v127, Arch_amdgpu_cdna2| VGPR | BITS_32 | 127 , "amdgpu_cdna2"); +DEF_REGISTER(v128, Arch_amdgpu_cdna2| VGPR | BITS_32 | 128 , "amdgpu_cdna2"); +DEF_REGISTER(v129, Arch_amdgpu_cdna2| VGPR | BITS_32 | 129 , "amdgpu_cdna2"); +DEF_REGISTER(v130, Arch_amdgpu_cdna2| VGPR | BITS_32 | 130 , "amdgpu_cdna2"); +DEF_REGISTER(v131, Arch_amdgpu_cdna2| VGPR | BITS_32 | 131 , "amdgpu_cdna2"); +DEF_REGISTER(v132, Arch_amdgpu_cdna2| VGPR | BITS_32 | 132 , "amdgpu_cdna2"); +DEF_REGISTER(v133, Arch_amdgpu_cdna2| VGPR | BITS_32 | 133 , "amdgpu_cdna2"); +DEF_REGISTER(v134, Arch_amdgpu_cdna2| VGPR | BITS_32 | 134 , "amdgpu_cdna2"); +DEF_REGISTER(v135, Arch_amdgpu_cdna2| VGPR | BITS_32 | 135 , "amdgpu_cdna2"); +DEF_REGISTER(v136, Arch_amdgpu_cdna2| VGPR | BITS_32 | 136 , "amdgpu_cdna2"); +DEF_REGISTER(v137, Arch_amdgpu_cdna2| VGPR | BITS_32 | 137 , "amdgpu_cdna2"); +DEF_REGISTER(v138, Arch_amdgpu_cdna2| VGPR | BITS_32 | 138 , "amdgpu_cdna2"); +DEF_REGISTER(v139, Arch_amdgpu_cdna2| VGPR | BITS_32 | 139 , "amdgpu_cdna2"); +DEF_REGISTER(v140, Arch_amdgpu_cdna2| VGPR | BITS_32 | 140 , "amdgpu_cdna2"); +DEF_REGISTER(v141, Arch_amdgpu_cdna2| VGPR | BITS_32 | 141 , "amdgpu_cdna2"); +DEF_REGISTER(v142, Arch_amdgpu_cdna2| VGPR | BITS_32 | 142 , "amdgpu_cdna2"); +DEF_REGISTER(v143, Arch_amdgpu_cdna2| VGPR | BITS_32 | 143 , "amdgpu_cdna2"); +DEF_REGISTER(v144, Arch_amdgpu_cdna2| VGPR | BITS_32 | 144 , "amdgpu_cdna2"); +DEF_REGISTER(v145, Arch_amdgpu_cdna2| VGPR | BITS_32 | 145 , "amdgpu_cdna2"); +DEF_REGISTER(v146, Arch_amdgpu_cdna2| VGPR | BITS_32 | 146 , "amdgpu_cdna2"); +DEF_REGISTER(v147, Arch_amdgpu_cdna2| VGPR | BITS_32 | 147 , "amdgpu_cdna2"); +DEF_REGISTER(v148, Arch_amdgpu_cdna2| VGPR | BITS_32 | 148 , "amdgpu_cdna2"); +DEF_REGISTER(v149, Arch_amdgpu_cdna2| VGPR | BITS_32 | 149 , "amdgpu_cdna2"); +DEF_REGISTER(v150, Arch_amdgpu_cdna2| VGPR | BITS_32 | 150 , "amdgpu_cdna2"); +DEF_REGISTER(v151, Arch_amdgpu_cdna2| VGPR | BITS_32 | 151 , "amdgpu_cdna2"); +DEF_REGISTER(v152, Arch_amdgpu_cdna2| VGPR | BITS_32 | 152 , "amdgpu_cdna2"); +DEF_REGISTER(v153, Arch_amdgpu_cdna2| VGPR | BITS_32 | 153 , "amdgpu_cdna2"); +DEF_REGISTER(v154, Arch_amdgpu_cdna2| VGPR | BITS_32 | 154 , "amdgpu_cdna2"); +DEF_REGISTER(v155, Arch_amdgpu_cdna2| VGPR | BITS_32 | 155 , "amdgpu_cdna2"); +DEF_REGISTER(v156, Arch_amdgpu_cdna2| VGPR | BITS_32 | 156 , "amdgpu_cdna2"); +DEF_REGISTER(v157, Arch_amdgpu_cdna2| VGPR | BITS_32 | 157 , "amdgpu_cdna2"); +DEF_REGISTER(v158, Arch_amdgpu_cdna2| VGPR | BITS_32 | 158 , "amdgpu_cdna2"); +DEF_REGISTER(v159, Arch_amdgpu_cdna2| VGPR | BITS_32 | 159 , "amdgpu_cdna2"); +DEF_REGISTER(v160, Arch_amdgpu_cdna2| VGPR | BITS_32 | 160 , "amdgpu_cdna2"); +DEF_REGISTER(v161, Arch_amdgpu_cdna2| VGPR | BITS_32 | 161 , "amdgpu_cdna2"); +DEF_REGISTER(v162, Arch_amdgpu_cdna2| VGPR | BITS_32 | 162 , "amdgpu_cdna2"); +DEF_REGISTER(v163, Arch_amdgpu_cdna2| VGPR | BITS_32 | 163 , "amdgpu_cdna2"); +DEF_REGISTER(v164, Arch_amdgpu_cdna2| VGPR | BITS_32 | 164 , "amdgpu_cdna2"); +DEF_REGISTER(v165, Arch_amdgpu_cdna2| VGPR | BITS_32 | 165 , "amdgpu_cdna2"); +DEF_REGISTER(v166, Arch_amdgpu_cdna2| VGPR | BITS_32 | 166 , "amdgpu_cdna2"); +DEF_REGISTER(v167, Arch_amdgpu_cdna2| VGPR | BITS_32 | 167 , "amdgpu_cdna2"); +DEF_REGISTER(v168, Arch_amdgpu_cdna2| VGPR | BITS_32 | 168 , "amdgpu_cdna2"); +DEF_REGISTER(v169, Arch_amdgpu_cdna2| VGPR | BITS_32 | 169 , "amdgpu_cdna2"); +DEF_REGISTER(v170, Arch_amdgpu_cdna2| VGPR | BITS_32 | 170 , "amdgpu_cdna2"); +DEF_REGISTER(v171, Arch_amdgpu_cdna2| VGPR | BITS_32 | 171 , "amdgpu_cdna2"); +DEF_REGISTER(v172, Arch_amdgpu_cdna2| VGPR | BITS_32 | 172 , "amdgpu_cdna2"); +DEF_REGISTER(v173, Arch_amdgpu_cdna2| VGPR | BITS_32 | 173 , "amdgpu_cdna2"); +DEF_REGISTER(v174, Arch_amdgpu_cdna2| VGPR | BITS_32 | 174 , "amdgpu_cdna2"); +DEF_REGISTER(v175, Arch_amdgpu_cdna2| VGPR | BITS_32 | 175 , "amdgpu_cdna2"); +DEF_REGISTER(v176, Arch_amdgpu_cdna2| VGPR | BITS_32 | 176 , "amdgpu_cdna2"); +DEF_REGISTER(v177, Arch_amdgpu_cdna2| VGPR | BITS_32 | 177 , "amdgpu_cdna2"); +DEF_REGISTER(v178, Arch_amdgpu_cdna2| VGPR | BITS_32 | 178 , "amdgpu_cdna2"); +DEF_REGISTER(v179, Arch_amdgpu_cdna2| VGPR | BITS_32 | 179 , "amdgpu_cdna2"); +DEF_REGISTER(v180, Arch_amdgpu_cdna2| VGPR | BITS_32 | 180 , "amdgpu_cdna2"); +DEF_REGISTER(v181, Arch_amdgpu_cdna2| VGPR | BITS_32 | 181 , "amdgpu_cdna2"); +DEF_REGISTER(v182, Arch_amdgpu_cdna2| VGPR | BITS_32 | 182 , "amdgpu_cdna2"); +DEF_REGISTER(v183, Arch_amdgpu_cdna2| VGPR | BITS_32 | 183 , "amdgpu_cdna2"); +DEF_REGISTER(v184, Arch_amdgpu_cdna2| VGPR | BITS_32 | 184 , "amdgpu_cdna2"); +DEF_REGISTER(v185, Arch_amdgpu_cdna2| VGPR | BITS_32 | 185 , "amdgpu_cdna2"); +DEF_REGISTER(v186, Arch_amdgpu_cdna2| VGPR | BITS_32 | 186 , "amdgpu_cdna2"); +DEF_REGISTER(v187, Arch_amdgpu_cdna2| VGPR | BITS_32 | 187 , "amdgpu_cdna2"); +DEF_REGISTER(v188, Arch_amdgpu_cdna2| VGPR | BITS_32 | 188 , "amdgpu_cdna2"); +DEF_REGISTER(v189, Arch_amdgpu_cdna2| VGPR | BITS_32 | 189 , "amdgpu_cdna2"); +DEF_REGISTER(v190, Arch_amdgpu_cdna2| VGPR | BITS_32 | 190 , "amdgpu_cdna2"); +DEF_REGISTER(v191, Arch_amdgpu_cdna2| VGPR | BITS_32 | 191 , "amdgpu_cdna2"); +DEF_REGISTER(v192, Arch_amdgpu_cdna2| VGPR | BITS_32 | 192 , "amdgpu_cdna2"); +DEF_REGISTER(v193, Arch_amdgpu_cdna2| VGPR | BITS_32 | 193 , "amdgpu_cdna2"); +DEF_REGISTER(v194, Arch_amdgpu_cdna2| VGPR | BITS_32 | 194 , "amdgpu_cdna2"); +DEF_REGISTER(v195, Arch_amdgpu_cdna2| VGPR | BITS_32 | 195 , "amdgpu_cdna2"); +DEF_REGISTER(v196, Arch_amdgpu_cdna2| VGPR | BITS_32 | 196 , "amdgpu_cdna2"); +DEF_REGISTER(v197, Arch_amdgpu_cdna2| VGPR | BITS_32 | 197 , "amdgpu_cdna2"); +DEF_REGISTER(v198, Arch_amdgpu_cdna2| VGPR | BITS_32 | 198 , "amdgpu_cdna2"); +DEF_REGISTER(v199, Arch_amdgpu_cdna2| VGPR | BITS_32 | 199 , "amdgpu_cdna2"); +DEF_REGISTER(v200, Arch_amdgpu_cdna2| VGPR | BITS_32 | 200 , "amdgpu_cdna2"); +DEF_REGISTER(v201, Arch_amdgpu_cdna2| VGPR | BITS_32 | 201 , "amdgpu_cdna2"); +DEF_REGISTER(v202, Arch_amdgpu_cdna2| VGPR | BITS_32 | 202 , "amdgpu_cdna2"); +DEF_REGISTER(v203, Arch_amdgpu_cdna2| VGPR | BITS_32 | 203 , "amdgpu_cdna2"); +DEF_REGISTER(v204, Arch_amdgpu_cdna2| VGPR | BITS_32 | 204 , "amdgpu_cdna2"); +DEF_REGISTER(v205, Arch_amdgpu_cdna2| VGPR | BITS_32 | 205 , "amdgpu_cdna2"); +DEF_REGISTER(v206, Arch_amdgpu_cdna2| VGPR | BITS_32 | 206 , "amdgpu_cdna2"); +DEF_REGISTER(v207, Arch_amdgpu_cdna2| VGPR | BITS_32 | 207 , "amdgpu_cdna2"); +DEF_REGISTER(v208, Arch_amdgpu_cdna2| VGPR | BITS_32 | 208 , "amdgpu_cdna2"); +DEF_REGISTER(v209, Arch_amdgpu_cdna2| VGPR | BITS_32 | 209 , "amdgpu_cdna2"); +DEF_REGISTER(v210, Arch_amdgpu_cdna2| VGPR | BITS_32 | 210 , "amdgpu_cdna2"); +DEF_REGISTER(v211, Arch_amdgpu_cdna2| VGPR | BITS_32 | 211 , "amdgpu_cdna2"); +DEF_REGISTER(v212, Arch_amdgpu_cdna2| VGPR | BITS_32 | 212 , "amdgpu_cdna2"); +DEF_REGISTER(v213, Arch_amdgpu_cdna2| VGPR | BITS_32 | 213 , "amdgpu_cdna2"); +DEF_REGISTER(v214, Arch_amdgpu_cdna2| VGPR | BITS_32 | 214 , "amdgpu_cdna2"); +DEF_REGISTER(v215, Arch_amdgpu_cdna2| VGPR | BITS_32 | 215 , "amdgpu_cdna2"); +DEF_REGISTER(v216, Arch_amdgpu_cdna2| VGPR | BITS_32 | 216 , "amdgpu_cdna2"); +DEF_REGISTER(v217, Arch_amdgpu_cdna2| VGPR | BITS_32 | 217 , "amdgpu_cdna2"); +DEF_REGISTER(v218, Arch_amdgpu_cdna2| VGPR | BITS_32 | 218 , "amdgpu_cdna2"); +DEF_REGISTER(v219, Arch_amdgpu_cdna2| VGPR | BITS_32 | 219 , "amdgpu_cdna2"); +DEF_REGISTER(v220, Arch_amdgpu_cdna2| VGPR | BITS_32 | 220 , "amdgpu_cdna2"); +DEF_REGISTER(v221, Arch_amdgpu_cdna2| VGPR | BITS_32 | 221 , "amdgpu_cdna2"); +DEF_REGISTER(v222, Arch_amdgpu_cdna2| VGPR | BITS_32 | 222 , "amdgpu_cdna2"); +DEF_REGISTER(v223, Arch_amdgpu_cdna2| VGPR | BITS_32 | 223 , "amdgpu_cdna2"); +DEF_REGISTER(v224, Arch_amdgpu_cdna2| VGPR | BITS_32 | 224 , "amdgpu_cdna2"); +DEF_REGISTER(v225, Arch_amdgpu_cdna2| VGPR | BITS_32 | 225 , "amdgpu_cdna2"); +DEF_REGISTER(v226, Arch_amdgpu_cdna2| VGPR | BITS_32 | 226 , "amdgpu_cdna2"); +DEF_REGISTER(v227, Arch_amdgpu_cdna2| VGPR | BITS_32 | 227 , "amdgpu_cdna2"); +DEF_REGISTER(v228, Arch_amdgpu_cdna2| VGPR | BITS_32 | 228 , "amdgpu_cdna2"); +DEF_REGISTER(v229, Arch_amdgpu_cdna2| VGPR | BITS_32 | 229 , "amdgpu_cdna2"); +DEF_REGISTER(v230, Arch_amdgpu_cdna2| VGPR | BITS_32 | 230 , "amdgpu_cdna2"); +DEF_REGISTER(v231, Arch_amdgpu_cdna2| VGPR | BITS_32 | 231 , "amdgpu_cdna2"); +DEF_REGISTER(v232, Arch_amdgpu_cdna2| VGPR | BITS_32 | 232 , "amdgpu_cdna2"); +DEF_REGISTER(v233, Arch_amdgpu_cdna2| VGPR | BITS_32 | 233 , "amdgpu_cdna2"); +DEF_REGISTER(v234, Arch_amdgpu_cdna2| VGPR | BITS_32 | 234 , "amdgpu_cdna2"); +DEF_REGISTER(v235, Arch_amdgpu_cdna2| VGPR | BITS_32 | 235 , "amdgpu_cdna2"); +DEF_REGISTER(v236, Arch_amdgpu_cdna2| VGPR | BITS_32 | 236 , "amdgpu_cdna2"); +DEF_REGISTER(v237, Arch_amdgpu_cdna2| VGPR | BITS_32 | 237 , "amdgpu_cdna2"); +DEF_REGISTER(v238, Arch_amdgpu_cdna2| VGPR | BITS_32 | 238 , "amdgpu_cdna2"); +DEF_REGISTER(v239, Arch_amdgpu_cdna2| VGPR | BITS_32 | 239 , "amdgpu_cdna2"); +DEF_REGISTER(v240, Arch_amdgpu_cdna2| VGPR | BITS_32 | 240 , "amdgpu_cdna2"); +DEF_REGISTER(v241, Arch_amdgpu_cdna2| VGPR | BITS_32 | 241 , "amdgpu_cdna2"); +DEF_REGISTER(v242, Arch_amdgpu_cdna2| VGPR | BITS_32 | 242 , "amdgpu_cdna2"); +DEF_REGISTER(v243, Arch_amdgpu_cdna2| VGPR | BITS_32 | 243 , "amdgpu_cdna2"); +DEF_REGISTER(v244, Arch_amdgpu_cdna2| VGPR | BITS_32 | 244 , "amdgpu_cdna2"); +DEF_REGISTER(v245, Arch_amdgpu_cdna2| VGPR | BITS_32 | 245 , "amdgpu_cdna2"); +DEF_REGISTER(v246, Arch_amdgpu_cdna2| VGPR | BITS_32 | 246 , "amdgpu_cdna2"); +DEF_REGISTER(v247, Arch_amdgpu_cdna2| VGPR | BITS_32 | 247 , "amdgpu_cdna2"); +DEF_REGISTER(v248, Arch_amdgpu_cdna2| VGPR | BITS_32 | 248 , "amdgpu_cdna2"); +DEF_REGISTER(v249, Arch_amdgpu_cdna2| VGPR | BITS_32 | 249 , "amdgpu_cdna2"); +DEF_REGISTER(v250, Arch_amdgpu_cdna2| VGPR | BITS_32 | 250 , "amdgpu_cdna2"); +DEF_REGISTER(v251, Arch_amdgpu_cdna2| VGPR | BITS_32 | 251 , "amdgpu_cdna2"); +DEF_REGISTER(v252, Arch_amdgpu_cdna2| VGPR | BITS_32 | 252 , "amdgpu_cdna2"); +DEF_REGISTER(v253, Arch_amdgpu_cdna2| VGPR | BITS_32 | 253 , "amdgpu_cdna2"); +DEF_REGISTER(v254, Arch_amdgpu_cdna2| VGPR | BITS_32 | 254 , "amdgpu_cdna2"); +DEF_REGISTER(v255, Arch_amdgpu_cdna2| VGPR | BITS_32 | 255 , "amdgpu_cdna2"); +DEF_REGISTER(acc0, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(acc1, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(acc2, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(acc3, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(acc4, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(acc5, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(acc6, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(acc7, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(acc8, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(acc9, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(acc10, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(acc11, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(acc12, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(acc13, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(acc14, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(acc15, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(acc16, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(acc17, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(acc18, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(acc19, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(acc20, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(acc21, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(acc22, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(acc23, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(acc24, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(acc25, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(acc26, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(acc27, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(acc28, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(acc29, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(acc30, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(acc31, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(acc32, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(acc33, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(acc34, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(acc35, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(acc36, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(acc37, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(acc38, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(acc39, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(acc40, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(acc41, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(acc42, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(acc43, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(acc44, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(acc45, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(acc46, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(acc47, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(acc48, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(acc49, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(acc50, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(acc51, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(acc52, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(acc53, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(acc54, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(acc55, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(acc56, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(acc57, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(acc58, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(acc59, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(acc60, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(acc61, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(acc62, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(acc63, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(acc64, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(acc65, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(acc66, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(acc67, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(acc68, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(acc69, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(acc70, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(acc71, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(acc72, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(acc73, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(acc74, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(acc75, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(acc76, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(acc77, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(acc78, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(acc79, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(acc80, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(acc81, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(acc82, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(acc83, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(acc84, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(acc85, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(acc86, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(acc87, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(acc88, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(acc89, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(acc90, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(acc91, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(acc92, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(acc93, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(acc94, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(acc95, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(acc96, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(acc97, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(acc98, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(acc99, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(acc100, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(acc101, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(acc102, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 102 , "amdgpu_cdna2"); +DEF_REGISTER(acc103, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 103 , "amdgpu_cdna2"); +DEF_REGISTER(acc104, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 104 , "amdgpu_cdna2"); +DEF_REGISTER(acc105, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 105 , "amdgpu_cdna2"); +DEF_REGISTER(acc106, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 106 , "amdgpu_cdna2"); +DEF_REGISTER(acc107, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 107 , "amdgpu_cdna2"); +DEF_REGISTER(acc108, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 108 , "amdgpu_cdna2"); +DEF_REGISTER(acc109, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 109 , "amdgpu_cdna2"); +DEF_REGISTER(acc110, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 110 , "amdgpu_cdna2"); +DEF_REGISTER(acc111, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 111 , "amdgpu_cdna2"); +DEF_REGISTER(acc112, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 112 , "amdgpu_cdna2"); +DEF_REGISTER(acc113, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 113 , "amdgpu_cdna2"); +DEF_REGISTER(acc114, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 114 , "amdgpu_cdna2"); +DEF_REGISTER(acc115, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 115 , "amdgpu_cdna2"); +DEF_REGISTER(acc116, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 116 , "amdgpu_cdna2"); +DEF_REGISTER(acc117, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 117 , "amdgpu_cdna2"); +DEF_REGISTER(acc118, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 118 , "amdgpu_cdna2"); +DEF_REGISTER(acc119, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 119 , "amdgpu_cdna2"); +DEF_REGISTER(acc120, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 120 , "amdgpu_cdna2"); +DEF_REGISTER(acc121, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 121 , "amdgpu_cdna2"); +DEF_REGISTER(acc122, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 122 , "amdgpu_cdna2"); +DEF_REGISTER(acc123, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 123 , "amdgpu_cdna2"); +DEF_REGISTER(acc124, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 124 , "amdgpu_cdna2"); +DEF_REGISTER(acc125, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 125 , "amdgpu_cdna2"); +DEF_REGISTER(acc126, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 126 , "amdgpu_cdna2"); +DEF_REGISTER(acc127, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 127 , "amdgpu_cdna2"); +DEF_REGISTER(acc128, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 128 , "amdgpu_cdna2"); +DEF_REGISTER(acc129, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 129 , "amdgpu_cdna2"); +DEF_REGISTER(acc130, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 130 , "amdgpu_cdna2"); +DEF_REGISTER(acc131, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 131 , "amdgpu_cdna2"); +DEF_REGISTER(acc132, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 132 , "amdgpu_cdna2"); +DEF_REGISTER(acc133, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 133 , "amdgpu_cdna2"); +DEF_REGISTER(acc134, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 134 , "amdgpu_cdna2"); +DEF_REGISTER(acc135, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 135 , "amdgpu_cdna2"); +DEF_REGISTER(acc136, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 136 , "amdgpu_cdna2"); +DEF_REGISTER(acc137, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 137 , "amdgpu_cdna2"); +DEF_REGISTER(acc138, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 138 , "amdgpu_cdna2"); +DEF_REGISTER(acc139, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 139 , "amdgpu_cdna2"); +DEF_REGISTER(acc140, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 140 , "amdgpu_cdna2"); +DEF_REGISTER(acc141, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 141 , "amdgpu_cdna2"); +DEF_REGISTER(acc142, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 142 , "amdgpu_cdna2"); +DEF_REGISTER(acc143, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 143 , "amdgpu_cdna2"); +DEF_REGISTER(acc144, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 144 , "amdgpu_cdna2"); +DEF_REGISTER(acc145, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 145 , "amdgpu_cdna2"); +DEF_REGISTER(acc146, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 146 , "amdgpu_cdna2"); +DEF_REGISTER(acc147, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 147 , "amdgpu_cdna2"); +DEF_REGISTER(acc148, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 148 , "amdgpu_cdna2"); +DEF_REGISTER(acc149, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 149 , "amdgpu_cdna2"); +DEF_REGISTER(acc150, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 150 , "amdgpu_cdna2"); +DEF_REGISTER(acc151, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 151 , "amdgpu_cdna2"); +DEF_REGISTER(acc152, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 152 , "amdgpu_cdna2"); +DEF_REGISTER(acc153, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 153 , "amdgpu_cdna2"); +DEF_REGISTER(acc154, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 154 , "amdgpu_cdna2"); +DEF_REGISTER(acc155, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 155 , "amdgpu_cdna2"); +DEF_REGISTER(acc156, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 156 , "amdgpu_cdna2"); +DEF_REGISTER(acc157, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 157 , "amdgpu_cdna2"); +DEF_REGISTER(acc158, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 158 , "amdgpu_cdna2"); +DEF_REGISTER(acc159, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 159 , "amdgpu_cdna2"); +DEF_REGISTER(acc160, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 160 , "amdgpu_cdna2"); +DEF_REGISTER(acc161, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 161 , "amdgpu_cdna2"); +DEF_REGISTER(acc162, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 162 , "amdgpu_cdna2"); +DEF_REGISTER(acc163, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 163 , "amdgpu_cdna2"); +DEF_REGISTER(acc164, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 164 , "amdgpu_cdna2"); +DEF_REGISTER(acc165, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 165 , "amdgpu_cdna2"); +DEF_REGISTER(acc166, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 166 , "amdgpu_cdna2"); +DEF_REGISTER(acc167, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 167 , "amdgpu_cdna2"); +DEF_REGISTER(acc168, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 168 , "amdgpu_cdna2"); +DEF_REGISTER(acc169, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 169 , "amdgpu_cdna2"); +DEF_REGISTER(acc170, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 170 , "amdgpu_cdna2"); +DEF_REGISTER(acc171, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 171 , "amdgpu_cdna2"); +DEF_REGISTER(acc172, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 172 , "amdgpu_cdna2"); +DEF_REGISTER(acc173, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 173 , "amdgpu_cdna2"); +DEF_REGISTER(acc174, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 174 , "amdgpu_cdna2"); +DEF_REGISTER(acc175, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 175 , "amdgpu_cdna2"); +DEF_REGISTER(acc176, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 176 , "amdgpu_cdna2"); +DEF_REGISTER(acc177, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 177 , "amdgpu_cdna2"); +DEF_REGISTER(acc178, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 178 , "amdgpu_cdna2"); +DEF_REGISTER(acc179, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 179 , "amdgpu_cdna2"); +DEF_REGISTER(acc180, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 180 , "amdgpu_cdna2"); +DEF_REGISTER(acc181, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 181 , "amdgpu_cdna2"); +DEF_REGISTER(acc182, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 182 , "amdgpu_cdna2"); +DEF_REGISTER(acc183, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 183 , "amdgpu_cdna2"); +DEF_REGISTER(acc184, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 184 , "amdgpu_cdna2"); +DEF_REGISTER(acc185, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 185 , "amdgpu_cdna2"); +DEF_REGISTER(acc186, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 186 , "amdgpu_cdna2"); +DEF_REGISTER(acc187, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 187 , "amdgpu_cdna2"); +DEF_REGISTER(acc188, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 188 , "amdgpu_cdna2"); +DEF_REGISTER(acc189, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 189 , "amdgpu_cdna2"); +DEF_REGISTER(acc190, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 190 , "amdgpu_cdna2"); +DEF_REGISTER(acc191, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 191 , "amdgpu_cdna2"); +DEF_REGISTER(acc192, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 192 , "amdgpu_cdna2"); +DEF_REGISTER(acc193, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 193 , "amdgpu_cdna2"); +DEF_REGISTER(acc194, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 194 , "amdgpu_cdna2"); +DEF_REGISTER(acc195, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 195 , "amdgpu_cdna2"); +DEF_REGISTER(acc196, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 196 , "amdgpu_cdna2"); +DEF_REGISTER(acc197, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 197 , "amdgpu_cdna2"); +DEF_REGISTER(acc198, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 198 , "amdgpu_cdna2"); +DEF_REGISTER(acc199, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 199 , "amdgpu_cdna2"); +DEF_REGISTER(acc200, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 200 , "amdgpu_cdna2"); +DEF_REGISTER(acc201, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 201 , "amdgpu_cdna2"); +DEF_REGISTER(acc202, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 202 , "amdgpu_cdna2"); +DEF_REGISTER(acc203, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 203 , "amdgpu_cdna2"); +DEF_REGISTER(acc204, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 204 , "amdgpu_cdna2"); +DEF_REGISTER(acc205, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 205 , "amdgpu_cdna2"); +DEF_REGISTER(acc206, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 206 , "amdgpu_cdna2"); +DEF_REGISTER(acc207, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 207 , "amdgpu_cdna2"); +DEF_REGISTER(acc208, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 208 , "amdgpu_cdna2"); +DEF_REGISTER(acc209, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 209 , "amdgpu_cdna2"); +DEF_REGISTER(acc210, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 210 , "amdgpu_cdna2"); +DEF_REGISTER(acc211, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 211 , "amdgpu_cdna2"); +DEF_REGISTER(acc212, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 212 , "amdgpu_cdna2"); +DEF_REGISTER(acc213, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 213 , "amdgpu_cdna2"); +DEF_REGISTER(acc214, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 214 , "amdgpu_cdna2"); +DEF_REGISTER(acc215, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 215 , "amdgpu_cdna2"); +DEF_REGISTER(acc216, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 216 , "amdgpu_cdna2"); +DEF_REGISTER(acc217, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 217 , "amdgpu_cdna2"); +DEF_REGISTER(acc218, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 218 , "amdgpu_cdna2"); +DEF_REGISTER(acc219, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 219 , "amdgpu_cdna2"); +DEF_REGISTER(acc220, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 220 , "amdgpu_cdna2"); +DEF_REGISTER(acc221, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 221 , "amdgpu_cdna2"); +DEF_REGISTER(acc222, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 222 , "amdgpu_cdna2"); +DEF_REGISTER(acc223, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 223 , "amdgpu_cdna2"); +DEF_REGISTER(acc224, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 224 , "amdgpu_cdna2"); +DEF_REGISTER(acc225, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 225 , "amdgpu_cdna2"); +DEF_REGISTER(acc226, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 226 , "amdgpu_cdna2"); +DEF_REGISTER(acc227, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 227 , "amdgpu_cdna2"); +DEF_REGISTER(acc228, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 228 , "amdgpu_cdna2"); +DEF_REGISTER(acc229, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 229 , "amdgpu_cdna2"); +DEF_REGISTER(acc230, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 230 , "amdgpu_cdna2"); +DEF_REGISTER(acc231, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 231 , "amdgpu_cdna2"); +DEF_REGISTER(acc232, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 232 , "amdgpu_cdna2"); +DEF_REGISTER(acc233, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 233 , "amdgpu_cdna2"); +DEF_REGISTER(acc234, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 234 , "amdgpu_cdna2"); +DEF_REGISTER(acc235, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 235 , "amdgpu_cdna2"); +DEF_REGISTER(acc236, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 236 , "amdgpu_cdna2"); +DEF_REGISTER(acc237, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 237 , "amdgpu_cdna2"); +DEF_REGISTER(acc238, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 238 , "amdgpu_cdna2"); +DEF_REGISTER(acc239, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 239 , "amdgpu_cdna2"); +DEF_REGISTER(acc240, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 240 , "amdgpu_cdna2"); +DEF_REGISTER(acc241, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 241 , "amdgpu_cdna2"); +DEF_REGISTER(acc242, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 242 , "amdgpu_cdna2"); +DEF_REGISTER(acc243, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 243 , "amdgpu_cdna2"); +DEF_REGISTER(acc244, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 244 , "amdgpu_cdna2"); +DEF_REGISTER(acc245, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 245 , "amdgpu_cdna2"); +DEF_REGISTER(acc246, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 246 , "amdgpu_cdna2"); +DEF_REGISTER(acc247, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 247 , "amdgpu_cdna2"); +DEF_REGISTER(acc248, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 248 , "amdgpu_cdna2"); +DEF_REGISTER(acc249, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 249 , "amdgpu_cdna2"); +DEF_REGISTER(acc250, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 250 , "amdgpu_cdna2"); +DEF_REGISTER(acc251, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 251 , "amdgpu_cdna2"); +DEF_REGISTER(acc252, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 252 , "amdgpu_cdna2"); +DEF_REGISTER(acc253, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 253 , "amdgpu_cdna2"); +DEF_REGISTER(acc254, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 254 , "amdgpu_cdna2"); +DEF_REGISTER(acc255, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 255 , "amdgpu_cdna2"); +#endif diff --git a/common/h/amdgpu_cdna2_op_table.h b/common/h/amdgpu_cdna2_op_table.h new file mode 100644 index 0000000000..90eb1cb315 --- /dev/null +++ b/common/h/amdgpu_cdna2_op_table.h @@ -0,0 +1,1135 @@ +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_AND, +amdgpu_cdna2_op_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_DEC, +amdgpu_cdna2_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_INC, +amdgpu_cdna2_op_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_MAX_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_MIN_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_OR, +amdgpu_cdna2_op_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SUB, +amdgpu_cdna2_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP, +amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_XOR, +amdgpu_cdna2_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna2_op_BUFFER_INVL2, +amdgpu_cdna2_op_BUFFER_LOAD_DWORD, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX2, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX3, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX4, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16, +amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_SSHORT, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_USHORT, +amdgpu_cdna2_op_BUFFER_STORE_BYTE, +amdgpu_cdna2_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_STORE_DWORD, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX2, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX3, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX4, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XY, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna2_op_BUFFER_STORE_LDS_DWORD, +amdgpu_cdna2_op_BUFFER_STORE_SHORT, +amdgpu_cdna2_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_BUFFER_WBINVL1, +amdgpu_cdna2_op_BUFFER_WBINVL1_VOL, +amdgpu_cdna2_op_BUFFER_WBL2, +amdgpu_cdna2_op_DS_ADD_F32, +amdgpu_cdna2_op_DS_ADD_F64, +amdgpu_cdna2_op_DS_ADD_RTN_F32, +amdgpu_cdna2_op_DS_ADD_RTN_F64, +amdgpu_cdna2_op_DS_ADD_RTN_U32, +amdgpu_cdna2_op_DS_ADD_RTN_U64, +amdgpu_cdna2_op_DS_ADD_U32, +amdgpu_cdna2_op_DS_ADD_U64, +amdgpu_cdna2_op_DS_AND_B32, +amdgpu_cdna2_op_DS_AND_B64, +amdgpu_cdna2_op_DS_AND_RTN_B32, +amdgpu_cdna2_op_DS_AND_RTN_B64, +amdgpu_cdna2_op_DS_APPEND, +amdgpu_cdna2_op_DS_BPERMUTE_B32, +amdgpu_cdna2_op_DS_CMPST_B32, +amdgpu_cdna2_op_DS_CMPST_B64, +amdgpu_cdna2_op_DS_CMPST_F32, +amdgpu_cdna2_op_DS_CMPST_F64, +amdgpu_cdna2_op_DS_CMPST_RTN_B32, +amdgpu_cdna2_op_DS_CMPST_RTN_B64, +amdgpu_cdna2_op_DS_CMPST_RTN_F32, +amdgpu_cdna2_op_DS_CMPST_RTN_F64, +amdgpu_cdna2_op_DS_CONDXCHG32_RTN_B64, +amdgpu_cdna2_op_DS_CONSUME, +amdgpu_cdna2_op_DS_DEC_RTN_U32, +amdgpu_cdna2_op_DS_DEC_RTN_U64, +amdgpu_cdna2_op_DS_DEC_U32, +amdgpu_cdna2_op_DS_DEC_U64, +amdgpu_cdna2_op_DS_GWS_BARRIER, +amdgpu_cdna2_op_DS_GWS_INIT, +amdgpu_cdna2_op_DS_GWS_SEMA_BR, +amdgpu_cdna2_op_DS_GWS_SEMA_P, +amdgpu_cdna2_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_cdna2_op_DS_GWS_SEMA_V, +amdgpu_cdna2_op_DS_INC_RTN_U32, +amdgpu_cdna2_op_DS_INC_RTN_U64, +amdgpu_cdna2_op_DS_INC_U32, +amdgpu_cdna2_op_DS_INC_U64, +amdgpu_cdna2_op_DS_MAX_F32, +amdgpu_cdna2_op_DS_MAX_F64, +amdgpu_cdna2_op_DS_MAX_I32, +amdgpu_cdna2_op_DS_MAX_I64, +amdgpu_cdna2_op_DS_MAX_RTN_F32, +amdgpu_cdna2_op_DS_MAX_RTN_F64, +amdgpu_cdna2_op_DS_MAX_RTN_I32, +amdgpu_cdna2_op_DS_MAX_RTN_I64, +amdgpu_cdna2_op_DS_MAX_RTN_U32, +amdgpu_cdna2_op_DS_MAX_RTN_U64, +amdgpu_cdna2_op_DS_MAX_U32, +amdgpu_cdna2_op_DS_MAX_U64, +amdgpu_cdna2_op_DS_MIN_F32, +amdgpu_cdna2_op_DS_MIN_F64, +amdgpu_cdna2_op_DS_MIN_I32, +amdgpu_cdna2_op_DS_MIN_I64, +amdgpu_cdna2_op_DS_MIN_RTN_F32, +amdgpu_cdna2_op_DS_MIN_RTN_F64, +amdgpu_cdna2_op_DS_MIN_RTN_I32, +amdgpu_cdna2_op_DS_MIN_RTN_I64, +amdgpu_cdna2_op_DS_MIN_RTN_U32, +amdgpu_cdna2_op_DS_MIN_RTN_U64, +amdgpu_cdna2_op_DS_MIN_U32, +amdgpu_cdna2_op_DS_MIN_U64, +amdgpu_cdna2_op_DS_MSKOR_B32, +amdgpu_cdna2_op_DS_MSKOR_B64, +amdgpu_cdna2_op_DS_MSKOR_RTN_B32, +amdgpu_cdna2_op_DS_MSKOR_RTN_B64, +amdgpu_cdna2_op_DS_NOP, +amdgpu_cdna2_op_DS_OR_B32, +amdgpu_cdna2_op_DS_OR_B64, +amdgpu_cdna2_op_DS_OR_RTN_B32, +amdgpu_cdna2_op_DS_OR_RTN_B64, +amdgpu_cdna2_op_DS_PERMUTE_B32, +amdgpu_cdna2_op_DS_READ2ST64_B32, +amdgpu_cdna2_op_DS_READ2ST64_B64, +amdgpu_cdna2_op_DS_READ2_B32, +amdgpu_cdna2_op_DS_READ2_B64, +amdgpu_cdna2_op_DS_READ_ADDTID_B32, +amdgpu_cdna2_op_DS_READ_B128, +amdgpu_cdna2_op_DS_READ_B32, +amdgpu_cdna2_op_DS_READ_B64, +amdgpu_cdna2_op_DS_READ_B96, +amdgpu_cdna2_op_DS_READ_I16, +amdgpu_cdna2_op_DS_READ_I8, +amdgpu_cdna2_op_DS_READ_I8_D16, +amdgpu_cdna2_op_DS_READ_I8_D16_HI, +amdgpu_cdna2_op_DS_READ_U16, +amdgpu_cdna2_op_DS_READ_U16_D16, +amdgpu_cdna2_op_DS_READ_U16_D16_HI, +amdgpu_cdna2_op_DS_READ_U8, +amdgpu_cdna2_op_DS_READ_U8_D16, +amdgpu_cdna2_op_DS_READ_U8_D16_HI, +amdgpu_cdna2_op_DS_RSUB_RTN_U32, +amdgpu_cdna2_op_DS_RSUB_RTN_U64, +amdgpu_cdna2_op_DS_RSUB_U32, +amdgpu_cdna2_op_DS_RSUB_U64, +amdgpu_cdna2_op_DS_SUB_RTN_U32, +amdgpu_cdna2_op_DS_SUB_RTN_U64, +amdgpu_cdna2_op_DS_SUB_U32, +amdgpu_cdna2_op_DS_SUB_U64, +amdgpu_cdna2_op_DS_SWIZZLE_B32, +amdgpu_cdna2_op_DS_WRAP_RTN_B32, +amdgpu_cdna2_op_DS_WRITE2ST64_B32, +amdgpu_cdna2_op_DS_WRITE2ST64_B64, +amdgpu_cdna2_op_DS_WRITE2_B32, +amdgpu_cdna2_op_DS_WRITE2_B64, +amdgpu_cdna2_op_DS_WRITE_ADDTID_B32, +amdgpu_cdna2_op_DS_WRITE_B128, +amdgpu_cdna2_op_DS_WRITE_B16, +amdgpu_cdna2_op_DS_WRITE_B16_D16_HI, +amdgpu_cdna2_op_DS_WRITE_B32, +amdgpu_cdna2_op_DS_WRITE_B64, +amdgpu_cdna2_op_DS_WRITE_B8, +amdgpu_cdna2_op_DS_WRITE_B8_D16_HI, +amdgpu_cdna2_op_DS_WRITE_B96, +amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_cdna2_op_DS_WRXCHG2_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG2_RTN_B64, +amdgpu_cdna2_op_DS_WRXCHG_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG_RTN_B64, +amdgpu_cdna2_op_DS_XOR_B32, +amdgpu_cdna2_op_DS_XOR_B64, +amdgpu_cdna2_op_DS_XOR_RTN_B32, +amdgpu_cdna2_op_DS_XOR_RTN_B64, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_AND, +amdgpu_cdna2_op_FLAT_ATOMIC_AND_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_DEC, +amdgpu_cdna2_op_FLAT_ATOMIC_DEC_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_INC, +amdgpu_cdna2_op_FLAT_ATOMIC_INC_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_MAX_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_MIN_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_OR, +amdgpu_cdna2_op_FLAT_ATOMIC_OR_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SMAX, +amdgpu_cdna2_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SMIN, +amdgpu_cdna2_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SUB, +amdgpu_cdna2_op_FLAT_ATOMIC_SUB_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SWAP, +amdgpu_cdna2_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_UMAX, +amdgpu_cdna2_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_UMIN, +amdgpu_cdna2_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_XOR, +amdgpu_cdna2_op_FLAT_ATOMIC_XOR_X2, +amdgpu_cdna2_op_FLAT_LOAD_DWORD, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX2, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX3, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX4, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16, +amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_SSHORT, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_USHORT, +amdgpu_cdna2_op_FLAT_STORE_BYTE, +amdgpu_cdna2_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_FLAT_STORE_DWORD, +amdgpu_cdna2_op_FLAT_STORE_DWORDX2, +amdgpu_cdna2_op_FLAT_STORE_DWORDX3, +amdgpu_cdna2_op_FLAT_STORE_DWORDX4, +amdgpu_cdna2_op_FLAT_STORE_SHORT, +amdgpu_cdna2_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_AND, +amdgpu_cdna2_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC, +amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_INC, +amdgpu_cdna2_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_MAX_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_MIN_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_OR, +amdgpu_cdna2_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR, +amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORD, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX2, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX3, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX4, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_SSHORT, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_USHORT, +amdgpu_cdna2_op_GLOBAL_STORE_BYTE, +amdgpu_cdna2_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_STORE_DWORD, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX2, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX3, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX4, +amdgpu_cdna2_op_GLOBAL_STORE_SHORT, +amdgpu_cdna2_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_IMAGE_ATOMIC_ADD, +amdgpu_cdna2_op_IMAGE_ATOMIC_AND, +amdgpu_cdna2_op_IMAGE_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_IMAGE_ATOMIC_DEC, +amdgpu_cdna2_op_IMAGE_ATOMIC_INC, +amdgpu_cdna2_op_IMAGE_ATOMIC_OR, +amdgpu_cdna2_op_IMAGE_ATOMIC_SMAX, +amdgpu_cdna2_op_IMAGE_ATOMIC_SMIN, +amdgpu_cdna2_op_IMAGE_ATOMIC_SUB, +amdgpu_cdna2_op_IMAGE_ATOMIC_SWAP, +amdgpu_cdna2_op_IMAGE_ATOMIC_UMAX, +amdgpu_cdna2_op_IMAGE_ATOMIC_UMIN, +amdgpu_cdna2_op_IMAGE_ATOMIC_XOR, +amdgpu_cdna2_op_IMAGE_GET_RESINFO, +amdgpu_cdna2_op_IMAGE_LOAD, +amdgpu_cdna2_op_IMAGE_LOAD_MIP, +amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK, +amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK_SGN, +amdgpu_cdna2_op_IMAGE_LOAD_PCK, +amdgpu_cdna2_op_IMAGE_LOAD_PCK_SGN, +amdgpu_cdna2_op_IMAGE_SAMPLE, +amdgpu_cdna2_op_IMAGE_STORE, +amdgpu_cdna2_op_IMAGE_STORE_MIP, +amdgpu_cdna2_op_IMAGE_STORE_MIP_PCK, +amdgpu_cdna2_op_IMAGE_STORE_PCK, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORD, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX3, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_SSHORT, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_USHORT, +amdgpu_cdna2_op_SCRATCH_STORE_BYTE, +amdgpu_cdna2_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_STORE_DWORD, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX2, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX3, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX4, +amdgpu_cdna2_op_SCRATCH_STORE_SHORT, +amdgpu_cdna2_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_S_ABSDIFF_I32, +amdgpu_cdna2_op_S_ABS_I32, +amdgpu_cdna2_op_S_ADDC_U32, +amdgpu_cdna2_op_S_ADDK_I32, +amdgpu_cdna2_op_S_ADD_I32, +amdgpu_cdna2_op_S_ADD_U32, +amdgpu_cdna2_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ANDN1_WREXEC_B64, +amdgpu_cdna2_op_S_ANDN2_B32, +amdgpu_cdna2_op_S_ANDN2_B64, +amdgpu_cdna2_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ANDN2_WREXEC_B64, +amdgpu_cdna2_op_S_AND_B32, +amdgpu_cdna2_op_S_AND_B64, +amdgpu_cdna2_op_S_AND_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ASHR_I32, +amdgpu_cdna2_op_S_ASHR_I64, +amdgpu_cdna2_op_S_ATC_PROBE, +amdgpu_cdna2_op_S_ATC_PROBE_BUFFER, +amdgpu_cdna2_op_S_ATOMIC_ADD, +amdgpu_cdna2_op_S_ATOMIC_ADD_X2, +amdgpu_cdna2_op_S_ATOMIC_AND, +amdgpu_cdna2_op_S_ATOMIC_AND_X2, +amdgpu_cdna2_op_S_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_S_ATOMIC_DEC, +amdgpu_cdna2_op_S_ATOMIC_DEC_X2, +amdgpu_cdna2_op_S_ATOMIC_INC, +amdgpu_cdna2_op_S_ATOMIC_INC_X2, +amdgpu_cdna2_op_S_ATOMIC_OR, +amdgpu_cdna2_op_S_ATOMIC_OR_X2, +amdgpu_cdna2_op_S_ATOMIC_SMAX, +amdgpu_cdna2_op_S_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_S_ATOMIC_SMIN, +amdgpu_cdna2_op_S_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_S_ATOMIC_SUB, +amdgpu_cdna2_op_S_ATOMIC_SUB_X2, +amdgpu_cdna2_op_S_ATOMIC_SWAP, +amdgpu_cdna2_op_S_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_S_ATOMIC_UMAX, +amdgpu_cdna2_op_S_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_S_ATOMIC_UMIN, +amdgpu_cdna2_op_S_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_S_ATOMIC_XOR, +amdgpu_cdna2_op_S_ATOMIC_XOR_X2, +amdgpu_cdna2_op_S_BARRIER, +amdgpu_cdna2_op_S_BCNT0_I32_B32, +amdgpu_cdna2_op_S_BCNT0_I32_B64, +amdgpu_cdna2_op_S_BCNT1_I32_B32, +amdgpu_cdna2_op_S_BCNT1_I32_B64, +amdgpu_cdna2_op_S_BFE_I32, +amdgpu_cdna2_op_S_BFE_I64, +amdgpu_cdna2_op_S_BFE_U32, +amdgpu_cdna2_op_S_BFE_U64, +amdgpu_cdna2_op_S_BFM_B32, +amdgpu_cdna2_op_S_BFM_B64, +amdgpu_cdna2_op_S_BITCMP0_B32, +amdgpu_cdna2_op_S_BITCMP0_B64, +amdgpu_cdna2_op_S_BITCMP1_B32, +amdgpu_cdna2_op_S_BITCMP1_B64, +amdgpu_cdna2_op_S_BITREPLICATE_B64_B32, +amdgpu_cdna2_op_S_BITSET0_B32, +amdgpu_cdna2_op_S_BITSET0_B64, +amdgpu_cdna2_op_S_BITSET1_B32, +amdgpu_cdna2_op_S_BITSET1_B64, +amdgpu_cdna2_op_S_BRANCH, +amdgpu_cdna2_op_S_BREV_B32, +amdgpu_cdna2_op_S_BREV_B64, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORD, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORD, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX2, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX4, +amdgpu_cdna2_op_S_CALL_B64, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_cdna2_op_S_CBRANCH_CDBGUSER, +amdgpu_cdna2_op_S_CBRANCH_EXECNZ, +amdgpu_cdna2_op_S_CBRANCH_EXECZ, +amdgpu_cdna2_op_S_CBRANCH_G_FORK, +amdgpu_cdna2_op_S_CBRANCH_I_FORK, +amdgpu_cdna2_op_S_CBRANCH_JOIN, +amdgpu_cdna2_op_S_CBRANCH_SCC0, +amdgpu_cdna2_op_S_CBRANCH_SCC1, +amdgpu_cdna2_op_S_CBRANCH_VCCNZ, +amdgpu_cdna2_op_S_CBRANCH_VCCZ, +amdgpu_cdna2_op_S_CMOVK_I32, +amdgpu_cdna2_op_S_CMOV_B32, +amdgpu_cdna2_op_S_CMOV_B64, +amdgpu_cdna2_op_S_CMPK_EQ_I32, +amdgpu_cdna2_op_S_CMPK_EQ_U32, +amdgpu_cdna2_op_S_CMPK_GE_I32, +amdgpu_cdna2_op_S_CMPK_GE_U32, +amdgpu_cdna2_op_S_CMPK_GT_I32, +amdgpu_cdna2_op_S_CMPK_GT_U32, +amdgpu_cdna2_op_S_CMPK_LE_I32, +amdgpu_cdna2_op_S_CMPK_LE_U32, +amdgpu_cdna2_op_S_CMPK_LG_I32, +amdgpu_cdna2_op_S_CMPK_LG_U32, +amdgpu_cdna2_op_S_CMPK_LT_I32, +amdgpu_cdna2_op_S_CMPK_LT_U32, +amdgpu_cdna2_op_S_CMP_EQ_I32, +amdgpu_cdna2_op_S_CMP_EQ_U32, +amdgpu_cdna2_op_S_CMP_EQ_U64, +amdgpu_cdna2_op_S_CMP_GE_I32, +amdgpu_cdna2_op_S_CMP_GE_U32, +amdgpu_cdna2_op_S_CMP_GT_I32, +amdgpu_cdna2_op_S_CMP_GT_U32, +amdgpu_cdna2_op_S_CMP_LE_I32, +amdgpu_cdna2_op_S_CMP_LE_U32, +amdgpu_cdna2_op_S_CMP_LG_I32, +amdgpu_cdna2_op_S_CMP_LG_U32, +amdgpu_cdna2_op_S_CMP_LG_U64, +amdgpu_cdna2_op_S_CMP_LT_I32, +amdgpu_cdna2_op_S_CMP_LT_U32, +amdgpu_cdna2_op_S_CSELECT_B32, +amdgpu_cdna2_op_S_CSELECT_B64, +amdgpu_cdna2_op_S_DCACHE_DISCARD, +amdgpu_cdna2_op_S_DCACHE_DISCARD_X2, +amdgpu_cdna2_op_S_DCACHE_INV, +amdgpu_cdna2_op_S_DCACHE_INV_VOL, +amdgpu_cdna2_op_S_DCACHE_WB, +amdgpu_cdna2_op_S_DCACHE_WB_VOL, +amdgpu_cdna2_op_S_DECPERFLEVEL, +amdgpu_cdna2_op_S_ENDPGM, +amdgpu_cdna2_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_cdna2_op_S_ENDPGM_SAVED, +amdgpu_cdna2_op_S_FF0_I32_B32, +amdgpu_cdna2_op_S_FF0_I32_B64, +amdgpu_cdna2_op_S_FF1_I32_B32, +amdgpu_cdna2_op_S_FF1_I32_B64, +amdgpu_cdna2_op_S_FLBIT_I32, +amdgpu_cdna2_op_S_FLBIT_I32_B32, +amdgpu_cdna2_op_S_FLBIT_I32_B64, +amdgpu_cdna2_op_S_FLBIT_I32_I64, +amdgpu_cdna2_op_S_GETPC_B64, +amdgpu_cdna2_op_S_GETREG_B32, +amdgpu_cdna2_op_S_ICACHE_INV, +amdgpu_cdna2_op_S_INCPERFLEVEL, +amdgpu_cdna2_op_S_LOAD_DWORD, +amdgpu_cdna2_op_S_LOAD_DWORDX16, +amdgpu_cdna2_op_S_LOAD_DWORDX2, +amdgpu_cdna2_op_S_LOAD_DWORDX4, +amdgpu_cdna2_op_S_LOAD_DWORDX8, +amdgpu_cdna2_op_S_LSHL1_ADD_U32, +amdgpu_cdna2_op_S_LSHL2_ADD_U32, +amdgpu_cdna2_op_S_LSHL3_ADD_U32, +amdgpu_cdna2_op_S_LSHL4_ADD_U32, +amdgpu_cdna2_op_S_LSHL_B32, +amdgpu_cdna2_op_S_LSHL_B64, +amdgpu_cdna2_op_S_LSHR_B32, +amdgpu_cdna2_op_S_LSHR_B64, +amdgpu_cdna2_op_S_MAX_I32, +amdgpu_cdna2_op_S_MAX_U32, +amdgpu_cdna2_op_S_MEMREALTIME, +amdgpu_cdna2_op_S_MEMTIME, +amdgpu_cdna2_op_S_MIN_I32, +amdgpu_cdna2_op_S_MIN_U32, +amdgpu_cdna2_op_S_MOVK_I32, +amdgpu_cdna2_op_S_MOVRELD_B32, +amdgpu_cdna2_op_S_MOVRELD_B64, +amdgpu_cdna2_op_S_MOVRELS_B32, +amdgpu_cdna2_op_S_MOVRELS_B64, +amdgpu_cdna2_op_S_MOV_B32, +amdgpu_cdna2_op_S_MOV_B64, +amdgpu_cdna2_op_S_MULK_I32, +amdgpu_cdna2_op_S_MUL_HI_I32, +amdgpu_cdna2_op_S_MUL_HI_U32, +amdgpu_cdna2_op_S_MUL_I32, +amdgpu_cdna2_op_S_NAND_B32, +amdgpu_cdna2_op_S_NAND_B64, +amdgpu_cdna2_op_S_NAND_SAVEEXEC_B64, +amdgpu_cdna2_op_S_NOP, +amdgpu_cdna2_op_S_NOR_B32, +amdgpu_cdna2_op_S_NOR_B64, +amdgpu_cdna2_op_S_NOR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_NOT_B32, +amdgpu_cdna2_op_S_NOT_B64, +amdgpu_cdna2_op_S_ORN1_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ORN2_B32, +amdgpu_cdna2_op_S_ORN2_B64, +amdgpu_cdna2_op_S_ORN2_SAVEEXEC_B64, +amdgpu_cdna2_op_S_OR_B32, +amdgpu_cdna2_op_S_OR_B64, +amdgpu_cdna2_op_S_OR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_PACK_HH_B32_B16, +amdgpu_cdna2_op_S_PACK_LH_B32_B16, +amdgpu_cdna2_op_S_PACK_LL_B32_B16, +amdgpu_cdna2_op_S_QUADMASK_B32, +amdgpu_cdna2_op_S_QUADMASK_B64, +amdgpu_cdna2_op_S_RFE_B64, +amdgpu_cdna2_op_S_RFE_RESTORE_B64, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORD, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORD, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_cdna2_op_S_SENDMSG, +amdgpu_cdna2_op_S_SENDMSGHALT, +amdgpu_cdna2_op_S_SETHALT, +amdgpu_cdna2_op_S_SETKILL, +amdgpu_cdna2_op_S_SETPC_B64, +amdgpu_cdna2_op_S_SETPRIO, +amdgpu_cdna2_op_S_SETREG_B32, +amdgpu_cdna2_op_S_SETREG_IMM32_B32, +amdgpu_cdna2_op_S_SETVSKIP, +amdgpu_cdna2_op_S_SET_GPR_IDX_IDX, +amdgpu_cdna2_op_S_SET_GPR_IDX_MODE, +amdgpu_cdna2_op_S_SET_GPR_IDX_OFF, +amdgpu_cdna2_op_S_SET_GPR_IDX_ON, +amdgpu_cdna2_op_S_SEXT_I32_I16, +amdgpu_cdna2_op_S_SEXT_I32_I8, +amdgpu_cdna2_op_S_SLEEP, +amdgpu_cdna2_op_S_STORE_DWORD, +amdgpu_cdna2_op_S_STORE_DWORDX2, +amdgpu_cdna2_op_S_STORE_DWORDX4, +amdgpu_cdna2_op_S_SUBB_U32, +amdgpu_cdna2_op_S_SUB_I32, +amdgpu_cdna2_op_S_SUB_U32, +amdgpu_cdna2_op_S_SWAPPC_B64, +amdgpu_cdna2_op_S_TRAP, +amdgpu_cdna2_op_S_TTRACEDATA, +amdgpu_cdna2_op_S_WAITCNT, +amdgpu_cdna2_op_S_WAKEUP, +amdgpu_cdna2_op_S_WQM_B32, +amdgpu_cdna2_op_S_WQM_B64, +amdgpu_cdna2_op_S_XNOR_B32, +amdgpu_cdna2_op_S_XNOR_B64, +amdgpu_cdna2_op_S_XNOR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_XOR_B32, +amdgpu_cdna2_op_S_XOR_B64, +amdgpu_cdna2_op_S_XOR_SAVEEXEC_B64, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_X, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna2_op_V_ACCVGPR_MOV_B32, +amdgpu_cdna2_op_V_ACCVGPR_READ, +amdgpu_cdna2_op_V_ACCVGPR_WRITE, +amdgpu_cdna2_op_V_ADD3_U32, +amdgpu_cdna2_op_V_ADDC_CO_U32, +amdgpu_cdna2_op_V_ADD_CO_U32, +amdgpu_cdna2_op_V_ADD_F16, +amdgpu_cdna2_op_V_ADD_F32, +amdgpu_cdna2_op_V_ADD_F64, +amdgpu_cdna2_op_V_ADD_I16, +amdgpu_cdna2_op_V_ADD_I32, +amdgpu_cdna2_op_V_ADD_LSHL_U32, +amdgpu_cdna2_op_V_ADD_U16, +amdgpu_cdna2_op_V_ADD_U32, +amdgpu_cdna2_op_V_ALIGNBIT_B32, +amdgpu_cdna2_op_V_ALIGNBYTE_B32, +amdgpu_cdna2_op_V_AND_B32, +amdgpu_cdna2_op_V_AND_OR_B32, +amdgpu_cdna2_op_V_ASHRREV_I16, +amdgpu_cdna2_op_V_ASHRREV_I32, +amdgpu_cdna2_op_V_ASHRREV_I64, +amdgpu_cdna2_op_V_BCNT_U32_B32, +amdgpu_cdna2_op_V_BFE_I32, +amdgpu_cdna2_op_V_BFE_U32, +amdgpu_cdna2_op_V_BFI_B32, +amdgpu_cdna2_op_V_BFM_B32, +amdgpu_cdna2_op_V_BFREV_B32, +amdgpu_cdna2_op_V_CEIL_F16, +amdgpu_cdna2_op_V_CEIL_F32, +amdgpu_cdna2_op_V_CEIL_F64, +amdgpu_cdna2_op_V_CLREXCP, +amdgpu_cdna2_op_V_CMPX_CLASS_F16, +amdgpu_cdna2_op_V_CMPX_CLASS_F32, +amdgpu_cdna2_op_V_CMPX_CLASS_F64, +amdgpu_cdna2_op_V_CMPX_EQ_F16, +amdgpu_cdna2_op_V_CMPX_EQ_F32, +amdgpu_cdna2_op_V_CMPX_EQ_F64, +amdgpu_cdna2_op_V_CMPX_EQ_I16, +amdgpu_cdna2_op_V_CMPX_EQ_I32, +amdgpu_cdna2_op_V_CMPX_EQ_I64, +amdgpu_cdna2_op_V_CMPX_EQ_U16, +amdgpu_cdna2_op_V_CMPX_EQ_U32, +amdgpu_cdna2_op_V_CMPX_EQ_U64, +amdgpu_cdna2_op_V_CMPX_F_F16, +amdgpu_cdna2_op_V_CMPX_F_F32, +amdgpu_cdna2_op_V_CMPX_F_F64, +amdgpu_cdna2_op_V_CMPX_F_I16, +amdgpu_cdna2_op_V_CMPX_F_I32, +amdgpu_cdna2_op_V_CMPX_F_I64, +amdgpu_cdna2_op_V_CMPX_F_U16, +amdgpu_cdna2_op_V_CMPX_F_U32, +amdgpu_cdna2_op_V_CMPX_F_U64, +amdgpu_cdna2_op_V_CMPX_GE_F16, +amdgpu_cdna2_op_V_CMPX_GE_F32, +amdgpu_cdna2_op_V_CMPX_GE_F64, +amdgpu_cdna2_op_V_CMPX_GE_I16, +amdgpu_cdna2_op_V_CMPX_GE_I32, +amdgpu_cdna2_op_V_CMPX_GE_I64, +amdgpu_cdna2_op_V_CMPX_GE_U16, +amdgpu_cdna2_op_V_CMPX_GE_U32, +amdgpu_cdna2_op_V_CMPX_GE_U64, +amdgpu_cdna2_op_V_CMPX_GT_F16, +amdgpu_cdna2_op_V_CMPX_GT_F32, +amdgpu_cdna2_op_V_CMPX_GT_F64, +amdgpu_cdna2_op_V_CMPX_GT_I16, +amdgpu_cdna2_op_V_CMPX_GT_I32, +amdgpu_cdna2_op_V_CMPX_GT_I64, +amdgpu_cdna2_op_V_CMPX_GT_U16, +amdgpu_cdna2_op_V_CMPX_GT_U32, +amdgpu_cdna2_op_V_CMPX_GT_U64, +amdgpu_cdna2_op_V_CMPX_LE_F16, +amdgpu_cdna2_op_V_CMPX_LE_F32, +amdgpu_cdna2_op_V_CMPX_LE_F64, +amdgpu_cdna2_op_V_CMPX_LE_I16, +amdgpu_cdna2_op_V_CMPX_LE_I32, +amdgpu_cdna2_op_V_CMPX_LE_I64, +amdgpu_cdna2_op_V_CMPX_LE_U16, +amdgpu_cdna2_op_V_CMPX_LE_U32, +amdgpu_cdna2_op_V_CMPX_LE_U64, +amdgpu_cdna2_op_V_CMPX_LG_F16, +amdgpu_cdna2_op_V_CMPX_LG_F32, +amdgpu_cdna2_op_V_CMPX_LG_F64, +amdgpu_cdna2_op_V_CMPX_LT_F16, +amdgpu_cdna2_op_V_CMPX_LT_F32, +amdgpu_cdna2_op_V_CMPX_LT_F64, +amdgpu_cdna2_op_V_CMPX_LT_I16, +amdgpu_cdna2_op_V_CMPX_LT_I32, +amdgpu_cdna2_op_V_CMPX_LT_I64, +amdgpu_cdna2_op_V_CMPX_LT_U16, +amdgpu_cdna2_op_V_CMPX_LT_U32, +amdgpu_cdna2_op_V_CMPX_LT_U64, +amdgpu_cdna2_op_V_CMPX_NEQ_F16, +amdgpu_cdna2_op_V_CMPX_NEQ_F32, +amdgpu_cdna2_op_V_CMPX_NEQ_F64, +amdgpu_cdna2_op_V_CMPX_NE_I16, +amdgpu_cdna2_op_V_CMPX_NE_I32, +amdgpu_cdna2_op_V_CMPX_NE_I64, +amdgpu_cdna2_op_V_CMPX_NE_U16, +amdgpu_cdna2_op_V_CMPX_NE_U32, +amdgpu_cdna2_op_V_CMPX_NE_U64, +amdgpu_cdna2_op_V_CMPX_NGE_F16, +amdgpu_cdna2_op_V_CMPX_NGE_F32, +amdgpu_cdna2_op_V_CMPX_NGE_F64, +amdgpu_cdna2_op_V_CMPX_NGT_F16, +amdgpu_cdna2_op_V_CMPX_NGT_F32, +amdgpu_cdna2_op_V_CMPX_NGT_F64, +amdgpu_cdna2_op_V_CMPX_NLE_F16, +amdgpu_cdna2_op_V_CMPX_NLE_F32, +amdgpu_cdna2_op_V_CMPX_NLE_F64, +amdgpu_cdna2_op_V_CMPX_NLG_F16, +amdgpu_cdna2_op_V_CMPX_NLG_F32, +amdgpu_cdna2_op_V_CMPX_NLG_F64, +amdgpu_cdna2_op_V_CMPX_NLT_F16, +amdgpu_cdna2_op_V_CMPX_NLT_F32, +amdgpu_cdna2_op_V_CMPX_NLT_F64, +amdgpu_cdna2_op_V_CMPX_O_F16, +amdgpu_cdna2_op_V_CMPX_O_F32, +amdgpu_cdna2_op_V_CMPX_O_F64, +amdgpu_cdna2_op_V_CMPX_TRU_F16, +amdgpu_cdna2_op_V_CMPX_TRU_F32, +amdgpu_cdna2_op_V_CMPX_TRU_F64, +amdgpu_cdna2_op_V_CMPX_T_I16, +amdgpu_cdna2_op_V_CMPX_T_I32, +amdgpu_cdna2_op_V_CMPX_T_I64, +amdgpu_cdna2_op_V_CMPX_T_U16, +amdgpu_cdna2_op_V_CMPX_T_U32, +amdgpu_cdna2_op_V_CMPX_T_U64, +amdgpu_cdna2_op_V_CMPX_U_F16, +amdgpu_cdna2_op_V_CMPX_U_F32, +amdgpu_cdna2_op_V_CMPX_U_F64, +amdgpu_cdna2_op_V_CMP_CLASS_F16, +amdgpu_cdna2_op_V_CMP_CLASS_F32, +amdgpu_cdna2_op_V_CMP_CLASS_F64, +amdgpu_cdna2_op_V_CMP_EQ_F16, +amdgpu_cdna2_op_V_CMP_EQ_F32, +amdgpu_cdna2_op_V_CMP_EQ_F64, +amdgpu_cdna2_op_V_CMP_EQ_I16, +amdgpu_cdna2_op_V_CMP_EQ_I32, +amdgpu_cdna2_op_V_CMP_EQ_I64, +amdgpu_cdna2_op_V_CMP_EQ_U16, +amdgpu_cdna2_op_V_CMP_EQ_U32, +amdgpu_cdna2_op_V_CMP_EQ_U64, +amdgpu_cdna2_op_V_CMP_F_F16, +amdgpu_cdna2_op_V_CMP_F_F32, +amdgpu_cdna2_op_V_CMP_F_F64, +amdgpu_cdna2_op_V_CMP_F_I16, +amdgpu_cdna2_op_V_CMP_F_I32, +amdgpu_cdna2_op_V_CMP_F_I64, +amdgpu_cdna2_op_V_CMP_F_U16, +amdgpu_cdna2_op_V_CMP_F_U32, +amdgpu_cdna2_op_V_CMP_F_U64, +amdgpu_cdna2_op_V_CMP_GE_F16, +amdgpu_cdna2_op_V_CMP_GE_F32, +amdgpu_cdna2_op_V_CMP_GE_F64, +amdgpu_cdna2_op_V_CMP_GE_I16, +amdgpu_cdna2_op_V_CMP_GE_I32, +amdgpu_cdna2_op_V_CMP_GE_I64, +amdgpu_cdna2_op_V_CMP_GE_U16, +amdgpu_cdna2_op_V_CMP_GE_U32, +amdgpu_cdna2_op_V_CMP_GE_U64, +amdgpu_cdna2_op_V_CMP_GT_F16, +amdgpu_cdna2_op_V_CMP_GT_F32, +amdgpu_cdna2_op_V_CMP_GT_F64, +amdgpu_cdna2_op_V_CMP_GT_I16, +amdgpu_cdna2_op_V_CMP_GT_I32, +amdgpu_cdna2_op_V_CMP_GT_I64, +amdgpu_cdna2_op_V_CMP_GT_U16, +amdgpu_cdna2_op_V_CMP_GT_U32, +amdgpu_cdna2_op_V_CMP_GT_U64, +amdgpu_cdna2_op_V_CMP_LE_F16, +amdgpu_cdna2_op_V_CMP_LE_F32, +amdgpu_cdna2_op_V_CMP_LE_F64, +amdgpu_cdna2_op_V_CMP_LE_I16, +amdgpu_cdna2_op_V_CMP_LE_I32, +amdgpu_cdna2_op_V_CMP_LE_I64, +amdgpu_cdna2_op_V_CMP_LE_U16, +amdgpu_cdna2_op_V_CMP_LE_U32, +amdgpu_cdna2_op_V_CMP_LE_U64, +amdgpu_cdna2_op_V_CMP_LG_F16, +amdgpu_cdna2_op_V_CMP_LG_F32, +amdgpu_cdna2_op_V_CMP_LG_F64, +amdgpu_cdna2_op_V_CMP_LT_F16, +amdgpu_cdna2_op_V_CMP_LT_F32, +amdgpu_cdna2_op_V_CMP_LT_F64, +amdgpu_cdna2_op_V_CMP_LT_I16, +amdgpu_cdna2_op_V_CMP_LT_I32, +amdgpu_cdna2_op_V_CMP_LT_I64, +amdgpu_cdna2_op_V_CMP_LT_U16, +amdgpu_cdna2_op_V_CMP_LT_U32, +amdgpu_cdna2_op_V_CMP_LT_U64, +amdgpu_cdna2_op_V_CMP_NEQ_F16, +amdgpu_cdna2_op_V_CMP_NEQ_F32, +amdgpu_cdna2_op_V_CMP_NEQ_F64, +amdgpu_cdna2_op_V_CMP_NE_I16, +amdgpu_cdna2_op_V_CMP_NE_I32, +amdgpu_cdna2_op_V_CMP_NE_I64, +amdgpu_cdna2_op_V_CMP_NE_U16, +amdgpu_cdna2_op_V_CMP_NE_U32, +amdgpu_cdna2_op_V_CMP_NE_U64, +amdgpu_cdna2_op_V_CMP_NGE_F16, +amdgpu_cdna2_op_V_CMP_NGE_F32, +amdgpu_cdna2_op_V_CMP_NGE_F64, +amdgpu_cdna2_op_V_CMP_NGT_F16, +amdgpu_cdna2_op_V_CMP_NGT_F32, +amdgpu_cdna2_op_V_CMP_NGT_F64, +amdgpu_cdna2_op_V_CMP_NLE_F16, +amdgpu_cdna2_op_V_CMP_NLE_F32, +amdgpu_cdna2_op_V_CMP_NLE_F64, +amdgpu_cdna2_op_V_CMP_NLG_F16, +amdgpu_cdna2_op_V_CMP_NLG_F32, +amdgpu_cdna2_op_V_CMP_NLG_F64, +amdgpu_cdna2_op_V_CMP_NLT_F16, +amdgpu_cdna2_op_V_CMP_NLT_F32, +amdgpu_cdna2_op_V_CMP_NLT_F64, +amdgpu_cdna2_op_V_CMP_O_F16, +amdgpu_cdna2_op_V_CMP_O_F32, +amdgpu_cdna2_op_V_CMP_O_F64, +amdgpu_cdna2_op_V_CMP_TRU_F16, +amdgpu_cdna2_op_V_CMP_TRU_F32, +amdgpu_cdna2_op_V_CMP_TRU_F64, +amdgpu_cdna2_op_V_CMP_T_I16, +amdgpu_cdna2_op_V_CMP_T_I32, +amdgpu_cdna2_op_V_CMP_T_I64, +amdgpu_cdna2_op_V_CMP_T_U16, +amdgpu_cdna2_op_V_CMP_T_U32, +amdgpu_cdna2_op_V_CMP_T_U64, +amdgpu_cdna2_op_V_CMP_U_F16, +amdgpu_cdna2_op_V_CMP_U_F32, +amdgpu_cdna2_op_V_CMP_U_F64, +amdgpu_cdna2_op_V_CNDMASK_B32, +amdgpu_cdna2_op_V_COS_F16, +amdgpu_cdna2_op_V_COS_F32, +amdgpu_cdna2_op_V_CUBEID_F32, +amdgpu_cdna2_op_V_CUBEMA_F32, +amdgpu_cdna2_op_V_CUBESC_F32, +amdgpu_cdna2_op_V_CUBETC_F32, +amdgpu_cdna2_op_V_CVT_F16_F32, +amdgpu_cdna2_op_V_CVT_F16_I16, +amdgpu_cdna2_op_V_CVT_F16_U16, +amdgpu_cdna2_op_V_CVT_F32_F16, +amdgpu_cdna2_op_V_CVT_F32_F64, +amdgpu_cdna2_op_V_CVT_F32_I32, +amdgpu_cdna2_op_V_CVT_F32_U32, +amdgpu_cdna2_op_V_CVT_F32_UBYTE0, +amdgpu_cdna2_op_V_CVT_F32_UBYTE1, +amdgpu_cdna2_op_V_CVT_F32_UBYTE2, +amdgpu_cdna2_op_V_CVT_F32_UBYTE3, +amdgpu_cdna2_op_V_CVT_F64_F32, +amdgpu_cdna2_op_V_CVT_F64_I32, +amdgpu_cdna2_op_V_CVT_F64_U32, +amdgpu_cdna2_op_V_CVT_FLR_I32_F32, +amdgpu_cdna2_op_V_CVT_I16_F16, +amdgpu_cdna2_op_V_CVT_I32_F32, +amdgpu_cdna2_op_V_CVT_I32_F64, +amdgpu_cdna2_op_V_CVT_NORM_I16_F16, +amdgpu_cdna2_op_V_CVT_NORM_U16_F16, +amdgpu_cdna2_op_V_CVT_OFF_F32_I4, +amdgpu_cdna2_op_V_CVT_PKACCUM_U8_F32, +amdgpu_cdna2_op_V_CVT_PKNORM_I16_F16, +amdgpu_cdna2_op_V_CVT_PKNORM_I16_F32, +amdgpu_cdna2_op_V_CVT_PKNORM_U16_F16, +amdgpu_cdna2_op_V_CVT_PKNORM_U16_F32, +amdgpu_cdna2_op_V_CVT_PKRTZ_F16_F32, +amdgpu_cdna2_op_V_CVT_PK_I16_I32, +amdgpu_cdna2_op_V_CVT_PK_U16_U32, +amdgpu_cdna2_op_V_CVT_PK_U8_F32, +amdgpu_cdna2_op_V_CVT_RPI_I32_F32, +amdgpu_cdna2_op_V_CVT_U16_F16, +amdgpu_cdna2_op_V_CVT_U32_F32, +amdgpu_cdna2_op_V_CVT_U32_F64, +amdgpu_cdna2_op_V_DIV_FIXUP_F16, +amdgpu_cdna2_op_V_DIV_FIXUP_F32, +amdgpu_cdna2_op_V_DIV_FIXUP_F64, +amdgpu_cdna2_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_cdna2_op_V_DIV_FMAS_F32, +amdgpu_cdna2_op_V_DIV_FMAS_F64, +amdgpu_cdna2_op_V_DIV_SCALE_F32, +amdgpu_cdna2_op_V_DIV_SCALE_F64, +amdgpu_cdna2_op_V_DOT2C_F32_F16, +amdgpu_cdna2_op_V_DOT2C_I32_I16, +amdgpu_cdna2_op_V_DOT2_F32_F16, +amdgpu_cdna2_op_V_DOT2_I32_I16, +amdgpu_cdna2_op_V_DOT2_U32_U16, +amdgpu_cdna2_op_V_DOT4C_I32_I8, +amdgpu_cdna2_op_V_DOT4_I32_I8, +amdgpu_cdna2_op_V_DOT4_U32_U8, +amdgpu_cdna2_op_V_DOT8C_I32_I4, +amdgpu_cdna2_op_V_DOT8_I32_I4, +amdgpu_cdna2_op_V_DOT8_U32_U4, +amdgpu_cdna2_op_V_EXP_F16, +amdgpu_cdna2_op_V_EXP_F32, +amdgpu_cdna2_op_V_EXP_LEGACY_F32, +amdgpu_cdna2_op_V_FFBH_I32, +amdgpu_cdna2_op_V_FFBH_U32, +amdgpu_cdna2_op_V_FFBL_B32, +amdgpu_cdna2_op_V_FLOOR_F16, +amdgpu_cdna2_op_V_FLOOR_F32, +amdgpu_cdna2_op_V_FLOOR_F64, +amdgpu_cdna2_op_V_FMAC_F32, +amdgpu_cdna2_op_V_FMAC_F64, +amdgpu_cdna2_op_V_FMA_F16, +amdgpu_cdna2_op_V_FMA_F32, +amdgpu_cdna2_op_V_FMA_F64, +amdgpu_cdna2_op_V_FMA_LEGACY_F16, +amdgpu_cdna2_op_V_FRACT_F16, +amdgpu_cdna2_op_V_FRACT_F32, +amdgpu_cdna2_op_V_FRACT_F64, +amdgpu_cdna2_op_V_FREXP_EXP_I16_F16, +amdgpu_cdna2_op_V_FREXP_EXP_I32_F32, +amdgpu_cdna2_op_V_FREXP_EXP_I32_F64, +amdgpu_cdna2_op_V_FREXP_MANT_F16, +amdgpu_cdna2_op_V_FREXP_MANT_F32, +amdgpu_cdna2_op_V_FREXP_MANT_F64, +amdgpu_cdna2_op_V_LDEXP_F16, +amdgpu_cdna2_op_V_LDEXP_F32, +amdgpu_cdna2_op_V_LDEXP_F64, +amdgpu_cdna2_op_V_LERP_U8, +amdgpu_cdna2_op_V_LOG_F16, +amdgpu_cdna2_op_V_LOG_F32, +amdgpu_cdna2_op_V_LOG_LEGACY_F32, +amdgpu_cdna2_op_V_LSHLREV_B16, +amdgpu_cdna2_op_V_LSHLREV_B32, +amdgpu_cdna2_op_V_LSHLREV_B64, +amdgpu_cdna2_op_V_LSHL_ADD_U32, +amdgpu_cdna2_op_V_LSHL_OR_B32, +amdgpu_cdna2_op_V_LSHRREV_B16, +amdgpu_cdna2_op_V_LSHRREV_B32, +amdgpu_cdna2_op_V_LSHRREV_B64, +amdgpu_cdna2_op_V_MAC_F16, +amdgpu_cdna2_op_V_MAC_F32, +amdgpu_cdna2_op_V_MADAK_F16, +amdgpu_cdna2_op_V_MADAK_F32, +amdgpu_cdna2_op_V_MADMK_F16, +amdgpu_cdna2_op_V_MADMK_F32, +amdgpu_cdna2_op_V_MAD_F16, +amdgpu_cdna2_op_V_MAD_F32, +amdgpu_cdna2_op_V_MAD_I16, +amdgpu_cdna2_op_V_MAD_I32_I16, +amdgpu_cdna2_op_V_MAD_I32_I24, +amdgpu_cdna2_op_V_MAD_I64_I32, +amdgpu_cdna2_op_V_MAD_LEGACY_F16, +amdgpu_cdna2_op_V_MAD_LEGACY_F32, +amdgpu_cdna2_op_V_MAD_LEGACY_I16, +amdgpu_cdna2_op_V_MAD_LEGACY_U16, +amdgpu_cdna2_op_V_MAD_MIXHI_F16, +amdgpu_cdna2_op_V_MAD_MIXLO_F16, +amdgpu_cdna2_op_V_MAD_MIX_F32, +amdgpu_cdna2_op_V_MAD_U16, +amdgpu_cdna2_op_V_MAD_U32_U16, +amdgpu_cdna2_op_V_MAD_U32_U24, +amdgpu_cdna2_op_V_MAD_U64_U32, +amdgpu_cdna2_op_V_MAX3_F16, +amdgpu_cdna2_op_V_MAX3_F32, +amdgpu_cdna2_op_V_MAX3_I16, +amdgpu_cdna2_op_V_MAX3_I32, +amdgpu_cdna2_op_V_MAX3_U16, +amdgpu_cdna2_op_V_MAX3_U32, +amdgpu_cdna2_op_V_MAX_F16, +amdgpu_cdna2_op_V_MAX_F32, +amdgpu_cdna2_op_V_MAX_F64, +amdgpu_cdna2_op_V_MAX_I16, +amdgpu_cdna2_op_V_MAX_I32, +amdgpu_cdna2_op_V_MAX_U16, +amdgpu_cdna2_op_V_MAX_U32, +amdgpu_cdna2_op_V_MBCNT_HI_U32_B32, +amdgpu_cdna2_op_V_MBCNT_LO_U32_B32, +amdgpu_cdna2_op_V_MED3_F16, +amdgpu_cdna2_op_V_MED3_F32, +amdgpu_cdna2_op_V_MED3_I16, +amdgpu_cdna2_op_V_MED3_I32, +amdgpu_cdna2_op_V_MED3_U16, +amdgpu_cdna2_op_V_MED3_U32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X16BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_16X16X16F16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X1F32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4F16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4F32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X8BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X1F32, +amdgpu_cdna2_op_V_MFMA_F32_32X32X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X2F32, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4F16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X8BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_32X32X8F16, +amdgpu_cdna2_op_V_MFMA_F32_4X4X1F32, +amdgpu_cdna2_op_V_MFMA_F32_4X4X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_4X4X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_4X4X4F16, +amdgpu_cdna2_op_V_MFMA_F64_16X16X4F64, +amdgpu_cdna2_op_V_MFMA_F64_4X4X4F64, +amdgpu_cdna2_op_V_MFMA_I32_16X16X16I8, +amdgpu_cdna2_op_V_MFMA_I32_16X16X4I8, +amdgpu_cdna2_op_V_MFMA_I32_32X32X4I8, +amdgpu_cdna2_op_V_MFMA_I32_32X32X8I8, +amdgpu_cdna2_op_V_MFMA_I32_4X4X4I8, +amdgpu_cdna2_op_V_MIN3_F16, +amdgpu_cdna2_op_V_MIN3_F32, +amdgpu_cdna2_op_V_MIN3_I16, +amdgpu_cdna2_op_V_MIN3_I32, +amdgpu_cdna2_op_V_MIN3_U16, +amdgpu_cdna2_op_V_MIN3_U32, +amdgpu_cdna2_op_V_MIN_F16, +amdgpu_cdna2_op_V_MIN_F32, +amdgpu_cdna2_op_V_MIN_F64, +amdgpu_cdna2_op_V_MIN_I16, +amdgpu_cdna2_op_V_MIN_I32, +amdgpu_cdna2_op_V_MIN_U16, +amdgpu_cdna2_op_V_MIN_U32, +amdgpu_cdna2_op_V_MOV_B32, +amdgpu_cdna2_op_V_MQSAD_PK_U16_U8, +amdgpu_cdna2_op_V_MQSAD_U32_U8, +amdgpu_cdna2_op_V_MSAD_U8, +amdgpu_cdna2_op_V_MUL_F16, +amdgpu_cdna2_op_V_MUL_F32, +amdgpu_cdna2_op_V_MUL_F64, +amdgpu_cdna2_op_V_MUL_HI_I32, +amdgpu_cdna2_op_V_MUL_HI_I32_I24, +amdgpu_cdna2_op_V_MUL_HI_U32, +amdgpu_cdna2_op_V_MUL_HI_U32_U24, +amdgpu_cdna2_op_V_MUL_I32_I24, +amdgpu_cdna2_op_V_MUL_LEGACY_F32, +amdgpu_cdna2_op_V_MUL_LO_U16, +amdgpu_cdna2_op_V_MUL_LO_U32, +amdgpu_cdna2_op_V_MUL_U32_U24, +amdgpu_cdna2_op_V_NOP, +amdgpu_cdna2_op_V_NOT_B32, +amdgpu_cdna2_op_V_OR3_B32, +amdgpu_cdna2_op_V_OR_B32, +amdgpu_cdna2_op_V_PACK_B32_F16, +amdgpu_cdna2_op_V_PERM_B32, +amdgpu_cdna2_op_V_PK_ADD_F16, +amdgpu_cdna2_op_V_PK_ADD_F32, +amdgpu_cdna2_op_V_PK_ADD_I16, +amdgpu_cdna2_op_V_PK_ADD_U16, +amdgpu_cdna2_op_V_PK_ASHRREV_I16, +amdgpu_cdna2_op_V_PK_FMAC_F16, +amdgpu_cdna2_op_V_PK_FMA_F16, +amdgpu_cdna2_op_V_PK_FMA_F32, +amdgpu_cdna2_op_V_PK_LSHLREV_B16, +amdgpu_cdna2_op_V_PK_LSHRREV_B16, +amdgpu_cdna2_op_V_PK_MAD_I16, +amdgpu_cdna2_op_V_PK_MAD_U16, +amdgpu_cdna2_op_V_PK_MAX_F16, +amdgpu_cdna2_op_V_PK_MAX_I16, +amdgpu_cdna2_op_V_PK_MAX_U16, +amdgpu_cdna2_op_V_PK_MIN_F16, +amdgpu_cdna2_op_V_PK_MIN_I16, +amdgpu_cdna2_op_V_PK_MIN_U16, +amdgpu_cdna2_op_V_PK_MOV_B32, +amdgpu_cdna2_op_V_PK_MUL_F16, +amdgpu_cdna2_op_V_PK_MUL_F32, +amdgpu_cdna2_op_V_PK_MUL_LO_U16, +amdgpu_cdna2_op_V_PK_SUB_I16, +amdgpu_cdna2_op_V_PK_SUB_U16, +amdgpu_cdna2_op_V_QSAD_PK_U16_U8, +amdgpu_cdna2_op_V_RCP_F16, +amdgpu_cdna2_op_V_RCP_F32, +amdgpu_cdna2_op_V_RCP_F64, +amdgpu_cdna2_op_V_RCP_IFLAG_F32, +amdgpu_cdna2_op_V_READFIRSTLANE_B32, +amdgpu_cdna2_op_V_READLANE_B32, +amdgpu_cdna2_op_V_RNDNE_F16, +amdgpu_cdna2_op_V_RNDNE_F32, +amdgpu_cdna2_op_V_RNDNE_F64, +amdgpu_cdna2_op_V_RSQ_F16, +amdgpu_cdna2_op_V_RSQ_F32, +amdgpu_cdna2_op_V_RSQ_F64, +amdgpu_cdna2_op_V_SAD_HI_U8, +amdgpu_cdna2_op_V_SAD_U16, +amdgpu_cdna2_op_V_SAD_U32, +amdgpu_cdna2_op_V_SAD_U8, +amdgpu_cdna2_op_V_SAT_PK_U8_I16, +amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_cdna2_op_V_SIN_F16, +amdgpu_cdna2_op_V_SIN_F32, +amdgpu_cdna2_op_V_SQRT_F16, +amdgpu_cdna2_op_V_SQRT_F32, +amdgpu_cdna2_op_V_SQRT_F64, +amdgpu_cdna2_op_V_SUBBREV_CO_U32, +amdgpu_cdna2_op_V_SUBB_CO_U32, +amdgpu_cdna2_op_V_SUBREV_CO_U32, +amdgpu_cdna2_op_V_SUBREV_F16, +amdgpu_cdna2_op_V_SUBREV_F32, +amdgpu_cdna2_op_V_SUBREV_U16, +amdgpu_cdna2_op_V_SUBREV_U32, +amdgpu_cdna2_op_V_SUB_CO_U32, +amdgpu_cdna2_op_V_SUB_F16, +amdgpu_cdna2_op_V_SUB_F32, +amdgpu_cdna2_op_V_SUB_I16, +amdgpu_cdna2_op_V_SUB_I32, +amdgpu_cdna2_op_V_SUB_U16, +amdgpu_cdna2_op_V_SUB_U32, +amdgpu_cdna2_op_V_SWAP_B32, +amdgpu_cdna2_op_V_TRIG_PREOP_F64, +amdgpu_cdna2_op_V_TRUNC_F16, +amdgpu_cdna2_op_V_TRUNC_F32, +amdgpu_cdna2_op_V_TRUNC_F64, +amdgpu_cdna2_op_V_WRITELANE_B32, +amdgpu_cdna2_op_V_XAD_U32, +amdgpu_cdna2_op_V_XNOR_B32, +amdgpu_cdna2_op_V_XOR_B32, diff --git a/common/h/amdgpu_cdna2_sys_regs.h b/common/h/amdgpu_cdna2_sys_regs.h new file mode 100644 index 0000000000..eb74b6cf98 --- /dev/null +++ b/common/h/amdgpu_cdna2_sys_regs.h @@ -0,0 +1,1563 @@ +#ifndef DYNINST_AMDGPU_CDNA2_SYS_REGS_H +#define DYNINST_AMDGPU_CDNA2_SYS_REGS_H +DEF_REGISTER(address_mode_32, Arch_amdgpu_cdna2 | HWR | BITS_32 | 0,"amdgpu_cdna2"); +DEF_REGISTER(exec, Arch_amdgpu_cdna2 | HWR | BITS_64 | 1,"amdgpu_cdna2"); +DEF_REGISTER(exec_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 1,"amdgpu_cdna2"); +DEF_REGISTER(exec_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 1,"amdgpu_cdna2"); +DEF_REGISTER(expcnt, Arch_amdgpu_cdna2 | HWR | BITS_3 | 2,"amdgpu_cdna2"); +DEF_REGISTER(export_icount, Arch_amdgpu_cdna2 | HWR | BITS_8 | 3,"amdgpu_cdna2"); +DEF_REGISTER(flat_scratch, Arch_amdgpu_cdna2 | HWR | BITS_64 | 4,"amdgpu_cdna2"); +DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 4,"amdgpu_cdna2"); +DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 4,"amdgpu_cdna2"); +DEF_REGISTER(gpr_alloc, Arch_amdgpu_cdna2 | HWR | BITS_32 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_base, Arch_amdgpu_cdna2 | 0x0 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpt_size, Arch_amdgpu_cdna2 | 0x80000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_base, Arch_amdgpu_cdna2 | 0x100000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_size, Arch_amdgpu_cdna2 | 0x180000 | BITS_4 | 0x8000 | 5,"amdgpu_cdna2"); +DEF_REGISTER(ib_sts, Arch_amdgpu_cdna2 | HWR | BITS_32 | 6,"amdgpu_cdna2"); +DEF_REGISTER(exp_cnt, Arch_amdgpu_cdna2 | 0x40000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna2"); +DEF_REGISTER(lgkm_cnt, Arch_amdgpu_cdna2 | 0x80000 | BITS_4 | 0x8000 | 6,"amdgpu_cdna2"); +DEF_REGISTER(valu_cnt, Arch_amdgpu_cdna2 | 0xc0000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vm_cnt, Arch_amdgpu_cdna2 | 0xf0000 | BITS_6 | 0x8000 | 6,"amdgpu_cdna2"); +DEF_REGISTER(lds_alloc, Arch_amdgpu_cdna2 | HWR | BITS_32 | 7,"amdgpu_cdna2"); +DEF_REGISTER(lds_base, Arch_amdgpu_cdna2 | 0x0 | BITS_8 | 0x8000 | 7,"amdgpu_cdna2"); +DEF_REGISTER(lds_size, Arch_amdgpu_cdna2 | 0xc0000 | BITS_9 | 0x8000 | 7,"amdgpu_cdna2"); +DEF_REGISTER(lds_gds_constant_message_count, Arch_amdgpu_cdna2 | HWR | BITS_8 | 8,"amdgpu_cdna2"); +DEF_REGISTER(lgkmcnt, Arch_amdgpu_cdna2 | HWR | BITS_4 | 9,"amdgpu_cdna2"); +DEF_REGISTER(m0, Arch_amdgpu_cdna2 | HWR | BITS_32 | 10,"amdgpu_cdna2"); +DEF_REGISTER(gds_size, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(lds_direct_address, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(lds_interpolation_parameter_offset, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(lds_memory_vfetch_offset, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(lds_direct_data_type, Arch_amdgpu_cdna2 | 0x100000 | BITS_3 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(lds_interpolation_new_prim_mask, Arch_amdgpu_cdna2 | 0x100000 | BITS_15 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(gds_base, Arch_amdgpu_cdna2 | 0x100000 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); +DEF_REGISTER(mode, Arch_amdgpu_cdna2 | HWR | BITS_32 | 11,"amdgpu_cdna2"); +DEF_REGISTER(fp_round, Arch_amdgpu_cdna2 | 0x0 | BITS_4 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(fp_denorm, Arch_amdgpu_cdna2 | 0x40000 | BITS_4 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(dx10_clamp, Arch_amdgpu_cdna2 | 0x80000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(ieee, Arch_amdgpu_cdna2 | 0x90000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(lod_clamped, Arch_amdgpu_cdna2 | 0xa0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(debug, Arch_amdgpu_cdna2 | 0xb0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(excp_en, Arch_amdgpu_cdna2 | 0xc0000 | BITS_7 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(fp16_ovfl, Arch_amdgpu_cdna2 | 0x170000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(pops_packer0, Arch_amdgpu_cdna2 | 0x180000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(pops_packer1, Arch_amdgpu_cdna2 | 0x190000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(disable_perf, Arch_amdgpu_cdna2 | 0x1a0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(gpr_idx_en, Arch_amdgpu_cdna2 | 0x1b0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vskip, Arch_amdgpu_cdna2 | 0x1c0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(csp, Arch_amdgpu_cdna2 | 0x1d0000 | BITS_3 | 0x8000 | 11,"amdgpu_cdna2"); +DEF_REGISTER(pc, Arch_amdgpu_cdna2 | PC | BITS_48 | 0,"amdgpu_cdna2"); +DEF_REGISTER(pops_exiting_wave_id, Arch_amdgpu_cdna2 | HWR | BITS_64 | 12,"amdgpu_cdna2"); +DEF_REGISTER(private_base, Arch_amdgpu_cdna2 | HWR | BITS_64 | 13,"amdgpu_cdna2"); +DEF_REGISTER(private_limit, Arch_amdgpu_cdna2 | HWR | BITS_64 | 14,"amdgpu_cdna2"); +DEF_REGISTER(shared_base, Arch_amdgpu_cdna2 | HWR | BITS_64 | 15,"amdgpu_cdna2"); +DEF_REGISTER(shared_limit, Arch_amdgpu_cdna2 | HWR | BITS_64 | 16,"amdgpu_cdna2"); +DEF_REGISTER(status, Arch_amdgpu_cdna2 | HWR | BITS_32 | 17,"amdgpu_cdna2"); +DEF_REGISTER(scc, Arch_amdgpu_cdna2 | 0x0 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(spi_prio, Arch_amdgpu_cdna2 | 0x10000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(wave_prio, Arch_amdgpu_cdna2 | 0x30000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(priv, Arch_amdgpu_cdna2 | 0x50000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(trap_en, Arch_amdgpu_cdna2 | 0x60000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(ttrace_en, Arch_amdgpu_cdna2 | 0x70000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(export_rdy, Arch_amdgpu_cdna2 | 0x80000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(execz, Arch_amdgpu_cdna2 | 0x90000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vccz, Arch_amdgpu_cdna2 | 0xa0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(in_tg, Arch_amdgpu_cdna2 | 0xb0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(in_barrier, Arch_amdgpu_cdna2 | 0xc0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(halt, Arch_amdgpu_cdna2 | 0xd0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(trap, Arch_amdgpu_cdna2 | 0xe0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(ttrace_cu_en, Arch_amdgpu_cdna2 | 0xf0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(valid, Arch_amdgpu_cdna2 | 0x100000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(ecc_err, Arch_amdgpu_cdna2 | 0x110000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(skin_export, Arch_amdgpu_cdna2 | 0x120000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(perf_en, Arch_amdgpu_cdna2 | 0x130000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(cond_dbg_user, Arch_amdgpu_cdna2 | 0x140000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(cond_dbg_sys, Arch_amdgpu_cdna2 | 0x150000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(allow_replay, Arch_amdgpu_cdna2 | 0x160000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(must_export, Arch_amdgpu_cdna2 | 0x1b0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); +DEF_REGISTER(tba, Arch_amdgpu_cdna2 | HWR | BITS_64 | 18,"amdgpu_cdna2"); +DEF_REGISTER(tid, Arch_amdgpu_cdna2 | HWR | BITS_32 | 19,"amdgpu_cdna2"); +DEF_REGISTER(tma, Arch_amdgpu_cdna2 | HWR | BITS_64 | 20,"amdgpu_cdna2"); +DEF_REGISTER(trap_base_address, Arch_amdgpu_cdna2 | HWR | BITS_64 | 21,"amdgpu_cdna2"); +DEF_REGISTER(trap_memory_address, Arch_amdgpu_cdna2 | HWR | BITS_64 | 22,"amdgpu_cdna2"); +DEF_REGISTER(ttmp0, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 0,"amdgpu_cdna2"); +DEF_REGISTER(ttmp1, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 1,"amdgpu_cdna2"); +DEF_REGISTER(ttmp10, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 2,"amdgpu_cdna2"); +DEF_REGISTER(ttmp11, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 3,"amdgpu_cdna2"); +DEF_REGISTER(ttmp12, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 4,"amdgpu_cdna2"); +DEF_REGISTER(ttmp13, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 5,"amdgpu_cdna2"); +DEF_REGISTER(ttmp14, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 6,"amdgpu_cdna2"); +DEF_REGISTER(ttmp15, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 7,"amdgpu_cdna2"); +DEF_REGISTER(ttmp2, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 8,"amdgpu_cdna2"); +DEF_REGISTER(ttmp3, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 9,"amdgpu_cdna2"); +DEF_REGISTER(ttmp4, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 10,"amdgpu_cdna2"); +DEF_REGISTER(ttmp5, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 11,"amdgpu_cdna2"); +DEF_REGISTER(ttmp6, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 12,"amdgpu_cdna2"); +DEF_REGISTER(ttmp7, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 13,"amdgpu_cdna2"); +DEF_REGISTER(ttmp8, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 14,"amdgpu_cdna2"); +DEF_REGISTER(ttmp9, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vcc, Arch_amdgpu_cdna2 | HWR | BITS_64 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vcc_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vcc_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vectory_memory_icount, Arch_amdgpu_cdna2 | HWR | BITS_8 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vmcnt, Arch_amdgpu_cdna2 | HWR | BITS_6 | 25,"amdgpu_cdna2"); +DEF_REGISTER(xnack_mask, Arch_amdgpu_cdna2 | HWR | BITS_64 | 26,"amdgpu_cdna2"); +DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 26,"amdgpu_cdna2"); +DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 26,"amdgpu_cdna2"); +DEF_REGISTER(sgpr0, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 0,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_0, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_0, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_0, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_0, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna2"); +DEF_REGISTER(sgpr1, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 1,"amdgpu_cdna2"); +DEF_REGISTER(sgpr2, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 2,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_2, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna2"); +DEF_REGISTER(sgpr3, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 3,"amdgpu_cdna2"); +DEF_REGISTER(sgpr4, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 4,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_4, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_4, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna2"); +DEF_REGISTER(sgpr5, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 5,"amdgpu_cdna2"); +DEF_REGISTER(sgpr6, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 6,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_6, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna2"); +DEF_REGISTER(sgpr7, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 7,"amdgpu_cdna2"); +DEF_REGISTER(sgpr8, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 8,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_8, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_8, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_8, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna2"); +DEF_REGISTER(sgpr9, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 9,"amdgpu_cdna2"); +DEF_REGISTER(sgpr10, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 10,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_10, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna2"); +DEF_REGISTER(sgpr11, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 11,"amdgpu_cdna2"); +DEF_REGISTER(sgpr12, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 12,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_12, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_12, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna2"); +DEF_REGISTER(sgpr13, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 13,"amdgpu_cdna2"); +DEF_REGISTER(sgpr14, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 14,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_14, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna2"); +DEF_REGISTER(sgpr15, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 15,"amdgpu_cdna2"); +DEF_REGISTER(sgpr16, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 16,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_16, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_16, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_16, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_16, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna2"); +DEF_REGISTER(sgpr17, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 17,"amdgpu_cdna2"); +DEF_REGISTER(sgpr18, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 18,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_18, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna2"); +DEF_REGISTER(sgpr19, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 19,"amdgpu_cdna2"); +DEF_REGISTER(sgpr20, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 20,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_20, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_20, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna2"); +DEF_REGISTER(sgpr21, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 21,"amdgpu_cdna2"); +DEF_REGISTER(sgpr22, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 22,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_22, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna2"); +DEF_REGISTER(sgpr23, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 23,"amdgpu_cdna2"); +DEF_REGISTER(sgpr24, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 24,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_24, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_24, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_24, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna2"); +DEF_REGISTER(sgpr25, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 25,"amdgpu_cdna2"); +DEF_REGISTER(sgpr26, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 26,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_26, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna2"); +DEF_REGISTER(sgpr27, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 27,"amdgpu_cdna2"); +DEF_REGISTER(sgpr28, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 28,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_28, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_28, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna2"); +DEF_REGISTER(sgpr29, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 29,"amdgpu_cdna2"); +DEF_REGISTER(sgpr30, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 30,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_30, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna2"); +DEF_REGISTER(sgpr31, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 31,"amdgpu_cdna2"); +DEF_REGISTER(sgpr32, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 32,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_32, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_32, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_32, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_32, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna2"); +DEF_REGISTER(sgpr33, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 33,"amdgpu_cdna2"); +DEF_REGISTER(sgpr34, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 34,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_34, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna2"); +DEF_REGISTER(sgpr35, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 35,"amdgpu_cdna2"); +DEF_REGISTER(sgpr36, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 36,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_36, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_36, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna2"); +DEF_REGISTER(sgpr37, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 37,"amdgpu_cdna2"); +DEF_REGISTER(sgpr38, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 38,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_38, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna2"); +DEF_REGISTER(sgpr39, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 39,"amdgpu_cdna2"); +DEF_REGISTER(sgpr40, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 40,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_40, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_40, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_40, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna2"); +DEF_REGISTER(sgpr41, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 41,"amdgpu_cdna2"); +DEF_REGISTER(sgpr42, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 42,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_42, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna2"); +DEF_REGISTER(sgpr43, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 43,"amdgpu_cdna2"); +DEF_REGISTER(sgpr44, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 44,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_44, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_44, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna2"); +DEF_REGISTER(sgpr45, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 45,"amdgpu_cdna2"); +DEF_REGISTER(sgpr46, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 46,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_46, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna2"); +DEF_REGISTER(sgpr47, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 47,"amdgpu_cdna2"); +DEF_REGISTER(sgpr48, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 48,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_48, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_48, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_48, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_48, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna2"); +DEF_REGISTER(sgpr49, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 49,"amdgpu_cdna2"); +DEF_REGISTER(sgpr50, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 50,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_50, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna2"); +DEF_REGISTER(sgpr51, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 51,"amdgpu_cdna2"); +DEF_REGISTER(sgpr52, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 52,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_52, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_52, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna2"); +DEF_REGISTER(sgpr53, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 53,"amdgpu_cdna2"); +DEF_REGISTER(sgpr54, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 54,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_54, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna2"); +DEF_REGISTER(sgpr55, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 55,"amdgpu_cdna2"); +DEF_REGISTER(sgpr56, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 56,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_56, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_56, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_56, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna2"); +DEF_REGISTER(sgpr57, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 57,"amdgpu_cdna2"); +DEF_REGISTER(sgpr58, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 58,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_58, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna2"); +DEF_REGISTER(sgpr59, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 59,"amdgpu_cdna2"); +DEF_REGISTER(sgpr60, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 60,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_60, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_60, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna2"); +DEF_REGISTER(sgpr61, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 61,"amdgpu_cdna2"); +DEF_REGISTER(sgpr62, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 62,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_62, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna2"); +DEF_REGISTER(sgpr63, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 63,"amdgpu_cdna2"); +DEF_REGISTER(sgpr64, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 64,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_64, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_64, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_64, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_64, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna2"); +DEF_REGISTER(sgpr65, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 65,"amdgpu_cdna2"); +DEF_REGISTER(sgpr66, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 66,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_66, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna2"); +DEF_REGISTER(sgpr67, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 67,"amdgpu_cdna2"); +DEF_REGISTER(sgpr68, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 68,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_68, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_68, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna2"); +DEF_REGISTER(sgpr69, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 69,"amdgpu_cdna2"); +DEF_REGISTER(sgpr70, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 70,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_70, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna2"); +DEF_REGISTER(sgpr71, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 71,"amdgpu_cdna2"); +DEF_REGISTER(sgpr72, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 72,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_72, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_72, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_72, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna2"); +DEF_REGISTER(sgpr73, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 73,"amdgpu_cdna2"); +DEF_REGISTER(sgpr74, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 74,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_74, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna2"); +DEF_REGISTER(sgpr75, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 75,"amdgpu_cdna2"); +DEF_REGISTER(sgpr76, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 76,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_76, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_76, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna2"); +DEF_REGISTER(sgpr77, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 77,"amdgpu_cdna2"); +DEF_REGISTER(sgpr78, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 78,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_78, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna2"); +DEF_REGISTER(sgpr79, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 79,"amdgpu_cdna2"); +DEF_REGISTER(sgpr80, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 80,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_80, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_80, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_80, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec16_80, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna2"); +DEF_REGISTER(sgpr81, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 81,"amdgpu_cdna2"); +DEF_REGISTER(sgpr82, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 82,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_82, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna2"); +DEF_REGISTER(sgpr83, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 83,"amdgpu_cdna2"); +DEF_REGISTER(sgpr84, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 84,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_84, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_84, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna2"); +DEF_REGISTER(sgpr85, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 85,"amdgpu_cdna2"); +DEF_REGISTER(sgpr86, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 86,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_86, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna2"); +DEF_REGISTER(sgpr87, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 87,"amdgpu_cdna2"); +DEF_REGISTER(sgpr88, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 88,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_88, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_88, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_88, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna2"); +DEF_REGISTER(sgpr89, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 89,"amdgpu_cdna2"); +DEF_REGISTER(sgpr90, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 90,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_90, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna2"); +DEF_REGISTER(sgpr91, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 91,"amdgpu_cdna2"); +DEF_REGISTER(sgpr92, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 92,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_92, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_92, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna2"); +DEF_REGISTER(sgpr93, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 93,"amdgpu_cdna2"); +DEF_REGISTER(sgpr94, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 94,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_94, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna2"); +DEF_REGISTER(sgpr95, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 95,"amdgpu_cdna2"); +DEF_REGISTER(sgpr96, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 96,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_96, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_96, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec8_96, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna2"); +DEF_REGISTER(sgpr97, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 97,"amdgpu_cdna2"); +DEF_REGISTER(sgpr98, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 98,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_98, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna2"); +DEF_REGISTER(sgpr99, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 99,"amdgpu_cdna2"); +DEF_REGISTER(sgpr100, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 100,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_100, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec4_100, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna2"); +DEF_REGISTER(sgpr101, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 101,"amdgpu_cdna2"); +DEF_REGISTER(sgpr102, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 102,"amdgpu_cdna2"); +DEF_REGISTER(sgpr_vec2_102, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna2"); +DEF_REGISTER(sgpr103, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr0, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 0,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_0, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_0, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_0, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_0, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna2"); +DEF_REGISTER(vgpr1, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 1,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_1, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 1,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_1, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 1,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_1, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 1,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_1, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 1,"amdgpu_cdna2"); +DEF_REGISTER(vgpr2, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 2,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_2, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_2, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 2,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_2, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 2,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_2, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 2,"amdgpu_cdna2"); +DEF_REGISTER(vgpr3, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 3,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_3, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 3,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_3, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 3,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_3, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 3,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_3, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 3,"amdgpu_cdna2"); +DEF_REGISTER(vgpr4, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 4,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_4, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_4, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_4, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 4,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_4, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 4,"amdgpu_cdna2"); +DEF_REGISTER(vgpr5, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_5, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_5, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_5, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_5, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 5,"amdgpu_cdna2"); +DEF_REGISTER(vgpr6, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_6, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_6, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_6, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_6, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 6,"amdgpu_cdna2"); +DEF_REGISTER(vgpr7, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 7,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_7, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 7,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_7, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 7,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_7, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 7,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_7, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 7,"amdgpu_cdna2"); +DEF_REGISTER(vgpr8, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 8,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_8, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_8, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_8, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_8, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 8,"amdgpu_cdna2"); +DEF_REGISTER(vgpr9, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 9,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_9, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 9,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_9, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 9,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_9, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 9,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_9, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 9,"amdgpu_cdna2"); +DEF_REGISTER(vgpr10, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 10,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_10, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_10, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 10,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_10, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 10,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_10, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 10,"amdgpu_cdna2"); +DEF_REGISTER(vgpr11, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_11, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_11, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_11, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_11, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 11,"amdgpu_cdna2"); +DEF_REGISTER(vgpr12, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 12,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_12, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_12, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_12, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 12,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_12, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 12,"amdgpu_cdna2"); +DEF_REGISTER(vgpr13, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 13,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_13, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 13,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_13, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 13,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_13, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 13,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_13, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 13,"amdgpu_cdna2"); +DEF_REGISTER(vgpr14, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 14,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_14, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_14, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 14,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_14, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 14,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_14, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 14,"amdgpu_cdna2"); +DEF_REGISTER(vgpr15, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_15, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_15, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_15, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_15, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 15,"amdgpu_cdna2"); +DEF_REGISTER(vgpr16, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 16,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_16, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_16, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_16, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_16, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna2"); +DEF_REGISTER(vgpr17, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_17, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_17, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_17, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_17, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 17,"amdgpu_cdna2"); +DEF_REGISTER(vgpr18, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 18,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_18, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_18, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 18,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_18, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 18,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_18, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 18,"amdgpu_cdna2"); +DEF_REGISTER(vgpr19, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 19,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_19, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 19,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_19, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 19,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_19, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 19,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_19, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 19,"amdgpu_cdna2"); +DEF_REGISTER(vgpr20, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 20,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_20, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_20, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_20, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 20,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_20, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 20,"amdgpu_cdna2"); +DEF_REGISTER(vgpr21, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 21,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_21, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 21,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_21, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 21,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_21, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 21,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_21, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 21,"amdgpu_cdna2"); +DEF_REGISTER(vgpr22, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 22,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_22, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_22, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 22,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_22, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 22,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_22, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 22,"amdgpu_cdna2"); +DEF_REGISTER(vgpr23, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_23, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_23, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_23, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_23, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 23,"amdgpu_cdna2"); +DEF_REGISTER(vgpr24, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_24, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_24, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_24, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_24, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 24,"amdgpu_cdna2"); +DEF_REGISTER(vgpr25, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 25,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_25, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 25,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_25, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 25,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_25, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 25,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_25, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 25,"amdgpu_cdna2"); +DEF_REGISTER(vgpr26, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 26,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_26, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_26, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 26,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_26, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 26,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_26, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 26,"amdgpu_cdna2"); +DEF_REGISTER(vgpr27, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 27,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_27, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 27,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_27, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 27,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_27, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 27,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_27, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 27,"amdgpu_cdna2"); +DEF_REGISTER(vgpr28, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 28,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_28, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_28, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_28, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 28,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_28, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 28,"amdgpu_cdna2"); +DEF_REGISTER(vgpr29, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 29,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_29, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 29,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_29, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 29,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_29, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 29,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_29, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 29,"amdgpu_cdna2"); +DEF_REGISTER(vgpr30, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 30,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_30, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_30, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 30,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_30, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 30,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_30, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 30,"amdgpu_cdna2"); +DEF_REGISTER(vgpr31, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 31,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_31, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 31,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_31, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 31,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_31, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 31,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_31, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 31,"amdgpu_cdna2"); +DEF_REGISTER(vgpr32, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 32,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_32, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_32, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_32, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_32, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna2"); +DEF_REGISTER(vgpr33, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 33,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_33, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 33,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_33, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 33,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_33, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 33,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_33, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 33,"amdgpu_cdna2"); +DEF_REGISTER(vgpr34, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 34,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_34, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_34, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 34,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_34, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 34,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_34, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 34,"amdgpu_cdna2"); +DEF_REGISTER(vgpr35, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 35,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_35, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 35,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_35, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 35,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_35, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 35,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_35, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 35,"amdgpu_cdna2"); +DEF_REGISTER(vgpr36, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 36,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_36, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_36, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_36, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 36,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_36, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 36,"amdgpu_cdna2"); +DEF_REGISTER(vgpr37, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 37,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_37, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 37,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_37, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 37,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_37, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 37,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_37, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 37,"amdgpu_cdna2"); +DEF_REGISTER(vgpr38, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 38,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_38, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_38, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 38,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_38, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 38,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_38, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 38,"amdgpu_cdna2"); +DEF_REGISTER(vgpr39, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 39,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_39, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 39,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_39, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 39,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_39, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 39,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_39, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 39,"amdgpu_cdna2"); +DEF_REGISTER(vgpr40, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 40,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_40, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_40, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_40, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_40, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 40,"amdgpu_cdna2"); +DEF_REGISTER(vgpr41, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 41,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_41, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 41,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_41, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 41,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_41, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 41,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_41, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 41,"amdgpu_cdna2"); +DEF_REGISTER(vgpr42, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 42,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_42, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_42, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 42,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_42, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 42,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_42, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 42,"amdgpu_cdna2"); +DEF_REGISTER(vgpr43, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 43,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_43, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 43,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_43, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 43,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_43, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 43,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_43, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 43,"amdgpu_cdna2"); +DEF_REGISTER(vgpr44, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 44,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_44, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_44, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_44, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 44,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_44, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 44,"amdgpu_cdna2"); +DEF_REGISTER(vgpr45, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 45,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_45, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 45,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_45, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 45,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_45, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 45,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_45, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 45,"amdgpu_cdna2"); +DEF_REGISTER(vgpr46, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 46,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_46, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_46, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 46,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_46, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 46,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_46, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 46,"amdgpu_cdna2"); +DEF_REGISTER(vgpr47, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 47,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_47, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 47,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_47, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 47,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_47, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 47,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_47, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 47,"amdgpu_cdna2"); +DEF_REGISTER(vgpr48, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 48,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_48, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_48, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_48, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_48, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna2"); +DEF_REGISTER(vgpr49, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 49,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_49, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 49,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_49, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 49,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_49, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 49,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_49, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 49,"amdgpu_cdna2"); +DEF_REGISTER(vgpr50, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 50,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_50, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_50, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 50,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_50, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 50,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_50, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 50,"amdgpu_cdna2"); +DEF_REGISTER(vgpr51, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 51,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_51, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 51,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_51, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 51,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_51, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 51,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_51, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 51,"amdgpu_cdna2"); +DEF_REGISTER(vgpr52, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 52,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_52, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_52, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_52, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 52,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_52, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 52,"amdgpu_cdna2"); +DEF_REGISTER(vgpr53, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 53,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_53, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 53,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_53, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 53,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_53, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 53,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_53, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 53,"amdgpu_cdna2"); +DEF_REGISTER(vgpr54, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 54,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_54, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_54, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 54,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_54, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 54,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_54, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 54,"amdgpu_cdna2"); +DEF_REGISTER(vgpr55, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 55,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_55, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 55,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_55, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 55,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_55, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 55,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_55, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 55,"amdgpu_cdna2"); +DEF_REGISTER(vgpr56, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 56,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_56, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_56, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_56, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_56, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 56,"amdgpu_cdna2"); +DEF_REGISTER(vgpr57, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 57,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_57, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 57,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_57, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 57,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_57, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 57,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_57, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 57,"amdgpu_cdna2"); +DEF_REGISTER(vgpr58, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 58,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_58, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_58, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 58,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_58, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 58,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_58, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 58,"amdgpu_cdna2"); +DEF_REGISTER(vgpr59, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 59,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_59, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 59,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_59, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 59,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_59, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 59,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_59, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 59,"amdgpu_cdna2"); +DEF_REGISTER(vgpr60, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 60,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_60, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_60, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_60, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 60,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_60, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 60,"amdgpu_cdna2"); +DEF_REGISTER(vgpr61, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 61,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_61, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 61,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_61, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 61,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_61, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 61,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_61, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 61,"amdgpu_cdna2"); +DEF_REGISTER(vgpr62, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 62,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_62, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_62, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 62,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_62, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 62,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_62, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 62,"amdgpu_cdna2"); +DEF_REGISTER(vgpr63, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 63,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_63, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 63,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_63, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 63,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_63, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 63,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_63, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 63,"amdgpu_cdna2"); +DEF_REGISTER(vgpr64, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 64,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_64, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_64, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_64, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_64, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna2"); +DEF_REGISTER(vgpr65, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 65,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_65, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 65,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_65, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 65,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_65, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 65,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_65, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 65,"amdgpu_cdna2"); +DEF_REGISTER(vgpr66, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 66,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_66, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_66, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 66,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_66, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 66,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_66, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 66,"amdgpu_cdna2"); +DEF_REGISTER(vgpr67, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 67,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_67, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 67,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_67, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 67,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_67, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 67,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_67, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 67,"amdgpu_cdna2"); +DEF_REGISTER(vgpr68, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 68,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_68, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_68, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_68, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 68,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_68, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 68,"amdgpu_cdna2"); +DEF_REGISTER(vgpr69, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 69,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_69, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 69,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_69, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 69,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_69, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 69,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_69, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 69,"amdgpu_cdna2"); +DEF_REGISTER(vgpr70, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 70,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_70, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_70, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 70,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_70, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 70,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_70, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 70,"amdgpu_cdna2"); +DEF_REGISTER(vgpr71, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 71,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_71, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 71,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_71, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 71,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_71, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 71,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_71, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 71,"amdgpu_cdna2"); +DEF_REGISTER(vgpr72, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 72,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_72, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_72, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_72, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_72, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 72,"amdgpu_cdna2"); +DEF_REGISTER(vgpr73, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 73,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_73, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 73,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_73, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 73,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_73, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 73,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_73, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 73,"amdgpu_cdna2"); +DEF_REGISTER(vgpr74, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 74,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_74, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_74, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 74,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_74, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 74,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_74, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 74,"amdgpu_cdna2"); +DEF_REGISTER(vgpr75, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 75,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_75, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 75,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_75, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 75,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_75, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 75,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_75, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 75,"amdgpu_cdna2"); +DEF_REGISTER(vgpr76, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 76,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_76, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_76, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_76, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 76,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_76, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 76,"amdgpu_cdna2"); +DEF_REGISTER(vgpr77, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 77,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_77, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 77,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_77, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 77,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_77, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 77,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_77, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 77,"amdgpu_cdna2"); +DEF_REGISTER(vgpr78, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 78,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_78, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_78, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 78,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_78, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 78,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_78, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 78,"amdgpu_cdna2"); +DEF_REGISTER(vgpr79, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 79,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_79, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 79,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_79, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 79,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_79, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 79,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_79, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 79,"amdgpu_cdna2"); +DEF_REGISTER(vgpr80, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 80,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_80, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_80, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_80, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_80, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna2"); +DEF_REGISTER(vgpr81, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 81,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_81, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 81,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_81, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 81,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_81, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 81,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_81, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 81,"amdgpu_cdna2"); +DEF_REGISTER(vgpr82, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 82,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_82, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_82, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 82,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_82, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 82,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_82, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 82,"amdgpu_cdna2"); +DEF_REGISTER(vgpr83, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 83,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_83, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 83,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_83, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 83,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_83, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 83,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_83, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 83,"amdgpu_cdna2"); +DEF_REGISTER(vgpr84, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 84,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_84, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_84, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_84, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 84,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_84, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 84,"amdgpu_cdna2"); +DEF_REGISTER(vgpr85, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 85,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_85, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 85,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_85, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 85,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_85, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 85,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_85, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 85,"amdgpu_cdna2"); +DEF_REGISTER(vgpr86, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 86,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_86, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_86, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 86,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_86, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 86,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_86, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 86,"amdgpu_cdna2"); +DEF_REGISTER(vgpr87, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 87,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_87, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 87,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_87, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 87,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_87, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 87,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_87, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 87,"amdgpu_cdna2"); +DEF_REGISTER(vgpr88, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 88,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_88, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_88, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_88, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_88, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 88,"amdgpu_cdna2"); +DEF_REGISTER(vgpr89, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 89,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_89, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 89,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_89, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 89,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_89, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 89,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_89, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 89,"amdgpu_cdna2"); +DEF_REGISTER(vgpr90, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 90,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_90, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_90, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 90,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_90, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 90,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_90, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 90,"amdgpu_cdna2"); +DEF_REGISTER(vgpr91, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 91,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_91, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 91,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_91, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 91,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_91, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 91,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_91, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 91,"amdgpu_cdna2"); +DEF_REGISTER(vgpr92, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 92,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_92, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_92, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_92, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 92,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_92, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 92,"amdgpu_cdna2"); +DEF_REGISTER(vgpr93, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 93,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_93, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 93,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_93, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 93,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_93, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 93,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_93, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 93,"amdgpu_cdna2"); +DEF_REGISTER(vgpr94, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 94,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_94, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_94, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 94,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_94, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 94,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_94, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 94,"amdgpu_cdna2"); +DEF_REGISTER(vgpr95, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 95,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_95, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 95,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_95, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 95,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_95, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 95,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_95, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 95,"amdgpu_cdna2"); +DEF_REGISTER(vgpr96, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 96,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_96, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_96, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_96, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_96, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 96,"amdgpu_cdna2"); +DEF_REGISTER(vgpr97, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 97,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_97, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 97,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_97, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 97,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_97, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 97,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_97, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 97,"amdgpu_cdna2"); +DEF_REGISTER(vgpr98, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 98,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_98, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_98, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 98,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_98, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 98,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_98, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 98,"amdgpu_cdna2"); +DEF_REGISTER(vgpr99, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 99,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_99, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 99,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_99, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 99,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_99, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 99,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_99, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 99,"amdgpu_cdna2"); +DEF_REGISTER(vgpr100, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 100,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_100, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_100, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_100, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 100,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_100, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 100,"amdgpu_cdna2"); +DEF_REGISTER(vgpr101, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 101,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_101, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 101,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_101, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 101,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_101, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 101,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_101, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 101,"amdgpu_cdna2"); +DEF_REGISTER(vgpr102, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 102,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_102, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_102, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 102,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_102, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 102,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_102, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 102,"amdgpu_cdna2"); +DEF_REGISTER(vgpr103, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_103, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_103, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_103, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_103, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 103,"amdgpu_cdna2"); +DEF_REGISTER(vgpr104, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 104,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_104, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 104,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_104, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 104,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_104, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 104,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_104, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 104,"amdgpu_cdna2"); +DEF_REGISTER(vgpr105, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 105,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_105, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 105,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_105, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 105,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_105, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 105,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_105, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 105,"amdgpu_cdna2"); +DEF_REGISTER(vgpr106, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 106,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_106, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 106,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_106, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 106,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_106, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 106,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_106, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 106,"amdgpu_cdna2"); +DEF_REGISTER(vgpr107, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 107,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_107, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 107,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_107, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 107,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_107, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 107,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_107, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 107,"amdgpu_cdna2"); +DEF_REGISTER(vgpr108, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 108,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_108, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 108,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_108, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 108,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_108, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 108,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_108, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 108,"amdgpu_cdna2"); +DEF_REGISTER(vgpr109, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 109,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_109, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 109,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_109, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 109,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_109, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 109,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_109, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 109,"amdgpu_cdna2"); +DEF_REGISTER(vgpr110, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 110,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_110, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 110,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_110, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 110,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_110, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 110,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_110, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 110,"amdgpu_cdna2"); +DEF_REGISTER(vgpr111, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 111,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_111, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 111,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_111, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 111,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_111, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 111,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_111, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 111,"amdgpu_cdna2"); +DEF_REGISTER(vgpr112, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 112,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_112, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 112,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_112, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 112,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_112, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 112,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_112, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 112,"amdgpu_cdna2"); +DEF_REGISTER(vgpr113, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 113,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_113, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 113,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_113, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 113,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_113, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 113,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_113, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 113,"amdgpu_cdna2"); +DEF_REGISTER(vgpr114, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 114,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_114, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 114,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_114, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 114,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_114, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 114,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_114, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 114,"amdgpu_cdna2"); +DEF_REGISTER(vgpr115, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 115,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_115, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 115,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_115, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 115,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_115, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 115,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_115, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 115,"amdgpu_cdna2"); +DEF_REGISTER(vgpr116, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 116,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_116, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 116,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_116, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 116,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_116, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 116,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_116, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 116,"amdgpu_cdna2"); +DEF_REGISTER(vgpr117, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 117,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_117, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 117,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_117, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 117,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_117, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 117,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_117, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 117,"amdgpu_cdna2"); +DEF_REGISTER(vgpr118, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 118,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_118, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 118,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_118, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 118,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_118, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 118,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_118, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 118,"amdgpu_cdna2"); +DEF_REGISTER(vgpr119, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 119,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_119, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 119,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_119, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 119,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_119, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 119,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_119, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 119,"amdgpu_cdna2"); +DEF_REGISTER(vgpr120, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 120,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_120, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 120,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_120, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 120,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_120, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 120,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_120, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 120,"amdgpu_cdna2"); +DEF_REGISTER(vgpr121, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 121,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_121, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 121,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_121, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 121,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_121, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 121,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_121, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 121,"amdgpu_cdna2"); +DEF_REGISTER(vgpr122, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 122,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_122, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 122,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_122, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 122,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_122, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 122,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_122, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 122,"amdgpu_cdna2"); +DEF_REGISTER(vgpr123, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 123,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_123, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 123,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_123, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 123,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_123, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 123,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_123, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 123,"amdgpu_cdna2"); +DEF_REGISTER(vgpr124, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 124,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_124, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 124,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_124, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 124,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_124, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 124,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_124, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 124,"amdgpu_cdna2"); +DEF_REGISTER(vgpr125, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 125,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_125, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 125,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_125, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 125,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_125, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 125,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_125, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 125,"amdgpu_cdna2"); +DEF_REGISTER(vgpr126, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 126,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_126, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 126,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_126, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 126,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_126, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 126,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_126, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 126,"amdgpu_cdna2"); +DEF_REGISTER(vgpr127, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 127,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_127, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 127,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_127, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 127,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_127, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 127,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_127, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 127,"amdgpu_cdna2"); +DEF_REGISTER(vgpr128, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 128,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_128, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 128,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_128, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 128,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_128, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 128,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_128, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 128,"amdgpu_cdna2"); +DEF_REGISTER(vgpr129, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 129,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_129, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 129,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_129, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 129,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_129, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 129,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_129, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 129,"amdgpu_cdna2"); +DEF_REGISTER(vgpr130, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 130,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_130, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 130,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_130, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 130,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_130, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 130,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_130, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 130,"amdgpu_cdna2"); +DEF_REGISTER(vgpr131, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 131,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_131, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 131,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_131, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 131,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_131, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 131,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_131, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 131,"amdgpu_cdna2"); +DEF_REGISTER(vgpr132, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 132,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_132, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 132,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_132, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 132,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_132, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 132,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_132, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 132,"amdgpu_cdna2"); +DEF_REGISTER(vgpr133, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 133,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_133, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 133,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_133, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 133,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_133, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 133,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_133, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 133,"amdgpu_cdna2"); +DEF_REGISTER(vgpr134, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 134,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_134, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 134,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_134, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 134,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_134, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 134,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_134, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 134,"amdgpu_cdna2"); +DEF_REGISTER(vgpr135, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 135,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_135, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 135,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_135, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 135,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_135, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 135,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_135, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 135,"amdgpu_cdna2"); +DEF_REGISTER(vgpr136, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 136,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_136, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 136,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_136, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 136,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_136, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 136,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_136, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 136,"amdgpu_cdna2"); +DEF_REGISTER(vgpr137, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 137,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_137, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 137,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_137, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 137,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_137, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 137,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_137, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 137,"amdgpu_cdna2"); +DEF_REGISTER(vgpr138, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 138,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_138, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 138,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_138, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 138,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_138, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 138,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_138, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 138,"amdgpu_cdna2"); +DEF_REGISTER(vgpr139, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 139,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_139, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 139,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_139, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 139,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_139, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 139,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_139, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 139,"amdgpu_cdna2"); +DEF_REGISTER(vgpr140, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 140,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_140, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 140,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_140, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 140,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_140, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 140,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_140, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 140,"amdgpu_cdna2"); +DEF_REGISTER(vgpr141, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 141,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_141, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 141,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_141, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 141,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_141, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 141,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_141, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 141,"amdgpu_cdna2"); +DEF_REGISTER(vgpr142, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 142,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_142, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 142,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_142, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 142,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_142, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 142,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_142, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 142,"amdgpu_cdna2"); +DEF_REGISTER(vgpr143, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 143,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_143, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 143,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_143, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 143,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_143, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 143,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_143, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 143,"amdgpu_cdna2"); +DEF_REGISTER(vgpr144, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 144,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_144, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 144,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_144, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 144,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_144, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 144,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_144, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 144,"amdgpu_cdna2"); +DEF_REGISTER(vgpr145, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 145,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_145, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 145,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_145, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 145,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_145, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 145,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_145, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 145,"amdgpu_cdna2"); +DEF_REGISTER(vgpr146, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 146,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_146, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 146,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_146, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 146,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_146, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 146,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_146, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 146,"amdgpu_cdna2"); +DEF_REGISTER(vgpr147, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 147,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_147, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 147,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_147, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 147,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_147, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 147,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_147, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 147,"amdgpu_cdna2"); +DEF_REGISTER(vgpr148, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 148,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_148, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 148,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_148, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 148,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_148, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 148,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_148, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 148,"amdgpu_cdna2"); +DEF_REGISTER(vgpr149, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 149,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_149, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 149,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_149, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 149,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_149, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 149,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_149, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 149,"amdgpu_cdna2"); +DEF_REGISTER(vgpr150, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 150,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_150, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 150,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_150, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 150,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_150, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 150,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_150, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 150,"amdgpu_cdna2"); +DEF_REGISTER(vgpr151, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 151,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_151, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 151,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_151, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 151,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_151, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 151,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_151, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 151,"amdgpu_cdna2"); +DEF_REGISTER(vgpr152, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 152,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_152, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 152,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_152, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 152,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_152, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 152,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_152, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 152,"amdgpu_cdna2"); +DEF_REGISTER(vgpr153, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 153,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_153, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 153,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_153, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 153,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_153, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 153,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_153, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 153,"amdgpu_cdna2"); +DEF_REGISTER(vgpr154, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 154,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_154, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 154,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_154, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 154,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_154, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 154,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_154, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 154,"amdgpu_cdna2"); +DEF_REGISTER(vgpr155, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 155,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_155, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 155,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_155, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 155,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_155, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 155,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_155, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 155,"amdgpu_cdna2"); +DEF_REGISTER(vgpr156, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 156,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_156, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 156,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_156, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 156,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_156, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 156,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_156, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 156,"amdgpu_cdna2"); +DEF_REGISTER(vgpr157, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 157,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_157, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 157,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_157, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 157,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_157, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 157,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_157, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 157,"amdgpu_cdna2"); +DEF_REGISTER(vgpr158, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 158,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_158, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 158,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_158, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 158,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_158, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 158,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_158, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 158,"amdgpu_cdna2"); +DEF_REGISTER(vgpr159, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 159,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_159, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 159,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_159, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 159,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_159, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 159,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_159, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 159,"amdgpu_cdna2"); +DEF_REGISTER(vgpr160, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 160,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_160, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 160,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_160, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 160,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_160, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 160,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_160, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 160,"amdgpu_cdna2"); +DEF_REGISTER(vgpr161, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 161,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_161, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 161,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_161, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 161,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_161, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 161,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_161, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 161,"amdgpu_cdna2"); +DEF_REGISTER(vgpr162, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 162,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_162, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 162,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_162, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 162,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_162, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 162,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_162, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 162,"amdgpu_cdna2"); +DEF_REGISTER(vgpr163, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 163,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_163, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 163,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_163, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 163,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_163, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 163,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_163, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 163,"amdgpu_cdna2"); +DEF_REGISTER(vgpr164, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 164,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_164, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 164,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_164, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 164,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_164, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 164,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_164, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 164,"amdgpu_cdna2"); +DEF_REGISTER(vgpr165, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 165,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_165, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 165,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_165, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 165,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_165, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 165,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_165, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 165,"amdgpu_cdna2"); +DEF_REGISTER(vgpr166, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 166,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_166, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 166,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_166, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 166,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_166, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 166,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_166, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 166,"amdgpu_cdna2"); +DEF_REGISTER(vgpr167, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 167,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_167, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 167,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_167, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 167,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_167, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 167,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_167, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 167,"amdgpu_cdna2"); +DEF_REGISTER(vgpr168, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 168,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_168, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 168,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_168, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 168,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_168, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 168,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_168, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 168,"amdgpu_cdna2"); +DEF_REGISTER(vgpr169, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 169,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_169, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 169,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_169, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 169,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_169, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 169,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_169, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 169,"amdgpu_cdna2"); +DEF_REGISTER(vgpr170, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 170,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_170, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 170,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_170, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 170,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_170, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 170,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_170, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 170,"amdgpu_cdna2"); +DEF_REGISTER(vgpr171, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 171,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_171, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 171,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_171, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 171,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_171, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 171,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_171, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 171,"amdgpu_cdna2"); +DEF_REGISTER(vgpr172, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 172,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_172, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 172,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_172, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 172,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_172, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 172,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_172, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 172,"amdgpu_cdna2"); +DEF_REGISTER(vgpr173, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 173,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_173, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 173,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_173, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 173,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_173, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 173,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_173, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 173,"amdgpu_cdna2"); +DEF_REGISTER(vgpr174, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 174,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_174, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 174,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_174, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 174,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_174, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 174,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_174, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 174,"amdgpu_cdna2"); +DEF_REGISTER(vgpr175, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 175,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_175, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 175,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_175, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 175,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_175, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 175,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_175, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 175,"amdgpu_cdna2"); +DEF_REGISTER(vgpr176, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 176,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_176, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 176,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_176, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 176,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_176, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 176,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_176, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 176,"amdgpu_cdna2"); +DEF_REGISTER(vgpr177, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 177,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_177, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 177,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_177, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 177,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_177, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 177,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_177, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 177,"amdgpu_cdna2"); +DEF_REGISTER(vgpr178, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 178,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_178, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 178,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_178, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 178,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_178, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 178,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_178, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 178,"amdgpu_cdna2"); +DEF_REGISTER(vgpr179, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 179,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_179, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 179,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_179, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 179,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_179, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 179,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_179, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 179,"amdgpu_cdna2"); +DEF_REGISTER(vgpr180, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 180,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_180, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 180,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_180, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 180,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_180, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 180,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_180, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 180,"amdgpu_cdna2"); +DEF_REGISTER(vgpr181, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 181,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_181, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 181,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_181, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 181,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_181, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 181,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_181, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 181,"amdgpu_cdna2"); +DEF_REGISTER(vgpr182, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 182,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_182, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 182,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_182, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 182,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_182, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 182,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_182, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 182,"amdgpu_cdna2"); +DEF_REGISTER(vgpr183, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 183,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_183, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 183,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_183, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 183,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_183, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 183,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_183, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 183,"amdgpu_cdna2"); +DEF_REGISTER(vgpr184, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 184,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_184, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 184,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_184, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 184,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_184, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 184,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_184, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 184,"amdgpu_cdna2"); +DEF_REGISTER(vgpr185, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 185,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_185, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 185,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_185, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 185,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_185, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 185,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_185, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 185,"amdgpu_cdna2"); +DEF_REGISTER(vgpr186, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 186,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_186, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 186,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_186, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 186,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_186, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 186,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_186, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 186,"amdgpu_cdna2"); +DEF_REGISTER(vgpr187, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 187,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_187, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 187,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_187, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 187,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_187, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 187,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_187, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 187,"amdgpu_cdna2"); +DEF_REGISTER(vgpr188, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 188,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_188, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 188,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_188, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 188,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_188, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 188,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_188, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 188,"amdgpu_cdna2"); +DEF_REGISTER(vgpr189, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 189,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_189, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 189,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_189, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 189,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_189, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 189,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_189, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 189,"amdgpu_cdna2"); +DEF_REGISTER(vgpr190, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 190,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_190, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 190,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_190, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 190,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_190, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 190,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_190, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 190,"amdgpu_cdna2"); +DEF_REGISTER(vgpr191, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 191,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_191, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 191,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_191, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 191,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_191, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 191,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_191, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 191,"amdgpu_cdna2"); +DEF_REGISTER(vgpr192, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 192,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_192, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 192,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_192, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 192,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_192, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 192,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_192, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 192,"amdgpu_cdna2"); +DEF_REGISTER(vgpr193, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 193,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_193, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 193,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_193, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 193,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_193, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 193,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_193, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 193,"amdgpu_cdna2"); +DEF_REGISTER(vgpr194, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 194,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_194, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 194,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_194, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 194,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_194, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 194,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_194, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 194,"amdgpu_cdna2"); +DEF_REGISTER(vgpr195, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 195,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_195, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 195,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_195, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 195,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_195, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 195,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_195, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 195,"amdgpu_cdna2"); +DEF_REGISTER(vgpr196, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 196,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_196, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 196,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_196, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 196,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_196, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 196,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_196, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 196,"amdgpu_cdna2"); +DEF_REGISTER(vgpr197, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 197,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_197, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 197,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_197, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 197,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_197, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 197,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_197, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 197,"amdgpu_cdna2"); +DEF_REGISTER(vgpr198, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 198,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_198, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 198,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_198, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 198,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_198, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 198,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_198, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 198,"amdgpu_cdna2"); +DEF_REGISTER(vgpr199, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 199,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_199, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 199,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_199, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 199,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_199, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 199,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_199, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 199,"amdgpu_cdna2"); +DEF_REGISTER(vgpr200, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 200,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_200, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 200,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_200, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 200,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_200, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 200,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_200, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 200,"amdgpu_cdna2"); +DEF_REGISTER(vgpr201, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 201,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_201, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 201,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_201, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 201,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_201, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 201,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_201, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 201,"amdgpu_cdna2"); +DEF_REGISTER(vgpr202, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 202,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_202, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 202,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_202, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 202,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_202, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 202,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_202, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 202,"amdgpu_cdna2"); +DEF_REGISTER(vgpr203, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 203,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_203, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 203,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_203, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 203,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_203, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 203,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_203, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 203,"amdgpu_cdna2"); +DEF_REGISTER(vgpr204, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 204,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_204, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 204,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_204, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 204,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_204, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 204,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_204, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 204,"amdgpu_cdna2"); +DEF_REGISTER(vgpr205, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 205,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_205, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 205,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_205, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 205,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_205, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 205,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_205, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 205,"amdgpu_cdna2"); +DEF_REGISTER(vgpr206, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 206,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_206, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 206,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_206, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 206,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_206, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 206,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_206, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 206,"amdgpu_cdna2"); +DEF_REGISTER(vgpr207, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 207,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_207, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 207,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_207, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 207,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_207, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 207,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_207, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 207,"amdgpu_cdna2"); +DEF_REGISTER(vgpr208, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 208,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_208, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 208,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_208, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 208,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_208, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 208,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_208, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 208,"amdgpu_cdna2"); +DEF_REGISTER(vgpr209, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 209,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_209, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 209,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_209, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 209,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_209, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 209,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_209, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 209,"amdgpu_cdna2"); +DEF_REGISTER(vgpr210, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 210,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_210, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 210,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_210, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 210,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_210, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 210,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_210, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 210,"amdgpu_cdna2"); +DEF_REGISTER(vgpr211, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 211,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_211, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 211,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_211, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 211,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_211, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 211,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_211, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 211,"amdgpu_cdna2"); +DEF_REGISTER(vgpr212, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 212,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_212, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 212,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_212, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 212,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_212, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 212,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_212, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 212,"amdgpu_cdna2"); +DEF_REGISTER(vgpr213, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 213,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_213, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 213,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_213, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 213,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_213, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 213,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_213, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 213,"amdgpu_cdna2"); +DEF_REGISTER(vgpr214, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 214,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_214, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 214,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_214, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 214,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_214, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 214,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_214, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 214,"amdgpu_cdna2"); +DEF_REGISTER(vgpr215, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 215,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_215, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 215,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_215, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 215,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_215, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 215,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_215, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 215,"amdgpu_cdna2"); +DEF_REGISTER(vgpr216, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 216,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_216, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 216,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_216, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 216,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_216, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 216,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_216, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 216,"amdgpu_cdna2"); +DEF_REGISTER(vgpr217, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 217,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_217, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 217,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_217, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 217,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_217, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 217,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_217, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 217,"amdgpu_cdna2"); +DEF_REGISTER(vgpr218, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 218,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_218, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 218,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_218, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 218,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_218, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 218,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_218, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 218,"amdgpu_cdna2"); +DEF_REGISTER(vgpr219, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 219,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_219, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 219,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_219, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 219,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_219, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 219,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_219, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 219,"amdgpu_cdna2"); +DEF_REGISTER(vgpr220, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 220,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_220, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 220,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_220, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 220,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_220, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 220,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_220, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 220,"amdgpu_cdna2"); +DEF_REGISTER(vgpr221, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 221,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_221, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 221,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_221, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 221,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_221, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 221,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_221, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 221,"amdgpu_cdna2"); +DEF_REGISTER(vgpr222, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 222,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_222, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 222,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_222, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 222,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_222, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 222,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_222, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 222,"amdgpu_cdna2"); +DEF_REGISTER(vgpr223, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 223,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_223, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 223,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_223, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 223,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_223, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 223,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_223, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 223,"amdgpu_cdna2"); +DEF_REGISTER(vgpr224, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 224,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_224, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 224,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_224, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 224,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_224, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 224,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_224, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 224,"amdgpu_cdna2"); +DEF_REGISTER(vgpr225, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 225,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_225, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 225,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_225, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 225,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_225, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 225,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_225, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 225,"amdgpu_cdna2"); +DEF_REGISTER(vgpr226, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 226,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_226, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 226,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_226, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 226,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_226, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 226,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_226, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 226,"amdgpu_cdna2"); +DEF_REGISTER(vgpr227, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 227,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_227, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 227,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_227, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 227,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_227, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 227,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_227, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 227,"amdgpu_cdna2"); +DEF_REGISTER(vgpr228, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 228,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_228, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 228,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_228, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 228,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_228, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 228,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_228, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 228,"amdgpu_cdna2"); +DEF_REGISTER(vgpr229, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 229,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_229, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 229,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_229, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 229,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_229, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 229,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_229, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 229,"amdgpu_cdna2"); +DEF_REGISTER(vgpr230, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 230,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_230, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 230,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_230, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 230,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_230, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 230,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_230, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 230,"amdgpu_cdna2"); +DEF_REGISTER(vgpr231, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 231,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_231, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 231,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_231, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 231,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_231, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 231,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_231, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 231,"amdgpu_cdna2"); +DEF_REGISTER(vgpr232, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 232,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_232, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 232,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_232, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 232,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_232, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 232,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_232, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 232,"amdgpu_cdna2"); +DEF_REGISTER(vgpr233, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 233,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_233, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 233,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_233, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 233,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_233, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 233,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_233, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 233,"amdgpu_cdna2"); +DEF_REGISTER(vgpr234, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 234,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_234, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 234,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_234, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 234,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_234, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 234,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_234, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 234,"amdgpu_cdna2"); +DEF_REGISTER(vgpr235, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 235,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_235, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 235,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_235, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 235,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_235, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 235,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_235, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 235,"amdgpu_cdna2"); +DEF_REGISTER(vgpr236, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 236,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_236, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 236,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_236, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 236,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_236, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 236,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_236, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 236,"amdgpu_cdna2"); +DEF_REGISTER(vgpr237, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 237,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_237, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 237,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_237, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 237,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_237, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 237,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_237, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 237,"amdgpu_cdna2"); +DEF_REGISTER(vgpr238, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 238,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_238, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 238,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_238, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 238,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_238, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 238,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_238, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 238,"amdgpu_cdna2"); +DEF_REGISTER(vgpr239, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 239,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_239, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 239,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_239, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 239,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_239, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 239,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_239, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 239,"amdgpu_cdna2"); +DEF_REGISTER(vgpr240, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 240,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_240, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 240,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_240, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 240,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_240, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 240,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec16_240, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 240,"amdgpu_cdna2"); +DEF_REGISTER(vgpr241, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 241,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_241, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 241,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_241, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 241,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_241, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 241,"amdgpu_cdna2"); +DEF_REGISTER(vgpr242, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 242,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_242, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 242,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_242, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 242,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_242, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 242,"amdgpu_cdna2"); +DEF_REGISTER(vgpr243, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 243,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_243, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 243,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_243, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 243,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_243, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 243,"amdgpu_cdna2"); +DEF_REGISTER(vgpr244, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 244,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_244, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 244,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_244, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 244,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_244, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 244,"amdgpu_cdna2"); +DEF_REGISTER(vgpr245, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 245,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_245, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 245,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_245, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 245,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_245, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 245,"amdgpu_cdna2"); +DEF_REGISTER(vgpr246, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 246,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_246, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 246,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_246, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 246,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_246, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 246,"amdgpu_cdna2"); +DEF_REGISTER(vgpr247, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 247,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_247, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 247,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_247, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 247,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_247, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 247,"amdgpu_cdna2"); +DEF_REGISTER(vgpr248, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 248,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_248, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 248,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_248, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 248,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec8_248, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 248,"amdgpu_cdna2"); +DEF_REGISTER(vgpr249, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 249,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_249, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 249,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_249, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 249,"amdgpu_cdna2"); +DEF_REGISTER(vgpr250, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 250,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_250, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 250,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_250, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 250,"amdgpu_cdna2"); +DEF_REGISTER(vgpr251, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 251,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_251, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 251,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_251, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 251,"amdgpu_cdna2"); +DEF_REGISTER(vgpr252, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 252,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_252, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 252,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec4_252, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 252,"amdgpu_cdna2"); +DEF_REGISTER(vgpr253, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 253,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_253, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 253,"amdgpu_cdna2"); +DEF_REGISTER(vgpr254, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 254,"amdgpu_cdna2"); +DEF_REGISTER(vgpr_vec2_254, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 254,"amdgpu_cdna2"); +DEF_REGISTER(vgpr255, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 255,"amdgpu_cdna2"); +#endif //DYNINST_AMDGPU_CDNA2_SYS_REGS_H diff --git a/common/h/amdgpu_cdna_op_table.h b/common/h/amdgpu_cdna_op_table.h new file mode 100644 index 0000000000..e27bcc8ff2 --- /dev/null +++ b/common/h/amdgpu_cdna_op_table.h @@ -0,0 +1,1152 @@ +amdgpu_cdna_op_BUFFER_ATOMIC_ADD, +amdgpu_cdna_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_cdna_op_BUFFER_ATOMIC_ADD_F64, +amdgpu_cdna_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_AND, +amdgpu_cdna_op_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_DEC, +amdgpu_cdna_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_INC, +amdgpu_cdna_op_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_MAX_F64, +amdgpu_cdna_op_BUFFER_ATOMIC_MIN_F64, +amdgpu_cdna_op_BUFFER_ATOMIC_OR, +amdgpu_cdna_op_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_cdna_op_BUFFER_ATOMIC_SMAX, +amdgpu_cdna_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_SMIN, +amdgpu_cdna_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_SUB, +amdgpu_cdna_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_SWAP, +amdgpu_cdna_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_UMAX, +amdgpu_cdna_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_UMIN, +amdgpu_cdna_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna_op_BUFFER_ATOMIC_XOR, +amdgpu_cdna_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna_op_BUFFER_INV, +amdgpu_cdna_op_BUFFER_LOAD_DWORD, +amdgpu_cdna_op_BUFFER_LOAD_DWORDX2, +amdgpu_cdna_op_BUFFER_LOAD_DWORDX3, +amdgpu_cdna_op_BUFFER_LOAD_DWORDX4, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_X, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna_op_BUFFER_LOAD_SBYTE, +amdgpu_cdna_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_cdna_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_cdna_op_BUFFER_LOAD_SHORT_D16, +amdgpu_cdna_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_cdna_op_BUFFER_LOAD_SSHORT, +amdgpu_cdna_op_BUFFER_LOAD_UBYTE, +amdgpu_cdna_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_cdna_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_cdna_op_BUFFER_LOAD_USHORT, +amdgpu_cdna_op_BUFFER_STORE_BYTE, +amdgpu_cdna_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_cdna_op_BUFFER_STORE_DWORD, +amdgpu_cdna_op_BUFFER_STORE_DWORDX2, +amdgpu_cdna_op_BUFFER_STORE_DWORDX3, +amdgpu_cdna_op_BUFFER_STORE_DWORDX4, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_X, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_XY, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna_op_BUFFER_STORE_SHORT, +amdgpu_cdna_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_cdna_op_BUFFER_WBL2, +amdgpu_cdna_op_DS_ADD_F32, +amdgpu_cdna_op_DS_ADD_F64, +amdgpu_cdna_op_DS_ADD_RTN_F32, +amdgpu_cdna_op_DS_ADD_RTN_F64, +amdgpu_cdna_op_DS_ADD_RTN_U32, +amdgpu_cdna_op_DS_ADD_RTN_U64, +amdgpu_cdna_op_DS_ADD_U32, +amdgpu_cdna_op_DS_ADD_U64, +amdgpu_cdna_op_DS_AND_B32, +amdgpu_cdna_op_DS_AND_B64, +amdgpu_cdna_op_DS_AND_RTN_B32, +amdgpu_cdna_op_DS_AND_RTN_B64, +amdgpu_cdna_op_DS_APPEND, +amdgpu_cdna_op_DS_BPERMUTE_B32, +amdgpu_cdna_op_DS_CMPST_B32, +amdgpu_cdna_op_DS_CMPST_B64, +amdgpu_cdna_op_DS_CMPST_F32, +amdgpu_cdna_op_DS_CMPST_F64, +amdgpu_cdna_op_DS_CMPST_RTN_B32, +amdgpu_cdna_op_DS_CMPST_RTN_B64, +amdgpu_cdna_op_DS_CMPST_RTN_F32, +amdgpu_cdna_op_DS_CMPST_RTN_F64, +amdgpu_cdna_op_DS_CONDXCHG32_RTN_B64, +amdgpu_cdna_op_DS_CONSUME, +amdgpu_cdna_op_DS_DEC_RTN_U32, +amdgpu_cdna_op_DS_DEC_RTN_U64, +amdgpu_cdna_op_DS_DEC_U32, +amdgpu_cdna_op_DS_DEC_U64, +amdgpu_cdna_op_DS_GWS_BARRIER, +amdgpu_cdna_op_DS_GWS_INIT, +amdgpu_cdna_op_DS_GWS_SEMA_BR, +amdgpu_cdna_op_DS_GWS_SEMA_P, +amdgpu_cdna_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_cdna_op_DS_GWS_SEMA_V, +amdgpu_cdna_op_DS_INC_RTN_U32, +amdgpu_cdna_op_DS_INC_RTN_U64, +amdgpu_cdna_op_DS_INC_U32, +amdgpu_cdna_op_DS_INC_U64, +amdgpu_cdna_op_DS_MAX_F32, +amdgpu_cdna_op_DS_MAX_F64, +amdgpu_cdna_op_DS_MAX_I32, +amdgpu_cdna_op_DS_MAX_I64, +amdgpu_cdna_op_DS_MAX_RTN_F32, +amdgpu_cdna_op_DS_MAX_RTN_F64, +amdgpu_cdna_op_DS_MAX_RTN_I32, +amdgpu_cdna_op_DS_MAX_RTN_I64, +amdgpu_cdna_op_DS_MAX_RTN_U32, +amdgpu_cdna_op_DS_MAX_RTN_U64, +amdgpu_cdna_op_DS_MAX_U32, +amdgpu_cdna_op_DS_MAX_U64, +amdgpu_cdna_op_DS_MIN_F32, +amdgpu_cdna_op_DS_MIN_F64, +amdgpu_cdna_op_DS_MIN_I32, +amdgpu_cdna_op_DS_MIN_I64, +amdgpu_cdna_op_DS_MIN_RTN_F32, +amdgpu_cdna_op_DS_MIN_RTN_F64, +amdgpu_cdna_op_DS_MIN_RTN_I32, +amdgpu_cdna_op_DS_MIN_RTN_I64, +amdgpu_cdna_op_DS_MIN_RTN_U32, +amdgpu_cdna_op_DS_MIN_RTN_U64, +amdgpu_cdna_op_DS_MIN_U32, +amdgpu_cdna_op_DS_MIN_U64, +amdgpu_cdna_op_DS_MSKOR_B32, +amdgpu_cdna_op_DS_MSKOR_B64, +amdgpu_cdna_op_DS_MSKOR_RTN_B32, +amdgpu_cdna_op_DS_MSKOR_RTN_B64, +amdgpu_cdna_op_DS_NOP, +amdgpu_cdna_op_DS_OR_B32, +amdgpu_cdna_op_DS_OR_B64, +amdgpu_cdna_op_DS_OR_RTN_B32, +amdgpu_cdna_op_DS_OR_RTN_B64, +amdgpu_cdna_op_DS_PERMUTE_B32, +amdgpu_cdna_op_DS_PK_ADD_BF16, +amdgpu_cdna_op_DS_PK_ADD_F16, +amdgpu_cdna_op_DS_PK_ADD_RTN_BF16, +amdgpu_cdna_op_DS_PK_ADD_RTN_F16, +amdgpu_cdna_op_DS_READ2ST64_B32, +amdgpu_cdna_op_DS_READ2ST64_B64, +amdgpu_cdna_op_DS_READ2_B32, +amdgpu_cdna_op_DS_READ2_B64, +amdgpu_cdna_op_DS_READ_ADDTID_B32, +amdgpu_cdna_op_DS_READ_B128, +amdgpu_cdna_op_DS_READ_B32, +amdgpu_cdna_op_DS_READ_B64, +amdgpu_cdna_op_DS_READ_B96, +amdgpu_cdna_op_DS_READ_I16, +amdgpu_cdna_op_DS_READ_I8, +amdgpu_cdna_op_DS_READ_I8_D16, +amdgpu_cdna_op_DS_READ_I8_D16_HI, +amdgpu_cdna_op_DS_READ_U16, +amdgpu_cdna_op_DS_READ_U16_D16, +amdgpu_cdna_op_DS_READ_U16_D16_HI, +amdgpu_cdna_op_DS_READ_U8, +amdgpu_cdna_op_DS_READ_U8_D16, +amdgpu_cdna_op_DS_READ_U8_D16_HI, +amdgpu_cdna_op_DS_RSUB_RTN_U32, +amdgpu_cdna_op_DS_RSUB_RTN_U64, +amdgpu_cdna_op_DS_RSUB_U32, +amdgpu_cdna_op_DS_RSUB_U64, +amdgpu_cdna_op_DS_SUB_RTN_U32, +amdgpu_cdna_op_DS_SUB_RTN_U64, +amdgpu_cdna_op_DS_SUB_U32, +amdgpu_cdna_op_DS_SUB_U64, +amdgpu_cdna_op_DS_SWIZZLE_B32, +amdgpu_cdna_op_DS_WRAP_RTN_B32, +amdgpu_cdna_op_DS_WRITE2ST64_B32, +amdgpu_cdna_op_DS_WRITE2ST64_B64, +amdgpu_cdna_op_DS_WRITE2_B32, +amdgpu_cdna_op_DS_WRITE2_B64, +amdgpu_cdna_op_DS_WRITE_ADDTID_B32, +amdgpu_cdna_op_DS_WRITE_B128, +amdgpu_cdna_op_DS_WRITE_B16, +amdgpu_cdna_op_DS_WRITE_B16_D16_HI, +amdgpu_cdna_op_DS_WRITE_B32, +amdgpu_cdna_op_DS_WRITE_B64, +amdgpu_cdna_op_DS_WRITE_B8, +amdgpu_cdna_op_DS_WRITE_B8_D16_HI, +amdgpu_cdna_op_DS_WRITE_B96, +amdgpu_cdna_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_cdna_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_cdna_op_DS_WRXCHG2_RTN_B32, +amdgpu_cdna_op_DS_WRXCHG2_RTN_B64, +amdgpu_cdna_op_DS_WRXCHG_RTN_B32, +amdgpu_cdna_op_DS_WRXCHG_RTN_B64, +amdgpu_cdna_op_DS_XOR_B32, +amdgpu_cdna_op_DS_XOR_B64, +amdgpu_cdna_op_DS_XOR_RTN_B32, +amdgpu_cdna_op_DS_XOR_RTN_B64, +amdgpu_cdna_op_FLAT_ATOMIC_ADD, +amdgpu_cdna_op_FLAT_ATOMIC_ADD_F32, +amdgpu_cdna_op_FLAT_ATOMIC_ADD_F64, +amdgpu_cdna_op_FLAT_ATOMIC_ADD_X2, +amdgpu_cdna_op_FLAT_ATOMIC_AND, +amdgpu_cdna_op_FLAT_ATOMIC_AND_X2, +amdgpu_cdna_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_cdna_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_cdna_op_FLAT_ATOMIC_DEC, +amdgpu_cdna_op_FLAT_ATOMIC_DEC_X2, +amdgpu_cdna_op_FLAT_ATOMIC_INC, +amdgpu_cdna_op_FLAT_ATOMIC_INC_X2, +amdgpu_cdna_op_FLAT_ATOMIC_MAX_F64, +amdgpu_cdna_op_FLAT_ATOMIC_MIN_F64, +amdgpu_cdna_op_FLAT_ATOMIC_OR, +amdgpu_cdna_op_FLAT_ATOMIC_OR_X2, +amdgpu_cdna_op_FLAT_ATOMIC_PK_ADD_BF16, +amdgpu_cdna_op_FLAT_ATOMIC_PK_ADD_F16, +amdgpu_cdna_op_FLAT_ATOMIC_SMAX, +amdgpu_cdna_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_cdna_op_FLAT_ATOMIC_SMIN, +amdgpu_cdna_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_cdna_op_FLAT_ATOMIC_SUB, +amdgpu_cdna_op_FLAT_ATOMIC_SUB_X2, +amdgpu_cdna_op_FLAT_ATOMIC_SWAP, +amdgpu_cdna_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_cdna_op_FLAT_ATOMIC_UMAX, +amdgpu_cdna_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_cdna_op_FLAT_ATOMIC_UMIN, +amdgpu_cdna_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_cdna_op_FLAT_ATOMIC_XOR, +amdgpu_cdna_op_FLAT_ATOMIC_XOR_X2, +amdgpu_cdna_op_FLAT_LOAD_DWORD, +amdgpu_cdna_op_FLAT_LOAD_DWORDX2, +amdgpu_cdna_op_FLAT_LOAD_DWORDX3, +amdgpu_cdna_op_FLAT_LOAD_DWORDX4, +amdgpu_cdna_op_FLAT_LOAD_SBYTE, +amdgpu_cdna_op_FLAT_LOAD_SBYTE_D16, +amdgpu_cdna_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_cdna_op_FLAT_LOAD_SHORT_D16, +amdgpu_cdna_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_cdna_op_FLAT_LOAD_SSHORT, +amdgpu_cdna_op_FLAT_LOAD_UBYTE, +amdgpu_cdna_op_FLAT_LOAD_UBYTE_D16, +amdgpu_cdna_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_cdna_op_FLAT_LOAD_USHORT, +amdgpu_cdna_op_FLAT_STORE_BYTE, +amdgpu_cdna_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_cdna_op_FLAT_STORE_DWORD, +amdgpu_cdna_op_FLAT_STORE_DWORDX2, +amdgpu_cdna_op_FLAT_STORE_DWORDX3, +amdgpu_cdna_op_FLAT_STORE_DWORDX4, +amdgpu_cdna_op_FLAT_STORE_SHORT, +amdgpu_cdna_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_cdna_op_GLOBAL_ATOMIC_ADD, +amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_F64, +amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_AND, +amdgpu_cdna_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_cdna_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_DEC, +amdgpu_cdna_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_INC, +amdgpu_cdna_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_MAX_F64, +amdgpu_cdna_op_GLOBAL_ATOMIC_MIN_F64, +amdgpu_cdna_op_GLOBAL_ATOMIC_OR, +amdgpu_cdna_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_PK_ADD_BF16, +amdgpu_cdna_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_cdna_op_GLOBAL_ATOMIC_SMAX, +amdgpu_cdna_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_SMIN, +amdgpu_cdna_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_SUB, +amdgpu_cdna_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_SWAP, +amdgpu_cdna_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_UMAX, +amdgpu_cdna_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_UMIN, +amdgpu_cdna_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_cdna_op_GLOBAL_ATOMIC_XOR, +amdgpu_cdna_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_cdna_op_GLOBAL_LOAD_DWORD, +amdgpu_cdna_op_GLOBAL_LOAD_DWORDX2, +amdgpu_cdna_op_GLOBAL_LOAD_DWORDX3, +amdgpu_cdna_op_GLOBAL_LOAD_DWORDX4, +amdgpu_cdna_op_GLOBAL_LOAD_LDS_DWORD, +amdgpu_cdna_op_GLOBAL_LOAD_LDS_SBYTE, +amdgpu_cdna_op_GLOBAL_LOAD_LDS_SSHORT, +amdgpu_cdna_op_GLOBAL_LOAD_LDS_UBYTE, +amdgpu_cdna_op_GLOBAL_LOAD_LDS_USHORT, +amdgpu_cdna_op_GLOBAL_LOAD_SBYTE, +amdgpu_cdna_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_cdna_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_cdna_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_cdna_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_cdna_op_GLOBAL_LOAD_SSHORT, +amdgpu_cdna_op_GLOBAL_LOAD_UBYTE, +amdgpu_cdna_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_cdna_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_cdna_op_GLOBAL_LOAD_USHORT, +amdgpu_cdna_op_GLOBAL_STORE_BYTE, +amdgpu_cdna_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_cdna_op_GLOBAL_STORE_DWORD, +amdgpu_cdna_op_GLOBAL_STORE_DWORDX2, +amdgpu_cdna_op_GLOBAL_STORE_DWORDX3, +amdgpu_cdna_op_GLOBAL_STORE_DWORDX4, +amdgpu_cdna_op_GLOBAL_STORE_SHORT, +amdgpu_cdna_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_cdna_op_SCRATCH_LOAD_DWORD, +amdgpu_cdna_op_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna_op_SCRATCH_LOAD_DWORDX3, +amdgpu_cdna_op_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna_op_SCRATCH_LOAD_LDS_DWORD, +amdgpu_cdna_op_SCRATCH_LOAD_LDS_SBYTE, +amdgpu_cdna_op_SCRATCH_LOAD_LDS_SSHORT, +amdgpu_cdna_op_SCRATCH_LOAD_LDS_UBYTE, +amdgpu_cdna_op_SCRATCH_LOAD_LDS_USHORT, +amdgpu_cdna_op_SCRATCH_LOAD_SBYTE, +amdgpu_cdna_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_cdna_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_cdna_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_cdna_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_cdna_op_SCRATCH_LOAD_SSHORT, +amdgpu_cdna_op_SCRATCH_LOAD_UBYTE, +amdgpu_cdna_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_cdna_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_cdna_op_SCRATCH_LOAD_USHORT, +amdgpu_cdna_op_SCRATCH_STORE_BYTE, +amdgpu_cdna_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_cdna_op_SCRATCH_STORE_DWORD, +amdgpu_cdna_op_SCRATCH_STORE_DWORDX2, +amdgpu_cdna_op_SCRATCH_STORE_DWORDX3, +amdgpu_cdna_op_SCRATCH_STORE_DWORDX4, +amdgpu_cdna_op_SCRATCH_STORE_SHORT, +amdgpu_cdna_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_cdna_op_S_ABSDIFF_I32, +amdgpu_cdna_op_S_ABS_I32, +amdgpu_cdna_op_S_ADDC_U32, +amdgpu_cdna_op_S_ADDK_I32, +amdgpu_cdna_op_S_ADD_I32, +amdgpu_cdna_op_S_ADD_U32, +amdgpu_cdna_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_cdna_op_S_ANDN1_WREXEC_B64, +amdgpu_cdna_op_S_ANDN2_B32, +amdgpu_cdna_op_S_ANDN2_B64, +amdgpu_cdna_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_cdna_op_S_ANDN2_WREXEC_B64, +amdgpu_cdna_op_S_AND_B32, +amdgpu_cdna_op_S_AND_B64, +amdgpu_cdna_op_S_AND_SAVEEXEC_B64, +amdgpu_cdna_op_S_ASHR_I32, +amdgpu_cdna_op_S_ASHR_I64, +amdgpu_cdna_op_S_ATC_PROBE, +amdgpu_cdna_op_S_ATC_PROBE_BUFFER, +amdgpu_cdna_op_S_ATOMIC_ADD, +amdgpu_cdna_op_S_ATOMIC_ADD_X2, +amdgpu_cdna_op_S_ATOMIC_AND, +amdgpu_cdna_op_S_ATOMIC_AND_X2, +amdgpu_cdna_op_S_ATOMIC_CMPSWAP, +amdgpu_cdna_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_cdna_op_S_ATOMIC_DEC, +amdgpu_cdna_op_S_ATOMIC_DEC_X2, +amdgpu_cdna_op_S_ATOMIC_INC, +amdgpu_cdna_op_S_ATOMIC_INC_X2, +amdgpu_cdna_op_S_ATOMIC_OR, +amdgpu_cdna_op_S_ATOMIC_OR_X2, +amdgpu_cdna_op_S_ATOMIC_SMAX, +amdgpu_cdna_op_S_ATOMIC_SMAX_X2, +amdgpu_cdna_op_S_ATOMIC_SMIN, +amdgpu_cdna_op_S_ATOMIC_SMIN_X2, +amdgpu_cdna_op_S_ATOMIC_SUB, +amdgpu_cdna_op_S_ATOMIC_SUB_X2, +amdgpu_cdna_op_S_ATOMIC_SWAP, +amdgpu_cdna_op_S_ATOMIC_SWAP_X2, +amdgpu_cdna_op_S_ATOMIC_UMAX, +amdgpu_cdna_op_S_ATOMIC_UMAX_X2, +amdgpu_cdna_op_S_ATOMIC_UMIN, +amdgpu_cdna_op_S_ATOMIC_UMIN_X2, +amdgpu_cdna_op_S_ATOMIC_XOR, +amdgpu_cdna_op_S_ATOMIC_XOR_X2, +amdgpu_cdna_op_S_BARRIER, +amdgpu_cdna_op_S_BCNT0_I32_B32, +amdgpu_cdna_op_S_BCNT0_I32_B64, +amdgpu_cdna_op_S_BCNT1_I32_B32, +amdgpu_cdna_op_S_BCNT1_I32_B64, +amdgpu_cdna_op_S_BFE_I32, +amdgpu_cdna_op_S_BFE_I64, +amdgpu_cdna_op_S_BFE_U32, +amdgpu_cdna_op_S_BFE_U64, +amdgpu_cdna_op_S_BFM_B32, +amdgpu_cdna_op_S_BFM_B64, +amdgpu_cdna_op_S_BITCMP0_B32, +amdgpu_cdna_op_S_BITCMP0_B64, +amdgpu_cdna_op_S_BITCMP1_B32, +amdgpu_cdna_op_S_BITCMP1_B64, +amdgpu_cdna_op_S_BITREPLICATE_B64_B32, +amdgpu_cdna_op_S_BITSET0_B32, +amdgpu_cdna_op_S_BITSET0_B64, +amdgpu_cdna_op_S_BITSET1_B32, +amdgpu_cdna_op_S_BITSET1_B64, +amdgpu_cdna_op_S_BRANCH, +amdgpu_cdna_op_S_BREV_B32, +amdgpu_cdna_op_S_BREV_B64, +amdgpu_cdna_op_S_BUFFER_ATOMIC_ADD, +amdgpu_cdna_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_AND, +amdgpu_cdna_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_DEC, +amdgpu_cdna_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_INC, +amdgpu_cdna_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_OR, +amdgpu_cdna_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SUB, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_cdna_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_cdna_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_cdna_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna_op_S_BUFFER_ATOMIC_XOR, +amdgpu_cdna_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna_op_S_BUFFER_LOAD_DWORD, +amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_cdna_op_S_BUFFER_STORE_DWORD, +amdgpu_cdna_op_S_BUFFER_STORE_DWORDX2, +amdgpu_cdna_op_S_BUFFER_STORE_DWORDX4, +amdgpu_cdna_op_S_CALL_B64, +amdgpu_cdna_op_S_CBRANCH_CDBGSYS, +amdgpu_cdna_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_cdna_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_cdna_op_S_CBRANCH_CDBGUSER, +amdgpu_cdna_op_S_CBRANCH_EXECNZ, +amdgpu_cdna_op_S_CBRANCH_EXECZ, +amdgpu_cdna_op_S_CBRANCH_G_FORK, +amdgpu_cdna_op_S_CBRANCH_I_FORK, +amdgpu_cdna_op_S_CBRANCH_JOIN, +amdgpu_cdna_op_S_CBRANCH_SCC0, +amdgpu_cdna_op_S_CBRANCH_SCC1, +amdgpu_cdna_op_S_CBRANCH_VCCNZ, +amdgpu_cdna_op_S_CBRANCH_VCCZ, +amdgpu_cdna_op_S_CMOVK_I32, +amdgpu_cdna_op_S_CMOV_B32, +amdgpu_cdna_op_S_CMOV_B64, +amdgpu_cdna_op_S_CMPK_EQ_I32, +amdgpu_cdna_op_S_CMPK_EQ_U32, +amdgpu_cdna_op_S_CMPK_GE_I32, +amdgpu_cdna_op_S_CMPK_GE_U32, +amdgpu_cdna_op_S_CMPK_GT_I32, +amdgpu_cdna_op_S_CMPK_GT_U32, +amdgpu_cdna_op_S_CMPK_LE_I32, +amdgpu_cdna_op_S_CMPK_LE_U32, +amdgpu_cdna_op_S_CMPK_LG_I32, +amdgpu_cdna_op_S_CMPK_LG_U32, +amdgpu_cdna_op_S_CMPK_LT_I32, +amdgpu_cdna_op_S_CMPK_LT_U32, +amdgpu_cdna_op_S_CMP_EQ_I32, +amdgpu_cdna_op_S_CMP_EQ_U32, +amdgpu_cdna_op_S_CMP_EQ_U64, +amdgpu_cdna_op_S_CMP_GE_I32, +amdgpu_cdna_op_S_CMP_GE_U32, +amdgpu_cdna_op_S_CMP_GT_I32, +amdgpu_cdna_op_S_CMP_GT_U32, +amdgpu_cdna_op_S_CMP_LE_I32, +amdgpu_cdna_op_S_CMP_LE_U32, +amdgpu_cdna_op_S_CMP_LG_I32, +amdgpu_cdna_op_S_CMP_LG_U32, +amdgpu_cdna_op_S_CMP_LG_U64, +amdgpu_cdna_op_S_CMP_LT_I32, +amdgpu_cdna_op_S_CMP_LT_U32, +amdgpu_cdna_op_S_CSELECT_B32, +amdgpu_cdna_op_S_CSELECT_B64, +amdgpu_cdna_op_S_DCACHE_DISCARD, +amdgpu_cdna_op_S_DCACHE_DISCARD_X2, +amdgpu_cdna_op_S_DCACHE_INV, +amdgpu_cdna_op_S_DCACHE_INV_VOL, +amdgpu_cdna_op_S_DCACHE_WB, +amdgpu_cdna_op_S_DCACHE_WB_VOL, +amdgpu_cdna_op_S_DECPERFLEVEL, +amdgpu_cdna_op_S_ENDPGM, +amdgpu_cdna_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_cdna_op_S_ENDPGM_SAVED, +amdgpu_cdna_op_S_FF0_I32_B32, +amdgpu_cdna_op_S_FF0_I32_B64, +amdgpu_cdna_op_S_FF1_I32_B32, +amdgpu_cdna_op_S_FF1_I32_B64, +amdgpu_cdna_op_S_FLBIT_I32, +amdgpu_cdna_op_S_FLBIT_I32_B32, +amdgpu_cdna_op_S_FLBIT_I32_B64, +amdgpu_cdna_op_S_FLBIT_I32_I64, +amdgpu_cdna_op_S_GETPC_B64, +amdgpu_cdna_op_S_GETREG_B32, +amdgpu_cdna_op_S_ICACHE_INV, +amdgpu_cdna_op_S_INCPERFLEVEL, +amdgpu_cdna_op_S_LOAD_DWORD, +amdgpu_cdna_op_S_LOAD_DWORDX16, +amdgpu_cdna_op_S_LOAD_DWORDX2, +amdgpu_cdna_op_S_LOAD_DWORDX4, +amdgpu_cdna_op_S_LOAD_DWORDX8, +amdgpu_cdna_op_S_LSHL1_ADD_U32, +amdgpu_cdna_op_S_LSHL2_ADD_U32, +amdgpu_cdna_op_S_LSHL3_ADD_U32, +amdgpu_cdna_op_S_LSHL4_ADD_U32, +amdgpu_cdna_op_S_LSHL_B32, +amdgpu_cdna_op_S_LSHL_B64, +amdgpu_cdna_op_S_LSHR_B32, +amdgpu_cdna_op_S_LSHR_B64, +amdgpu_cdna_op_S_MAX_I32, +amdgpu_cdna_op_S_MAX_U32, +amdgpu_cdna_op_S_MEMREALTIME, +amdgpu_cdna_op_S_MEMTIME, +amdgpu_cdna_op_S_MIN_I32, +amdgpu_cdna_op_S_MIN_U32, +amdgpu_cdna_op_S_MOVK_I32, +amdgpu_cdna_op_S_MOVRELD_B32, +amdgpu_cdna_op_S_MOVRELD_B64, +amdgpu_cdna_op_S_MOVRELS_B32, +amdgpu_cdna_op_S_MOVRELS_B64, +amdgpu_cdna_op_S_MOV_B32, +amdgpu_cdna_op_S_MOV_B64, +amdgpu_cdna_op_S_MULK_I32, +amdgpu_cdna_op_S_MUL_HI_I32, +amdgpu_cdna_op_S_MUL_HI_U32, +amdgpu_cdna_op_S_MUL_I32, +amdgpu_cdna_op_S_NAND_B32, +amdgpu_cdna_op_S_NAND_B64, +amdgpu_cdna_op_S_NAND_SAVEEXEC_B64, +amdgpu_cdna_op_S_NOP, +amdgpu_cdna_op_S_NOR_B32, +amdgpu_cdna_op_S_NOR_B64, +amdgpu_cdna_op_S_NOR_SAVEEXEC_B64, +amdgpu_cdna_op_S_NOT_B32, +amdgpu_cdna_op_S_NOT_B64, +amdgpu_cdna_op_S_ORN1_SAVEEXEC_B64, +amdgpu_cdna_op_S_ORN2_B32, +amdgpu_cdna_op_S_ORN2_B64, +amdgpu_cdna_op_S_ORN2_SAVEEXEC_B64, +amdgpu_cdna_op_S_OR_B32, +amdgpu_cdna_op_S_OR_B64, +amdgpu_cdna_op_S_OR_SAVEEXEC_B64, +amdgpu_cdna_op_S_PACK_HH_B32_B16, +amdgpu_cdna_op_S_PACK_LH_B32_B16, +amdgpu_cdna_op_S_PACK_LL_B32_B16, +amdgpu_cdna_op_S_QUADMASK_B32, +amdgpu_cdna_op_S_QUADMASK_B64, +amdgpu_cdna_op_S_RFE_B64, +amdgpu_cdna_op_S_RFE_RESTORE_B64, +amdgpu_cdna_op_S_SCRATCH_LOAD_DWORD, +amdgpu_cdna_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna_op_S_SCRATCH_STORE_DWORD, +amdgpu_cdna_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_cdna_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_cdna_op_S_SENDMSG, +amdgpu_cdna_op_S_SENDMSGHALT, +amdgpu_cdna_op_S_SETHALT, +amdgpu_cdna_op_S_SETKILL, +amdgpu_cdna_op_S_SETPC_B64, +amdgpu_cdna_op_S_SETPRIO, +amdgpu_cdna_op_S_SETREG_B32, +amdgpu_cdna_op_S_SETREG_IMM32_B32, +amdgpu_cdna_op_S_SETVSKIP, +amdgpu_cdna_op_S_SET_GPR_IDX_IDX, +amdgpu_cdna_op_S_SET_GPR_IDX_MODE, +amdgpu_cdna_op_S_SET_GPR_IDX_OFF, +amdgpu_cdna_op_S_SET_GPR_IDX_ON, +amdgpu_cdna_op_S_SET_VALU_COEXEC_MODE, +amdgpu_cdna_op_S_SEXT_I32_I16, +amdgpu_cdna_op_S_SEXT_I32_I8, +amdgpu_cdna_op_S_SLEEP, +amdgpu_cdna_op_S_STORE_DWORD, +amdgpu_cdna_op_S_STORE_DWORDX2, +amdgpu_cdna_op_S_STORE_DWORDX4, +amdgpu_cdna_op_S_SUBB_U32, +amdgpu_cdna_op_S_SUB_I32, +amdgpu_cdna_op_S_SUB_U32, +amdgpu_cdna_op_S_SWAPPC_B64, +amdgpu_cdna_op_S_TRAP, +amdgpu_cdna_op_S_TTRACEDATA, +amdgpu_cdna_op_S_WAITCNT, +amdgpu_cdna_op_S_WAKEUP, +amdgpu_cdna_op_S_WQM_B32, +amdgpu_cdna_op_S_WQM_B64, +amdgpu_cdna_op_S_XNOR_B32, +amdgpu_cdna_op_S_XNOR_B64, +amdgpu_cdna_op_S_XNOR_SAVEEXEC_B64, +amdgpu_cdna_op_S_XOR_B32, +amdgpu_cdna_op_S_XOR_B64, +amdgpu_cdna_op_S_XOR_SAVEEXEC_B64, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_X, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna_op_V_ACCVGPR_MOV_B32, +amdgpu_cdna_op_V_ACCVGPR_READ, +amdgpu_cdna_op_V_ACCVGPR_WRITE, +amdgpu_cdna_op_V_ADD3_U32, +amdgpu_cdna_op_V_ADDC_CO_U32, +amdgpu_cdna_op_V_ADD_CO_U32, +amdgpu_cdna_op_V_ADD_F16, +amdgpu_cdna_op_V_ADD_F32, +amdgpu_cdna_op_V_ADD_F64, +amdgpu_cdna_op_V_ADD_I16, +amdgpu_cdna_op_V_ADD_I32, +amdgpu_cdna_op_V_ADD_LSHL_U32, +amdgpu_cdna_op_V_ADD_U16, +amdgpu_cdna_op_V_ADD_U32, +amdgpu_cdna_op_V_ALIGNBIT_B32, +amdgpu_cdna_op_V_ALIGNBYTE_B32, +amdgpu_cdna_op_V_AND_B32, +amdgpu_cdna_op_V_AND_OR_B32, +amdgpu_cdna_op_V_ASHRREV_I16, +amdgpu_cdna_op_V_ASHRREV_I32, +amdgpu_cdna_op_V_ASHRREV_I64, +amdgpu_cdna_op_V_BCNT_U32_B32, +amdgpu_cdna_op_V_BFE_I32, +amdgpu_cdna_op_V_BFE_U32, +amdgpu_cdna_op_V_BFI_B32, +amdgpu_cdna_op_V_BFM_B32, +amdgpu_cdna_op_V_BFREV_B32, +amdgpu_cdna_op_V_CEIL_F16, +amdgpu_cdna_op_V_CEIL_F32, +amdgpu_cdna_op_V_CEIL_F64, +amdgpu_cdna_op_V_CLREXCP, +amdgpu_cdna_op_V_CMPX_CLASS_F16, +amdgpu_cdna_op_V_CMPX_CLASS_F32, +amdgpu_cdna_op_V_CMPX_CLASS_F64, +amdgpu_cdna_op_V_CMPX_EQ_F16, +amdgpu_cdna_op_V_CMPX_EQ_F32, +amdgpu_cdna_op_V_CMPX_EQ_F64, +amdgpu_cdna_op_V_CMPX_EQ_I16, +amdgpu_cdna_op_V_CMPX_EQ_I32, +amdgpu_cdna_op_V_CMPX_EQ_I64, +amdgpu_cdna_op_V_CMPX_EQ_U16, +amdgpu_cdna_op_V_CMPX_EQ_U32, +amdgpu_cdna_op_V_CMPX_EQ_U64, +amdgpu_cdna_op_V_CMPX_F_F16, +amdgpu_cdna_op_V_CMPX_F_F32, +amdgpu_cdna_op_V_CMPX_F_F64, +amdgpu_cdna_op_V_CMPX_F_I16, +amdgpu_cdna_op_V_CMPX_F_I32, +amdgpu_cdna_op_V_CMPX_F_I64, +amdgpu_cdna_op_V_CMPX_F_U16, +amdgpu_cdna_op_V_CMPX_F_U32, +amdgpu_cdna_op_V_CMPX_F_U64, +amdgpu_cdna_op_V_CMPX_GE_F16, +amdgpu_cdna_op_V_CMPX_GE_F32, +amdgpu_cdna_op_V_CMPX_GE_F64, +amdgpu_cdna_op_V_CMPX_GE_I16, +amdgpu_cdna_op_V_CMPX_GE_I32, +amdgpu_cdna_op_V_CMPX_GE_I64, +amdgpu_cdna_op_V_CMPX_GE_U16, +amdgpu_cdna_op_V_CMPX_GE_U32, +amdgpu_cdna_op_V_CMPX_GE_U64, +amdgpu_cdna_op_V_CMPX_GT_F16, +amdgpu_cdna_op_V_CMPX_GT_F32, +amdgpu_cdna_op_V_CMPX_GT_F64, +amdgpu_cdna_op_V_CMPX_GT_I16, +amdgpu_cdna_op_V_CMPX_GT_I32, +amdgpu_cdna_op_V_CMPX_GT_I64, +amdgpu_cdna_op_V_CMPX_GT_U16, +amdgpu_cdna_op_V_CMPX_GT_U32, +amdgpu_cdna_op_V_CMPX_GT_U64, +amdgpu_cdna_op_V_CMPX_LE_F16, +amdgpu_cdna_op_V_CMPX_LE_F32, +amdgpu_cdna_op_V_CMPX_LE_F64, +amdgpu_cdna_op_V_CMPX_LE_I16, +amdgpu_cdna_op_V_CMPX_LE_I32, +amdgpu_cdna_op_V_CMPX_LE_I64, +amdgpu_cdna_op_V_CMPX_LE_U16, +amdgpu_cdna_op_V_CMPX_LE_U32, +amdgpu_cdna_op_V_CMPX_LE_U64, +amdgpu_cdna_op_V_CMPX_LG_F16, +amdgpu_cdna_op_V_CMPX_LG_F32, +amdgpu_cdna_op_V_CMPX_LG_F64, +amdgpu_cdna_op_V_CMPX_LT_F16, +amdgpu_cdna_op_V_CMPX_LT_F32, +amdgpu_cdna_op_V_CMPX_LT_F64, +amdgpu_cdna_op_V_CMPX_LT_I16, +amdgpu_cdna_op_V_CMPX_LT_I32, +amdgpu_cdna_op_V_CMPX_LT_I64, +amdgpu_cdna_op_V_CMPX_LT_U16, +amdgpu_cdna_op_V_CMPX_LT_U32, +amdgpu_cdna_op_V_CMPX_LT_U64, +amdgpu_cdna_op_V_CMPX_NEQ_F16, +amdgpu_cdna_op_V_CMPX_NEQ_F32, +amdgpu_cdna_op_V_CMPX_NEQ_F64, +amdgpu_cdna_op_V_CMPX_NE_I16, +amdgpu_cdna_op_V_CMPX_NE_I32, +amdgpu_cdna_op_V_CMPX_NE_I64, +amdgpu_cdna_op_V_CMPX_NE_U16, +amdgpu_cdna_op_V_CMPX_NE_U32, +amdgpu_cdna_op_V_CMPX_NE_U64, +amdgpu_cdna_op_V_CMPX_NGE_F16, +amdgpu_cdna_op_V_CMPX_NGE_F32, +amdgpu_cdna_op_V_CMPX_NGE_F64, +amdgpu_cdna_op_V_CMPX_NGT_F16, +amdgpu_cdna_op_V_CMPX_NGT_F32, +amdgpu_cdna_op_V_CMPX_NGT_F64, +amdgpu_cdna_op_V_CMPX_NLE_F16, +amdgpu_cdna_op_V_CMPX_NLE_F32, +amdgpu_cdna_op_V_CMPX_NLE_F64, +amdgpu_cdna_op_V_CMPX_NLG_F16, +amdgpu_cdna_op_V_CMPX_NLG_F32, +amdgpu_cdna_op_V_CMPX_NLG_F64, +amdgpu_cdna_op_V_CMPX_NLT_F16, +amdgpu_cdna_op_V_CMPX_NLT_F32, +amdgpu_cdna_op_V_CMPX_NLT_F64, +amdgpu_cdna_op_V_CMPX_O_F16, +amdgpu_cdna_op_V_CMPX_O_F32, +amdgpu_cdna_op_V_CMPX_O_F64, +amdgpu_cdna_op_V_CMPX_TRU_F16, +amdgpu_cdna_op_V_CMPX_TRU_F32, +amdgpu_cdna_op_V_CMPX_TRU_F64, +amdgpu_cdna_op_V_CMPX_T_I16, +amdgpu_cdna_op_V_CMPX_T_I32, +amdgpu_cdna_op_V_CMPX_T_I64, +amdgpu_cdna_op_V_CMPX_T_U16, +amdgpu_cdna_op_V_CMPX_T_U32, +amdgpu_cdna_op_V_CMPX_T_U64, +amdgpu_cdna_op_V_CMPX_U_F16, +amdgpu_cdna_op_V_CMPX_U_F32, +amdgpu_cdna_op_V_CMPX_U_F64, +amdgpu_cdna_op_V_CMP_CLASS_F16, +amdgpu_cdna_op_V_CMP_CLASS_F32, +amdgpu_cdna_op_V_CMP_CLASS_F64, +amdgpu_cdna_op_V_CMP_EQ_F16, +amdgpu_cdna_op_V_CMP_EQ_F32, +amdgpu_cdna_op_V_CMP_EQ_F64, +amdgpu_cdna_op_V_CMP_EQ_I16, +amdgpu_cdna_op_V_CMP_EQ_I32, +amdgpu_cdna_op_V_CMP_EQ_I64, +amdgpu_cdna_op_V_CMP_EQ_U16, +amdgpu_cdna_op_V_CMP_EQ_U32, +amdgpu_cdna_op_V_CMP_EQ_U64, +amdgpu_cdna_op_V_CMP_F_F16, +amdgpu_cdna_op_V_CMP_F_F32, +amdgpu_cdna_op_V_CMP_F_F64, +amdgpu_cdna_op_V_CMP_F_I16, +amdgpu_cdna_op_V_CMP_F_I32, +amdgpu_cdna_op_V_CMP_F_I64, +amdgpu_cdna_op_V_CMP_F_U16, +amdgpu_cdna_op_V_CMP_F_U32, +amdgpu_cdna_op_V_CMP_F_U64, +amdgpu_cdna_op_V_CMP_GE_F16, +amdgpu_cdna_op_V_CMP_GE_F32, +amdgpu_cdna_op_V_CMP_GE_F64, +amdgpu_cdna_op_V_CMP_GE_I16, +amdgpu_cdna_op_V_CMP_GE_I32, +amdgpu_cdna_op_V_CMP_GE_I64, +amdgpu_cdna_op_V_CMP_GE_U16, +amdgpu_cdna_op_V_CMP_GE_U32, +amdgpu_cdna_op_V_CMP_GE_U64, +amdgpu_cdna_op_V_CMP_GT_F16, +amdgpu_cdna_op_V_CMP_GT_F32, +amdgpu_cdna_op_V_CMP_GT_F64, +amdgpu_cdna_op_V_CMP_GT_I16, +amdgpu_cdna_op_V_CMP_GT_I32, +amdgpu_cdna_op_V_CMP_GT_I64, +amdgpu_cdna_op_V_CMP_GT_U16, +amdgpu_cdna_op_V_CMP_GT_U32, +amdgpu_cdna_op_V_CMP_GT_U64, +amdgpu_cdna_op_V_CMP_LE_F16, +amdgpu_cdna_op_V_CMP_LE_F32, +amdgpu_cdna_op_V_CMP_LE_F64, +amdgpu_cdna_op_V_CMP_LE_I16, +amdgpu_cdna_op_V_CMP_LE_I32, +amdgpu_cdna_op_V_CMP_LE_I64, +amdgpu_cdna_op_V_CMP_LE_U16, +amdgpu_cdna_op_V_CMP_LE_U32, +amdgpu_cdna_op_V_CMP_LE_U64, +amdgpu_cdna_op_V_CMP_LG_F16, +amdgpu_cdna_op_V_CMP_LG_F32, +amdgpu_cdna_op_V_CMP_LG_F64, +amdgpu_cdna_op_V_CMP_LT_F16, +amdgpu_cdna_op_V_CMP_LT_F32, +amdgpu_cdna_op_V_CMP_LT_F64, +amdgpu_cdna_op_V_CMP_LT_I16, +amdgpu_cdna_op_V_CMP_LT_I32, +amdgpu_cdna_op_V_CMP_LT_I64, +amdgpu_cdna_op_V_CMP_LT_U16, +amdgpu_cdna_op_V_CMP_LT_U32, +amdgpu_cdna_op_V_CMP_LT_U64, +amdgpu_cdna_op_V_CMP_NEQ_F16, +amdgpu_cdna_op_V_CMP_NEQ_F32, +amdgpu_cdna_op_V_CMP_NEQ_F64, +amdgpu_cdna_op_V_CMP_NE_I16, +amdgpu_cdna_op_V_CMP_NE_I32, +amdgpu_cdna_op_V_CMP_NE_I64, +amdgpu_cdna_op_V_CMP_NE_U16, +amdgpu_cdna_op_V_CMP_NE_U32, +amdgpu_cdna_op_V_CMP_NE_U64, +amdgpu_cdna_op_V_CMP_NGE_F16, +amdgpu_cdna_op_V_CMP_NGE_F32, +amdgpu_cdna_op_V_CMP_NGE_F64, +amdgpu_cdna_op_V_CMP_NGT_F16, +amdgpu_cdna_op_V_CMP_NGT_F32, +amdgpu_cdna_op_V_CMP_NGT_F64, +amdgpu_cdna_op_V_CMP_NLE_F16, +amdgpu_cdna_op_V_CMP_NLE_F32, +amdgpu_cdna_op_V_CMP_NLE_F64, +amdgpu_cdna_op_V_CMP_NLG_F16, +amdgpu_cdna_op_V_CMP_NLG_F32, +amdgpu_cdna_op_V_CMP_NLG_F64, +amdgpu_cdna_op_V_CMP_NLT_F16, +amdgpu_cdna_op_V_CMP_NLT_F32, +amdgpu_cdna_op_V_CMP_NLT_F64, +amdgpu_cdna_op_V_CMP_O_F16, +amdgpu_cdna_op_V_CMP_O_F32, +amdgpu_cdna_op_V_CMP_O_F64, +amdgpu_cdna_op_V_CMP_TRU_F16, +amdgpu_cdna_op_V_CMP_TRU_F32, +amdgpu_cdna_op_V_CMP_TRU_F64, +amdgpu_cdna_op_V_CMP_T_I16, +amdgpu_cdna_op_V_CMP_T_I32, +amdgpu_cdna_op_V_CMP_T_I64, +amdgpu_cdna_op_V_CMP_T_U16, +amdgpu_cdna_op_V_CMP_T_U32, +amdgpu_cdna_op_V_CMP_T_U64, +amdgpu_cdna_op_V_CMP_U_F16, +amdgpu_cdna_op_V_CMP_U_F32, +amdgpu_cdna_op_V_CMP_U_F64, +amdgpu_cdna_op_V_CNDMASK_B32, +amdgpu_cdna_op_V_COS_F16, +amdgpu_cdna_op_V_COS_F32, +amdgpu_cdna_op_V_CUBEID_F32, +amdgpu_cdna_op_V_CUBEMA_F32, +amdgpu_cdna_op_V_CUBESC_F32, +amdgpu_cdna_op_V_CUBETC_F32, +amdgpu_cdna_op_V_CVT_F16_F32, +amdgpu_cdna_op_V_CVT_F16_I16, +amdgpu_cdna_op_V_CVT_F16_U16, +amdgpu_cdna_op_V_CVT_F32_BF8, +amdgpu_cdna_op_V_CVT_F32_F16, +amdgpu_cdna_op_V_CVT_F32_F64, +amdgpu_cdna_op_V_CVT_F32_FP8, +amdgpu_cdna_op_V_CVT_F32_I32, +amdgpu_cdna_op_V_CVT_F32_U32, +amdgpu_cdna_op_V_CVT_F32_UBYTE0, +amdgpu_cdna_op_V_CVT_F32_UBYTE1, +amdgpu_cdna_op_V_CVT_F32_UBYTE2, +amdgpu_cdna_op_V_CVT_F32_UBYTE3, +amdgpu_cdna_op_V_CVT_F64_F32, +amdgpu_cdna_op_V_CVT_F64_I32, +amdgpu_cdna_op_V_CVT_F64_U32, +amdgpu_cdna_op_V_CVT_FLR_I32_F32, +amdgpu_cdna_op_V_CVT_I16_F16, +amdgpu_cdna_op_V_CVT_I32_F32, +amdgpu_cdna_op_V_CVT_I32_F64, +amdgpu_cdna_op_V_CVT_NORM_I16_F16, +amdgpu_cdna_op_V_CVT_NORM_U16_F16, +amdgpu_cdna_op_V_CVT_OFF_F32_I4, +amdgpu_cdna_op_V_CVT_PKACCUM_U8_F32, +amdgpu_cdna_op_V_CVT_PKNORM_I16_F16, +amdgpu_cdna_op_V_CVT_PKNORM_I16_F32, +amdgpu_cdna_op_V_CVT_PKNORM_U16_F16, +amdgpu_cdna_op_V_CVT_PKNORM_U16_F32, +amdgpu_cdna_op_V_CVT_PKRTZ_F16_F32, +amdgpu_cdna_op_V_CVT_PK_BF8_F32, +amdgpu_cdna_op_V_CVT_PK_F32_BF8, +amdgpu_cdna_op_V_CVT_PK_F32_FP8, +amdgpu_cdna_op_V_CVT_PK_FP8_F32, +amdgpu_cdna_op_V_CVT_PK_I16_I32, +amdgpu_cdna_op_V_CVT_PK_U16_U32, +amdgpu_cdna_op_V_CVT_PK_U8_F32, +amdgpu_cdna_op_V_CVT_RPI_I32_F32, +amdgpu_cdna_op_V_CVT_SR_BF8_F32, +amdgpu_cdna_op_V_CVT_SR_FP8_F32, +amdgpu_cdna_op_V_CVT_U16_F16, +amdgpu_cdna_op_V_CVT_U32_F32, +amdgpu_cdna_op_V_CVT_U32_F64, +amdgpu_cdna_op_V_DIV_FIXUP_F16, +amdgpu_cdna_op_V_DIV_FIXUP_F32, +amdgpu_cdna_op_V_DIV_FIXUP_F64, +amdgpu_cdna_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_cdna_op_V_DIV_FMAS_F32, +amdgpu_cdna_op_V_DIV_FMAS_F64, +amdgpu_cdna_op_V_DIV_SCALE_F32, +amdgpu_cdna_op_V_DIV_SCALE_F64, +amdgpu_cdna_op_V_DOT2C_F32_F16, +amdgpu_cdna_op_V_DOT2C_I32_I16, +amdgpu_cdna_op_V_DOT2_F32_F16, +amdgpu_cdna_op_V_DOT2_I32_I16, +amdgpu_cdna_op_V_DOT2_U32_U16, +amdgpu_cdna_op_V_DOT4C_I32_I8, +amdgpu_cdna_op_V_DOT4_I32_I8, +amdgpu_cdna_op_V_DOT4_U32_U8, +amdgpu_cdna_op_V_DOT8C_I32_I4, +amdgpu_cdna_op_V_DOT8_I32_I4, +amdgpu_cdna_op_V_DOT8_U32_U4, +amdgpu_cdna_op_V_EXP_F16, +amdgpu_cdna_op_V_EXP_F32, +amdgpu_cdna_op_V_EXP_LEGACY_F32, +amdgpu_cdna_op_V_FFBH_I32, +amdgpu_cdna_op_V_FFBH_U32, +amdgpu_cdna_op_V_FFBL_B32, +amdgpu_cdna_op_V_FLOOR_F16, +amdgpu_cdna_op_V_FLOOR_F32, +amdgpu_cdna_op_V_FLOOR_F64, +amdgpu_cdna_op_V_FMAAK_F32, +amdgpu_cdna_op_V_FMAC_F32, +amdgpu_cdna_op_V_FMAC_F64, +amdgpu_cdna_op_V_FMAMK_F32, +amdgpu_cdna_op_V_FMA_F16, +amdgpu_cdna_op_V_FMA_F32, +amdgpu_cdna_op_V_FMA_F64, +amdgpu_cdna_op_V_FMA_LEGACY_F16, +amdgpu_cdna_op_V_FRACT_F16, +amdgpu_cdna_op_V_FRACT_F32, +amdgpu_cdna_op_V_FRACT_F64, +amdgpu_cdna_op_V_FREXP_EXP_I16_F16, +amdgpu_cdna_op_V_FREXP_EXP_I32_F32, +amdgpu_cdna_op_V_FREXP_EXP_I32_F64, +amdgpu_cdna_op_V_FREXP_MANT_F16, +amdgpu_cdna_op_V_FREXP_MANT_F32, +amdgpu_cdna_op_V_FREXP_MANT_F64, +amdgpu_cdna_op_V_LDEXP_F16, +amdgpu_cdna_op_V_LDEXP_F32, +amdgpu_cdna_op_V_LDEXP_F64, +amdgpu_cdna_op_V_LERP_U8, +amdgpu_cdna_op_V_LOG_F16, +amdgpu_cdna_op_V_LOG_F32, +amdgpu_cdna_op_V_LOG_LEGACY_F32, +amdgpu_cdna_op_V_LSHLREV_B16, +amdgpu_cdna_op_V_LSHLREV_B32, +amdgpu_cdna_op_V_LSHLREV_B64, +amdgpu_cdna_op_V_LSHL_ADD_U32, +amdgpu_cdna_op_V_LSHL_ADD_U64, +amdgpu_cdna_op_V_LSHL_OR_B32, +amdgpu_cdna_op_V_LSHRREV_B16, +amdgpu_cdna_op_V_LSHRREV_B32, +amdgpu_cdna_op_V_LSHRREV_B64, +amdgpu_cdna_op_V_MAC_F16, +amdgpu_cdna_op_V_MADAK_F16, +amdgpu_cdna_op_V_MADMK_F16, +amdgpu_cdna_op_V_MAD_F16, +amdgpu_cdna_op_V_MAD_I16, +amdgpu_cdna_op_V_MAD_I32_I16, +amdgpu_cdna_op_V_MAD_I32_I24, +amdgpu_cdna_op_V_MAD_I64_I32, +amdgpu_cdna_op_V_MAD_LEGACY_F16, +amdgpu_cdna_op_V_MAD_LEGACY_I16, +amdgpu_cdna_op_V_MAD_LEGACY_U16, +amdgpu_cdna_op_V_MAD_MIXHI_F16, +amdgpu_cdna_op_V_MAD_MIXLO_F16, +amdgpu_cdna_op_V_MAD_MIX_F32, +amdgpu_cdna_op_V_MAD_U16, +amdgpu_cdna_op_V_MAD_U32_U16, +amdgpu_cdna_op_V_MAD_U32_U24, +amdgpu_cdna_op_V_MAD_U64_U32, +amdgpu_cdna_op_V_MAX3_F16, +amdgpu_cdna_op_V_MAX3_F32, +amdgpu_cdna_op_V_MAX3_I16, +amdgpu_cdna_op_V_MAX3_I32, +amdgpu_cdna_op_V_MAX3_U16, +amdgpu_cdna_op_V_MAX3_U32, +amdgpu_cdna_op_V_MAX_F16, +amdgpu_cdna_op_V_MAX_F32, +amdgpu_cdna_op_V_MAX_F64, +amdgpu_cdna_op_V_MAX_I16, +amdgpu_cdna_op_V_MAX_I32, +amdgpu_cdna_op_V_MAX_U16, +amdgpu_cdna_op_V_MAX_U32, +amdgpu_cdna_op_V_MBCNT_HI_U32_B32, +amdgpu_cdna_op_V_MBCNT_LO_U32_B32, +amdgpu_cdna_op_V_MED3_F16, +amdgpu_cdna_op_V_MED3_F32, +amdgpu_cdna_op_V_MED3_I16, +amdgpu_cdna_op_V_MED3_I32, +amdgpu_cdna_op_V_MED3_U16, +amdgpu_cdna_op_V_MED3_U32, +amdgpu_cdna_op_V_MFMA_F32_16X16X16_BF16, +amdgpu_cdna_op_V_MFMA_F32_16X16X16_F16, +amdgpu_cdna_op_V_MFMA_F32_16X16X1_4B_F32, +amdgpu_cdna_op_V_MFMA_F32_16X16X32_BF8_BF8, +amdgpu_cdna_op_V_MFMA_F32_16X16X32_BF8_FP8, +amdgpu_cdna_op_V_MFMA_F32_16X16X32_FP8_BF8, +amdgpu_cdna_op_V_MFMA_F32_16X16X32_FP8_FP8, +amdgpu_cdna_op_V_MFMA_F32_16X16X4_4B_BF16, +amdgpu_cdna_op_V_MFMA_F32_16X16X4_4B_F16, +amdgpu_cdna_op_V_MFMA_F32_16X16X4_F32, +amdgpu_cdna_op_V_MFMA_F32_16X16X8_XF32, +amdgpu_cdna_op_V_MFMA_F32_32X32X16_BF8_BF8, +amdgpu_cdna_op_V_MFMA_F32_32X32X16_BF8_FP8, +amdgpu_cdna_op_V_MFMA_F32_32X32X16_FP8_BF8, +amdgpu_cdna_op_V_MFMA_F32_32X32X16_FP8_FP8, +amdgpu_cdna_op_V_MFMA_F32_32X32X1_2B_F32, +amdgpu_cdna_op_V_MFMA_F32_32X32X2_F32, +amdgpu_cdna_op_V_MFMA_F32_32X32X4_2B_BF16, +amdgpu_cdna_op_V_MFMA_F32_32X32X4_2B_F16, +amdgpu_cdna_op_V_MFMA_F32_32X32X4_XF32, +amdgpu_cdna_op_V_MFMA_F32_32X32X8_BF16, +amdgpu_cdna_op_V_MFMA_F32_32X32X8_F16, +amdgpu_cdna_op_V_MFMA_F32_4X4X1_16B_F32, +amdgpu_cdna_op_V_MFMA_F32_4X4X4_16B_BF16, +amdgpu_cdna_op_V_MFMA_F32_4X4X4_16B_F16, +amdgpu_cdna_op_V_MFMA_F64_16X16X4_F64, +amdgpu_cdna_op_V_MFMA_F64_4X4X4_4B_F64, +amdgpu_cdna_op_V_MFMA_I32_16X16X32_I8, +amdgpu_cdna_op_V_MFMA_I32_16X16X4_4B_I8, +amdgpu_cdna_op_V_MFMA_I32_32X32X16_I8, +amdgpu_cdna_op_V_MFMA_I32_32X32X4_2B_I8, +amdgpu_cdna_op_V_MFMA_I32_4X4X4_16B_I8, +amdgpu_cdna_op_V_MIN3_F16, +amdgpu_cdna_op_V_MIN3_F32, +amdgpu_cdna_op_V_MIN3_I16, +amdgpu_cdna_op_V_MIN3_I32, +amdgpu_cdna_op_V_MIN3_U16, +amdgpu_cdna_op_V_MIN3_U32, +amdgpu_cdna_op_V_MIN_F16, +amdgpu_cdna_op_V_MIN_F32, +amdgpu_cdna_op_V_MIN_F64, +amdgpu_cdna_op_V_MIN_I16, +amdgpu_cdna_op_V_MIN_I32, +amdgpu_cdna_op_V_MIN_U16, +amdgpu_cdna_op_V_MIN_U32, +amdgpu_cdna_op_V_MOV_B32, +amdgpu_cdna_op_V_MOV_B64, +amdgpu_cdna_op_V_MQSAD_PK_U16_U8, +amdgpu_cdna_op_V_MQSAD_U32_U8, +amdgpu_cdna_op_V_MSAD_U8, +amdgpu_cdna_op_V_MUL_F16, +amdgpu_cdna_op_V_MUL_F32, +amdgpu_cdna_op_V_MUL_F64, +amdgpu_cdna_op_V_MUL_HI_I32, +amdgpu_cdna_op_V_MUL_HI_I32_I24, +amdgpu_cdna_op_V_MUL_HI_U32, +amdgpu_cdna_op_V_MUL_HI_U32_U24, +amdgpu_cdna_op_V_MUL_I32_I24, +amdgpu_cdna_op_V_MUL_LEGACY_F32, +amdgpu_cdna_op_V_MUL_LO_U16, +amdgpu_cdna_op_V_MUL_LO_U32, +amdgpu_cdna_op_V_MUL_U32_U24, +amdgpu_cdna_op_V_NOP, +amdgpu_cdna_op_V_NOT_B32, +amdgpu_cdna_op_V_OR3_B32, +amdgpu_cdna_op_V_OR_B32, +amdgpu_cdna_op_V_PACK_B32_F16, +amdgpu_cdna_op_V_PERM_B32, +amdgpu_cdna_op_V_PK_ADD_F16, +amdgpu_cdna_op_V_PK_ADD_F32, +amdgpu_cdna_op_V_PK_ADD_I16, +amdgpu_cdna_op_V_PK_ADD_U16, +amdgpu_cdna_op_V_PK_ASHRREV_I16, +amdgpu_cdna_op_V_PK_FMAC_F16, +amdgpu_cdna_op_V_PK_FMA_F16, +amdgpu_cdna_op_V_PK_FMA_F32, +amdgpu_cdna_op_V_PK_LSHLREV_B16, +amdgpu_cdna_op_V_PK_LSHRREV_B16, +amdgpu_cdna_op_V_PK_MAD_I16, +amdgpu_cdna_op_V_PK_MAD_U16, +amdgpu_cdna_op_V_PK_MAX_F16, +amdgpu_cdna_op_V_PK_MAX_I16, +amdgpu_cdna_op_V_PK_MAX_U16, +amdgpu_cdna_op_V_PK_MIN_F16, +amdgpu_cdna_op_V_PK_MIN_I16, +amdgpu_cdna_op_V_PK_MIN_U16, +amdgpu_cdna_op_V_PK_MOV_B32, +amdgpu_cdna_op_V_PK_MUL_F16, +amdgpu_cdna_op_V_PK_MUL_F32, +amdgpu_cdna_op_V_PK_MUL_LO_U16, +amdgpu_cdna_op_V_PK_SUB_I16, +amdgpu_cdna_op_V_PK_SUB_U16, +amdgpu_cdna_op_V_QSAD_PK_U16_U8, +amdgpu_cdna_op_V_RCP_F16, +amdgpu_cdna_op_V_RCP_F32, +amdgpu_cdna_op_V_RCP_F64, +amdgpu_cdna_op_V_RCP_IFLAG_F32, +amdgpu_cdna_op_V_READFIRSTLANE_B32, +amdgpu_cdna_op_V_READLANE_B32, +amdgpu_cdna_op_V_RNDNE_F16, +amdgpu_cdna_op_V_RNDNE_F32, +amdgpu_cdna_op_V_RNDNE_F64, +amdgpu_cdna_op_V_RSQ_F16, +amdgpu_cdna_op_V_RSQ_F32, +amdgpu_cdna_op_V_RSQ_F64, +amdgpu_cdna_op_V_SAD_HI_U8, +amdgpu_cdna_op_V_SAD_U16, +amdgpu_cdna_op_V_SAD_U32, +amdgpu_cdna_op_V_SAD_U8, +amdgpu_cdna_op_V_SAT_PK_U8_I16, +amdgpu_cdna_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_cdna_op_V_SIN_F16, +amdgpu_cdna_op_V_SIN_F32, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X32_BF16, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X32_F16, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_BF8_BF8, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_BF8_FP8, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_FP8_BF8, +amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_FP8_FP8, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X16_BF16, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X16_F16, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_BF8_BF8, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_BF8_FP8, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_FP8_BF8, +amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_FP8_FP8, +amdgpu_cdna_op_V_SMFMAC_I32_16X16X64_I8, +amdgpu_cdna_op_V_SMFMAC_I32_32X32X32_I8, +amdgpu_cdna_op_V_SQRT_F16, +amdgpu_cdna_op_V_SQRT_F32, +amdgpu_cdna_op_V_SQRT_F64, +amdgpu_cdna_op_V_SUBBREV_CO_U32, +amdgpu_cdna_op_V_SUBB_CO_U32, +amdgpu_cdna_op_V_SUBREV_CO_U32, +amdgpu_cdna_op_V_SUBREV_F16, +amdgpu_cdna_op_V_SUBREV_F32, +amdgpu_cdna_op_V_SUBREV_U16, +amdgpu_cdna_op_V_SUBREV_U32, +amdgpu_cdna_op_V_SUB_CO_U32, +amdgpu_cdna_op_V_SUB_F16, +amdgpu_cdna_op_V_SUB_F32, +amdgpu_cdna_op_V_SUB_I16, +amdgpu_cdna_op_V_SUB_I32, +amdgpu_cdna_op_V_SUB_U16, +amdgpu_cdna_op_V_SUB_U32, +amdgpu_cdna_op_V_SWAP_B32, +amdgpu_cdna_op_V_TRIG_PREOP_F64, +amdgpu_cdna_op_V_TRUNC_F16, +amdgpu_cdna_op_V_TRUNC_F32, +amdgpu_cdna_op_V_TRUNC_F64, +amdgpu_cdna_op_V_WRITELANE_B32, +amdgpu_cdna_op_V_XAD_U32, +amdgpu_cdna_op_V_XNOR_B32, +amdgpu_cdna_op_V_XOR_B32, diff --git a/common/h/amdgpu_cdna_sys_regs.h b/common/h/amdgpu_cdna_sys_regs.h new file mode 100644 index 0000000000..c90bf12e57 --- /dev/null +++ b/common/h/amdgpu_cdna_sys_regs.h @@ -0,0 +1,1563 @@ +#ifndef DYNINST_AMDGPU_CDNA_SYS_REGS_H +#define DYNINST_AMDGPU_CDNA_SYS_REGS_H +DEF_REGISTER(address_mode_32, Arch_amdgpu_cdna | HWR | BITS_32 | 0,"amdgpu_cdna"); +DEF_REGISTER(exec, Arch_amdgpu_cdna | HWR | BITS_64 | 1,"amdgpu_cdna"); +DEF_REGISTER(exec_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 1,"amdgpu_cdna"); +DEF_REGISTER(exec_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 1,"amdgpu_cdna"); +DEF_REGISTER(expcnt, Arch_amdgpu_cdna | HWR | BITS_3 | 2,"amdgpu_cdna"); +DEF_REGISTER(export_icount, Arch_amdgpu_cdna | HWR | BITS_8 | 3,"amdgpu_cdna"); +DEF_REGISTER(flat_scratch, Arch_amdgpu_cdna | HWR | BITS_64 | 4,"amdgpu_cdna"); +DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 4,"amdgpu_cdna"); +DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 4,"amdgpu_cdna"); +DEF_REGISTER(gpr_alloc, Arch_amdgpu_cdna | HWR | BITS_32 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr_base, Arch_amdgpu_cdna | 0x0 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpt_size, Arch_amdgpu_cdna | 0x80000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); +DEF_REGISTER(sgpr_base, Arch_amdgpu_cdna | 0x100000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); +DEF_REGISTER(sgpr_size, Arch_amdgpu_cdna | 0x180000 | BITS_4 | 0x8000 | 5,"amdgpu_cdna"); +DEF_REGISTER(ib_sts, Arch_amdgpu_cdna | HWR | BITS_32 | 6,"amdgpu_cdna"); +DEF_REGISTER(exp_cnt, Arch_amdgpu_cdna | 0x40000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna"); +DEF_REGISTER(lgkm_cnt, Arch_amdgpu_cdna | 0x80000 | BITS_4 | 0x8000 | 6,"amdgpu_cdna"); +DEF_REGISTER(valu_cnt, Arch_amdgpu_cdna | 0xc0000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna"); +DEF_REGISTER(vm_cnt, Arch_amdgpu_cdna | 0xf0000 | BITS_6 | 0x8000 | 6,"amdgpu_cdna"); +DEF_REGISTER(lds_alloc, Arch_amdgpu_cdna | HWR | BITS_32 | 7,"amdgpu_cdna"); +DEF_REGISTER(lds_base, Arch_amdgpu_cdna | 0x0 | BITS_8 | 0x8000 | 7,"amdgpu_cdna"); +DEF_REGISTER(lds_size, Arch_amdgpu_cdna | 0xc0000 | BITS_9 | 0x8000 | 7,"amdgpu_cdna"); +DEF_REGISTER(lds_gds_constant_message_count, Arch_amdgpu_cdna | HWR | BITS_8 | 8,"amdgpu_cdna"); +DEF_REGISTER(lgkmcnt, Arch_amdgpu_cdna | HWR | BITS_4 | 9,"amdgpu_cdna"); +DEF_REGISTER(m0, Arch_amdgpu_cdna | HWR | BITS_32 | 10,"amdgpu_cdna"); +DEF_REGISTER(gds_size, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(lds_direct_address, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(lds_interpolation_parameter_offset, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(lds_memory_vfetch_offset, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(lds_direct_data_type, Arch_amdgpu_cdna | 0x100000 | BITS_3 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(lds_interpolation_new_prim_mask, Arch_amdgpu_cdna | 0x100000 | BITS_15 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(gds_base, Arch_amdgpu_cdna | 0x100000 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); +DEF_REGISTER(mode, Arch_amdgpu_cdna | HWR | BITS_32 | 11,"amdgpu_cdna"); +DEF_REGISTER(fp_round, Arch_amdgpu_cdna | 0x0 | BITS_4 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(fp_denorm, Arch_amdgpu_cdna | 0x40000 | BITS_4 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(dx10_clamp, Arch_amdgpu_cdna | 0x80000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(ieee, Arch_amdgpu_cdna | 0x90000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(lod_clamped, Arch_amdgpu_cdna | 0xa0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(debug, Arch_amdgpu_cdna | 0xb0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(excp_en, Arch_amdgpu_cdna | 0xc0000 | BITS_7 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(fp16_ovfl, Arch_amdgpu_cdna | 0x170000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(pops_packer0, Arch_amdgpu_cdna | 0x180000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(pops_packer1, Arch_amdgpu_cdna | 0x190000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(disable_perf, Arch_amdgpu_cdna | 0x1a0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(gpr_idx_en, Arch_amdgpu_cdna | 0x1b0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(vskip, Arch_amdgpu_cdna | 0x1c0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(csp, Arch_amdgpu_cdna | 0x1d0000 | BITS_3 | 0x8000 | 11,"amdgpu_cdna"); +DEF_REGISTER(pc, Arch_amdgpu_cdna | PC | BITS_48 | 0,"amdgpu_cdna"); +DEF_REGISTER(pops_exiting_wave_id, Arch_amdgpu_cdna | HWR | BITS_64 | 12,"amdgpu_cdna"); +DEF_REGISTER(private_base, Arch_amdgpu_cdna | HWR | BITS_64 | 13,"amdgpu_cdna"); +DEF_REGISTER(private_limit, Arch_amdgpu_cdna | HWR | BITS_64 | 14,"amdgpu_cdna"); +DEF_REGISTER(shared_base, Arch_amdgpu_cdna | HWR | BITS_64 | 15,"amdgpu_cdna"); +DEF_REGISTER(shared_limit, Arch_amdgpu_cdna | HWR | BITS_64 | 16,"amdgpu_cdna"); +DEF_REGISTER(status, Arch_amdgpu_cdna | HWR | BITS_32 | 17,"amdgpu_cdna"); +DEF_REGISTER(scc, Arch_amdgpu_cdna | 0x0 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(spi_prio, Arch_amdgpu_cdna | 0x10000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(wave_prio, Arch_amdgpu_cdna | 0x30000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(priv, Arch_amdgpu_cdna | 0x50000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(trap_en, Arch_amdgpu_cdna | 0x60000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(ttrace_en, Arch_amdgpu_cdna | 0x70000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(export_rdy, Arch_amdgpu_cdna | 0x80000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(execz, Arch_amdgpu_cdna | 0x90000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(vccz, Arch_amdgpu_cdna | 0xa0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(in_tg, Arch_amdgpu_cdna | 0xb0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(in_barrier, Arch_amdgpu_cdna | 0xc0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(halt, Arch_amdgpu_cdna | 0xd0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(trap, Arch_amdgpu_cdna | 0xe0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(ttrace_cu_en, Arch_amdgpu_cdna | 0xf0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(valid, Arch_amdgpu_cdna | 0x100000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(ecc_err, Arch_amdgpu_cdna | 0x110000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(skin_export, Arch_amdgpu_cdna | 0x120000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(perf_en, Arch_amdgpu_cdna | 0x130000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(cond_dbg_user, Arch_amdgpu_cdna | 0x140000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(cond_dbg_sys, Arch_amdgpu_cdna | 0x150000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(allow_replay, Arch_amdgpu_cdna | 0x160000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(must_export, Arch_amdgpu_cdna | 0x1b0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); +DEF_REGISTER(tba, Arch_amdgpu_cdna | HWR | BITS_64 | 18,"amdgpu_cdna"); +DEF_REGISTER(tid, Arch_amdgpu_cdna | HWR | BITS_32 | 19,"amdgpu_cdna"); +DEF_REGISTER(tma, Arch_amdgpu_cdna | HWR | BITS_64 | 20,"amdgpu_cdna"); +DEF_REGISTER(trap_base_address, Arch_amdgpu_cdna | HWR | BITS_64 | 21,"amdgpu_cdna"); +DEF_REGISTER(trap_memory_address, Arch_amdgpu_cdna | HWR | BITS_64 | 22,"amdgpu_cdna"); +DEF_REGISTER(ttmp0, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 0,"amdgpu_cdna"); +DEF_REGISTER(ttmp1, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 1,"amdgpu_cdna"); +DEF_REGISTER(ttmp10, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 2,"amdgpu_cdna"); +DEF_REGISTER(ttmp11, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 3,"amdgpu_cdna"); +DEF_REGISTER(ttmp12, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 4,"amdgpu_cdna"); +DEF_REGISTER(ttmp13, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 5,"amdgpu_cdna"); +DEF_REGISTER(ttmp14, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 6,"amdgpu_cdna"); +DEF_REGISTER(ttmp15, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 7,"amdgpu_cdna"); +DEF_REGISTER(ttmp2, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 8,"amdgpu_cdna"); +DEF_REGISTER(ttmp3, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 9,"amdgpu_cdna"); +DEF_REGISTER(ttmp4, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 10,"amdgpu_cdna"); +DEF_REGISTER(ttmp5, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 11,"amdgpu_cdna"); +DEF_REGISTER(ttmp6, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 12,"amdgpu_cdna"); +DEF_REGISTER(ttmp7, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 13,"amdgpu_cdna"); +DEF_REGISTER(ttmp8, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 14,"amdgpu_cdna"); +DEF_REGISTER(ttmp9, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 15,"amdgpu_cdna"); +DEF_REGISTER(vcc, Arch_amdgpu_cdna | HWR | BITS_64 | 23,"amdgpu_cdna"); +DEF_REGISTER(vcc_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 23,"amdgpu_cdna"); +DEF_REGISTER(vcc_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 23,"amdgpu_cdna"); +DEF_REGISTER(vectory_memory_icount, Arch_amdgpu_cdna | HWR | BITS_8 | 24,"amdgpu_cdna"); +DEF_REGISTER(vmcnt, Arch_amdgpu_cdna | HWR | BITS_6 | 25,"amdgpu_cdna"); +DEF_REGISTER(xnack_mask, Arch_amdgpu_cdna | HWR | BITS_64 | 26,"amdgpu_cdna"); +DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 26,"amdgpu_cdna"); +DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 26,"amdgpu_cdna"); +DEF_REGISTER(sgpr0, Arch_amdgpu_cdna | SGPR | BITS_32 | 0,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_0, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_0, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_0, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_0, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna"); +DEF_REGISTER(sgpr1, Arch_amdgpu_cdna | SGPR | BITS_32 | 1,"amdgpu_cdna"); +DEF_REGISTER(sgpr2, Arch_amdgpu_cdna | SGPR | BITS_32 | 2,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_2, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna"); +DEF_REGISTER(sgpr3, Arch_amdgpu_cdna | SGPR | BITS_32 | 3,"amdgpu_cdna"); +DEF_REGISTER(sgpr4, Arch_amdgpu_cdna | SGPR | BITS_32 | 4,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_4, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_4, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna"); +DEF_REGISTER(sgpr5, Arch_amdgpu_cdna | SGPR | BITS_32 | 5,"amdgpu_cdna"); +DEF_REGISTER(sgpr6, Arch_amdgpu_cdna | SGPR | BITS_32 | 6,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_6, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna"); +DEF_REGISTER(sgpr7, Arch_amdgpu_cdna | SGPR | BITS_32 | 7,"amdgpu_cdna"); +DEF_REGISTER(sgpr8, Arch_amdgpu_cdna | SGPR | BITS_32 | 8,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_8, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_8, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_8, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna"); +DEF_REGISTER(sgpr9, Arch_amdgpu_cdna | SGPR | BITS_32 | 9,"amdgpu_cdna"); +DEF_REGISTER(sgpr10, Arch_amdgpu_cdna | SGPR | BITS_32 | 10,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_10, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna"); +DEF_REGISTER(sgpr11, Arch_amdgpu_cdna | SGPR | BITS_32 | 11,"amdgpu_cdna"); +DEF_REGISTER(sgpr12, Arch_amdgpu_cdna | SGPR | BITS_32 | 12,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_12, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_12, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna"); +DEF_REGISTER(sgpr13, Arch_amdgpu_cdna | SGPR | BITS_32 | 13,"amdgpu_cdna"); +DEF_REGISTER(sgpr14, Arch_amdgpu_cdna | SGPR | BITS_32 | 14,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_14, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna"); +DEF_REGISTER(sgpr15, Arch_amdgpu_cdna | SGPR | BITS_32 | 15,"amdgpu_cdna"); +DEF_REGISTER(sgpr16, Arch_amdgpu_cdna | SGPR | BITS_32 | 16,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_16, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_16, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_16, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_16, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna"); +DEF_REGISTER(sgpr17, Arch_amdgpu_cdna | SGPR | BITS_32 | 17,"amdgpu_cdna"); +DEF_REGISTER(sgpr18, Arch_amdgpu_cdna | SGPR | BITS_32 | 18,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_18, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna"); +DEF_REGISTER(sgpr19, Arch_amdgpu_cdna | SGPR | BITS_32 | 19,"amdgpu_cdna"); +DEF_REGISTER(sgpr20, Arch_amdgpu_cdna | SGPR | BITS_32 | 20,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_20, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_20, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna"); +DEF_REGISTER(sgpr21, Arch_amdgpu_cdna | SGPR | BITS_32 | 21,"amdgpu_cdna"); +DEF_REGISTER(sgpr22, Arch_amdgpu_cdna | SGPR | BITS_32 | 22,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_22, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna"); +DEF_REGISTER(sgpr23, Arch_amdgpu_cdna | SGPR | BITS_32 | 23,"amdgpu_cdna"); +DEF_REGISTER(sgpr24, Arch_amdgpu_cdna | SGPR | BITS_32 | 24,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_24, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_24, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_24, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna"); +DEF_REGISTER(sgpr25, Arch_amdgpu_cdna | SGPR | BITS_32 | 25,"amdgpu_cdna"); +DEF_REGISTER(sgpr26, Arch_amdgpu_cdna | SGPR | BITS_32 | 26,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_26, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna"); +DEF_REGISTER(sgpr27, Arch_amdgpu_cdna | SGPR | BITS_32 | 27,"amdgpu_cdna"); +DEF_REGISTER(sgpr28, Arch_amdgpu_cdna | SGPR | BITS_32 | 28,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_28, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_28, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna"); +DEF_REGISTER(sgpr29, Arch_amdgpu_cdna | SGPR | BITS_32 | 29,"amdgpu_cdna"); +DEF_REGISTER(sgpr30, Arch_amdgpu_cdna | SGPR | BITS_32 | 30,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_30, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna"); +DEF_REGISTER(sgpr31, Arch_amdgpu_cdna | SGPR | BITS_32 | 31,"amdgpu_cdna"); +DEF_REGISTER(sgpr32, Arch_amdgpu_cdna | SGPR | BITS_32 | 32,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_32, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_32, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_32, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_32, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna"); +DEF_REGISTER(sgpr33, Arch_amdgpu_cdna | SGPR | BITS_32 | 33,"amdgpu_cdna"); +DEF_REGISTER(sgpr34, Arch_amdgpu_cdna | SGPR | BITS_32 | 34,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_34, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna"); +DEF_REGISTER(sgpr35, Arch_amdgpu_cdna | SGPR | BITS_32 | 35,"amdgpu_cdna"); +DEF_REGISTER(sgpr36, Arch_amdgpu_cdna | SGPR | BITS_32 | 36,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_36, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_36, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna"); +DEF_REGISTER(sgpr37, Arch_amdgpu_cdna | SGPR | BITS_32 | 37,"amdgpu_cdna"); +DEF_REGISTER(sgpr38, Arch_amdgpu_cdna | SGPR | BITS_32 | 38,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_38, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna"); +DEF_REGISTER(sgpr39, Arch_amdgpu_cdna | SGPR | BITS_32 | 39,"amdgpu_cdna"); +DEF_REGISTER(sgpr40, Arch_amdgpu_cdna | SGPR | BITS_32 | 40,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_40, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_40, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_40, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna"); +DEF_REGISTER(sgpr41, Arch_amdgpu_cdna | SGPR | BITS_32 | 41,"amdgpu_cdna"); +DEF_REGISTER(sgpr42, Arch_amdgpu_cdna | SGPR | BITS_32 | 42,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_42, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna"); +DEF_REGISTER(sgpr43, Arch_amdgpu_cdna | SGPR | BITS_32 | 43,"amdgpu_cdna"); +DEF_REGISTER(sgpr44, Arch_amdgpu_cdna | SGPR | BITS_32 | 44,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_44, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_44, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna"); +DEF_REGISTER(sgpr45, Arch_amdgpu_cdna | SGPR | BITS_32 | 45,"amdgpu_cdna"); +DEF_REGISTER(sgpr46, Arch_amdgpu_cdna | SGPR | BITS_32 | 46,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_46, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna"); +DEF_REGISTER(sgpr47, Arch_amdgpu_cdna | SGPR | BITS_32 | 47,"amdgpu_cdna"); +DEF_REGISTER(sgpr48, Arch_amdgpu_cdna | SGPR | BITS_32 | 48,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_48, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_48, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_48, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_48, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna"); +DEF_REGISTER(sgpr49, Arch_amdgpu_cdna | SGPR | BITS_32 | 49,"amdgpu_cdna"); +DEF_REGISTER(sgpr50, Arch_amdgpu_cdna | SGPR | BITS_32 | 50,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_50, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna"); +DEF_REGISTER(sgpr51, Arch_amdgpu_cdna | SGPR | BITS_32 | 51,"amdgpu_cdna"); +DEF_REGISTER(sgpr52, Arch_amdgpu_cdna | SGPR | BITS_32 | 52,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_52, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_52, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna"); +DEF_REGISTER(sgpr53, Arch_amdgpu_cdna | SGPR | BITS_32 | 53,"amdgpu_cdna"); +DEF_REGISTER(sgpr54, Arch_amdgpu_cdna | SGPR | BITS_32 | 54,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_54, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna"); +DEF_REGISTER(sgpr55, Arch_amdgpu_cdna | SGPR | BITS_32 | 55,"amdgpu_cdna"); +DEF_REGISTER(sgpr56, Arch_amdgpu_cdna | SGPR | BITS_32 | 56,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_56, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_56, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_56, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna"); +DEF_REGISTER(sgpr57, Arch_amdgpu_cdna | SGPR | BITS_32 | 57,"amdgpu_cdna"); +DEF_REGISTER(sgpr58, Arch_amdgpu_cdna | SGPR | BITS_32 | 58,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_58, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna"); +DEF_REGISTER(sgpr59, Arch_amdgpu_cdna | SGPR | BITS_32 | 59,"amdgpu_cdna"); +DEF_REGISTER(sgpr60, Arch_amdgpu_cdna | SGPR | BITS_32 | 60,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_60, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_60, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna"); +DEF_REGISTER(sgpr61, Arch_amdgpu_cdna | SGPR | BITS_32 | 61,"amdgpu_cdna"); +DEF_REGISTER(sgpr62, Arch_amdgpu_cdna | SGPR | BITS_32 | 62,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_62, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna"); +DEF_REGISTER(sgpr63, Arch_amdgpu_cdna | SGPR | BITS_32 | 63,"amdgpu_cdna"); +DEF_REGISTER(sgpr64, Arch_amdgpu_cdna | SGPR | BITS_32 | 64,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_64, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_64, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_64, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_64, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna"); +DEF_REGISTER(sgpr65, Arch_amdgpu_cdna | SGPR | BITS_32 | 65,"amdgpu_cdna"); +DEF_REGISTER(sgpr66, Arch_amdgpu_cdna | SGPR | BITS_32 | 66,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_66, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna"); +DEF_REGISTER(sgpr67, Arch_amdgpu_cdna | SGPR | BITS_32 | 67,"amdgpu_cdna"); +DEF_REGISTER(sgpr68, Arch_amdgpu_cdna | SGPR | BITS_32 | 68,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_68, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_68, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna"); +DEF_REGISTER(sgpr69, Arch_amdgpu_cdna | SGPR | BITS_32 | 69,"amdgpu_cdna"); +DEF_REGISTER(sgpr70, Arch_amdgpu_cdna | SGPR | BITS_32 | 70,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_70, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna"); +DEF_REGISTER(sgpr71, Arch_amdgpu_cdna | SGPR | BITS_32 | 71,"amdgpu_cdna"); +DEF_REGISTER(sgpr72, Arch_amdgpu_cdna | SGPR | BITS_32 | 72,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_72, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_72, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_72, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna"); +DEF_REGISTER(sgpr73, Arch_amdgpu_cdna | SGPR | BITS_32 | 73,"amdgpu_cdna"); +DEF_REGISTER(sgpr74, Arch_amdgpu_cdna | SGPR | BITS_32 | 74,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_74, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna"); +DEF_REGISTER(sgpr75, Arch_amdgpu_cdna | SGPR | BITS_32 | 75,"amdgpu_cdna"); +DEF_REGISTER(sgpr76, Arch_amdgpu_cdna | SGPR | BITS_32 | 76,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_76, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_76, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna"); +DEF_REGISTER(sgpr77, Arch_amdgpu_cdna | SGPR | BITS_32 | 77,"amdgpu_cdna"); +DEF_REGISTER(sgpr78, Arch_amdgpu_cdna | SGPR | BITS_32 | 78,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_78, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna"); +DEF_REGISTER(sgpr79, Arch_amdgpu_cdna | SGPR | BITS_32 | 79,"amdgpu_cdna"); +DEF_REGISTER(sgpr80, Arch_amdgpu_cdna | SGPR | BITS_32 | 80,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_80, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_80, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_80, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec16_80, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna"); +DEF_REGISTER(sgpr81, Arch_amdgpu_cdna | SGPR | BITS_32 | 81,"amdgpu_cdna"); +DEF_REGISTER(sgpr82, Arch_amdgpu_cdna | SGPR | BITS_32 | 82,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_82, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna"); +DEF_REGISTER(sgpr83, Arch_amdgpu_cdna | SGPR | BITS_32 | 83,"amdgpu_cdna"); +DEF_REGISTER(sgpr84, Arch_amdgpu_cdna | SGPR | BITS_32 | 84,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_84, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_84, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna"); +DEF_REGISTER(sgpr85, Arch_amdgpu_cdna | SGPR | BITS_32 | 85,"amdgpu_cdna"); +DEF_REGISTER(sgpr86, Arch_amdgpu_cdna | SGPR | BITS_32 | 86,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_86, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna"); +DEF_REGISTER(sgpr87, Arch_amdgpu_cdna | SGPR | BITS_32 | 87,"amdgpu_cdna"); +DEF_REGISTER(sgpr88, Arch_amdgpu_cdna | SGPR | BITS_32 | 88,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_88, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_88, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_88, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna"); +DEF_REGISTER(sgpr89, Arch_amdgpu_cdna | SGPR | BITS_32 | 89,"amdgpu_cdna"); +DEF_REGISTER(sgpr90, Arch_amdgpu_cdna | SGPR | BITS_32 | 90,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_90, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna"); +DEF_REGISTER(sgpr91, Arch_amdgpu_cdna | SGPR | BITS_32 | 91,"amdgpu_cdna"); +DEF_REGISTER(sgpr92, Arch_amdgpu_cdna | SGPR | BITS_32 | 92,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_92, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_92, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna"); +DEF_REGISTER(sgpr93, Arch_amdgpu_cdna | SGPR | BITS_32 | 93,"amdgpu_cdna"); +DEF_REGISTER(sgpr94, Arch_amdgpu_cdna | SGPR | BITS_32 | 94,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_94, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna"); +DEF_REGISTER(sgpr95, Arch_amdgpu_cdna | SGPR | BITS_32 | 95,"amdgpu_cdna"); +DEF_REGISTER(sgpr96, Arch_amdgpu_cdna | SGPR | BITS_32 | 96,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_96, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_96, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec8_96, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna"); +DEF_REGISTER(sgpr97, Arch_amdgpu_cdna | SGPR | BITS_32 | 97,"amdgpu_cdna"); +DEF_REGISTER(sgpr98, Arch_amdgpu_cdna | SGPR | BITS_32 | 98,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_98, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna"); +DEF_REGISTER(sgpr99, Arch_amdgpu_cdna | SGPR | BITS_32 | 99,"amdgpu_cdna"); +DEF_REGISTER(sgpr100, Arch_amdgpu_cdna | SGPR | BITS_32 | 100,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_100, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec4_100, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna"); +DEF_REGISTER(sgpr101, Arch_amdgpu_cdna | SGPR | BITS_32 | 101,"amdgpu_cdna"); +DEF_REGISTER(sgpr102, Arch_amdgpu_cdna | SGPR | BITS_32 | 102,"amdgpu_cdna"); +DEF_REGISTER(sgpr_vec2_102, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna"); +DEF_REGISTER(sgpr103, Arch_amdgpu_cdna | SGPR | BITS_32 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr0, Arch_amdgpu_cdna | VGPR | BITS_32 | 0,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_0, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_0, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_0, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_0, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna"); +DEF_REGISTER(vgpr1, Arch_amdgpu_cdna | VGPR | BITS_32 | 1,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_1, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 1,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_1, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 1,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_1, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 1,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_1, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 1,"amdgpu_cdna"); +DEF_REGISTER(vgpr2, Arch_amdgpu_cdna | VGPR | BITS_32 | 2,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_2, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_2, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 2,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_2, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 2,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_2, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 2,"amdgpu_cdna"); +DEF_REGISTER(vgpr3, Arch_amdgpu_cdna | VGPR | BITS_32 | 3,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_3, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 3,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_3, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 3,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_3, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 3,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_3, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 3,"amdgpu_cdna"); +DEF_REGISTER(vgpr4, Arch_amdgpu_cdna | VGPR | BITS_32 | 4,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_4, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_4, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_4, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 4,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_4, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 4,"amdgpu_cdna"); +DEF_REGISTER(vgpr5, Arch_amdgpu_cdna | VGPR | BITS_32 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_5, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_5, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_5, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_5, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 5,"amdgpu_cdna"); +DEF_REGISTER(vgpr6, Arch_amdgpu_cdna | VGPR | BITS_32 | 6,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_6, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_6, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 6,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_6, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 6,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_6, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 6,"amdgpu_cdna"); +DEF_REGISTER(vgpr7, Arch_amdgpu_cdna | VGPR | BITS_32 | 7,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_7, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 7,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_7, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 7,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_7, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 7,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_7, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 7,"amdgpu_cdna"); +DEF_REGISTER(vgpr8, Arch_amdgpu_cdna | VGPR | BITS_32 | 8,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_8, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_8, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_8, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_8, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 8,"amdgpu_cdna"); +DEF_REGISTER(vgpr9, Arch_amdgpu_cdna | VGPR | BITS_32 | 9,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_9, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 9,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_9, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 9,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_9, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 9,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_9, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 9,"amdgpu_cdna"); +DEF_REGISTER(vgpr10, Arch_amdgpu_cdna | VGPR | BITS_32 | 10,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_10, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_10, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 10,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_10, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 10,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_10, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 10,"amdgpu_cdna"); +DEF_REGISTER(vgpr11, Arch_amdgpu_cdna | VGPR | BITS_32 | 11,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_11, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 11,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_11, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 11,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_11, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 11,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_11, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 11,"amdgpu_cdna"); +DEF_REGISTER(vgpr12, Arch_amdgpu_cdna | VGPR | BITS_32 | 12,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_12, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_12, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_12, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 12,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_12, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 12,"amdgpu_cdna"); +DEF_REGISTER(vgpr13, Arch_amdgpu_cdna | VGPR | BITS_32 | 13,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_13, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 13,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_13, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 13,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_13, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 13,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_13, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 13,"amdgpu_cdna"); +DEF_REGISTER(vgpr14, Arch_amdgpu_cdna | VGPR | BITS_32 | 14,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_14, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_14, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 14,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_14, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 14,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_14, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 14,"amdgpu_cdna"); +DEF_REGISTER(vgpr15, Arch_amdgpu_cdna | VGPR | BITS_32 | 15,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_15, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 15,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_15, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 15,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_15, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 15,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_15, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 15,"amdgpu_cdna"); +DEF_REGISTER(vgpr16, Arch_amdgpu_cdna | VGPR | BITS_32 | 16,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_16, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_16, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_16, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_16, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna"); +DEF_REGISTER(vgpr17, Arch_amdgpu_cdna | VGPR | BITS_32 | 17,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_17, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 17,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_17, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 17,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_17, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 17,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_17, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 17,"amdgpu_cdna"); +DEF_REGISTER(vgpr18, Arch_amdgpu_cdna | VGPR | BITS_32 | 18,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_18, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_18, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 18,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_18, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 18,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_18, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 18,"amdgpu_cdna"); +DEF_REGISTER(vgpr19, Arch_amdgpu_cdna | VGPR | BITS_32 | 19,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_19, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 19,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_19, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 19,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_19, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 19,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_19, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 19,"amdgpu_cdna"); +DEF_REGISTER(vgpr20, Arch_amdgpu_cdna | VGPR | BITS_32 | 20,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_20, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_20, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_20, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 20,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_20, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 20,"amdgpu_cdna"); +DEF_REGISTER(vgpr21, Arch_amdgpu_cdna | VGPR | BITS_32 | 21,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_21, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 21,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_21, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 21,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_21, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 21,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_21, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 21,"amdgpu_cdna"); +DEF_REGISTER(vgpr22, Arch_amdgpu_cdna | VGPR | BITS_32 | 22,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_22, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_22, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 22,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_22, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 22,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_22, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 22,"amdgpu_cdna"); +DEF_REGISTER(vgpr23, Arch_amdgpu_cdna | VGPR | BITS_32 | 23,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_23, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 23,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_23, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 23,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_23, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 23,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_23, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 23,"amdgpu_cdna"); +DEF_REGISTER(vgpr24, Arch_amdgpu_cdna | VGPR | BITS_32 | 24,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_24, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_24, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_24, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_24, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 24,"amdgpu_cdna"); +DEF_REGISTER(vgpr25, Arch_amdgpu_cdna | VGPR | BITS_32 | 25,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_25, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 25,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_25, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 25,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_25, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 25,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_25, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 25,"amdgpu_cdna"); +DEF_REGISTER(vgpr26, Arch_amdgpu_cdna | VGPR | BITS_32 | 26,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_26, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_26, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 26,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_26, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 26,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_26, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 26,"amdgpu_cdna"); +DEF_REGISTER(vgpr27, Arch_amdgpu_cdna | VGPR | BITS_32 | 27,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_27, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 27,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_27, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 27,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_27, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 27,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_27, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 27,"amdgpu_cdna"); +DEF_REGISTER(vgpr28, Arch_amdgpu_cdna | VGPR | BITS_32 | 28,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_28, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_28, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_28, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 28,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_28, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 28,"amdgpu_cdna"); +DEF_REGISTER(vgpr29, Arch_amdgpu_cdna | VGPR | BITS_32 | 29,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_29, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 29,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_29, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 29,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_29, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 29,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_29, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 29,"amdgpu_cdna"); +DEF_REGISTER(vgpr30, Arch_amdgpu_cdna | VGPR | BITS_32 | 30,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_30, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_30, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 30,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_30, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 30,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_30, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 30,"amdgpu_cdna"); +DEF_REGISTER(vgpr31, Arch_amdgpu_cdna | VGPR | BITS_32 | 31,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_31, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 31,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_31, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 31,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_31, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 31,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_31, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 31,"amdgpu_cdna"); +DEF_REGISTER(vgpr32, Arch_amdgpu_cdna | VGPR | BITS_32 | 32,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_32, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_32, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_32, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_32, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna"); +DEF_REGISTER(vgpr33, Arch_amdgpu_cdna | VGPR | BITS_32 | 33,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_33, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 33,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_33, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 33,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_33, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 33,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_33, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 33,"amdgpu_cdna"); +DEF_REGISTER(vgpr34, Arch_amdgpu_cdna | VGPR | BITS_32 | 34,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_34, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_34, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 34,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_34, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 34,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_34, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 34,"amdgpu_cdna"); +DEF_REGISTER(vgpr35, Arch_amdgpu_cdna | VGPR | BITS_32 | 35,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_35, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 35,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_35, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 35,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_35, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 35,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_35, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 35,"amdgpu_cdna"); +DEF_REGISTER(vgpr36, Arch_amdgpu_cdna | VGPR | BITS_32 | 36,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_36, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_36, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_36, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 36,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_36, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 36,"amdgpu_cdna"); +DEF_REGISTER(vgpr37, Arch_amdgpu_cdna | VGPR | BITS_32 | 37,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_37, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 37,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_37, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 37,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_37, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 37,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_37, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 37,"amdgpu_cdna"); +DEF_REGISTER(vgpr38, Arch_amdgpu_cdna | VGPR | BITS_32 | 38,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_38, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_38, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 38,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_38, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 38,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_38, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 38,"amdgpu_cdna"); +DEF_REGISTER(vgpr39, Arch_amdgpu_cdna | VGPR | BITS_32 | 39,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_39, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 39,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_39, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 39,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_39, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 39,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_39, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 39,"amdgpu_cdna"); +DEF_REGISTER(vgpr40, Arch_amdgpu_cdna | VGPR | BITS_32 | 40,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_40, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_40, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_40, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_40, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 40,"amdgpu_cdna"); +DEF_REGISTER(vgpr41, Arch_amdgpu_cdna | VGPR | BITS_32 | 41,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_41, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 41,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_41, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 41,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_41, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 41,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_41, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 41,"amdgpu_cdna"); +DEF_REGISTER(vgpr42, Arch_amdgpu_cdna | VGPR | BITS_32 | 42,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_42, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_42, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 42,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_42, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 42,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_42, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 42,"amdgpu_cdna"); +DEF_REGISTER(vgpr43, Arch_amdgpu_cdna | VGPR | BITS_32 | 43,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_43, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 43,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_43, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 43,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_43, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 43,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_43, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 43,"amdgpu_cdna"); +DEF_REGISTER(vgpr44, Arch_amdgpu_cdna | VGPR | BITS_32 | 44,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_44, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_44, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_44, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 44,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_44, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 44,"amdgpu_cdna"); +DEF_REGISTER(vgpr45, Arch_amdgpu_cdna | VGPR | BITS_32 | 45,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_45, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 45,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_45, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 45,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_45, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 45,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_45, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 45,"amdgpu_cdna"); +DEF_REGISTER(vgpr46, Arch_amdgpu_cdna | VGPR | BITS_32 | 46,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_46, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_46, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 46,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_46, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 46,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_46, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 46,"amdgpu_cdna"); +DEF_REGISTER(vgpr47, Arch_amdgpu_cdna | VGPR | BITS_32 | 47,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_47, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 47,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_47, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 47,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_47, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 47,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_47, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 47,"amdgpu_cdna"); +DEF_REGISTER(vgpr48, Arch_amdgpu_cdna | VGPR | BITS_32 | 48,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_48, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_48, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_48, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_48, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna"); +DEF_REGISTER(vgpr49, Arch_amdgpu_cdna | VGPR | BITS_32 | 49,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_49, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 49,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_49, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 49,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_49, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 49,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_49, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 49,"amdgpu_cdna"); +DEF_REGISTER(vgpr50, Arch_amdgpu_cdna | VGPR | BITS_32 | 50,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_50, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_50, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 50,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_50, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 50,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_50, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 50,"amdgpu_cdna"); +DEF_REGISTER(vgpr51, Arch_amdgpu_cdna | VGPR | BITS_32 | 51,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_51, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 51,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_51, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 51,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_51, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 51,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_51, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 51,"amdgpu_cdna"); +DEF_REGISTER(vgpr52, Arch_amdgpu_cdna | VGPR | BITS_32 | 52,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_52, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_52, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_52, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 52,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_52, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 52,"amdgpu_cdna"); +DEF_REGISTER(vgpr53, Arch_amdgpu_cdna | VGPR | BITS_32 | 53,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_53, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 53,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_53, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 53,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_53, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 53,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_53, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 53,"amdgpu_cdna"); +DEF_REGISTER(vgpr54, Arch_amdgpu_cdna | VGPR | BITS_32 | 54,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_54, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_54, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 54,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_54, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 54,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_54, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 54,"amdgpu_cdna"); +DEF_REGISTER(vgpr55, Arch_amdgpu_cdna | VGPR | BITS_32 | 55,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_55, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 55,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_55, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 55,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_55, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 55,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_55, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 55,"amdgpu_cdna"); +DEF_REGISTER(vgpr56, Arch_amdgpu_cdna | VGPR | BITS_32 | 56,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_56, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_56, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_56, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_56, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 56,"amdgpu_cdna"); +DEF_REGISTER(vgpr57, Arch_amdgpu_cdna | VGPR | BITS_32 | 57,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_57, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 57,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_57, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 57,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_57, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 57,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_57, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 57,"amdgpu_cdna"); +DEF_REGISTER(vgpr58, Arch_amdgpu_cdna | VGPR | BITS_32 | 58,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_58, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_58, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 58,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_58, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 58,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_58, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 58,"amdgpu_cdna"); +DEF_REGISTER(vgpr59, Arch_amdgpu_cdna | VGPR | BITS_32 | 59,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_59, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 59,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_59, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 59,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_59, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 59,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_59, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 59,"amdgpu_cdna"); +DEF_REGISTER(vgpr60, Arch_amdgpu_cdna | VGPR | BITS_32 | 60,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_60, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_60, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_60, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 60,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_60, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 60,"amdgpu_cdna"); +DEF_REGISTER(vgpr61, Arch_amdgpu_cdna | VGPR | BITS_32 | 61,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_61, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 61,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_61, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 61,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_61, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 61,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_61, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 61,"amdgpu_cdna"); +DEF_REGISTER(vgpr62, Arch_amdgpu_cdna | VGPR | BITS_32 | 62,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_62, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_62, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 62,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_62, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 62,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_62, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 62,"amdgpu_cdna"); +DEF_REGISTER(vgpr63, Arch_amdgpu_cdna | VGPR | BITS_32 | 63,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_63, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 63,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_63, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 63,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_63, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 63,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_63, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 63,"amdgpu_cdna"); +DEF_REGISTER(vgpr64, Arch_amdgpu_cdna | VGPR | BITS_32 | 64,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_64, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_64, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_64, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_64, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna"); +DEF_REGISTER(vgpr65, Arch_amdgpu_cdna | VGPR | BITS_32 | 65,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_65, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 65,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_65, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 65,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_65, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 65,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_65, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 65,"amdgpu_cdna"); +DEF_REGISTER(vgpr66, Arch_amdgpu_cdna | VGPR | BITS_32 | 66,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_66, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_66, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 66,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_66, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 66,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_66, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 66,"amdgpu_cdna"); +DEF_REGISTER(vgpr67, Arch_amdgpu_cdna | VGPR | BITS_32 | 67,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_67, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 67,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_67, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 67,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_67, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 67,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_67, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 67,"amdgpu_cdna"); +DEF_REGISTER(vgpr68, Arch_amdgpu_cdna | VGPR | BITS_32 | 68,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_68, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_68, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_68, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 68,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_68, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 68,"amdgpu_cdna"); +DEF_REGISTER(vgpr69, Arch_amdgpu_cdna | VGPR | BITS_32 | 69,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_69, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 69,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_69, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 69,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_69, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 69,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_69, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 69,"amdgpu_cdna"); +DEF_REGISTER(vgpr70, Arch_amdgpu_cdna | VGPR | BITS_32 | 70,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_70, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_70, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 70,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_70, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 70,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_70, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 70,"amdgpu_cdna"); +DEF_REGISTER(vgpr71, Arch_amdgpu_cdna | VGPR | BITS_32 | 71,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_71, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 71,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_71, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 71,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_71, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 71,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_71, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 71,"amdgpu_cdna"); +DEF_REGISTER(vgpr72, Arch_amdgpu_cdna | VGPR | BITS_32 | 72,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_72, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_72, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_72, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_72, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 72,"amdgpu_cdna"); +DEF_REGISTER(vgpr73, Arch_amdgpu_cdna | VGPR | BITS_32 | 73,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_73, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 73,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_73, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 73,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_73, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 73,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_73, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 73,"amdgpu_cdna"); +DEF_REGISTER(vgpr74, Arch_amdgpu_cdna | VGPR | BITS_32 | 74,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_74, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_74, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 74,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_74, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 74,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_74, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 74,"amdgpu_cdna"); +DEF_REGISTER(vgpr75, Arch_amdgpu_cdna | VGPR | BITS_32 | 75,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_75, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 75,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_75, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 75,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_75, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 75,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_75, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 75,"amdgpu_cdna"); +DEF_REGISTER(vgpr76, Arch_amdgpu_cdna | VGPR | BITS_32 | 76,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_76, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_76, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_76, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 76,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_76, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 76,"amdgpu_cdna"); +DEF_REGISTER(vgpr77, Arch_amdgpu_cdna | VGPR | BITS_32 | 77,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_77, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 77,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_77, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 77,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_77, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 77,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_77, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 77,"amdgpu_cdna"); +DEF_REGISTER(vgpr78, Arch_amdgpu_cdna | VGPR | BITS_32 | 78,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_78, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_78, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 78,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_78, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 78,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_78, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 78,"amdgpu_cdna"); +DEF_REGISTER(vgpr79, Arch_amdgpu_cdna | VGPR | BITS_32 | 79,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_79, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 79,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_79, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 79,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_79, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 79,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_79, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 79,"amdgpu_cdna"); +DEF_REGISTER(vgpr80, Arch_amdgpu_cdna | VGPR | BITS_32 | 80,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_80, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_80, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_80, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_80, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna"); +DEF_REGISTER(vgpr81, Arch_amdgpu_cdna | VGPR | BITS_32 | 81,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_81, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 81,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_81, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 81,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_81, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 81,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_81, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 81,"amdgpu_cdna"); +DEF_REGISTER(vgpr82, Arch_amdgpu_cdna | VGPR | BITS_32 | 82,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_82, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_82, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 82,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_82, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 82,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_82, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 82,"amdgpu_cdna"); +DEF_REGISTER(vgpr83, Arch_amdgpu_cdna | VGPR | BITS_32 | 83,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_83, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 83,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_83, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 83,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_83, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 83,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_83, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 83,"amdgpu_cdna"); +DEF_REGISTER(vgpr84, Arch_amdgpu_cdna | VGPR | BITS_32 | 84,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_84, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_84, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_84, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 84,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_84, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 84,"amdgpu_cdna"); +DEF_REGISTER(vgpr85, Arch_amdgpu_cdna | VGPR | BITS_32 | 85,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_85, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 85,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_85, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 85,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_85, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 85,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_85, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 85,"amdgpu_cdna"); +DEF_REGISTER(vgpr86, Arch_amdgpu_cdna | VGPR | BITS_32 | 86,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_86, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_86, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 86,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_86, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 86,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_86, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 86,"amdgpu_cdna"); +DEF_REGISTER(vgpr87, Arch_amdgpu_cdna | VGPR | BITS_32 | 87,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_87, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 87,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_87, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 87,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_87, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 87,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_87, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 87,"amdgpu_cdna"); +DEF_REGISTER(vgpr88, Arch_amdgpu_cdna | VGPR | BITS_32 | 88,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_88, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_88, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_88, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_88, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 88,"amdgpu_cdna"); +DEF_REGISTER(vgpr89, Arch_amdgpu_cdna | VGPR | BITS_32 | 89,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_89, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 89,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_89, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 89,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_89, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 89,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_89, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 89,"amdgpu_cdna"); +DEF_REGISTER(vgpr90, Arch_amdgpu_cdna | VGPR | BITS_32 | 90,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_90, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_90, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 90,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_90, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 90,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_90, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 90,"amdgpu_cdna"); +DEF_REGISTER(vgpr91, Arch_amdgpu_cdna | VGPR | BITS_32 | 91,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_91, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 91,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_91, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 91,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_91, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 91,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_91, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 91,"amdgpu_cdna"); +DEF_REGISTER(vgpr92, Arch_amdgpu_cdna | VGPR | BITS_32 | 92,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_92, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_92, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_92, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 92,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_92, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 92,"amdgpu_cdna"); +DEF_REGISTER(vgpr93, Arch_amdgpu_cdna | VGPR | BITS_32 | 93,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_93, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 93,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_93, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 93,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_93, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 93,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_93, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 93,"amdgpu_cdna"); +DEF_REGISTER(vgpr94, Arch_amdgpu_cdna | VGPR | BITS_32 | 94,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_94, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_94, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 94,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_94, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 94,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_94, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 94,"amdgpu_cdna"); +DEF_REGISTER(vgpr95, Arch_amdgpu_cdna | VGPR | BITS_32 | 95,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_95, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 95,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_95, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 95,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_95, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 95,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_95, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 95,"amdgpu_cdna"); +DEF_REGISTER(vgpr96, Arch_amdgpu_cdna | VGPR | BITS_32 | 96,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_96, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_96, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_96, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_96, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 96,"amdgpu_cdna"); +DEF_REGISTER(vgpr97, Arch_amdgpu_cdna | VGPR | BITS_32 | 97,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_97, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 97,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_97, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 97,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_97, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 97,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_97, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 97,"amdgpu_cdna"); +DEF_REGISTER(vgpr98, Arch_amdgpu_cdna | VGPR | BITS_32 | 98,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_98, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_98, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 98,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_98, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 98,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_98, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 98,"amdgpu_cdna"); +DEF_REGISTER(vgpr99, Arch_amdgpu_cdna | VGPR | BITS_32 | 99,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_99, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 99,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_99, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 99,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_99, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 99,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_99, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 99,"amdgpu_cdna"); +DEF_REGISTER(vgpr100, Arch_amdgpu_cdna | VGPR | BITS_32 | 100,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_100, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_100, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_100, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 100,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_100, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 100,"amdgpu_cdna"); +DEF_REGISTER(vgpr101, Arch_amdgpu_cdna | VGPR | BITS_32 | 101,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_101, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 101,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_101, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 101,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_101, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 101,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_101, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 101,"amdgpu_cdna"); +DEF_REGISTER(vgpr102, Arch_amdgpu_cdna | VGPR | BITS_32 | 102,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_102, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_102, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 102,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_102, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 102,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_102, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 102,"amdgpu_cdna"); +DEF_REGISTER(vgpr103, Arch_amdgpu_cdna | VGPR | BITS_32 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_103, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_103, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_103, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_103, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 103,"amdgpu_cdna"); +DEF_REGISTER(vgpr104, Arch_amdgpu_cdna | VGPR | BITS_32 | 104,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_104, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 104,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_104, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 104,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_104, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 104,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_104, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 104,"amdgpu_cdna"); +DEF_REGISTER(vgpr105, Arch_amdgpu_cdna | VGPR | BITS_32 | 105,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_105, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 105,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_105, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 105,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_105, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 105,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_105, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 105,"amdgpu_cdna"); +DEF_REGISTER(vgpr106, Arch_amdgpu_cdna | VGPR | BITS_32 | 106,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_106, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 106,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_106, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 106,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_106, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 106,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_106, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 106,"amdgpu_cdna"); +DEF_REGISTER(vgpr107, Arch_amdgpu_cdna | VGPR | BITS_32 | 107,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_107, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 107,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_107, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 107,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_107, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 107,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_107, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 107,"amdgpu_cdna"); +DEF_REGISTER(vgpr108, Arch_amdgpu_cdna | VGPR | BITS_32 | 108,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_108, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 108,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_108, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 108,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_108, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 108,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_108, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 108,"amdgpu_cdna"); +DEF_REGISTER(vgpr109, Arch_amdgpu_cdna | VGPR | BITS_32 | 109,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_109, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 109,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_109, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 109,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_109, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 109,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_109, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 109,"amdgpu_cdna"); +DEF_REGISTER(vgpr110, Arch_amdgpu_cdna | VGPR | BITS_32 | 110,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_110, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 110,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_110, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 110,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_110, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 110,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_110, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 110,"amdgpu_cdna"); +DEF_REGISTER(vgpr111, Arch_amdgpu_cdna | VGPR | BITS_32 | 111,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_111, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 111,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_111, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 111,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_111, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 111,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_111, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 111,"amdgpu_cdna"); +DEF_REGISTER(vgpr112, Arch_amdgpu_cdna | VGPR | BITS_32 | 112,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_112, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 112,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_112, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 112,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_112, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 112,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_112, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 112,"amdgpu_cdna"); +DEF_REGISTER(vgpr113, Arch_amdgpu_cdna | VGPR | BITS_32 | 113,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_113, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 113,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_113, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 113,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_113, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 113,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_113, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 113,"amdgpu_cdna"); +DEF_REGISTER(vgpr114, Arch_amdgpu_cdna | VGPR | BITS_32 | 114,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_114, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 114,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_114, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 114,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_114, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 114,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_114, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 114,"amdgpu_cdna"); +DEF_REGISTER(vgpr115, Arch_amdgpu_cdna | VGPR | BITS_32 | 115,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_115, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 115,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_115, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 115,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_115, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 115,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_115, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 115,"amdgpu_cdna"); +DEF_REGISTER(vgpr116, Arch_amdgpu_cdna | VGPR | BITS_32 | 116,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_116, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 116,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_116, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 116,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_116, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 116,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_116, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 116,"amdgpu_cdna"); +DEF_REGISTER(vgpr117, Arch_amdgpu_cdna | VGPR | BITS_32 | 117,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_117, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 117,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_117, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 117,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_117, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 117,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_117, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 117,"amdgpu_cdna"); +DEF_REGISTER(vgpr118, Arch_amdgpu_cdna | VGPR | BITS_32 | 118,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_118, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 118,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_118, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 118,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_118, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 118,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_118, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 118,"amdgpu_cdna"); +DEF_REGISTER(vgpr119, Arch_amdgpu_cdna | VGPR | BITS_32 | 119,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_119, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 119,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_119, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 119,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_119, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 119,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_119, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 119,"amdgpu_cdna"); +DEF_REGISTER(vgpr120, Arch_amdgpu_cdna | VGPR | BITS_32 | 120,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_120, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 120,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_120, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 120,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_120, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 120,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_120, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 120,"amdgpu_cdna"); +DEF_REGISTER(vgpr121, Arch_amdgpu_cdna | VGPR | BITS_32 | 121,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_121, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 121,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_121, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 121,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_121, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 121,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_121, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 121,"amdgpu_cdna"); +DEF_REGISTER(vgpr122, Arch_amdgpu_cdna | VGPR | BITS_32 | 122,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_122, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 122,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_122, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 122,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_122, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 122,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_122, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 122,"amdgpu_cdna"); +DEF_REGISTER(vgpr123, Arch_amdgpu_cdna | VGPR | BITS_32 | 123,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_123, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 123,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_123, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 123,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_123, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 123,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_123, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 123,"amdgpu_cdna"); +DEF_REGISTER(vgpr124, Arch_amdgpu_cdna | VGPR | BITS_32 | 124,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_124, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 124,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_124, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 124,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_124, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 124,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_124, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 124,"amdgpu_cdna"); +DEF_REGISTER(vgpr125, Arch_amdgpu_cdna | VGPR | BITS_32 | 125,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_125, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 125,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_125, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 125,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_125, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 125,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_125, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 125,"amdgpu_cdna"); +DEF_REGISTER(vgpr126, Arch_amdgpu_cdna | VGPR | BITS_32 | 126,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_126, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 126,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_126, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 126,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_126, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 126,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_126, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 126,"amdgpu_cdna"); +DEF_REGISTER(vgpr127, Arch_amdgpu_cdna | VGPR | BITS_32 | 127,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_127, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 127,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_127, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 127,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_127, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 127,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_127, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 127,"amdgpu_cdna"); +DEF_REGISTER(vgpr128, Arch_amdgpu_cdna | VGPR | BITS_32 | 128,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_128, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 128,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_128, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 128,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_128, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 128,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_128, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 128,"amdgpu_cdna"); +DEF_REGISTER(vgpr129, Arch_amdgpu_cdna | VGPR | BITS_32 | 129,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_129, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 129,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_129, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 129,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_129, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 129,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_129, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 129,"amdgpu_cdna"); +DEF_REGISTER(vgpr130, Arch_amdgpu_cdna | VGPR | BITS_32 | 130,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_130, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 130,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_130, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 130,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_130, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 130,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_130, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 130,"amdgpu_cdna"); +DEF_REGISTER(vgpr131, Arch_amdgpu_cdna | VGPR | BITS_32 | 131,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_131, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 131,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_131, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 131,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_131, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 131,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_131, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 131,"amdgpu_cdna"); +DEF_REGISTER(vgpr132, Arch_amdgpu_cdna | VGPR | BITS_32 | 132,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_132, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 132,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_132, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 132,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_132, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 132,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_132, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 132,"amdgpu_cdna"); +DEF_REGISTER(vgpr133, Arch_amdgpu_cdna | VGPR | BITS_32 | 133,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_133, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 133,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_133, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 133,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_133, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 133,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_133, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 133,"amdgpu_cdna"); +DEF_REGISTER(vgpr134, Arch_amdgpu_cdna | VGPR | BITS_32 | 134,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_134, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 134,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_134, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 134,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_134, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 134,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_134, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 134,"amdgpu_cdna"); +DEF_REGISTER(vgpr135, Arch_amdgpu_cdna | VGPR | BITS_32 | 135,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_135, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 135,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_135, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 135,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_135, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 135,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_135, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 135,"amdgpu_cdna"); +DEF_REGISTER(vgpr136, Arch_amdgpu_cdna | VGPR | BITS_32 | 136,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_136, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 136,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_136, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 136,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_136, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 136,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_136, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 136,"amdgpu_cdna"); +DEF_REGISTER(vgpr137, Arch_amdgpu_cdna | VGPR | BITS_32 | 137,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_137, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 137,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_137, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 137,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_137, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 137,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_137, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 137,"amdgpu_cdna"); +DEF_REGISTER(vgpr138, Arch_amdgpu_cdna | VGPR | BITS_32 | 138,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_138, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 138,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_138, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 138,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_138, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 138,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_138, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 138,"amdgpu_cdna"); +DEF_REGISTER(vgpr139, Arch_amdgpu_cdna | VGPR | BITS_32 | 139,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_139, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 139,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_139, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 139,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_139, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 139,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_139, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 139,"amdgpu_cdna"); +DEF_REGISTER(vgpr140, Arch_amdgpu_cdna | VGPR | BITS_32 | 140,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_140, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 140,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_140, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 140,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_140, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 140,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_140, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 140,"amdgpu_cdna"); +DEF_REGISTER(vgpr141, Arch_amdgpu_cdna | VGPR | BITS_32 | 141,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_141, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 141,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_141, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 141,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_141, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 141,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_141, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 141,"amdgpu_cdna"); +DEF_REGISTER(vgpr142, Arch_amdgpu_cdna | VGPR | BITS_32 | 142,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_142, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 142,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_142, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 142,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_142, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 142,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_142, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 142,"amdgpu_cdna"); +DEF_REGISTER(vgpr143, Arch_amdgpu_cdna | VGPR | BITS_32 | 143,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_143, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 143,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_143, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 143,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_143, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 143,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_143, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 143,"amdgpu_cdna"); +DEF_REGISTER(vgpr144, Arch_amdgpu_cdna | VGPR | BITS_32 | 144,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_144, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 144,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_144, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 144,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_144, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 144,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_144, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 144,"amdgpu_cdna"); +DEF_REGISTER(vgpr145, Arch_amdgpu_cdna | VGPR | BITS_32 | 145,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_145, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 145,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_145, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 145,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_145, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 145,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_145, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 145,"amdgpu_cdna"); +DEF_REGISTER(vgpr146, Arch_amdgpu_cdna | VGPR | BITS_32 | 146,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_146, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 146,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_146, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 146,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_146, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 146,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_146, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 146,"amdgpu_cdna"); +DEF_REGISTER(vgpr147, Arch_amdgpu_cdna | VGPR | BITS_32 | 147,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_147, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 147,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_147, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 147,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_147, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 147,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_147, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 147,"amdgpu_cdna"); +DEF_REGISTER(vgpr148, Arch_amdgpu_cdna | VGPR | BITS_32 | 148,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_148, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 148,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_148, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 148,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_148, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 148,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_148, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 148,"amdgpu_cdna"); +DEF_REGISTER(vgpr149, Arch_amdgpu_cdna | VGPR | BITS_32 | 149,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_149, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 149,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_149, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 149,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_149, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 149,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_149, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 149,"amdgpu_cdna"); +DEF_REGISTER(vgpr150, Arch_amdgpu_cdna | VGPR | BITS_32 | 150,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_150, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 150,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_150, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 150,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_150, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 150,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_150, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 150,"amdgpu_cdna"); +DEF_REGISTER(vgpr151, Arch_amdgpu_cdna | VGPR | BITS_32 | 151,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_151, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 151,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_151, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 151,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_151, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 151,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_151, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 151,"amdgpu_cdna"); +DEF_REGISTER(vgpr152, Arch_amdgpu_cdna | VGPR | BITS_32 | 152,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_152, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 152,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_152, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 152,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_152, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 152,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_152, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 152,"amdgpu_cdna"); +DEF_REGISTER(vgpr153, Arch_amdgpu_cdna | VGPR | BITS_32 | 153,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_153, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 153,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_153, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 153,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_153, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 153,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_153, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 153,"amdgpu_cdna"); +DEF_REGISTER(vgpr154, Arch_amdgpu_cdna | VGPR | BITS_32 | 154,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_154, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 154,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_154, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 154,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_154, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 154,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_154, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 154,"amdgpu_cdna"); +DEF_REGISTER(vgpr155, Arch_amdgpu_cdna | VGPR | BITS_32 | 155,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_155, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 155,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_155, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 155,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_155, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 155,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_155, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 155,"amdgpu_cdna"); +DEF_REGISTER(vgpr156, Arch_amdgpu_cdna | VGPR | BITS_32 | 156,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_156, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 156,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_156, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 156,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_156, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 156,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_156, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 156,"amdgpu_cdna"); +DEF_REGISTER(vgpr157, Arch_amdgpu_cdna | VGPR | BITS_32 | 157,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_157, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 157,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_157, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 157,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_157, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 157,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_157, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 157,"amdgpu_cdna"); +DEF_REGISTER(vgpr158, Arch_amdgpu_cdna | VGPR | BITS_32 | 158,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_158, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 158,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_158, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 158,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_158, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 158,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_158, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 158,"amdgpu_cdna"); +DEF_REGISTER(vgpr159, Arch_amdgpu_cdna | VGPR | BITS_32 | 159,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_159, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 159,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_159, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 159,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_159, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 159,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_159, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 159,"amdgpu_cdna"); +DEF_REGISTER(vgpr160, Arch_amdgpu_cdna | VGPR | BITS_32 | 160,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_160, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 160,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_160, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 160,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_160, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 160,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_160, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 160,"amdgpu_cdna"); +DEF_REGISTER(vgpr161, Arch_amdgpu_cdna | VGPR | BITS_32 | 161,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_161, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 161,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_161, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 161,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_161, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 161,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_161, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 161,"amdgpu_cdna"); +DEF_REGISTER(vgpr162, Arch_amdgpu_cdna | VGPR | BITS_32 | 162,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_162, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 162,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_162, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 162,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_162, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 162,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_162, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 162,"amdgpu_cdna"); +DEF_REGISTER(vgpr163, Arch_amdgpu_cdna | VGPR | BITS_32 | 163,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_163, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 163,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_163, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 163,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_163, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 163,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_163, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 163,"amdgpu_cdna"); +DEF_REGISTER(vgpr164, Arch_amdgpu_cdna | VGPR | BITS_32 | 164,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_164, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 164,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_164, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 164,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_164, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 164,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_164, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 164,"amdgpu_cdna"); +DEF_REGISTER(vgpr165, Arch_amdgpu_cdna | VGPR | BITS_32 | 165,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_165, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 165,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_165, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 165,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_165, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 165,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_165, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 165,"amdgpu_cdna"); +DEF_REGISTER(vgpr166, Arch_amdgpu_cdna | VGPR | BITS_32 | 166,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_166, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 166,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_166, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 166,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_166, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 166,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_166, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 166,"amdgpu_cdna"); +DEF_REGISTER(vgpr167, Arch_amdgpu_cdna | VGPR | BITS_32 | 167,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_167, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 167,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_167, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 167,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_167, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 167,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_167, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 167,"amdgpu_cdna"); +DEF_REGISTER(vgpr168, Arch_amdgpu_cdna | VGPR | BITS_32 | 168,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_168, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 168,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_168, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 168,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_168, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 168,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_168, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 168,"amdgpu_cdna"); +DEF_REGISTER(vgpr169, Arch_amdgpu_cdna | VGPR | BITS_32 | 169,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_169, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 169,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_169, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 169,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_169, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 169,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_169, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 169,"amdgpu_cdna"); +DEF_REGISTER(vgpr170, Arch_amdgpu_cdna | VGPR | BITS_32 | 170,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_170, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 170,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_170, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 170,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_170, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 170,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_170, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 170,"amdgpu_cdna"); +DEF_REGISTER(vgpr171, Arch_amdgpu_cdna | VGPR | BITS_32 | 171,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_171, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 171,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_171, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 171,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_171, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 171,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_171, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 171,"amdgpu_cdna"); +DEF_REGISTER(vgpr172, Arch_amdgpu_cdna | VGPR | BITS_32 | 172,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_172, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 172,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_172, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 172,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_172, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 172,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_172, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 172,"amdgpu_cdna"); +DEF_REGISTER(vgpr173, Arch_amdgpu_cdna | VGPR | BITS_32 | 173,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_173, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 173,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_173, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 173,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_173, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 173,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_173, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 173,"amdgpu_cdna"); +DEF_REGISTER(vgpr174, Arch_amdgpu_cdna | VGPR | BITS_32 | 174,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_174, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 174,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_174, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 174,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_174, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 174,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_174, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 174,"amdgpu_cdna"); +DEF_REGISTER(vgpr175, Arch_amdgpu_cdna | VGPR | BITS_32 | 175,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_175, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 175,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_175, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 175,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_175, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 175,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_175, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 175,"amdgpu_cdna"); +DEF_REGISTER(vgpr176, Arch_amdgpu_cdna | VGPR | BITS_32 | 176,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_176, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 176,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_176, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 176,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_176, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 176,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_176, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 176,"amdgpu_cdna"); +DEF_REGISTER(vgpr177, Arch_amdgpu_cdna | VGPR | BITS_32 | 177,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_177, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 177,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_177, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 177,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_177, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 177,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_177, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 177,"amdgpu_cdna"); +DEF_REGISTER(vgpr178, Arch_amdgpu_cdna | VGPR | BITS_32 | 178,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_178, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 178,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_178, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 178,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_178, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 178,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_178, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 178,"amdgpu_cdna"); +DEF_REGISTER(vgpr179, Arch_amdgpu_cdna | VGPR | BITS_32 | 179,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_179, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 179,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_179, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 179,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_179, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 179,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_179, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 179,"amdgpu_cdna"); +DEF_REGISTER(vgpr180, Arch_amdgpu_cdna | VGPR | BITS_32 | 180,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_180, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 180,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_180, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 180,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_180, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 180,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_180, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 180,"amdgpu_cdna"); +DEF_REGISTER(vgpr181, Arch_amdgpu_cdna | VGPR | BITS_32 | 181,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_181, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 181,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_181, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 181,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_181, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 181,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_181, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 181,"amdgpu_cdna"); +DEF_REGISTER(vgpr182, Arch_amdgpu_cdna | VGPR | BITS_32 | 182,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_182, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 182,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_182, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 182,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_182, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 182,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_182, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 182,"amdgpu_cdna"); +DEF_REGISTER(vgpr183, Arch_amdgpu_cdna | VGPR | BITS_32 | 183,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_183, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 183,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_183, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 183,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_183, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 183,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_183, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 183,"amdgpu_cdna"); +DEF_REGISTER(vgpr184, Arch_amdgpu_cdna | VGPR | BITS_32 | 184,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_184, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 184,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_184, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 184,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_184, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 184,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_184, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 184,"amdgpu_cdna"); +DEF_REGISTER(vgpr185, Arch_amdgpu_cdna | VGPR | BITS_32 | 185,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_185, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 185,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_185, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 185,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_185, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 185,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_185, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 185,"amdgpu_cdna"); +DEF_REGISTER(vgpr186, Arch_amdgpu_cdna | VGPR | BITS_32 | 186,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_186, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 186,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_186, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 186,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_186, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 186,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_186, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 186,"amdgpu_cdna"); +DEF_REGISTER(vgpr187, Arch_amdgpu_cdna | VGPR | BITS_32 | 187,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_187, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 187,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_187, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 187,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_187, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 187,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_187, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 187,"amdgpu_cdna"); +DEF_REGISTER(vgpr188, Arch_amdgpu_cdna | VGPR | BITS_32 | 188,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_188, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 188,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_188, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 188,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_188, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 188,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_188, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 188,"amdgpu_cdna"); +DEF_REGISTER(vgpr189, Arch_amdgpu_cdna | VGPR | BITS_32 | 189,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_189, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 189,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_189, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 189,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_189, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 189,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_189, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 189,"amdgpu_cdna"); +DEF_REGISTER(vgpr190, Arch_amdgpu_cdna | VGPR | BITS_32 | 190,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_190, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 190,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_190, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 190,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_190, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 190,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_190, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 190,"amdgpu_cdna"); +DEF_REGISTER(vgpr191, Arch_amdgpu_cdna | VGPR | BITS_32 | 191,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_191, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 191,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_191, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 191,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_191, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 191,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_191, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 191,"amdgpu_cdna"); +DEF_REGISTER(vgpr192, Arch_amdgpu_cdna | VGPR | BITS_32 | 192,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_192, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 192,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_192, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 192,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_192, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 192,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_192, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 192,"amdgpu_cdna"); +DEF_REGISTER(vgpr193, Arch_amdgpu_cdna | VGPR | BITS_32 | 193,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_193, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 193,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_193, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 193,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_193, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 193,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_193, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 193,"amdgpu_cdna"); +DEF_REGISTER(vgpr194, Arch_amdgpu_cdna | VGPR | BITS_32 | 194,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_194, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 194,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_194, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 194,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_194, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 194,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_194, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 194,"amdgpu_cdna"); +DEF_REGISTER(vgpr195, Arch_amdgpu_cdna | VGPR | BITS_32 | 195,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_195, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 195,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_195, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 195,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_195, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 195,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_195, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 195,"amdgpu_cdna"); +DEF_REGISTER(vgpr196, Arch_amdgpu_cdna | VGPR | BITS_32 | 196,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_196, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 196,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_196, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 196,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_196, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 196,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_196, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 196,"amdgpu_cdna"); +DEF_REGISTER(vgpr197, Arch_amdgpu_cdna | VGPR | BITS_32 | 197,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_197, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 197,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_197, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 197,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_197, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 197,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_197, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 197,"amdgpu_cdna"); +DEF_REGISTER(vgpr198, Arch_amdgpu_cdna | VGPR | BITS_32 | 198,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_198, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 198,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_198, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 198,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_198, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 198,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_198, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 198,"amdgpu_cdna"); +DEF_REGISTER(vgpr199, Arch_amdgpu_cdna | VGPR | BITS_32 | 199,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_199, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 199,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_199, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 199,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_199, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 199,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_199, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 199,"amdgpu_cdna"); +DEF_REGISTER(vgpr200, Arch_amdgpu_cdna | VGPR | BITS_32 | 200,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_200, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 200,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_200, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 200,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_200, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 200,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_200, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 200,"amdgpu_cdna"); +DEF_REGISTER(vgpr201, Arch_amdgpu_cdna | VGPR | BITS_32 | 201,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_201, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 201,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_201, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 201,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_201, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 201,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_201, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 201,"amdgpu_cdna"); +DEF_REGISTER(vgpr202, Arch_amdgpu_cdna | VGPR | BITS_32 | 202,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_202, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 202,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_202, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 202,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_202, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 202,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_202, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 202,"amdgpu_cdna"); +DEF_REGISTER(vgpr203, Arch_amdgpu_cdna | VGPR | BITS_32 | 203,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_203, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 203,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_203, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 203,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_203, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 203,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_203, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 203,"amdgpu_cdna"); +DEF_REGISTER(vgpr204, Arch_amdgpu_cdna | VGPR | BITS_32 | 204,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_204, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 204,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_204, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 204,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_204, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 204,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_204, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 204,"amdgpu_cdna"); +DEF_REGISTER(vgpr205, Arch_amdgpu_cdna | VGPR | BITS_32 | 205,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_205, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 205,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_205, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 205,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_205, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 205,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_205, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 205,"amdgpu_cdna"); +DEF_REGISTER(vgpr206, Arch_amdgpu_cdna | VGPR | BITS_32 | 206,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_206, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 206,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_206, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 206,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_206, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 206,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_206, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 206,"amdgpu_cdna"); +DEF_REGISTER(vgpr207, Arch_amdgpu_cdna | VGPR | BITS_32 | 207,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_207, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 207,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_207, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 207,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_207, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 207,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_207, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 207,"amdgpu_cdna"); +DEF_REGISTER(vgpr208, Arch_amdgpu_cdna | VGPR | BITS_32 | 208,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_208, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 208,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_208, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 208,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_208, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 208,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_208, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 208,"amdgpu_cdna"); +DEF_REGISTER(vgpr209, Arch_amdgpu_cdna | VGPR | BITS_32 | 209,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_209, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 209,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_209, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 209,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_209, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 209,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_209, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 209,"amdgpu_cdna"); +DEF_REGISTER(vgpr210, Arch_amdgpu_cdna | VGPR | BITS_32 | 210,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_210, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 210,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_210, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 210,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_210, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 210,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_210, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 210,"amdgpu_cdna"); +DEF_REGISTER(vgpr211, Arch_amdgpu_cdna | VGPR | BITS_32 | 211,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_211, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 211,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_211, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 211,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_211, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 211,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_211, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 211,"amdgpu_cdna"); +DEF_REGISTER(vgpr212, Arch_amdgpu_cdna | VGPR | BITS_32 | 212,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_212, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 212,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_212, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 212,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_212, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 212,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_212, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 212,"amdgpu_cdna"); +DEF_REGISTER(vgpr213, Arch_amdgpu_cdna | VGPR | BITS_32 | 213,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_213, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 213,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_213, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 213,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_213, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 213,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_213, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 213,"amdgpu_cdna"); +DEF_REGISTER(vgpr214, Arch_amdgpu_cdna | VGPR | BITS_32 | 214,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_214, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 214,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_214, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 214,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_214, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 214,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_214, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 214,"amdgpu_cdna"); +DEF_REGISTER(vgpr215, Arch_amdgpu_cdna | VGPR | BITS_32 | 215,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_215, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 215,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_215, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 215,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_215, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 215,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_215, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 215,"amdgpu_cdna"); +DEF_REGISTER(vgpr216, Arch_amdgpu_cdna | VGPR | BITS_32 | 216,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_216, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 216,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_216, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 216,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_216, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 216,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_216, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 216,"amdgpu_cdna"); +DEF_REGISTER(vgpr217, Arch_amdgpu_cdna | VGPR | BITS_32 | 217,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_217, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 217,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_217, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 217,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_217, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 217,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_217, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 217,"amdgpu_cdna"); +DEF_REGISTER(vgpr218, Arch_amdgpu_cdna | VGPR | BITS_32 | 218,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_218, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 218,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_218, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 218,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_218, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 218,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_218, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 218,"amdgpu_cdna"); +DEF_REGISTER(vgpr219, Arch_amdgpu_cdna | VGPR | BITS_32 | 219,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_219, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 219,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_219, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 219,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_219, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 219,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_219, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 219,"amdgpu_cdna"); +DEF_REGISTER(vgpr220, Arch_amdgpu_cdna | VGPR | BITS_32 | 220,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_220, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 220,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_220, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 220,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_220, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 220,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_220, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 220,"amdgpu_cdna"); +DEF_REGISTER(vgpr221, Arch_amdgpu_cdna | VGPR | BITS_32 | 221,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_221, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 221,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_221, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 221,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_221, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 221,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_221, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 221,"amdgpu_cdna"); +DEF_REGISTER(vgpr222, Arch_amdgpu_cdna | VGPR | BITS_32 | 222,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_222, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 222,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_222, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 222,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_222, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 222,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_222, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 222,"amdgpu_cdna"); +DEF_REGISTER(vgpr223, Arch_amdgpu_cdna | VGPR | BITS_32 | 223,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_223, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 223,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_223, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 223,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_223, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 223,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_223, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 223,"amdgpu_cdna"); +DEF_REGISTER(vgpr224, Arch_amdgpu_cdna | VGPR | BITS_32 | 224,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_224, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 224,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_224, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 224,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_224, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 224,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_224, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 224,"amdgpu_cdna"); +DEF_REGISTER(vgpr225, Arch_amdgpu_cdna | VGPR | BITS_32 | 225,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_225, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 225,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_225, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 225,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_225, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 225,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_225, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 225,"amdgpu_cdna"); +DEF_REGISTER(vgpr226, Arch_amdgpu_cdna | VGPR | BITS_32 | 226,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_226, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 226,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_226, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 226,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_226, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 226,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_226, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 226,"amdgpu_cdna"); +DEF_REGISTER(vgpr227, Arch_amdgpu_cdna | VGPR | BITS_32 | 227,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_227, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 227,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_227, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 227,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_227, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 227,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_227, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 227,"amdgpu_cdna"); +DEF_REGISTER(vgpr228, Arch_amdgpu_cdna | VGPR | BITS_32 | 228,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_228, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 228,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_228, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 228,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_228, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 228,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_228, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 228,"amdgpu_cdna"); +DEF_REGISTER(vgpr229, Arch_amdgpu_cdna | VGPR | BITS_32 | 229,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_229, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 229,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_229, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 229,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_229, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 229,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_229, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 229,"amdgpu_cdna"); +DEF_REGISTER(vgpr230, Arch_amdgpu_cdna | VGPR | BITS_32 | 230,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_230, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 230,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_230, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 230,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_230, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 230,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_230, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 230,"amdgpu_cdna"); +DEF_REGISTER(vgpr231, Arch_amdgpu_cdna | VGPR | BITS_32 | 231,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_231, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 231,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_231, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 231,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_231, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 231,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_231, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 231,"amdgpu_cdna"); +DEF_REGISTER(vgpr232, Arch_amdgpu_cdna | VGPR | BITS_32 | 232,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_232, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 232,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_232, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 232,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_232, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 232,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_232, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 232,"amdgpu_cdna"); +DEF_REGISTER(vgpr233, Arch_amdgpu_cdna | VGPR | BITS_32 | 233,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_233, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 233,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_233, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 233,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_233, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 233,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_233, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 233,"amdgpu_cdna"); +DEF_REGISTER(vgpr234, Arch_amdgpu_cdna | VGPR | BITS_32 | 234,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_234, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 234,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_234, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 234,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_234, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 234,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_234, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 234,"amdgpu_cdna"); +DEF_REGISTER(vgpr235, Arch_amdgpu_cdna | VGPR | BITS_32 | 235,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_235, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 235,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_235, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 235,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_235, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 235,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_235, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 235,"amdgpu_cdna"); +DEF_REGISTER(vgpr236, Arch_amdgpu_cdna | VGPR | BITS_32 | 236,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_236, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 236,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_236, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 236,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_236, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 236,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_236, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 236,"amdgpu_cdna"); +DEF_REGISTER(vgpr237, Arch_amdgpu_cdna | VGPR | BITS_32 | 237,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_237, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 237,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_237, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 237,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_237, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 237,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_237, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 237,"amdgpu_cdna"); +DEF_REGISTER(vgpr238, Arch_amdgpu_cdna | VGPR | BITS_32 | 238,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_238, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 238,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_238, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 238,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_238, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 238,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_238, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 238,"amdgpu_cdna"); +DEF_REGISTER(vgpr239, Arch_amdgpu_cdna | VGPR | BITS_32 | 239,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_239, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 239,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_239, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 239,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_239, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 239,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_239, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 239,"amdgpu_cdna"); +DEF_REGISTER(vgpr240, Arch_amdgpu_cdna | VGPR | BITS_32 | 240,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_240, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 240,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_240, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 240,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_240, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 240,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec16_240, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 240,"amdgpu_cdna"); +DEF_REGISTER(vgpr241, Arch_amdgpu_cdna | VGPR | BITS_32 | 241,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_241, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 241,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_241, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 241,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_241, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 241,"amdgpu_cdna"); +DEF_REGISTER(vgpr242, Arch_amdgpu_cdna | VGPR | BITS_32 | 242,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_242, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 242,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_242, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 242,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_242, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 242,"amdgpu_cdna"); +DEF_REGISTER(vgpr243, Arch_amdgpu_cdna | VGPR | BITS_32 | 243,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_243, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 243,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_243, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 243,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_243, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 243,"amdgpu_cdna"); +DEF_REGISTER(vgpr244, Arch_amdgpu_cdna | VGPR | BITS_32 | 244,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_244, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 244,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_244, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 244,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_244, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 244,"amdgpu_cdna"); +DEF_REGISTER(vgpr245, Arch_amdgpu_cdna | VGPR | BITS_32 | 245,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_245, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 245,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_245, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 245,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_245, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 245,"amdgpu_cdna"); +DEF_REGISTER(vgpr246, Arch_amdgpu_cdna | VGPR | BITS_32 | 246,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_246, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 246,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_246, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 246,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_246, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 246,"amdgpu_cdna"); +DEF_REGISTER(vgpr247, Arch_amdgpu_cdna | VGPR | BITS_32 | 247,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_247, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 247,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_247, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 247,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_247, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 247,"amdgpu_cdna"); +DEF_REGISTER(vgpr248, Arch_amdgpu_cdna | VGPR | BITS_32 | 248,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_248, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 248,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_248, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 248,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec8_248, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 248,"amdgpu_cdna"); +DEF_REGISTER(vgpr249, Arch_amdgpu_cdna | VGPR | BITS_32 | 249,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_249, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 249,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_249, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 249,"amdgpu_cdna"); +DEF_REGISTER(vgpr250, Arch_amdgpu_cdna | VGPR | BITS_32 | 250,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_250, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 250,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_250, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 250,"amdgpu_cdna"); +DEF_REGISTER(vgpr251, Arch_amdgpu_cdna | VGPR | BITS_32 | 251,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_251, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 251,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_251, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 251,"amdgpu_cdna"); +DEF_REGISTER(vgpr252, Arch_amdgpu_cdna | VGPR | BITS_32 | 252,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_252, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 252,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec4_252, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 252,"amdgpu_cdna"); +DEF_REGISTER(vgpr253, Arch_amdgpu_cdna | VGPR | BITS_32 | 253,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_253, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 253,"amdgpu_cdna"); +DEF_REGISTER(vgpr254, Arch_amdgpu_cdna | VGPR | BITS_32 | 254,"amdgpu_cdna"); +DEF_REGISTER(vgpr_vec2_254, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 254,"amdgpu_cdna"); +DEF_REGISTER(vgpr255, Arch_amdgpu_cdna | VGPR | BITS_32 | 255,"amdgpu_cdna"); +#endif //DYNINST_AMDGPU_CDNA_SYS_REGS_H diff --git a/common/h/amdgpu_op_table.h b/common/h/amdgpu_op_table.h index 8162eaa5a7..e23acad4a7 100644 --- a/common/h/amdgpu_op_table.h +++ b/common/h/amdgpu_op_table.h @@ -1,416 +1,431 @@ -amdgpu_op_v_max_i16_e64, -amdgpu_op_v_mul_lo_u16_e64, -amdgpu_op_v_max_i16, -amdgpu_op_s_lshsl2_add_u32, -amdgpu_op_s_flbit_i32_b32, -amdgpu_op_tbuffer_store_format_d16_xyzw, -amdgpu_op_s_cmpk_eq_i32, -amdgpu_op_buffer_load_format_xyzw, -amdgpu_op_v_subrev_u32_e64, -amdgpu_op_v_subrev_f16, -amdgpu_op_v_ldexp_f16, -amdgpu_op_s_load_dwordx8, -amdgpu_op_s_cmpk_lt_u32, -amdgpu_op_s_bfe_i64, +amdgpu_op_s_brev_b32, +amdgpu_op_v_cvt_f32_u32, +amdgpu_op_v_max_u32_e64, +amdgpu_op_v_nop_e64, +amdgpu_op_v_mul_hi_u32_u24, +amdgpu_op_v_max_f32, +amdgpu_op_v_sub_f32, amdgpu_op_v_cmp_eq_u64_e64, -amdgpu_op_s_lshl3_add_u32, -amdgpu_op_s_sub_u32, -amdgpu_op_v_mul_u32_u24, -amdgpu_op_s_add_u32, -amdgpu_op_v_madmk_f32, -amdgpu_op_tbuffer_store_format_xyz, -amdgpu_op_v_sub_u16_e64, +amdgpu_op_s_rfe_b64, +amdgpu_op_v_add_co_u32_e64, +amdgpu_op_v_subrev_u16, +amdgpu_op_v_ashrrev_i16_e64, +amdgpu_op_ds_read_b128, +amdgpu_op_s_andn2_b64, +amdgpu_op_v_addc_co_u32, +amdgpu_op_v_cmp_le_u32_e64, +amdgpu_op_s_max_i32, amdgpu_op_s_invalid_1, -amdgpu_op_v_cvt_i32_f64_e64, -amdgpu_op_s_addc_u32, -amdgpu_op_s_pack_lh_b32_b16, -amdgpu_op_s_nor_savexec_b64, -amdgpu_op_s_sethalt, +amdgpu_op_v_addc_co_u32_e64, +amdgpu_op_s_dcache_wb, +amdgpu_op_s_cmov_b32, +amdgpu_op_s_andn2_wrexec_b64, +amdgpu_op_buffer_load_dword, +amdgpu_op_s_trap, +amdgpu_op_s_bitreplicate_b64_b32, +amdgpu_op_v_madak_f16, +amdgpu_op_v_mac_f16, +amdgpu_op_v_add_co_u32, +amdgpu_op_s_bcnt0_i32_b32, +amdgpu_op_v_cndmask_b32, +amdgpu_op_s_sub_u32, +amdgpu_op_s_sendmsghalt, +amdgpu_op_s_bitcmp0_b64, +amdgpu_op_v_cvt_off_f32_i4_e64, +amdgpu_op_v_cmpx_t_u64_e64, +amdgpu_op_s_brev_b64, +amdgpu_op_s_sleep, +amdgpu_op_v_or_b32, +amdgpu_op_v_mov_b32_e64, +amdgpu_op_v_add_f32_e64, +amdgpu_op_s_set_gpr_idx_off, +amdgpu_op_v_sub_co_u32_e64, +amdgpu_op_s_bitcmp1_b32, +amdgpu_op_v_cvt_off_f32_i4, +amdgpu_op_s_cmpk_lg_u32, +amdgpu_op_s_bitset1_b64, +amdgpu_op_v_cvt_rpi_i32_f32_e64, +amdgpu_op_v_max_u16, +amdgpu_op_buffer_store_format_x, +amdgpu_op_s_not_b32, +amdgpu_op_v_madak_f32, +amdgpu_op_v_min_i16, +amdgpu_op_s_pack_hh_b32_B16, +amdgpu_op_v_mul_hi_i32_i24, +amdgpu_op_v_cvt_i32_f32, +amdgpu_op_s_orn2_savexec_b64, +amdgpu_op_v_madmk_f32_e64, +amdgpu_op_s_xor_b64, +amdgpu_op_v_cmp_lt_u32, +amdgpu_op_s_buffer_store_dwordx2, +amdgpu_op_s_xor_b32, +amdgpu_op_s_movk_i32, +amdgpu_op_buffer_load_format_xyz, amdgpu_op_v_cvt_flr_i32_f32_e64, -amdgpu_op_v_cvt_u32_f32, +amdgpu_op_v_subbrev_co_u32, +amdgpu_op_s_cbranch_g_fork, +amdgpu_op_v_lshlrev_b64, +amdgpu_op_v_cvt_f64_i32_e64, +amdgpu_op_s_bfe_u64, +amdgpu_op_s_andn2_savexec_b64, +amdgpu_op_v_cvt_f32_f16, +amdgpu_op_s_wqm_b64, +amdgpu_op_s_nand_b32, +amdgpu_op_v_mov_b32, +amdgpu_op_s_lshsl2_add_u32, +amdgpu_op_v_add_u32_e64, +amdgpu_op_v_pack_b32_f16, +amdgpu_op_v_sub_f16_e64, +amdgpu_op_v_cvt_f32_i32, +amdgpu_op_buffer_store_format_xyz, +amdgpu_op_s_ttracedata, +amdgpu_op_s_scratch_load_dwordx2, +amdgpu_op_v_subrev_u32, +amdgpu_op_s_cmp_lg_u64, +amdgpu_op_s_cmpk_le_u32, +amdgpu_op_v_cmp_eq_u64, +amdgpu_op_s_branch, +amdgpu_op_s_and_saveexec_b64, +amdgpu_op_buffer_load_format_xy, +amdgpu_op_v_subrev_co_u32_e64, +amdgpu_op_v_ashrrev_i16, +amdgpu_op_v_cmp_neq_f16, +amdgpu_op_s_atomic_dec_x2, +amdgpu_op_s_incperflevel, +amdgpu_op_v_mad_u64_u32, +amdgpu_op_s_setreg_b32, +amdgpu_op_v_max_i32_e64, +amdgpu_op_s_cmovk_i32, +amdgpu_op_s_sendmsg, +amdgpu_op_s_endpgm, +amdgpu_op_s_decperflevel, +amdgpu_op_s_bcnt0_i32_b64, +amdgpu_op_s_dcache_inv_vol, +amdgpu_op_v_min_f32_e64, +amdgpu_op_v_madak_f32_e64, +amdgpu_op_s_cmpk_gt_u32, amdgpu_op_s_quadmask_b64, -amdgpu_op_tbuffer_load_format_xyz, -amdgpu_op_s_min_i32, -amdgpu_op_s_cbranch_scc1, -amdgpu_op_s_not_b32, -amdgpu_op_s_lshl_b64, -amdgpu_op_s_invalid_2, +amdgpu_op_buffer_store_format_xy, +amdgpu_op_v_cmp_le_u32, +amdgpu_op_tbuffer_load_format_xy, +amdgpu_op_v_min_f16_e64, +amdgpu_op_v_readfirstlane_b32, +amdgpu_op_s_bfe_u32, +amdgpu_op_v_subrev_f32, +amdgpu_op_s_buffer_load_dwordx4, +amdgpu_op_v_cvt_f32_u32_e64, +amdgpu_op_v_subrev_f16, +amdgpu_op_s_mov_b32, +amdgpu_op_v_min_f32, +amdgpu_op_buffer_load_dwordx4, +amdgpu_op_s_cmp_ge_i32, amdgpu_op_s_cbranch_cdbgsys, -amdgpu_op_s_cmp_ge_u32, -amdgpu_op_s_movrels_b64, -amdgpu_op_s_movrels_b32, -amdgpu_op_s_bitcmp1_b32, -amdgpu_op_s_nor_b64, -amdgpu_op_v_mul_f16, -amdgpu_op_v_interp_p2_f32, -amdgpu_op_s_cmp_lt_i32, -amdgpu_op_s_max_i32, -amdgpu_op_s_bcnt1_i32_b64, -amdgpu_op_v_xor_b32, -amdgpu_op_v_max_f16, -amdgpu_op_v_min_u16, -amdgpu_op_v_cmp_ge_u32, -amdgpu_op_v_subrev_f16_e64, -amdgpu_op_v_cmp_class_f32, -amdgpu_op_v_max_i32, -amdgpu_op_s_cbranch_execnz, +amdgpu_op_s_cmp_lg_u32, +amdgpu_op_v_min_u32, +amdgpu_op_v_min_u32_e64, +amdgpu_op_s_load_dwordx16, +amdgpu_op_s_nop, +amdgpu_op_s_endpgm_saved, +amdgpu_op_v_min_i32, +amdgpu_op_v_mul_i32_i24, +amdgpu_op_s_setprio, +amdgpu_op_s_lshl_b64, +amdgpu_op_s_flbit_i32_b32, +amdgpu_op_v_xno2_b32_e64, +amdgpu_op_v_pk_mad_i16, amdgpu_op_v_cmp_lt_u32_e64, -amdgpu_op_buffer_store_format_xy, +amdgpu_op_s_cbranch_cdbgsys_and_user, +amdgpu_op_v_cvt_flr_i32_f32, amdgpu_op_v_mul_hi_i32_i24_e64, -amdgpu_op_v_cvt_f32_f16_e64, -amdgpu_op_v_lshlrev_b32, -amdgpu_op_s_xnor_b64, -amdgpu_op_v_max_u32, -amdgpu_op_v_subrev_co_u32, -amdgpu_op_v_add_u32_e64, -amdgpu_op_v_interp_p1_f32, -amdgpu_op_v_cmp_eq_u64, -amdgpu_op_s_bitcmp0_b64, +amdgpu_op_s_xor_savexec_b64, +amdgpu_op_s_setvkip, +amdgpu_op_s_load_dword, +amdgpu_op_v_cmp_ge_u64_e64, +amdgpu_op_s_pack_ll_b32_b16, amdgpu_op_s_bitset1_b32, -amdgpu_op_v_cmp_ge_u32_e64, -amdgpu_op_s_addk_i32, -amdgpu_op_v_add_co_u32_e64, -amdgpu_op_s_ff0_i32_b64, -amdgpu_op_s_sext_i32_i8, +amdgpu_op_s_icache_inv, +amdgpu_op_s_load_dwordx2, +amdgpu_op_v_mul_hi_u32, +amdgpu_op_s_cbranch_i_fork, +amdgpu_op_s_cslect_b64, +amdgpu_op_s_orn2_b32, +amdgpu_op_s_sub_i32, +amdgpu_op_v_subrev_f16_e64, +amdgpu_op_v_max_f16, +amdgpu_op_v_swap_b32_e64, +amdgpu_op_s_bitcmp1_b64, amdgpu_op_v_min_f16, -amdgpu_op_s_cbranch_vccnz, -amdgpu_op_v_min_u32_e64, -amdgpu_op_v_sub_f16_e64, -amdgpu_op_v_subrev_f32_e64, -amdgpu_op_v_sub_u32_e64, -amdgpu_op_v_cmp_gt_u32_e64, -amdgpu_op_s_mov_b64, -amdgpu_op_s_load_dwordx4, -amdgpu_op_s_wakeup, -amdgpu_op_v_cndmask_b32, +amdgpu_op_s_scratch_store_dword, amdgpu_op_v_lshrrev_b16_e64, -amdgpu_op_s_abs_i32, -amdgpu_op_s_dcache_memrealtime, -amdgpu_op_v_cmp_neq_f16, -amdgpu_op_s_cbranch_i_fork, -amdgpu_op_v_xno2_b32_e64, -amdgpu_op_s_cmpk_lg_u32, -amdgpu_op_s_cmpk_lt_i32, -amdgpu_op_v_mul_f16_e64, -amdgpu_op_s_pack_hh_b32_B16, -amdgpu_op_v_cvt_off_f32_i4, -amdgpu_op_v_ashrrev_i16_e64, -amdgpu_op_s_orn1_saveexec_b64, -amdgpu_op_v_subrev_f32, -amdgpu_op_s_cbranch_execz, -amdgpu_op_s_not_b64, -amdgpu_op_s_buffer_load_dwordx2, -amdgpu_op_tbuffer_store_format_xy, -amdgpu_op_v_addc_co_u32, -amdgpu_op_v_pack_b32_f16, -amdgpu_op_v_lshlrev_b32_e64, -amdgpu_op_s_cslect_b32, -amdgpu_op_v_min_f32_e64, -amdgpu_op_v_swap_b32, -amdgpu_op_s_subb_u32, -amdgpu_op_s_dcache_wb_vol, -amdgpu_op_s_store_dwordx2, -amdgpu_op_s_load_dword, -amdgpu_op_v_addc_co_u32_e64, +amdgpu_op_v_madmk_f32, +amdgpu_op_v_xor_b32_e64, +amdgpu_op_v_ashrrev_i32_e64, +amdgpu_op_v_cmp_class_f32, amdgpu_op_s_bfm_b64, -amdgpu_op_v_mul_legacy_f32, -amdgpu_op_s_branch, -amdgpu_op_s_absdiff_i32, -amdgpu_op_s_getpc_b64, -amdgpu_op_v_readfirstlane_b32_e64, -amdgpu_op_buffer_load_format_xy, -amdgpu_op_s_bfm_b32, -amdgpu_op_v_add_f16, -amdgpu_op_s_movk_i32, -amdgpu_op_load_dword, -amdgpu_op_v_mac_f16_e64, -amdgpu_op_buffer_atomic_dec_x2, -amdgpu_op_s_nand_savexec_b64, -amdgpu_op_s_min_u32, -amdgpu_op_s_andn1_wrexec_b64, +amdgpu_op_s_ff0_i32_b32, +amdgpu_op_s_fltbit_i32_i64, +amdgpu_op_buffer_load_format_x, +amdgpu_op_v_sub_f32_e64, +amdgpu_op_s_store_dwordx4, +amdgpu_op_v_min_i32_e64, +amdgpu_op_s_cmp_eq_u32, +amdgpu_op_v_add_f32, +amdgpu_op_s_cmp_lt_u32, +amdgpu_op_s_swappc_b64, +amdgpu_op_s_bfe_i64, +amdgpu_op_v_min_u16, +amdgpu_op_v_xor_b32, +amdgpu_op_ds_read2_b32, +amdgpu_op_s_dcache_inv, +amdgpu_op_v_lshrrev_b32_e64, +amdgpu_op_v_add_b32, +amdgpu_op_v_lshlrev_b32_e64, +amdgpu_op_s_cmp_ge_u32, +amdgpu_op_flat_load_dword, +amdgpu_op_s_cbranch_vccnz, +amdgpu_op_v_mul_f32_e64, +amdgpu_op_v_cvt_i32_f64, +amdgpu_op_v_mac_b32, amdgpu_op_s_or_savexec_b64, -amdgpu_op_s_setreg_imm32_b32, -amdgpu_op_load_ubyte, -amdgpu_op_v_mul_f32, -amdgpu_op_s_waitcnt, -amdgpu_op_v_max_u32_e64, +amdgpu_op_v_nop, +amdgpu_op_v_sub_co_u32, +amdgpu_op_v_max_u32, +amdgpu_op_v_add_f16_e64, +amdgpu_op_v_cmp_gt_u64, +amdgpu_op_v_max_u16_e64, +amdgpu_op_s_ashr_i32, +amdgpu_op_s_bfm_b32, +amdgpu_op_s_orn1_saveexec_b64, +amdgpu_op_v_cmp_gt_u32, +amdgpu_op_tbuffer_store_format_xy, +amdgpu_op_v_ldexp_f16, +amdgpu_op_s_mov_b64, amdgpu_op_v_max_f32_e64, -amdgpu_op_s_lshl_b32, -amdgpu_op_buffer_store_format_xyz, -amdgpu_op_s_flbit_i32_b64, -amdgpu_op_s_sext_i32_i16, -amdgpu_op_v_subb_co_u32_e64, -amdgpu_op_s_setreg_b32, -amdgpu_op_v_cvt_f64_i32_e64, -amdgpu_op_v_cvt_f32_u32, -amdgpu_op_buffer_load_format_x, -amdgpu_op_v_min_i16_e64, +amdgpu_op_s_setpc_b64, amdgpu_op_v_cmp_ne_u64_e64, -amdgpu_op_s_and_saveexec_b64, +amdgpu_op_v_cmp_le_u64_e64, +amdgpu_op_s_or_b64, +amdgpu_op_s_buffer_load_dwordx2, +amdgpu_op_s_invalid_2, +amdgpu_op_v_cmp_lt_u64, +amdgpu_op_s_nand_savexec_b64, +amdgpu_op_s_xnor_savexec_b64, +amdgpu_op_s_nor_savexec_b64, +amdgpu_op_v_max_i16_e64, +amdgpu_op_buffer_load_dwordx3, +amdgpu_op_v_cmp_gt_u32_e64, amdgpu_op_v_dot8_u32_u4, -amdgpu_op_v_madak_f32_e64, +amdgpu_op_s_abs_i32, +amdgpu_op_s_cbranch_cdbgsys_or_user, +amdgpu_op_v_cndmask_b32_e64, amdgpu_op_s_mulk_i32, -amdgpu_op_s_scratch_load_dword, -amdgpu_op_s_bitreplicate_b64_b32, -amdgpu_op_s_set_gpr_idx_mode, -amdgpu_op_v_subbrev_co_u32_e64, -amdgpu_op_v_ashrrev_i32_e64, -amdgpu_op_s_cmovk_i32, +amdgpu_op_s_endpgm_ordered_ps_done, +amdgpu_op_tbuffer_store_format_xyz, +amdgpu_op_s_min_i32, +amdgpu_op_tbuffer_store_format_x, +amdgpu_op_v_mul_lo_u16_e64, +amdgpu_op_v_or_b32_e64, +amdgpu_op_s_and_b32, +amdgpu_op_s_bitset0_b32, +amdgpu_op_v_lshlrev_b32, +amdgpu_op_v_cmp_gt_u64_e64, +amdgpu_op_s_ashr_i64, +amdgpu_op_s_lshr_b32, +amdgpu_op_s_scratch_store_dwordx4, +amdgpu_op_s_cbranch_execz, +amdgpu_op_v_mul_u32_u24_e64, +amdgpu_op_v_madmk_f16, +amdgpu_op_s_nor_b64, +amdgpu_op_s_sethalt, +amdgpu_op_v_add_u16, +amdgpu_op_s_nand_b64, +amdgpu_op_s_flbit_i32_b64, +amdgpu_op_buffer_atomic_dec_x2, amdgpu_op_s_rfe_restore_b64, -amdgpu_op_s_sendmsghalt, -amdgpu_op_s_nop, -amdgpu_op_tbuffer_load_format_xy, -amdgpu_op_s_dcache_wb, -amdgpu_op_s_bitcmp1_b64, -amdgpu_op_buffer_store_format_xyzw, -amdgpu_op_s_load_dwordx16, -amdgpu_op_s_cmpk_eq_u32, -amdgpu_op_v_min_i32_e64, -amdgpu_op_v_cmp_class_f32_e64, +amdgpu_op_ds_write_b32, +amdgpu_op_s_mul_i32, +amdgpu_op_s_andn1_wrexec_b64, +amdgpu_op_buffer_load_format_xyzw, +amdgpu_op_v_rcp_iflag_f32_e64, +amdgpu_op_v_cvt_f32_i32_e64, +amdgpu_op_s_nor_b32, +amdgpu_op_s_store_dwordx2, +amdgpu_op_v_cvt_rpi_i32_f32, +amdgpu_op_v_rcp_iflag_f32, +amdgpu_op_s_buffer_load_dwordx8, +amdgpu_op_s_setkill, +amdgpu_op_s_cmp_gt_i32, +amdgpu_op_v_add_f16, +amdgpu_op_s_wakeup, +amdgpu_op_v_add_u16_e64, +amdgpu_op_s_cmp_gt_u32, +amdgpu_op_v_max_f16_e64, +amdgpu_op_s_cmov_b64, +amdgpu_op_v_ldexp_f16_e64, +amdgpu_op_v_sub_f16, +amdgpu_op_v_lshlrev_b16_e64, +amdgpu_op_v_cvt_i32_f32_e64, +amdgpu_op_v_lshlrev_b16, +amdgpu_op_s_cmpk_le_i32, +amdgpu_op_s_cmp_eq_u64, +amdgpu_op_tbuffer_store_format_d16_xyzw, +amdgpu_op_s_mul_hi_i32, +amdgpu_op_s_load_dwordx4, +amdgpu_op_s_cmp_le_i32, +amdgpu_op_v_max_i16, +amdgpu_op_tbuffer_load_format_xyzw, +amdgpu_op_v_cmp_le_u64, +amdgpu_op_s_movreld_b32, +amdgpu_op_s_load_dwordx8, +amdgpu_op_v_mul_hi_i32, +amdgpu_op_s_bcnt1_i32_b64, +amdgpu_op_flat_load_ubyte, +amdgpu_op_s_cmpk_ge_i32, +amdgpu_op_v_mul_f32, +amdgpu_op_tbuffer_store_format_xyzw, +amdgpu_op_s_call_b64, +amdgpu_op_s_buffer_store_dword, +amdgpu_op_s_lshr_b64, +amdgpu_op_s_or_b32, +amdgpu_op_v_cvt_f64_i32, +amdgpu_op_s_lshl_b32, +amdgpu_op_s_scratch_store_dwordx2, +amdgpu_op_s_set_gpr_idx_idx, +amdgpu_op_s_setreg_imm32_b32, +amdgpu_op_s_getpc_b64, amdgpu_op_v_cmp_ge_u64, -amdgpu_op_v_cndmask_b32_e64, -amdgpu_op_v_ashrrev_i16, -amdgpu_op_v_sub_co_u32_e64, -amdgpu_op_v_sub_f32, -amdgpu_op_s_cmov_b32, +amdgpu_op_v_cvt_u32_f32_e64, +amdgpu_op_s_movrels_b64, +amdgpu_op_v_mul_f16_e64, amdgpu_op_v_subrev_u16_e64, -amdgpu_op_s_cmpk_le_i32, -amdgpu_op_v_mul_hi_u32_u24, -amdgpu_op_ds_read_b128, -amdgpu_op_s_buffer_load_dword, -amdgpu_op_v_mac_b32_e64, -amdgpu_op_s_barrier, -amdgpu_op_v_cvt_i32_f64, -amdgpu_op_s_mul_hi_u32, -amdgpu_op_s_endpgm_ordered_ps_done, -amdgpu_op_v_sub_u32, -amdgpu_op_s_scratch_load_dwordx2, -amdgpu_op_s_xor_savexec_b64, -amdgpu_op_s_sendmsg, -amdgpu_op_s_cbranch_g_fork, -amdgpu_op_s_set_gpr_idx_on, -amdgpu_op_v_min_f16_e64, -amdgpu_op_s_ff0_i32_b32, -amdgpu_op_s_getreg_b32, -amdgpu_op_v_cvt_f16_f32, +amdgpu_op_s_not_b64, +amdgpu_op_s_wqm_b32, +amdgpu_op_v_cvt_f32_f16_e64, +amdgpu_op_v_interp_p2_f32, +amdgpu_op_v_min_i16_e64, +amdgpu_op_v_mad_f32, +amdgpu_op_v_sub_u32_e64, amdgpu_op_s_cbranch_cdbguser, -amdgpu_op_v_add_u16_e64, -amdgpu_op_v_cvt_flr_i32_f32, -amdgpu_op_s_lshr_b64, -amdgpu_op_v_max_f32, -amdgpu_op_v_swap_b32_e64, -amdgpu_op_s_cmpk_gt_u32, -amdgpu_op_v_cvt_f32_i32_e64, -amdgpu_op_s_ff1_i32_b32, -amdgpu_op_s_endpgm_saved, -amdgpu_op_s_cbranch_scc0, -amdgpu_op_v_cmp_le_u32_e64, -amdgpu_op_v_xno2_b32, -amdgpu_op_v_cmp_eq_u32_e64, -amdgpu_op_buffer_load_format_xyz, -amdgpu_op_v_readfirstlane_b32, +amdgpu_op_v_subrev_f32_e64, +amdgpu_op_s_ff1_i32_b64, +amdgpu_op_s_andn1_saveexec_b64, +amdgpu_op_s_fltbit_i32, +amdgpu_op_v_cvt_i32_f64_e64, +amdgpu_op_v_cmp_ge_u32_e64, +amdgpu_op_v_cmp_ge_u32, +amdgpu_op_s_cmpk_eq_u32, +amdgpu_op_s_cslect_b32, +amdgpu_op_s_add_u32, +amdgpu_op_s_cmpk_lg_i32, +amdgpu_op_s_addk_i32, +amdgpu_op_s_scratch_load_dwordx4, +amdgpu_op_s_lshl1_add_u32, +amdgpu_op_s_bcnt1_i32_b32, +amdgpu_op_tbuffer_load_format_x, +amdgpu_op_flat_store_dword, +amdgpu_op_s_cbranch_scc1, +amdgpu_op_s_mul_hi_u32, +amdgpu_op_v_swap_b32, +amdgpu_op_s_bitset0_b64, +amdgpu_op_v_mad_legacy_f32, +amdgpu_op_buffer_store_format_xyzw, +amdgpu_op_v_sub_u16_e64, +amdgpu_op_s_cbranch_vccz, +amdgpu_op_tbuffer_load_format_xyz, +amdgpu_op_s_cmpk_lt_u32, +amdgpu_op_v_sub_u16, +amdgpu_op_s_lshl3_add_u32, +amdgpu_op_s_cbranch_execnz, +amdgpu_op_s_dcache_memtime, +amdgpu_op_v_mul_i32_i24_e64, +amdgpu_op_v_cmp_class_f32_e64, +amdgpu_op_v_lshrrev_b32, +amdgpu_op_v_cmp_lt_u64_e64, +amdgpu_op_s_dcache_wb_vol, +amdgpu_op_s_set_gpr_idx_mode, +amdgpu_op_v_subb_co_u32_e64, +amdgpu_op_v_readfirstlane_b32_e64, +amdgpu_op_s_bfe_i32, +amdgpu_op_s_sext_i32_i8, +amdgpu_op_v_lshrrev_b16, +amdgpu_op_s_cmpk_gt_i32, +amdgpu_op_v_ashrrev_i32, +amdgpu_op_v_interp_p1_f32, +amdgpu_op_s_barrier, +amdgpu_op_s_buffer_load_dwordx16, +amdgpu_op_s_add_i32, +amdgpu_op_s_addc_u32, amdgpu_op_s_orn2_b64, amdgpu_op_v_cmp_ne_u64, -amdgpu_op_v_mul_lo_u16, -amdgpu_op_v_lshrrev_b32, +amdgpu_op_v_cmpx_t_u64, amdgpu_op_s_movreld_b64, -amdgpu_op_s_mul_i32, +amdgpu_op_v_mad_i64_i32, amdgpu_op_atomic_dec_x2, -amdgpu_op_v_mul_hi_u32_u24_e64, -amdgpu_op_s_bitset0_b32, -amdgpu_op_s_endpgm, -amdgpu_op_v_mac_b32, -amdgpu_op_v_mov_b32, -amdgpu_op_v_cmp_lt_u64, -amdgpu_op_s_sleep, -amdgpu_op_s_rfe_b64, -amdgpu_op_v_lshrrev_b32_e64, -amdgpu_op_s_xor_b64, -amdgpu_op_s_sub_i32, -amdgpu_op_s_cmp_ge_eq_i32, -amdgpu_op_s_cmpk_lg_i32, -amdgpu_op_s_set_gpr_idx_idx, -amdgpu_op_v_add_f16_e64, -amdgpu_op_s_andn2_savexec_b64, -amdgpu_op_v_mad_legacy_f32, -amdgpu_op_s_cmpk_ge_u32, +amdgpu_op_s_andn2_b32, +amdgpu_op_s_waitcnt, +amdgpu_op_buffer_load_dwordx2, +amdgpu_op_s_ff0_i32_b64, +amdgpu_op_v_mul_lo_u16, +amdgpu_op_s_set_gpr_idx_on, +amdgpu_op_s_cmp_eq_i32, +amdgpu_op_v_cmp_eq_u32_e64, +amdgpu_op_v_interp_mov_f32, +amdgpu_op_s_movrels_b32, amdgpu_op_ds_add_u32, -amdgpu_op_v_cvt_i32_f32_e64, -amdgpu_op_s_pack_ll_b32_b16, -amdgpu_op_s_quadmask_b32, -amdgpu_op_s_max_u32, -amdgpu_op_v_subbrev_co_u32, -amdgpu_op_s_buffer_load_dwordx4, -amdgpu_op_s_cmpk_le_u32, -amdgpu_op_v_cvt_rpi_i32_f32, -amdgpu_op_s_load_dwordx2, -amdgpu_op_s_wqm_b64, -amdgpu_op_v_min_i32, -amdgpu_op_s_swappc_b64, -amdgpu_op_s_cmpk_gt_i32, -amdgpu_op_s_brev_b64, -amdgpu_op_s_andn2_b64, -amdgpu_op_v_mul_u32_u24_e64, -amdgpu_op_s_bcnt0_i32_b32, -amdgpu_op_s_nand_b32, -amdgpu_op_v_cmp_gt_u64_e64, -amdgpu_op_s_cmp_le_i32, -amdgpu_op_v_cmp_neq_f16_e64, -amdgpu_op_v_max_i32_e64, -amdgpu_op_s_bitcmp0_b32, -amdgpu_op_v_sub_co_u32, -amdgpu_op_s_and_b32, -amdgpu_op_v_cmp_ne_u32_e64, -amdgpu_op_s_dcache_inv_vol, -amdgpu_op_v_mul_f32_e64, -amdgpu_op_s_mov_b32, -amdgpu_op_s_setpc_b64, -amdgpu_op_s_set_gpr_idx_off, -amdgpu_op_v_min_f32, -amdgpu_op_s_incperflevel, -amdgpu_op_v_min_u32, -amdgpu_op_v_cvt_i32_f32, -amdgpu_op_v_min_u16_e64, -amdgpu_op_v_add_f32, -amdgpu_op_s_bitset0_b64, -amdgpu_op_s_cmp_ge_i32, -amdgpu_op_v_mul_hi_i32_i24, -amdgpu_op_s_setkill, -amdgpu_op_s_scratch_store_dword, -amdgpu_op_v_subrev_u32, -amdgpu_op_s_brev_b32, -amdgpu_op_v_xor_b32_e64, -amdgpu_op_s_buffer_store_dwordx2, -amdgpu_op_v_cmp_le_u64, +amdgpu_op_s_xnor_b64, +amdgpu_op_s_and_b64, +amdgpu_op_v_cvt_f16_f32, +amdgpu_op_s_cbranch_scc0, +amdgpu_op_v_div_scale_f64, amdgpu_op_v_cvt_f16_f32_e64, -amdgpu_op_s_icache_inv, -amdgpu_op_s_cmov_b64, -amdgpu_op_s_fltbit_i32, -amdgpu_op_v_cvt_f32_i32, -amdgpu_op_v_sub_f32_e64, -amdgpu_op_v_cmp_ge_u64_e64, -amdgpu_op_v_mov_b32_e64, -amdgpu_op_v_sub_f16, -amdgpu_op_v_min_i16, -amdgpu_op_s_xor_b32, -amdgpu_op_s_bfe_u64, -amdgpu_op_s_ashr_i32, -amdgpu_op_s_atomic_dec_x2, -amdgpu_op_s_cmp_lt_u32, -amdgpu_op_v_ashrrev_i32, -amdgpu_op_v_add_u16, -amdgpu_op_v_max_u16_e64, -amdgpu_op_s_buffer_load_dwordx8, +amdgpu_op_s_pack_lh_b32_b16, +amdgpu_op_s_cbranch_join, +amdgpu_op_v_div_scale_f32, +amdgpu_op_v_subbrev_co_u32_e64, +amdgpu_op_s_cmp_lg_i32, +amdgpu_op_v_cvt_u32_f32, +amdgpu_op_v_mul_legacy_f32_e64, +amdgpu_op_v_madak_f16_e64, +amdgpu_op_s_ff1_i32_b32, +amdgpu_op_v_subrev_co_u32, +amdgpu_op_s_getreg_b32, +amdgpu_op_v_min_u16_e64, +amdgpu_op_v_max_i32, amdgpu_op_v_add_u32, -amdgpu_op_s_cmp_lg_u64, -amdgpu_op_v_or_b32, -amdgpu_op_v_subb_co_u32, -amdgpu_op_v_madmk_f32_e64, -amdgpu_op_s_xnor_savexec_b64, -amdgpu_op_v_lshlrev_b16, -amdgpu_op_v_cmp_gt_u32, -amdgpu_op_s_cmp_ge_eq_u32, -amdgpu_op_v_subrev_co_u32_e64, -amdgpu_op_v_cmpx_t_u64_e64, -amdgpu_op_s_ff1_i32_b64, -amdgpu_op_v_max_u16, -amdgpu_op_v_madak_f32, -amdgpu_op_store_dword, -amdgpu_op_v_cmp_lt_u32, -amdgpu_op_s_scratch_store_dwordx2, -amdgpu_op_v_cmp_le_u32, -amdgpu_op_v_cvt_f32_f16, -amdgpu_op_s_cbranch_cdbgsys_or_user, -amdgpu_op_v_add_f32_e64, -amdgpu_op_v_pk_mad_i16, -amdgpu_op_s_nor_b32, +amdgpu_op_v_mul_hi_u32_u24_e64, +amdgpu_op_s_cmpk_lt_i32, +amdgpu_op_s_cmpk_eq_i32, +amdgpu_op_v_mac_b32_e64, amdgpu_op_v_madmk_f16_e64, -amdgpu_op_v_subrev_u16, -amdgpu_op_s_or_b32, -amdgpu_op_v_nop, -amdgpu_op_s_movreld_b32, -amdgpu_op_v_or_b32_e64, -amdgpu_op_v_cvt_f64_i32, -amdgpu_op_v_cmp_le_u64_e64, -amdgpu_op_s_andn2_b32, -amdgpu_op_s_dcache_inv, -amdgpu_op_s_wqm_b32, -amdgpu_op_s_cmp_lg_i32, -amdgpu_op_s_scratch_store_dwordx4, -amdgpu_op_s_buffer_store_dword, -amdgpu_op_s_nand_b64, -amdgpu_op_v_cmpx_t_u64, -amdgpu_op_buffer_store_format_x, -amdgpu_op_s_mul_hi_i32, -amdgpu_op_s_ashr_i64, -amdgpu_op_s_cbranch_join, -amdgpu_op_tbuffer_load_format_x, +amdgpu_op_s_min_u32, +amdgpu_op_v_sub_u32, +amdgpu_op_s_absdiff_i32, +amdgpu_op_v_mul_f16, +amdgpu_op_s_store_dword, +amdgpu_op_v_mul_legacy_f32, amdgpu_op_v_add_b32_e64, -amdgpu_op_s_buffer_load_dwordx16, -amdgpu_op_v_mad_f32, -amdgpu_op_v_mul_i32_i24, -amdgpu_op_v_ldexp_f16_e64, -amdgpu_op_tbuffer_store_format_x, -amdgpu_op_s_bcnt0_i32_b64, -amdgpu_op_s_cmp_le_u32, amdgpu_op_s_lshl4_add_u32, -amdgpu_op_v_mul_legacy_f32_e64, -amdgpu_op_s_add_i32, -amdgpu_op_v_lshlrev_b16_e64, -amdgpu_op_v_nop_e64, -amdgpu_op_tbuffer_load_format_xyzw, -amdgpu_op_s_ttracedata, -amdgpu_op_v_cmp_lt_u64_e64, -amdgpu_op_s_store_dword, -amdgpu_op_s_setprio, -amdgpu_op_s_fltbit_i32_i64, -amdgpu_op_s_orn2_savexec_b64, -amdgpu_op_v_add_co_u32, -amdgpu_op_s_bfe_u32, -amdgpu_op_v_mul_i32_i24_e64, -amdgpu_op_s_or_b64, -amdgpu_op_buffer_load_dwordx4, -amdgpu_op_v_cvt_off_f32_i4_e64, -amdgpu_op_s_bitset1_b64, -amdgpu_op_s_cmp_gt_u32, -amdgpu_op_s_cbranch_vccz, -amdgpu_op_s_store_dwordx4, -amdgpu_op_s_orn2_b32, -amdgpu_op_s_bcnt1_i32_b32, -amdgpu_op_v_madak_f16_e64, -amdgpu_op_s_and_b64, +amdgpu_op_v_mul_u32_u24, +amdgpu_op_v_mac_f16_e64, +amdgpu_op_s_xnor_b32, +amdgpu_op_s_bitcmp0_b32, +amdgpu_op_s_subb_u32, +amdgpu_op_s_buffer_load_dword, +amdgpu_op_s_cmpk_ge_u32, +amdgpu_op_v_cmp_eq_u32, +amdgpu_op_s_dcache_memrealtime, +amdgpu_op_s_cmp_lt_i32, +amdgpu_op_s_scratch_load_dword, +amdgpu_op_v_xno2_b32, +amdgpu_op_ds_read_b32, amdgpu_op_s_buffer_store_dwordx4, -amdgpu_op_v_cmp_gt_u64, -amdgpu_op_v_madmk_f16, +amdgpu_op_s_quadmask_b32, +amdgpu_op_v_subb_co_u32, +amdgpu_op_v_subrev_u32_e64, +amdgpu_op_v_cmp_neq_f16_e64, +amdgpu_op_v_mul_lo_u32, +amdgpu_op_v_cmp_ne_u32_e64, amdgpu_op_v_cmp_ne_u32, -amdgpu_op_v_cvt_f32_u32_e64, -amdgpu_op_v_cvt_u32_f32_e64, -amdgpu_op_v_cmp_eq_u32, -amdgpu_op_s_cmp_lg_u32, -amdgpu_op_s_setvkip, -amdgpu_op_s_cslect_b64, -amdgpu_op_s_scratch_load_dwordx4, -amdgpu_op_v_lshrrev_b16, -amdgpu_op_s_cmp_gt_i32, -amdgpu_op_s_call_b64, -amdgpu_op_v_add_b32, -amdgpu_op_s_xnor_b32, -amdgpu_op_s_lshl1_add_u32, -amdgpu_op_v_cvt_rpi_i32_f32_e64, -amdgpu_op_s_trap, -amdgpu_op_s_lshr_b32, -amdgpu_op_v_madak_f16, -amdgpu_op_tbuffer_store_format_xyzw, -amdgpu_op_s_decperflevel, -amdgpu_op_s_andn1_saveexec_b64, -amdgpu_op_s_bfe_i32, -amdgpu_op_s_cmp_eq_u64, -amdgpu_op_v_sub_u16, -amdgpu_op_v_lshlrev_b64, -amdgpu_op_v_interp_mov_f32, -amdgpu_op_s_andn2_wrexec_b64, -amdgpu_op_s_dcache_memtime, -amdgpu_op_s_cbranch_cdbgsys_and_user, -amdgpu_op_s_cmpk_ge_i32, -amdgpu_op_v_max_f16_e64, -amdgpu_op_v_mac_f16, +amdgpu_op_s_sext_i32_i16, +amdgpu_op_s_cmp_le_u32, +amdgpu_op_s_max_u32, diff --git a/common/h/dyn_regs.h b/common/h/dyn_regs.h index a34584ca48..f4e1cfe06f 100644 --- a/common/h/dyn_regs.h +++ b/common/h/dyn_regs.h @@ -50,16 +50,16 @@ namespace Dyninst //0xff000000 is used to encode architecture typedef enum { - Arch_none = 0x00000000, - Arch_x86 = 0x14000000, - Arch_x86_64 = 0x18000000, - Arch_ppc32 = 0x24000000, - Arch_ppc64 = 0x28000000, - Arch_aarch32 = 0x44000000, //for later use - Arch_aarch64 = 0x48000000, - Arch_amdgpu_vega = 0x84000000, - Arch_cuda = 0x88000000, - Arch_amdgpu_rdna = 0x8c000000, //future support for rdna + Arch_none = 0x00000000, + Arch_x86 = 0x14000000, + Arch_x86_64 = 0x18000000, + Arch_ppc32 = 0x24000000, + Arch_ppc64 = 0x28000000, + Arch_aarch32 = 0x44000000, //for later use + Arch_aarch64 = 0x48000000, + Arch_amdgpu_vega = 0x84000000, + Arch_cuda = 0x88000000, + Arch_amdgpu_cdna2 = 0x94000000, //future support for cdna2 Arch_intelGen9 = 0xb6000000 //same as machine no. retrevied from eu-readelf } Architecture; @@ -70,7 +70,7 @@ namespace Dyninst friend struct ::Dyninst::x86OperandParser; friend struct ::Dyninst::ppcOperandParser; friend struct ::Dyninst::aarch64OperandParser; - private: + private: signed int reg; typedef std::map NameMap; @@ -80,7 +80,7 @@ namespace Dyninst // reg_idx is set to the index/id of the register for future lookup // offset is set to the byte offset from where the register value starts, that is, sub register access ( or register access in a register vector) void getAMDGPUROSERegister(int ®_class, int ®_idx, int &offset); - public: + public: MachRegister(); explicit MachRegister(signed int r); @@ -98,6 +98,8 @@ namespace Dyninst bool operator==(const MachRegister &a) const; operator signed int() const; signed int val() const; + + // Return the category of the MachRegister unsigned int regClass() const; static MachRegister getPC(Dyninst::Architecture arch); @@ -107,15 +109,15 @@ namespace Dyninst static MachRegister getSyscallNumberReg(Dyninst::Architecture arch); static MachRegister getSyscallNumberOReg(Dyninst::Architecture arch); static MachRegister getSyscallReturnValueReg(Dyninst::Architecture arch); - static MachRegister getZeroFlag(Dyninst::Architecture arch); + static MachRegister getZeroFlag(Dyninst::Architecture arch); bool isPC() const; bool isFramePointer() const; bool isStackPointer() const; bool isSyscallNumberReg() const; bool isSyscallReturnValueReg() const; - bool isFlag() const; - bool isZeroFlag() const; + bool isFlag() const; + bool isZeroFlag() const; void getROSERegister(int &c, int &n, int &p); @@ -124,1891 +126,2069 @@ namespace Dyninst int getDwarfEnc() const; static MachRegister getArchReg(unsigned int regNum, Dyninst::Architecture arch); - }; - - /** - * DEF_REGISTER will define its first parameter as the name of the object - * it's declaring, and 'i' as the integer value representing that object. - * As an example, the name of a register may be - * x86::EAX - * with that register having a value of - * x86::iEAX - * - * The value is mostly useful in the 'case' part switch statements. - **/ + }; + + /** + * DEF_REGISTER will define its first parameter as the name of the object + * it's declaring, and 'i' as the integer value representing that object. + * As an example, the name of a register may be + * x86::EAX + * with that register having a value of + * x86::iEAX + * + * The value is mostly useful in the 'case' part switch statements. + **/ #if defined(DYN_DEFINE_REGS) - //DYN_DEFINE_REGS Should only be defined in libcommon. - //We want one definition, which will be in libcommon, and declarations - //for everyone else. - // - //I wanted these to be const MachRegister objects, but that changes the - //linker scope. Instead they're non-const. Every accessor function is - //const anyways, so we'll just close our eyes and pretend they're declared - //const. + //DYN_DEFINE_REGS Should only be defined in libcommon. + //We want one definition, which will be in libcommon, and declarations + //for everyone else. + // + //I wanted these to be const MachRegister objects, but that changes the + //linker scope. Instead they're non-const. Every accessor function is + //const anyways, so we'll just close our eyes and pretend they're declared + //const. #define DEF_REGISTER(name, value, Arch) \ - const signed int i##name = (value); \ - COMMON_EXPORT MachRegister name(i##name, Arch "::" #name) + const signed int i##name = (value); \ + COMMON_EXPORT MachRegister name(i##name, Arch "::" #name) #else #define DEF_REGISTER(name, value, Arch) \ - const signed int i##name = (value); \ - COMMON_EXPORT extern MachRegister name + const signed int i##name = (value); \ + COMMON_EXPORT extern MachRegister name #endif - /** - * For interpreting constants: - * Lowest 16 bits (0x000000ff) is base register ID - * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- - * used on x86/x86_64 to distinguish between things like EAX and AH - * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... - * Top 16 bits (0xff000000) are the architecture. - * - * These values/layout are not guaranteed to remain the same as part of the - * public interface, and may change. - **/ - - //Abstract registers used for stackwalking - DEF_REGISTER(InvalidReg, 0 | Arch_none, "abstract"); - DEF_REGISTER(FrameBase, 1 | Arch_none, "abstract"); - DEF_REGISTER(ReturnAddr, 2 | Arch_none, "abstract"); - DEF_REGISTER(StackTop, 3 | Arch_none, "abstract"); - // DWARF-ism; the CFA is the value of the stack pointer in the previous frame - DEF_REGISTER(CFA, 4 | Arch_none, "abstract"); - - namespace x86 - { - const signed int L_REG = 0x00000100; //8-bit, first byte - const signed int H_REG = 0x00000200; //8-bit, second byte - const signed int W_REG = 0x00000300; //16-bit, first word - // MachRegister::getBaseRegister clears the bit field for size, - // so the full register size has to be 0 - const signed int FULL = 0x00000000; //32 bits - const signed int OCT = 0x00000600; //128 bits - const signed int FPDBL = 0x00000700; // 80 bits - const signed int BIT = 0x00000800; // 1 bit - const signed int YMMS = 0x00000900; // YMM are 256 bits - const signed int ZMMS = 0x00000A00; // ZMM are 512 bits - const signed int GPR = 0x00010000; - const signed int SEG = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int MISC = 0x00040000; - const signed int KMASK = 0x00050000; - const signed int XMM = 0x00060000; - const signed int YMM = 0x00070000; - const signed int ZMM = 0x00080000; - const signed int MMX = 0x00090000; - const signed int CTL = 0x000A0000; - const signed int DBG = 0x000B0000; - const signed int TST = 0x000C0000; - const signed int BASEA = 0x0; - const signed int BASEC = 0x1; - const signed int BASED = 0x2; - const signed int BASEB = 0x3; - const signed int BASESP = 0x4; - const signed int BASEBP = 0x5; - const signed int BASESI = 0x6; - const signed int BASEDI = 0x7; - const signed int FLAGS = 0x0; - - const signed int CF = 0x0; - const signed int FLAG1 = 0x1; - const signed int PF = 0x2; - const signed int FLAG3 = 0x3; - const signed int AF = 0x4; - const signed int FLAG5 = 0x5; - const signed int ZF = 0x6; - const signed int SF = 0x7; - const signed int TF = 0x8; - const signed int IF = 0x9; - const signed int DF = 0xa; - const signed int OF = 0xb; - const signed int FLAGC = 0xc; - const signed int FLAGD = 0xd; - const signed int NT = 0xe; - const signed int FLAGF = 0xf; - const signed int RF = 0x10; - - DEF_REGISTER(eax, BASEA | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ecx, BASEC | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(edx, BASED | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ebx, BASEB | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(esp, BASESP | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ebp, BASEBP | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(esi, BASESI | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(edi, BASEDI | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(eip, 0x10 | FULL | Arch_x86, "x86"); - DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86, "x86"); - DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag1, FLAG1 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag3, FLAG3 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag5, FLAG5 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagc, FLAGC | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagd, FLAGD | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagf, FLAGF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(ds, 0x0 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(es, 0x1 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(fs, 0x2 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(gs, 0x3 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(cs, 0x4 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(ss, 0x5 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(oeax, 0x0 | FULL | MISC | Arch_x86, "x86"); - DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86, "x86"); - DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86, "x86"); - - DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86, "x86"); - - DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86, "x86"); - - - DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86, "x86"); - - DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86, "x86"); - - DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); - } - namespace x86_64 - { - const signed int L_REG = 0x00000100; //8-bit, first byte - const signed int H_REG = 0x00000200; //8-bit, second byte - const signed int W_REG = 0x00000300; //16 bit, first work - const signed int D_REG = 0x00000F00; //32 bit, first double word - // MachRegister::getBaseRegister clears the bit field for size, - // so the full register size has to be 0 - const signed int FULL = 0x00000000; //64 bits - const signed int OCT = 0x00000600; //128 bits - const signed int FPDBL = 0x00000700; // 80 bits - const signed int BIT = 0x00000800; // 1 bit - const signed int YMMS = 0x00000900; // YMM are 256 bits - const signed int ZMMS = 0x00000A00; // ZMM are 512 bits - const signed int GPR = 0x00010000; - const signed int SEG = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int MISC = 0x00040000; - const signed int KMASK = 0x00050000; - const signed int XMM = 0x00060000; - const signed int YMM = 0x00070000; - const signed int ZMM = 0x00080000; - const signed int MMX = 0x00090000; - const signed int CTL = 0x000A0000; - const signed int DBG = 0x000B0000; - const signed int TST = 0x000C0000; - const signed int FLAGS = 0x00000000; - const signed int BASEA = 0x0; - const signed int BASEC = 0x1; - const signed int BASED = 0x2; - const signed int BASEB = 0x3; - const signed int BASESP = 0x4; - const signed int BASEBP = 0x5; - const signed int BASESI = 0x6; - const signed int BASEDI = 0x7; - const signed int BASE8 = 0x8; - const signed int BASE9 = 0x9; - const signed int BASE10 = 0xa; - const signed int BASE11 = 0xb; - const signed int BASE12 = 0xc; - const signed int BASE13 = 0xd; - const signed int BASE14 = 0xe; - const signed int BASE15 = 0xf; - - const signed int CF = x86::CF; - const signed int PF = x86::PF; - const signed int AF = x86::AF; - const signed int ZF = x86::ZF; - const signed int SF = x86::SF; - const signed int TF = x86::TF; - const signed int IF = x86::IF; - const signed int DF = x86::DF; - const signed int OF = x86::OF; - const signed int NT = x86::NT; - const signed int RF = x86::RF; - - DEF_REGISTER(rax, BASEA | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rcx, BASEC | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rdx, BASED | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rbx, BASEB | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rsp, BASESP | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rbp, BASEBP | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rsi, BASESI | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rdi, BASEDI | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8, BASE8 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9, BASE9 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10, BASE10 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11, BASE11 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12, BASE12 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13, BASE13 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14, BASE14 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15, BASE15 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(eax, BASEA | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ecx, BASEC | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(edx, BASED | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ebx, BASEB | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(spl, BASESP | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(esp, BASESP | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bpl, BASEBP | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ebp, BASEBP | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dil, BASEDI | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(edi, BASEDI | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(sil, BASESI | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(esi, BASESI | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8b, BASE8 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8w, BASE8 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8d, BASE8 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9b, BASE9 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9w, BASE9 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9d, BASE9 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10b, BASE10 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10w, BASE10 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10d, BASE10 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11b, BASE11 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11w, BASE11 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11d, BASE11 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12b, BASE12 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12w, BASE12 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12d, BASE12 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13b, BASE13 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13w, BASE13 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13d, BASE13 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14b, BASE14 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14w, BASE14 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14d, BASE14 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15b, BASE15 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15w, BASE15 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15d, BASE15 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rip, 0x10 | FULL | Arch_x86_64, "x86_64"); - DEF_REGISTER(eip, 0x10 | D_REG | Arch_x86_64, "x86_64"); - DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(ds, 0x0 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(es, 0x1 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(fs, 0x2 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(gs, 0x3 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(cs, 0x4 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(ss, 0x5 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(orax, 0x0 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); - } - namespace ppc32 { - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - - DEF_REGISTER(r0, 0 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r1, 1 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r2, 2 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r3, 3 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r4, 4 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r5, 5 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r6, 6 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r7, 7 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r8, 8 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r9, 9 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r10, 10 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r11, 11 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r12, 12 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r13, 13 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r14, 14 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r15, 15 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r16, 16 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r17, 17 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r18, 18 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r19, 19 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r20, 20 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r21, 21 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r22, 22 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r23, 23 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r24, 24 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r25, 25 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r26, 26 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r27, 27 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r28, 28 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r29, 29 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r30, 30 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r31, 31 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(mq, 0 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(xer, 1 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lr, 8 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ctr, 9 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(amr, 13 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dscr, 17 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dar, 19 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dec, 22 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(srr0, 26 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(srr1, 27 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cfar, 28 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(amr_pri, 29 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pid, 48 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(gdecar, 53 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(decar, 54 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(mcivpr, 55 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lper, 56 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lperu, 57 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(csrr0, 58 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(csrr1, 59 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(gtsrwr, 60 | SPR | Arch_ppc32, "ppc32"); -// DEF_REGISTER(iamr, 61 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(esr, 62 | SPR | Arch_ppc32, "ppc32"); -// DEF_REGISTER(ivpr, 66 | SPR | Arch_ppc32, "ppc32"); - - DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc32, "ppc32"); - - - DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc32, "ppc32"); - - DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc32, "ppc32"); - - - DEF_REGISTER(ear, 282 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pvr, 287 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pc, 600 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(msr, 610 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg0, 613 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg1, 614 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg2, 615 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg3, 616 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg4, 617 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg5, 618 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg6, 619 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg7, 620 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0, 621 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1, 622 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2, 623 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3, 624 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4, 625 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5, 626 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6, 627 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7, 628 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr, 629 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(or3, 630 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(trap, 631 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ppr, 896 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc32, "ppc32"); - - - } - namespace ppc64 { - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - const signed int VSR = 0x00000000; - - DEF_REGISTER(r0, 0 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r1, 1 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r2, 2 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r3, 3 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r4, 4 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r5, 5 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r6, 6 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r7, 7 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r8, 8 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r9, 9 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r10, 10 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r11, 11 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r12, 12 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r13, 13 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r14, 14 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r15, 15 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r16, 16 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r17, 17 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r18, 18 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r19, 19 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r20, 20 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r21, 21 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r22, 22 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r23, 23 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r24, 24 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r25, 25 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r26, 26 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r27, 27 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r28, 28 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r29, 29 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r30, 30 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r31, 31 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(mq, 0 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(xer, 1 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(lr, 8 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ctr, 9 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dar, 19 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dec, 22 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(srr0, 26 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(srr1, 27 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc64, "ppc64"); - - DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ear, 282 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(pvr, 287 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(pc, 600 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(msr, 610 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg0, 613 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg1, 614 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg2, 615 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg3, 616 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg4, 617 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg5, 618 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg6, 619 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg7, 620 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0, 621 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1, 622 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2, 623 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3, 624 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4, 625 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5, 626 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6, 627 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7, 628 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr, 629 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(or3, 630 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(trap, 631 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ppr, 896 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc64, "ppc64"); - - DEF_REGISTER(vsr0, 0 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr1, 1 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr2, 2 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr3, 3 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr4, 4 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr5, 5 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr6, 6 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr7, 7 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr8, 8 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr9, 9 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr10, 10 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr11, 11 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr12, 12 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr13, 13 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr14, 14 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr15, 15 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr16, 16 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr17, 17 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr18, 18 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr19, 19 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr20, 20 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr21, 21 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr22, 22 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr23, 23 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr24, 24 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr25, 25 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr26, 26 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr27, 27 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr28, 28 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr29, 29 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr30, 30 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr31, 31 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr32, 32 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr33, 33 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr34, 34 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr35, 35 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr36, 36 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr37, 37 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr38, 38 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr39, 39 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr40, 40 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr41, 41 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr42, 42 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr43, 43 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr44, 44 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr45, 45 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr46, 46 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr47, 47 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr48, 48 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr49, 49 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr50, 50 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr51, 51 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr52, 52 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr53, 53 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr54, 54 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr55, 55 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr56, 56 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr57, 57 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr58, 58 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr59, 59 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr60, 60 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr61, 61 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr62, 62 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr63, 63 | VSR | Arch_ppc64, "ppc64"); - - - - - } - - namespace aarch64{ - //0xff000000 0x00ff0000 0x0000ff00 0x000000ff - //arch reg cat:GPR alias&subrange reg ID - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - const signed int SYSREG = 0x00100000; - - const signed int BIT = 0x00008000; - const signed int B_REG = 0x00000100; //8bit byte reg - const signed int W_REG = 0x00000300; //16bit half-wor reg - const signed int D_REG = 0x00000f00; //32bit single-word reg - const signed int FULL = 0x00000000; //64bit double-word reg - const signed int Q_REG = 0x00000400; //128bit reg - const signed int HQ_REG = 0x00000500; //second 64bit in 128bit reg - - //31 GPRs, double word long registers - // (name regID| alias | cat | arch arch ) - DEF_REGISTER(x0, 0 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w0, 0 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x1, 1 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w1, 1 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x2, 2 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w2, 2 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x3, 3 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w3, 3 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x4, 4 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w4, 4 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x5, 5 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w5, 5 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x6, 6 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w6, 6 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x7, 7 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w7, 7 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x8, 8 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w8, 8 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x9, 9 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w9, 9 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x10, 10 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w10, 10 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x11, 11 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w11, 11 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x12, 12 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w12, 12 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x13, 13 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w13, 13 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x14, 14 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w14, 14 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x15, 15 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w15, 15 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x16, 16 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w16, 16 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x17, 17 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w17, 17 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x18, 18 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w18, 18 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x19, 19 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w19, 19 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x20, 20 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w20, 20 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x21, 21 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w21, 21 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x22, 22 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w22, 22 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x23, 23 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w23, 23 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x24, 24 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w24, 24 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x25, 25 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w25, 25 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x26, 26 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w26, 26 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x27, 27 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w27, 27 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x28, 28 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w28, 28 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x29, 29 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w29, 29 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x30, 30 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w30, 30 | D_REG |GPR | Arch_aarch64, "aarch64"); - - //32 FPRs-----------q-d-s-h-b - //128 bit - DEF_REGISTER(q0, 0 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q1, 1 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q2, 2 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q3, 3 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q4, 4 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q5, 5 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q6, 6 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q7, 7 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q8, 8 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q9, 9 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q10, 10 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q11, 11 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q12, 12 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q13, 13 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q14, 14 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q15, 15 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q16, 16 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q17, 17 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q18, 18 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q19, 19 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q20, 20 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q21, 21 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q22, 22 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q23, 23 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q24, 24 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q25, 25 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q26, 26 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q27, 27 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q28, 28 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q29, 29 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q30, 30 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q31, 31 | Q_REG |FPR | Arch_aarch64, "aarch64"); - - // second 64bit - DEF_REGISTER(hq0, 0 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq1, 1 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq2, 2 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq3, 3 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq4, 4 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq5, 5 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq6, 6 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq7, 7 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq8, 8 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq9, 9 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq10, 10 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq11, 11 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq12, 12 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq13, 13 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq14, 14 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq15, 15 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq16, 16 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq17, 17 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq18, 18 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq19, 19 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq20, 20 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq21, 21 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq22, 22 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq23, 23 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq24, 24 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq25, 25 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq26, 26 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq27, 27 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq28, 28 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq29, 29 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq30, 30 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq31, 31 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - - //64bit FP regs - DEF_REGISTER(d0, 0 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d1, 1 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d2, 2 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d3, 3 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d4, 4 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d5, 5 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d6, 6 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d7, 7 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d8, 8 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d9, 9 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d10, 10 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d11, 11 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d12, 12 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d13, 13 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d14, 14 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d15, 15 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d16, 16 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d17, 17 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d18, 18 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d19, 19 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d20, 20 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d21, 21 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d22, 22 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d23, 23 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d24, 24 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d25, 25 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d26, 26 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d27, 27 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d28, 28 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d29, 29 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d30, 30 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d31, 31 | FULL |FPR | Arch_aarch64, "aarch64"); - - //32 bit FP regs - DEF_REGISTER(s0, 0 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s1, 1 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s2, 2 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s3, 3 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s4, 4 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s5, 5 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s6, 6 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s7, 7 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s8, 8 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s9, 9 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s10, 10 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s11, 11 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s12, 12 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s13, 13 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s14, 14 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s15, 15 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s16, 16 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s17, 17 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s18, 18 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s19, 19 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s20, 20 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s21, 21 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s22, 22 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s23, 23 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s24, 24 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s25, 25 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s26, 26 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s27, 27 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s28, 28 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s29, 29 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s30, 30 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s31, 31 | D_REG |FPR | Arch_aarch64, "aarch64"); - - - //16 bit FP regs - DEF_REGISTER(h0, 0 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h1, 1 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h2, 2 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h3, 3 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h4, 4 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h5, 5 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h6, 6 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h7, 7 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h8, 8 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h9, 9 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h10, 10 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h11, 11 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h12, 12 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h13, 13 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h14, 14 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h15, 15 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h16, 16 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h17, 17 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h18, 18 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h19, 19 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h20, 20 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h21, 21 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h22, 22 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h23, 23 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h24, 24 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h25, 25 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h26, 26 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h27, 27 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h28, 28 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h29, 29 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h30, 30 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h31, 31 | W_REG |FPR | Arch_aarch64, "aarch64"); - - //8 bit FP regs - DEF_REGISTER(b0, 0 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b1, 1 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b2, 2 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b3, 3 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b4, 4 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b5, 5 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b6, 6 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b7, 7 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b8, 8 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b9, 9 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b10, 10 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b11, 11 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b12, 12 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b13, 13 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b14, 14 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b15, 15 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b16, 16 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b17, 17 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b18, 18 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b19, 19 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b20, 20 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b21, 21 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b22, 22 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b23, 23 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b24, 24 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b25, 25 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b26, 26 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b27, 27 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b28, 28 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b29, 29 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b30, 30 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b31, 31 | B_REG |FPR | Arch_aarch64, "aarch64"); + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + //Abstract registers used for stackwalking + DEF_REGISTER(InvalidReg, 0 | Arch_none, "abstract"); + DEF_REGISTER(FrameBase, 1 | Arch_none, "abstract"); + DEF_REGISTER(ReturnAddr, 2 | Arch_none, "abstract"); + DEF_REGISTER(StackTop, 3 | Arch_none, "abstract"); + // DWARF-ism; the CFA is the value of the stack pointer in the previous frame + DEF_REGISTER(CFA, 4 | Arch_none, "abstract"); + + namespace x86 + { + const signed int L_REG = 0x00000100; //8-bit, first byte + const signed int H_REG = 0x00000200; //8-bit, second byte + const signed int W_REG = 0x00000300; //16-bit, first word + // MachRegister::getBaseRegister clears the bit field for size, + // so the full register size has to be 0 + const signed int FULL = 0x00000000; //32 bits + const signed int OCT = 0x00000600; //128 bits + const signed int FPDBL = 0x00000700; // 80 bits + const signed int BIT = 0x00000800; // 1 bit + const signed int YMMS = 0x00000900; // YMM are 256 bits + const signed int ZMMS = 0x00000A00; // ZMM are 512 bits + const signed int GPR = 0x00010000; + const signed int SEG = 0x00020000; + const signed int FLAG = 0x00030000; + const signed int MISC = 0x00040000; + const signed int KMASK = 0x00050000; + const signed int XMM = 0x00060000; + const signed int YMM = 0x00070000; + const signed int ZMM = 0x00080000; + const signed int MMX = 0x00090000; + const signed int CTL = 0x000A0000; + const signed int DBG = 0x000B0000; + const signed int TST = 0x000C0000; + const signed int BASEA = 0x0; + const signed int BASEC = 0x1; + const signed int BASED = 0x2; + const signed int BASEB = 0x3; + const signed int BASESP = 0x4; + const signed int BASEBP = 0x5; + const signed int BASESI = 0x6; + const signed int BASEDI = 0x7; + const signed int FLAGS = 0x0; + + const signed int CF = 0x0; + const signed int FLAG1 = 0x1; + const signed int PF = 0x2; + const signed int FLAG3 = 0x3; + const signed int AF = 0x4; + const signed int FLAG5 = 0x5; + const signed int ZF = 0x6; + const signed int SF = 0x7; + const signed int TF = 0x8; + const signed int IF = 0x9; + const signed int DF = 0xa; + const signed int OF = 0xb; + const signed int FLAGC = 0xc; + const signed int FLAGD = 0xd; + const signed int NT = 0xe; + const signed int FLAGF = 0xf; + const signed int RF = 0x10; + + DEF_REGISTER(eax, BASEA | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(ecx, BASEC | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(edx, BASED | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(ebx, BASEB | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(esp, BASESP | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(ebp, BASEBP | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(esi, BASESI | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(edi, BASEDI | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER(eip, 0x10 | FULL | Arch_x86, "x86"); + DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86, "x86"); + DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flag1, FLAG1 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flag3, FLAG3 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flag5, FLAG5 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flagc, FLAGC | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flagd, FLAGD | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(flagf, FLAGF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER(ds, 0x0 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(es, 0x1 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(fs, 0x2 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(gs, 0x3 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(cs, 0x4 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(ss, 0x5 | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER(oeax, 0x0 | FULL | MISC | Arch_x86, "x86"); + DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86, "x86"); + DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86, "x86"); + + DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86, "x86"); + DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86, "x86"); + + DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86, "x86"); + DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86, "x86"); + + + DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86, "x86"); + + DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86, "x86"); + + DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); + DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); + } + namespace x86_64 + { + const signed int L_REG = 0x00000100; //8-bit, first byte + const signed int H_REG = 0x00000200; //8-bit, second byte + const signed int W_REG = 0x00000300; //16 bit, first work + const signed int D_REG = 0x00000F00; //32 bit, first double word + // MachRegister::getBaseRegister clears the bit field for size, + // so the full register size has to be 0 + const signed int FULL = 0x00000000; //64 bits + const signed int OCT = 0x00000600; //128 bits + const signed int FPDBL = 0x00000700; // 80 bits + const signed int BIT = 0x00000800; // 1 bit + const signed int YMMS = 0x00000900; // YMM are 256 bits + const signed int ZMMS = 0x00000A00; // ZMM are 512 bits + const signed int GPR = 0x00010000; + const signed int SEG = 0x00020000; + const signed int FLAG = 0x00030000; + const signed int MISC = 0x00040000; + const signed int KMASK = 0x00050000; + const signed int XMM = 0x00060000; + const signed int YMM = 0x00070000; + const signed int ZMM = 0x00080000; + const signed int MMX = 0x00090000; + const signed int CTL = 0x000A0000; + const signed int DBG = 0x000B0000; + const signed int TST = 0x000C0000; + const signed int FLAGS = 0x00000000; + const signed int BASEA = 0x0; + const signed int BASEC = 0x1; + const signed int BASED = 0x2; + const signed int BASEB = 0x3; + const signed int BASESP = 0x4; + const signed int BASEBP = 0x5; + const signed int BASESI = 0x6; + const signed int BASEDI = 0x7; + const signed int BASE8 = 0x8; + const signed int BASE9 = 0x9; + const signed int BASE10 = 0xa; + const signed int BASE11 = 0xb; + const signed int BASE12 = 0xc; + const signed int BASE13 = 0xd; + const signed int BASE14 = 0xe; + const signed int BASE15 = 0xf; + + const signed int CF = x86::CF; + const signed int PF = x86::PF; + const signed int AF = x86::AF; + const signed int ZF = x86::ZF; + const signed int SF = x86::SF; + const signed int TF = x86::TF; + const signed int IF = x86::IF; + const signed int DF = x86::DF; + const signed int OF = x86::OF; + const signed int NT = x86::NT; + const signed int RF = x86::RF; + + DEF_REGISTER(rax, BASEA | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rcx, BASEC | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rdx, BASED | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rbx, BASEB | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rsp, BASESP | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rbp, BASEBP | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rsi, BASESI | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rdi, BASEDI | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r8, BASE8 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r9, BASE9 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r10, BASE10 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r11, BASE11 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r12, BASE12 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r13, BASE13 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r14, BASE14 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r15, BASE15 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(eax, BASEA | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ecx, BASEC | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(edx, BASED | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ebx, BASEB | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(spl, BASESP | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(esp, BASESP | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(bpl, BASEBP | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(ebp, BASEBP | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(dil, BASEDI | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(edi, BASEDI | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(sil, BASESI | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(esi, BASESI | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r8b, BASE8 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r8w, BASE8 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r8d, BASE8 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r9b, BASE9 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r9w, BASE9 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r9d, BASE9 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r10b, BASE10 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r10w, BASE10 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r10d, BASE10 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r11b, BASE11 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r11w, BASE11 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r11d, BASE11 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r12b, BASE12 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r12w, BASE12 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r12d, BASE12 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r13b, BASE13 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r13w, BASE13 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r13d, BASE13 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r14b, BASE14 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r14w, BASE14 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r14d, BASE14 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r15b, BASE15 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r15w, BASE15 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(r15d, BASE15 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER(rip, 0x10 | FULL | Arch_x86_64, "x86_64"); + DEF_REGISTER(eip, 0x10 | D_REG | Arch_x86_64, "x86_64"); + DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER(ds, 0x0 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(es, 0x1 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(fs, 0x2 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(gs, 0x3 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(cs, 0x4 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(ss, 0x5 | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER(orax, 0x0 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); + } + namespace ppc32 { + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + + DEF_REGISTER(r0, 0 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r1, 1 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r2, 2 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r3, 3 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r4, 4 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r5, 5 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r6, 6 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r7, 7 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r8, 8 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r9, 9 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r10, 10 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r11, 11 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r12, 12 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r13, 13 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r14, 14 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r15, 15 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r16, 16 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r17, 17 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r18, 18 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r19, 19 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r20, 20 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r21, 21 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r22, 22 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r23, 23 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r24, 24 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r25, 25 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r26, 26 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r27, 27 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r28, 28 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r29, 29 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r30, 30 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(r31, 31 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER(mq, 0 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(xer, 1 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(lr, 8 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ctr, 9 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(amr, 13 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dscr, 17 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dar, 19 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dec, 22 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(srr0, 26 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(srr1, 27 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cfar, 28 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(amr_pri, 29 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(pid, 48 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(gdecar, 53 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(decar, 54 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(mcivpr, 55 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(lper, 56 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(lperu, 57 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(csrr0, 58 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(csrr1, 59 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(gtsrwr, 60 | SPR | Arch_ppc32, "ppc32"); + // DEF_REGISTER(iamr, 61 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(esr, 62 | SPR | Arch_ppc32, "ppc32"); + // DEF_REGISTER(ivpr, 66 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc32, "ppc32"); + + + DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc32, "ppc32"); + + + DEF_REGISTER(ear, 282 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(pvr, 287 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(pc, 600 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(msr, 610 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg0, 613 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg1, 614 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg2, 615 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg3, 616 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg4, 617 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg5, 618 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg6, 619 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(seg7, 620 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr0, 621 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr1, 622 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr2, 623 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr3, 624 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr4, 625 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr5, 626 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr6, 627 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr7, 628 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr, 629 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(or3, 630 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(trap, 631 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ppr, 896 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc32, "ppc32"); + + + } + namespace ppc64 { + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + const signed int VSR = 0x00000000; + + DEF_REGISTER(r0, 0 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r1, 1 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r2, 2 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r3, 3 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r4, 4 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r5, 5 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r6, 6 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r7, 7 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r8, 8 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r9, 9 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r10, 10 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r11, 11 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r12, 12 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r13, 13 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r14, 14 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r15, 15 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r16, 16 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r17, 17 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r18, 18 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r19, 19 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r20, 20 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r21, 21 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r22, 22 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r23, 23 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r24, 24 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r25, 25 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r26, 26 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r27, 27 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r28, 28 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r29, 29 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r30, 30 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(r31, 31 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(mq, 0 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(xer, 1 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(lr, 8 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ctr, 9 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dar, 19 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dec, 22 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(srr0, 26 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(srr1, 27 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc64, "ppc64"); + + DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ear, 282 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(pvr, 287 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(pc, 600 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(msr, 610 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg0, 613 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg1, 614 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg2, 615 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg3, 616 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg4, 617 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg5, 618 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg6, 619 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(seg7, 620 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr0, 621 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr1, 622 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr2, 623 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr3, 624 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr4, 625 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr5, 626 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr6, 627 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr7, 628 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr, 629 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(or3, 630 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(trap, 631 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ppr, 896 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc64, "ppc64"); + + DEF_REGISTER(vsr0, 0 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr1, 1 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr2, 2 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr3, 3 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr4, 4 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr5, 5 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr6, 6 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr7, 7 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr8, 8 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr9, 9 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr10, 10 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr11, 11 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr12, 12 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr13, 13 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr14, 14 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr15, 15 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr16, 16 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr17, 17 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr18, 18 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr19, 19 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr20, 20 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr21, 21 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr22, 22 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr23, 23 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr24, 24 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr25, 25 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr26, 26 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr27, 27 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr28, 28 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr29, 29 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr30, 30 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr31, 31 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr32, 32 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr33, 33 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr34, 34 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr35, 35 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr36, 36 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr37, 37 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr38, 38 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr39, 39 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr40, 40 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr41, 41 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr42, 42 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr43, 43 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr44, 44 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr45, 45 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr46, 46 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr47, 47 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr48, 48 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr49, 49 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr50, 50 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr51, 51 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr52, 52 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr53, 53 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr54, 54 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr55, 55 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr56, 56 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr57, 57 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr58, 58 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr59, 59 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr60, 60 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr61, 61 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr62, 62 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER(vsr63, 63 | VSR | Arch_ppc64, "ppc64"); + + + + + } + + namespace aarch64{ + //0xff000000 0x00ff0000 0x0000ff00 0x000000ff + //arch reg cat:GPR alias&subrange reg ID + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FLAG = 0x00030000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + const signed int SYSREG = 0x00100000; + + const signed int BIT = 0x00008000; + const signed int B_REG = 0x00000100; //8bit byte reg + const signed int W_REG = 0x00000300; //16bit half-wor reg + const signed int D_REG = 0x00000f00; //32bit single-word reg + const signed int FULL = 0x00000000; //64bit double-word reg + const signed int Q_REG = 0x00000400; //128bit reg + const signed int HQ_REG = 0x00000500; //second 64bit in 128bit reg + + //31 GPRs, double word long registers + // (name regID| alias | cat | arch arch ) + DEF_REGISTER(x0, 0 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w0, 0 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x1, 1 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w1, 1 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x2, 2 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w2, 2 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x3, 3 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w3, 3 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x4, 4 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w4, 4 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x5, 5 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w5, 5 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x6, 6 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w6, 6 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x7, 7 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w7, 7 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x8, 8 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w8, 8 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x9, 9 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w9, 9 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x10, 10 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w10, 10 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x11, 11 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w11, 11 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x12, 12 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w12, 12 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x13, 13 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w13, 13 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x14, 14 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w14, 14 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x15, 15 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w15, 15 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x16, 16 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w16, 16 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x17, 17 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w17, 17 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x18, 18 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w18, 18 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x19, 19 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w19, 19 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x20, 20 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w20, 20 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x21, 21 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w21, 21 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x22, 22 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w22, 22 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x23, 23 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w23, 23 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x24, 24 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w24, 24 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x25, 25 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w25, 25 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x26, 26 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w26, 26 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x27, 27 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w27, 27 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x28, 28 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w28, 28 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x29, 29 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w29, 29 | D_REG |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(x30, 30 | FULL |GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(w30, 30 | D_REG |GPR | Arch_aarch64, "aarch64"); + + //32 FPRs-----------q-d-s-h-b + //128 bit + DEF_REGISTER(q0, 0 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q1, 1 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q2, 2 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q3, 3 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q4, 4 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q5, 5 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q6, 6 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q7, 7 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q8, 8 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q9, 9 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q10, 10 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q11, 11 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q12, 12 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q13, 13 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q14, 14 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q15, 15 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q16, 16 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q17, 17 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q18, 18 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q19, 19 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q20, 20 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q21, 21 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q22, 22 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q23, 23 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q24, 24 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q25, 25 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q26, 26 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q27, 27 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q28, 28 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q29, 29 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q30, 30 | Q_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(q31, 31 | Q_REG |FPR | Arch_aarch64, "aarch64"); + + // second 64bit + DEF_REGISTER(hq0, 0 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq1, 1 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq2, 2 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq3, 3 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq4, 4 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq5, 5 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq6, 6 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq7, 7 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq8, 8 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq9, 9 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq10, 10 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq11, 11 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq12, 12 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq13, 13 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq14, 14 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq15, 15 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq16, 16 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq17, 17 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq18, 18 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq19, 19 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq20, 20 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq21, 21 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq22, 22 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq23, 23 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq24, 24 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq25, 25 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq26, 26 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq27, 27 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq28, 28 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq29, 29 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq30, 30 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(hq31, 31 | HQ_REG |FPR | Arch_aarch64, "aarch64"); + + //64bit FP regs + DEF_REGISTER(d0, 0 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d1, 1 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d2, 2 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d3, 3 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d4, 4 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d5, 5 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d6, 6 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d7, 7 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d8, 8 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d9, 9 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d10, 10 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d11, 11 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d12, 12 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d13, 13 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d14, 14 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d15, 15 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d16, 16 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d17, 17 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d18, 18 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d19, 19 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d20, 20 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d21, 21 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d22, 22 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d23, 23 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d24, 24 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d25, 25 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d26, 26 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d27, 27 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d28, 28 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d29, 29 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d30, 30 | FULL |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(d31, 31 | FULL |FPR | Arch_aarch64, "aarch64"); + + //32 bit FP regs + DEF_REGISTER(s0, 0 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s1, 1 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s2, 2 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s3, 3 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s4, 4 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s5, 5 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s6, 6 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s7, 7 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s8, 8 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s9, 9 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s10, 10 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s11, 11 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s12, 12 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s13, 13 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s14, 14 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s15, 15 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s16, 16 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s17, 17 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s18, 18 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s19, 19 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s20, 20 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s21, 21 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s22, 22 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s23, 23 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s24, 24 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s25, 25 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s26, 26 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s27, 27 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s28, 28 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s29, 29 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s30, 30 | D_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(s31, 31 | D_REG |FPR | Arch_aarch64, "aarch64"); + + + //16 bit FP regs + DEF_REGISTER(h0, 0 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h1, 1 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h2, 2 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h3, 3 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h4, 4 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h5, 5 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h6, 6 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h7, 7 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h8, 8 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h9, 9 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h10, 10 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h11, 11 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h12, 12 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h13, 13 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h14, 14 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h15, 15 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h16, 16 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h17, 17 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h18, 18 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h19, 19 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h20, 20 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h21, 21 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h22, 22 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h23, 23 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h24, 24 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h25, 25 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h26, 26 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h27, 27 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h28, 28 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h29, 29 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h30, 30 | W_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(h31, 31 | W_REG |FPR | Arch_aarch64, "aarch64"); + + //8 bit FP regs + DEF_REGISTER(b0, 0 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b1, 1 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b2, 2 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b3, 3 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b4, 4 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b5, 5 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b6, 6 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b7, 7 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b8, 8 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b9, 9 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b10, 10 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b11, 11 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b12, 12 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b13, 13 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b14, 14 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b15, 15 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b16, 16 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b17, 17 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b18, 18 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b19, 19 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b20, 20 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b21, 21 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b22, 22 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b23, 23 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b24, 24 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b25, 25 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b26, 26 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b27, 27 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b28, 28 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b29, 29 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b30, 30 | B_REG |FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(b31, 31 | B_REG |FPR | Arch_aarch64, "aarch64"); #include "aarch64_sys_regs.h" - //GPRs aliases: - //by convention - //x29 is used as frame pointer - //x30 is the linking register - //x31 can be sp or zero register depending on the context - - //special registers - //PC is not writable in aarch64 - const signed int N_FLAG = 31; - const signed int Z_FLAG = 30; - const signed int C_FLAG = 29; - const signed int V_FLAG = 28; - - DEF_REGISTER(sp, 31| FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(wsp, 0 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(pc, 32| FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(pstate, 2 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(xzr, 3 | FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(n, N_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(z, Z_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(c, C_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(v, V_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(wzr, 3 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(fpcr, 4 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(fpsr, 5 | D_REG |SPR | Arch_aarch64, "aarch64"); - - } //end of aarch64 namespace - namespace amdgpu_vega{ - //0xff000000 0x00ff0000 0x0000ff00 0x000000ff - //arch reg cat:GPR alias&subrange reg ID - const signed int SGPR = 0x00010000; - const signed int SGPR_VEC2 = 0x00020000; - const signed int SGPR_VEC4 = 0x00030000; - const signed int SGPR_VEC8 = 0x00040000; - const signed int SGPR_VEC16 = 0x00050000; - - const signed int VGPR = 0x00060000; - const signed int VGPR_VEC2 = 0x00070000; - const signed int VGPR_VEC4 = 0x00080000; - const signed int VGPR_VEC8 = 0x00090000; - const signed int VGPR_VEC16 = 0x000A0000; - - const signed int HWR = 0x000B0000; - const signed int TTMP_SGPR = 0x000C0000; - const signed int FLAGS = 0x000D0000; - const signed int PC = 0x000E0000; - const signed int SYSREG = 0x00100000; - - // aliasing for flags - // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 - // so we use thhat part to encode the low offset in the base register - // - - - - const signed int BITS_1 = 0x00000100; - const signed int BITS_2 = 0x00000200; - const signed int BITS_3 = 0x00000300; - const signed int BITS_4 = 0x00000400; - const signed int BITS_6 = 0x00000500; - const signed int BITS_7 = 0x00000600; - const signed int BITS_8 = 0x00000700; - const signed int BITS_9 = 0x00000800; - const signed int BITS_15 = 0x00000900; - const signed int BITS_16 = 0x00000A00; - const signed int BITS_32 = 0x00000B00; - const signed int BITS_48 = 0x00000C00; - const signed int BITS_64 = 0x00000D00; - const signed int BITS_128 = 0x00000E00; - const signed int BITS_256 = 0x00000F00; - const signed int BITS_512 = 0x00001000; - - - - - /*const signed int BIT = 0x00001000; - const signed int D_BIT = 0x00002000; - const signed int T_BIT = 0x00003000; - const signed int Q_BIT = 0x00004000; - const signed int H_BIT = 0x00006000; - const signed int S_BIT = 0x00007000; - const signed int O_BIT = 0x00008000; - const signed int N_BIT = 0x00009000; - const signed int D_REG_BIT = 0x0000A000; - - const signed int B_REG = 0x00000100; //8bit byte reg - const signed int W_REG = 0x00000200; //16bit half-wor reg - const signed int D_REG = 0x00000300; //32bit single-word reg - const signed int FE_REG = 0x00000400; //48bit reg - const signed int FULL = 0x00000500; //64bit double-word reg - const signed int Q_REG = 0x00000600; //128bit reg - const signed int YMMS = 0x00000700; //256bit reg - const signed int ZMMS = 0x00000800; //512bit reg - const signed int HQ_REG = 0x00000900; //second 64bit in 128bit reg*/ - - #include "amdgpu_vega_sys_regs.h" + //GPRs aliases: + //by convention + //x29 is used as frame pointer + //x30 is the linking register + //x31 can be sp or zero register depending on the context + + //special registers + //PC is not writable in aarch64 + const signed int N_FLAG = 31; + const signed int Z_FLAG = 30; + const signed int C_FLAG = 29; + const signed int V_FLAG = 28; + + DEF_REGISTER(sp, 31| FULL |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(wsp, 0 | D_REG |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(pc, 32| FULL |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(pstate, 2 | D_REG |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(xzr, 3 | FULL |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(n, N_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); + DEF_REGISTER(z, Z_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); + DEF_REGISTER(c, C_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); + DEF_REGISTER(v, V_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); + DEF_REGISTER(wzr, 3 | D_REG |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(fpcr, 4 | D_REG |SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER(fpsr, 5 | D_REG |SPR | Arch_aarch64, "aarch64"); + + } //end of aarch64 namespace + namespace amdgpu_vega{ + //0xff000000 0x00ff0000 0x0000ff00 0x000000ff + //arch reg cat:GPR alias&subrange reg ID + const signed int SGPR = 0x00010000; + const signed int SGPR_VEC2 = 0x00020000; + const signed int SGPR_VEC4 = 0x00030000; + const signed int SGPR_VEC8 = 0x00040000; + const signed int SGPR_VEC16 = 0x00050000; + + const signed int VGPR = 0x00060000; + const signed int VGPR_VEC2 = 0x00070000; + const signed int VGPR_VEC4 = 0x00080000; + const signed int VGPR_VEC8 = 0x00090000; + const signed int VGPR_VEC16 = 0x000A0000; + + const signed int HWR = 0x000B0000; + const signed int TTMP_SGPR = 0x000C0000; + const signed int FLAGS = 0x000D0000; + const signed int PC = 0x000E0000; + const signed int SYSREG = 0x00100000; + + // aliasing for flags + // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 + // so we use thhat part to encode the low offset in the base register + // + + + + const signed int BITS_1 = 0x00000100; + const signed int BITS_2 = 0x00000200; + const signed int BITS_3 = 0x00000300; + const signed int BITS_4 = 0x00000400; + const signed int BITS_6 = 0x00000500; + const signed int BITS_7 = 0x00000600; + const signed int BITS_8 = 0x00000700; + const signed int BITS_9 = 0x00000800; + const signed int BITS_15 = 0x00000900; + const signed int BITS_16 = 0x00000A00; + const signed int BITS_32 = 0x00000B00; + const signed int BITS_48 = 0x00000C00; + const signed int BITS_64 = 0x00000D00; + const signed int BITS_128 = 0x00000E00; + const signed int BITS_256 = 0x00000F00; + const signed int BITS_512 = 0x00001000; + +#include "amdgpu_vega_sys_regs.h" + } + + namespace amdgpu_cdna2{ + //0xff000000 0x00ff0000 0x0000ff00 0x000000ff + //arch reg cat:GPR alias&subrange reg ID + const signed int SGPR = 0x00010000; + const signed int SGPR_VEC2 = 0x00020000; + const signed int SGPR_VEC4 = 0x00030000; + const signed int SGPR_VEC8 = 0x00040000; + const signed int SGPR_VEC16 = 0x00050000; + + const signed int VGPR = 0x00060000; + const signed int VGPR_VEC2 = 0x00070000; + const signed int VGPR_VEC4 = 0x00080000; + const signed int VGPR_VEC8 = 0x00090000; + const signed int VGPR_VEC16 = 0x000A0000; + + const signed int ACC_VGPR = 0x000B0000; + + const signed int HWR = 0x000C0000; + const signed int TTMP_SGPR = 0x000D0000; + const signed int FLAGS = 0x000E0000; + const signed int PC = 0x000F0000; + const signed int SYSREG = 0x00100000; + const signed int TGT = 0x00110000; // I have no idea what TGT is yet + const signed int ATTR = 0x00120000; + const signed int PARAM = 0x00130000; // LDS Parameter + + // aliasing for flags + // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 + // so we use that part to encode the low offset in the base register + // + + + const signed int BITS_1 = 0x00000100; + const signed int BITS_2 = 0x00000200; + const signed int BITS_3 = 0x00000300; + const signed int BITS_4 = 0x00000400; + const signed int BITS_6 = 0x00000500; + const signed int BITS_7 = 0x00000600; + const signed int BITS_8 = 0x00000700; + const signed int BITS_9 = 0x00000800; + const signed int BITS_15 = 0x00000900; + const signed int BITS_16 = 0x00000A00; + const signed int BITS_32 = 0x00000B00; + const signed int BITS_48 = 0x00000C00; + const signed int BITS_64 = 0x00000D00; + const signed int BITS_128 = 0x00000E00; + const signed int BITS_256 = 0x00000F00; + const signed int BITS_512 = 0x00001000; + + + + DEF_REGISTER(tid, Arch_amdgpu_cdna2| SYSREG | BITS_32 | 0 , "amdgpu_cdna2"); + + DEF_REGISTER(invalid, Arch_amdgpu_cdna2| SYSREG | BITS_32 | 1 , "amdgpu_cdna2"); + DEF_REGISTER(pc_all, Arch_amdgpu_cdna2| PC | BITS_48 | 0 , "amdgpu_cdna2"); + + + DEF_REGISTER(src_scc, Arch_amdgpu_cdna2| HWR | BITS_32 | 0 , "amdgpu_cdna2"); + + + DEF_REGISTER(src_vccz, Arch_amdgpu_cdna2| HWR | BITS_1 | 1 , "amdgpu_cdna2"); + DEF_REGISTER(vcc_lo, Arch_amdgpu_cdna2| HWR | BITS_32 | 2 , "amdgpu_cdna2"); + DEF_REGISTER(vcc_hi, Arch_amdgpu_cdna2| HWR | BITS_32 | 3 , "amdgpu_cdna2"); + DEF_REGISTER(vcc, Arch_amdgpu_cdna2| HWR | BITS_64 | 2 , "amdgpu_cdna2"); + + + + DEF_REGISTER(src_execz, Arch_amdgpu_cdna2| HWR | BITS_1 | 4 , "amdgpu_cdna2"); + DEF_REGISTER(exec_lo, Arch_amdgpu_cdna2| HWR | BITS_32 | 5 , "amdgpu_cdna2"); + DEF_REGISTER(exec_hi, Arch_amdgpu_cdna2| HWR | BITS_32 | 6 , "amdgpu_cdna2"); + DEF_REGISTER(exec, Arch_amdgpu_cdna2| HWR | BITS_64 | 5 , "amdgpu_cdna2"); + + + DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_cdna2| HWR | BITS_64 | 7 , "amdgpu_cdna2"); + DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_cdna2| HWR | BITS_32 | 8 , "amdgpu_cdna2"); + DEF_REGISTER(flat_scratch_all, Arch_amdgpu_cdna2| HWR | BITS_32 | 7 , "amdgpu_cdna2"); + + DEF_REGISTER(m0, Arch_amdgpu_cdna2| HWR | BITS_32 | 10 , "amdgpu_cdna2"); + + DEF_REGISTER(src_literal, Arch_amdgpu_cdna2| HWR | BITS_32 | 11 , "amdgpu_cdna2");// TODO + DEF_REGISTER(src_pops_exiting_wave_id, Arch_amdgpu_cdna2| HWR | BITS_32 | 12 , "amdgpu_cdna2");// TODO + + DEF_REGISTER(src_private_base, Arch_amdgpu_cdna2| HWR | BITS_32 | 13 , "amdgpu_cdna2"); + DEF_REGISTER(src_private_limit, Arch_amdgpu_cdna2| HWR | BITS_32 | 14 , "amdgpu_cdna2"); + DEF_REGISTER(src_shared_base, Arch_amdgpu_cdna2| HWR | BITS_32 | 15 , "amdgpu_cdna2"); + DEF_REGISTER(src_shared_limit, Arch_amdgpu_cdna2| HWR | BITS_32 | 16, "amdgpu_cdna2"); + + DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_cdna2| HWR | BITS_32 | 17, "amdgpu_cdna2"); + DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_cdna2| HWR | BITS_32 | 18, "amdgpu_cdna2"); + + + DEF_REGISTER(ttmp0, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 0 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp1, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 1 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp2, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 2 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp3, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 3 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp4, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 4 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp5, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 5 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp6, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 6 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp7, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 7 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp8, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 8 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp9, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 9 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp10, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 10 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp11, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 11 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp12, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 12 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp13, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 13 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp14, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 14 , "amdgpu_cdna2"); + DEF_REGISTER(ttmp15, Arch_amdgpu_cdna2| TTMP_SGPR | BITS_32 | 15 , "amdgpu_cdna2"); + + + + DEF_REGISTER(mrt0, Arch_amdgpu_cdna2| TGT | BITS_32 | 0 , "amdgpu_cdna2"); + DEF_REGISTER(mrt1, Arch_amdgpu_cdna2| TGT | BITS_32 | 1 , "amdgpu_cdna2"); + DEF_REGISTER(mrt2, Arch_amdgpu_cdna2| TGT | BITS_32 | 2 , "amdgpu_cdna2"); + DEF_REGISTER(mrt3, Arch_amdgpu_cdna2| TGT | BITS_32 | 3 , "amdgpu_cdna2"); + DEF_REGISTER(mrt4, Arch_amdgpu_cdna2| TGT | BITS_32 | 4 , "amdgpu_cdna2"); + DEF_REGISTER(mrt5, Arch_amdgpu_cdna2| TGT | BITS_32 | 5 , "amdgpu_cdna2"); + DEF_REGISTER(mrt6, Arch_amdgpu_cdna2| TGT | BITS_32 | 6 , "amdgpu_cdna2"); + DEF_REGISTER(mrt7, Arch_amdgpu_cdna2| TGT | BITS_32 | 7 , "amdgpu_cdna2"); + DEF_REGISTER(mrtz, Arch_amdgpu_cdna2| TGT | BITS_32 | 8 , "amdgpu_cdna2"); + DEF_REGISTER(null, Arch_amdgpu_cdna2| TGT | BITS_32 | 9 , "amdgpu_cdna2"); + DEF_REGISTER(pos0, Arch_amdgpu_cdna2| TGT | BITS_32 | 12 , "amdgpu_cdna2"); + DEF_REGISTER(pos1, Arch_amdgpu_cdna2| TGT | BITS_32 | 13 , "amdgpu_cdna2"); + DEF_REGISTER(pos2, Arch_amdgpu_cdna2| TGT | BITS_32 | 14 , "amdgpu_cdna2"); + DEF_REGISTER(pos3, Arch_amdgpu_cdna2| TGT | BITS_32 | 15 , "amdgpu_cdna2"); + DEF_REGISTER(param0, Arch_amdgpu_cdna2| TGT | BITS_32 | 32 , "amdgpu_cdna2"); + DEF_REGISTER(param1, Arch_amdgpu_cdna2| TGT | BITS_32 | 33 , "amdgpu_cdna2"); + DEF_REGISTER(param2, Arch_amdgpu_cdna2| TGT | BITS_32 | 34 , "amdgpu_cdna2"); + DEF_REGISTER(param3, Arch_amdgpu_cdna2| TGT | BITS_32 | 35 , "amdgpu_cdna2"); + DEF_REGISTER(param4, Arch_amdgpu_cdna2| TGT | BITS_32 | 36 , "amdgpu_cdna2"); + DEF_REGISTER(param5, Arch_amdgpu_cdna2| TGT | BITS_32 | 37 , "amdgpu_cdna2"); + DEF_REGISTER(param6, Arch_amdgpu_cdna2| TGT | BITS_32 | 38 , "amdgpu_cdna2"); + DEF_REGISTER(param7, Arch_amdgpu_cdna2| TGT | BITS_32 | 39 , "amdgpu_cdna2"); + DEF_REGISTER(param8, Arch_amdgpu_cdna2| TGT | BITS_32 | 40 , "amdgpu_cdna2"); + DEF_REGISTER(param9, Arch_amdgpu_cdna2| TGT | BITS_32 | 41 , "amdgpu_cdna2"); + DEF_REGISTER(param10, Arch_amdgpu_cdna2| TGT | BITS_32 | 42 , "amdgpu_cdna2"); + DEF_REGISTER(param11, Arch_amdgpu_cdna2| TGT | BITS_32 | 43 , "amdgpu_cdna2"); + DEF_REGISTER(param12, Arch_amdgpu_cdna2| TGT | BITS_32 | 44 , "amdgpu_cdna2"); + DEF_REGISTER(param13, Arch_amdgpu_cdna2| TGT | BITS_32 | 45 , "amdgpu_cdna2"); + DEF_REGISTER(param14, Arch_amdgpu_cdna2| TGT | BITS_32 | 46 , "amdgpu_cdna2"); + DEF_REGISTER(param15, Arch_amdgpu_cdna2| TGT | BITS_32 | 47 , "amdgpu_cdna2"); + DEF_REGISTER(param16, Arch_amdgpu_cdna2| TGT | BITS_32 | 48 , "amdgpu_cdna2"); + DEF_REGISTER(param17, Arch_amdgpu_cdna2| TGT | BITS_32 | 49 , "amdgpu_cdna2"); + DEF_REGISTER(param18, Arch_amdgpu_cdna2| TGT | BITS_32 | 50 , "amdgpu_cdna2"); + DEF_REGISTER(param19, Arch_amdgpu_cdna2| TGT | BITS_32 | 51 , "amdgpu_cdna2"); + DEF_REGISTER(param20, Arch_amdgpu_cdna2| TGT | BITS_32 | 52 , "amdgpu_cdna2"); + DEF_REGISTER(param21, Arch_amdgpu_cdna2| TGT | BITS_32 | 53 , "amdgpu_cdna2"); + DEF_REGISTER(param22, Arch_amdgpu_cdna2| TGT | BITS_32 | 54 , "amdgpu_cdna2"); + DEF_REGISTER(param23, Arch_amdgpu_cdna2| TGT | BITS_32 | 55 , "amdgpu_cdna2"); + DEF_REGISTER(param24, Arch_amdgpu_cdna2| TGT | BITS_32 | 56 , "amdgpu_cdna2"); + DEF_REGISTER(param25, Arch_amdgpu_cdna2| TGT | BITS_32 | 57 , "amdgpu_cdna2"); + DEF_REGISTER(param26, Arch_amdgpu_cdna2| TGT | BITS_32 | 58 , "amdgpu_cdna2"); + DEF_REGISTER(param27, Arch_amdgpu_cdna2| TGT | BITS_32 | 59 , "amdgpu_cdna2"); + DEF_REGISTER(param28, Arch_amdgpu_cdna2| TGT | BITS_32 | 60 , "amdgpu_cdna2"); + DEF_REGISTER(param29, Arch_amdgpu_cdna2| TGT | BITS_32 | 61 , "amdgpu_cdna2"); + DEF_REGISTER(param30, Arch_amdgpu_cdna2| TGT | BITS_32 | 62 , "amdgpu_cdna2"); + DEF_REGISTER(param31, Arch_amdgpu_cdna2| TGT | BITS_32 | 63 , "amdgpu_cdna2"); + + DEF_REGISTER(attr0, Arch_amdgpu_cdna2| ATTR | BITS_32 | 0 , "amdgpu_cdna2"); + DEF_REGISTER(attr1, Arch_amdgpu_cdna2| ATTR | BITS_32 | 1 , "amdgpu_cdna2"); + DEF_REGISTER(attr2, Arch_amdgpu_cdna2| ATTR | BITS_32 | 2 , "amdgpu_cdna2"); + DEF_REGISTER(attr3, Arch_amdgpu_cdna2| ATTR | BITS_32 | 3 , "amdgpu_cdna2"); + DEF_REGISTER(attr4, Arch_amdgpu_cdna2| ATTR | BITS_32 | 4 , "amdgpu_cdna2"); + DEF_REGISTER(attr5, Arch_amdgpu_cdna2| ATTR | BITS_32 | 5 , "amdgpu_cdna2"); + DEF_REGISTER(attr6, Arch_amdgpu_cdna2| ATTR | BITS_32 | 6 , "amdgpu_cdna2"); + DEF_REGISTER(attr7, Arch_amdgpu_cdna2| ATTR | BITS_32 | 7 , "amdgpu_cdna2"); + DEF_REGISTER(attr8, Arch_amdgpu_cdna2| ATTR | BITS_32 | 8 , "amdgpu_cdna2"); + DEF_REGISTER(attr9, Arch_amdgpu_cdna2| ATTR | BITS_32 | 9 , "amdgpu_cdna2"); + DEF_REGISTER(attr10, Arch_amdgpu_cdna2| ATTR | BITS_32 | 10 , "amdgpu_cdna2"); + DEF_REGISTER(attr11, Arch_amdgpu_cdna2| ATTR | BITS_32 | 11 , "amdgpu_cdna2"); + DEF_REGISTER(attr12, Arch_amdgpu_cdna2| ATTR | BITS_32 | 12 , "amdgpu_cdna2"); + DEF_REGISTER(attr13, Arch_amdgpu_cdna2| ATTR | BITS_32 | 13 , "amdgpu_cdna2"); + DEF_REGISTER(attr14, Arch_amdgpu_cdna2| ATTR | BITS_32 | 14 , "amdgpu_cdna2"); + DEF_REGISTER(attr15, Arch_amdgpu_cdna2| ATTR | BITS_32 | 15 , "amdgpu_cdna2"); + DEF_REGISTER(attr16, Arch_amdgpu_cdna2| ATTR | BITS_32 | 16 , "amdgpu_cdna2"); + DEF_REGISTER(attr17, Arch_amdgpu_cdna2| ATTR | BITS_32 | 17 , "amdgpu_cdna2"); + DEF_REGISTER(attr18, Arch_amdgpu_cdna2| ATTR | BITS_32 | 18 , "amdgpu_cdna2"); + DEF_REGISTER(attr19, Arch_amdgpu_cdna2| ATTR | BITS_32 | 19 , "amdgpu_cdna2"); + DEF_REGISTER(attr20, Arch_amdgpu_cdna2| ATTR | BITS_32 | 20 , "amdgpu_cdna2"); + DEF_REGISTER(attr21, Arch_amdgpu_cdna2| ATTR | BITS_32 | 21 , "amdgpu_cdna2"); + DEF_REGISTER(attr22, Arch_amdgpu_cdna2| ATTR | BITS_32 | 22 , "amdgpu_cdna2"); + DEF_REGISTER(attr23, Arch_amdgpu_cdna2| ATTR | BITS_32 | 23 , "amdgpu_cdna2"); + DEF_REGISTER(attr24, Arch_amdgpu_cdna2| ATTR | BITS_32 | 24 , "amdgpu_cdna2"); + DEF_REGISTER(attr25, Arch_amdgpu_cdna2| ATTR | BITS_32 | 25 , "amdgpu_cdna2"); + DEF_REGISTER(attr26, Arch_amdgpu_cdna2| ATTR | BITS_32 | 26 , "amdgpu_cdna2"); + DEF_REGISTER(attr27, Arch_amdgpu_cdna2| ATTR | BITS_32 | 27 , "amdgpu_cdna2"); + DEF_REGISTER(attr28, Arch_amdgpu_cdna2| ATTR | BITS_32 | 28 , "amdgpu_cdna2"); + DEF_REGISTER(attr29, Arch_amdgpu_cdna2| ATTR | BITS_32 | 29 , "amdgpu_cdna2"); + DEF_REGISTER(attr30, Arch_amdgpu_cdna2| ATTR | BITS_32 | 30 , "amdgpu_cdna2"); + DEF_REGISTER(attr31, Arch_amdgpu_cdna2| ATTR | BITS_32 | 31 , "amdgpu_cdna2"); + DEF_REGISTER(attr32, Arch_amdgpu_cdna2| ATTR | BITS_32 | 32 , "amdgpu_cdna2"); + + + + DEF_REGISTER(p10, Arch_amdgpu_cdna2| PARAM | BITS_32 | 32 , "amdgpu_cdna2"); + DEF_REGISTER(p20, Arch_amdgpu_cdna2| PARAM | BITS_32 | 32 , "amdgpu_cdna2"); + DEF_REGISTER(p0, Arch_amdgpu_cdna2| PARAM | BITS_32 | 32 , "amdgpu_cdna2"); + +#include "AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h" } - namespace cuda { - const signed int GPR = 0x00000000; - const signed int PR = 0x00010000; - const signed int BR = 0x00020000; - const signed int UR = 0x00040000; - const signed int UPR = 0x00080000; - - // General purpose registers - DEF_REGISTER(r0, 0 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r1, 1 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r2, 2 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r3, 3 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r4, 4 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r5, 5 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r6, 6 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r7, 7 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r8, 8 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r9, 9 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r10, 10 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r11, 11 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r12, 12 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r13, 13 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r14, 14 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r15, 15 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r16, 16 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r17, 17 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r18, 18 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r19, 19 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r20, 20 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r21, 21 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r22, 22 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r23, 23 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r24, 24 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r25, 25 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r26, 26 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r27, 27 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r28, 28 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r29, 29 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r30, 30 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r31, 31 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r32, 32 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r33, 33 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r34, 34 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r35, 35 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r36, 36 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r37, 37 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r38, 38 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r39, 39 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r40, 40 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r41, 41 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r42, 42 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r43, 43 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r44, 44 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r45, 45 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r46, 46 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r47, 47 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r48, 48 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r49, 49 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r50, 50 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r51, 51 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r52, 52 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r53, 53 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r54, 54 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r55, 55 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r56, 56 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r57, 57 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r58, 58 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r59, 59 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r60, 60 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r61, 61 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r62, 62 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r63, 63 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r64, 64 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r65, 65 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r66, 66 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r67, 67 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r68, 68 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r69, 69 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r70, 70 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r71, 71 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r72, 72 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r73, 73 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r74, 74 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r75, 75 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r76, 76 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r77, 77 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r78, 78 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r79, 79 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r80, 80 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r81, 81 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r82, 82 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r83, 83 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r84, 84 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r85, 85 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r86, 86 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r87, 87 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r88, 88 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r89, 89 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r90, 90 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r91, 91 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r92, 92 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r93, 93 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r94, 94 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r95, 95 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r96, 96 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r97, 97 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r98, 98 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r99, 99 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r100, 100 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r101, 101 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r102, 102 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r103, 103 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r104, 104 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r105, 105 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r106, 106 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r107, 107 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r108, 108 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r109, 109 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r110, 110 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r111, 111 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r112, 112 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r113, 113 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r114, 114 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r115, 115 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r116, 116 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r117, 117 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r118, 118 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r119, 119 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r120, 120 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r121, 121 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r122, 122 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r123, 123 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r124, 124 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r125, 125 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r126, 126 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r127, 127 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r128, 128 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r129, 129 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r130, 130 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r131, 131 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r132, 132 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r133, 133 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r134, 134 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r135, 135 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r136, 136 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r137, 137 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r138, 138 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r139, 139 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r140, 140 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r141, 141 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r142, 142 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r143, 143 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r144, 144 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r145, 145 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r146, 146 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r147, 147 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r148, 148 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r149, 149 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r150, 150 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r151, 151 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r152, 152 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r153, 153 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r154, 154 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r155, 155 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r156, 156 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r157, 157 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r158, 158 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r159, 159 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r160, 160 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r161, 161 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r162, 162 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r163, 163 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r164, 164 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r165, 165 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r166, 166 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r167, 167 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r168, 168 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r169, 169 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r170, 170 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r171, 171 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r172, 172 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r173, 173 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r174, 174 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r175, 175 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r176, 176 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r177, 177 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r178, 178 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r179, 179 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r180, 180 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r181, 181 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r182, 182 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r183, 183 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r184, 184 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r185, 185 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r186, 186 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r187, 187 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r188, 188 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r189, 189 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r190, 190 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r191, 191 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r192, 192 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r193, 193 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r194, 194 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r195, 195 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r196, 196 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r197, 197 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r198, 198 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r199, 199 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r200, 200 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r201, 201 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r202, 202 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r203, 203 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r204, 204 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r205, 205 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r206, 206 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r207, 207 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r208, 208 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r209, 209 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r210, 210 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r211, 211 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r212, 212 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r213, 213 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r214, 214 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r215, 215 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r216, 216 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r217, 217 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r218, 218 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r219, 219 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r220, 220 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r221, 221 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r222, 222 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r223, 223 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r224, 224 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r225, 225 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r226, 226 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r227, 227 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r228, 228 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r229, 229 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r230, 230 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r231, 231 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r232, 232 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r233, 233 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r234, 234 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r235, 235 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r236, 236 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r237, 237 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r238, 238 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r239, 239 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r240, 240 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r241, 241 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r242, 242 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r243, 243 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r244, 244 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r245, 245 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r246, 246 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r247, 247 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r248, 248 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r249, 249 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r250, 250 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r251, 251 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r252, 252 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r253, 253 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r254, 254 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r255, 255 | GPR| Arch_cuda, "cuda"); - - // uniform registers - DEF_REGISTER(ur0, 0 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur1, 1 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur2, 2 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur3, 3 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur4, 4 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur5, 5 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur6, 6 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur7, 7 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur8, 8 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur9, 9 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur10, 10 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur11, 11 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur12, 12 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur13, 13 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur14, 14 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur15, 15 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur16, 16 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur17, 17 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur18, 18 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur19, 19 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur20, 20 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur21, 21 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur22, 22 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur23, 23 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur24, 24 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur25, 25 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur26, 26 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur27, 27 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur28, 28 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur29, 29 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur30, 30 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur31, 31 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur32, 32 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur33, 33 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur34, 34 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur35, 35 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur36, 36 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur37, 37 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur38, 38 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur39, 39 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur40, 40 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur41, 41 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur42, 42 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur43, 43 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur44, 44 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur45, 45 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur46, 46 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur47, 47 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur48, 48 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur49, 49 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur50, 50 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur51, 51 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur52, 52 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur53, 53 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur54, 54 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur55, 55 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur56, 56 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur57, 57 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur58, 58 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur59, 59 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur60, 60 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur61, 61 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur62, 62 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur63, 63 | UR | Arch_cuda, "cuda"); - - // Placeholder for a pc register, so that we don't assert - DEF_REGISTER(pc, 256 | GPR| Arch_cuda, "cuda"); - - // Predicate registers used as source or dest operands - // Different from a predicate register used as instruction predicate, - // which is handle by operand::isTruePredicate and operand::isFalsePredicate - DEF_REGISTER(p0, 0 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p1, 1 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p2, 2 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p3, 3 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p4, 4 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p5, 5 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p6, 6 | PR | Arch_cuda, "cuda"); - - DEF_REGISTER(b1, 1 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b2, 2 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b3, 3 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b4, 4 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b5, 5 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b6, 6 | BR | Arch_cuda, "cuda"); - - // XXX(Keren): not sure how many uprs, use 16 for safety - DEF_REGISTER(up0, 0 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up1, 1 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up2, 2 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up3, 3 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up4, 4 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up5, 5 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up6, 6 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up7, 7 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up8, 8 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up9, 9 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up10, 10 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up11, 11 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up12, 12 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up13, 13 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up14, 14 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up15, 15 | UPR | Arch_cuda, "cuda"); - } //end of cuda namespace + + namespace cuda { + const signed int GPR = 0x00000000; + const signed int PR = 0x00010000; + const signed int BR = 0x00020000; + const signed int UR = 0x00040000; + const signed int UPR = 0x00080000; + + // General purpose registers + DEF_REGISTER(r0, 0 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r1, 1 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r2, 2 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r3, 3 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r4, 4 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r5, 5 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r6, 6 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r7, 7 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r8, 8 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r9, 9 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r10, 10 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r11, 11 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r12, 12 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r13, 13 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r14, 14 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r15, 15 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r16, 16 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r17, 17 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r18, 18 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r19, 19 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r20, 20 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r21, 21 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r22, 22 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r23, 23 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r24, 24 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r25, 25 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r26, 26 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r27, 27 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r28, 28 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r29, 29 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r30, 30 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r31, 31 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r32, 32 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r33, 33 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r34, 34 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r35, 35 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r36, 36 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r37, 37 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r38, 38 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r39, 39 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r40, 40 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r41, 41 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r42, 42 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r43, 43 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r44, 44 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r45, 45 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r46, 46 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r47, 47 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r48, 48 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r49, 49 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r50, 50 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r51, 51 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r52, 52 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r53, 53 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r54, 54 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r55, 55 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r56, 56 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r57, 57 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r58, 58 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r59, 59 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r60, 60 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r61, 61 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r62, 62 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r63, 63 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r64, 64 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r65, 65 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r66, 66 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r67, 67 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r68, 68 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r69, 69 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r70, 70 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r71, 71 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r72, 72 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r73, 73 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r74, 74 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r75, 75 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r76, 76 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r77, 77 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r78, 78 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r79, 79 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r80, 80 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r81, 81 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r82, 82 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r83, 83 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r84, 84 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r85, 85 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r86, 86 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r87, 87 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r88, 88 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r89, 89 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r90, 90 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r91, 91 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r92, 92 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r93, 93 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r94, 94 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r95, 95 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r96, 96 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r97, 97 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r98, 98 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r99, 99 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER(r100, 100 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r101, 101 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r102, 102 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r103, 103 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r104, 104 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r105, 105 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r106, 106 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r107, 107 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r108, 108 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r109, 109 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r110, 110 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r111, 111 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r112, 112 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r113, 113 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r114, 114 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r115, 115 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r116, 116 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r117, 117 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r118, 118 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r119, 119 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r120, 120 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r121, 121 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r122, 122 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r123, 123 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r124, 124 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r125, 125 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r126, 126 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r127, 127 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r128, 128 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r129, 129 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r130, 130 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r131, 131 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r132, 132 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r133, 133 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r134, 134 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r135, 135 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r136, 136 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r137, 137 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r138, 138 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r139, 139 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r140, 140 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r141, 141 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r142, 142 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r143, 143 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r144, 144 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r145, 145 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r146, 146 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r147, 147 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r148, 148 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r149, 149 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r150, 150 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r151, 151 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r152, 152 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r153, 153 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r154, 154 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r155, 155 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r156, 156 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r157, 157 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r158, 158 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r159, 159 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r160, 160 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r161, 161 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r162, 162 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r163, 163 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r164, 164 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r165, 165 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r166, 166 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r167, 167 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r168, 168 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r169, 169 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r170, 170 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r171, 171 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r172, 172 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r173, 173 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r174, 174 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r175, 175 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r176, 176 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r177, 177 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r178, 178 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r179, 179 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r180, 180 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r181, 181 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r182, 182 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r183, 183 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r184, 184 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r185, 185 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r186, 186 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r187, 187 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r188, 188 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r189, 189 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r190, 190 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r191, 191 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r192, 192 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r193, 193 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r194, 194 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r195, 195 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r196, 196 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r197, 197 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r198, 198 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r199, 199 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r200, 200 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r201, 201 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r202, 202 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r203, 203 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r204, 204 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r205, 205 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r206, 206 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r207, 207 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r208, 208 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r209, 209 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r210, 210 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r211, 211 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r212, 212 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r213, 213 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r214, 214 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r215, 215 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r216, 216 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r217, 217 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r218, 218 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r219, 219 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r220, 220 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r221, 221 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r222, 222 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r223, 223 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r224, 224 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r225, 225 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r226, 226 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r227, 227 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r228, 228 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r229, 229 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r230, 230 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r231, 231 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r232, 232 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r233, 233 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r234, 234 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r235, 235 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r236, 236 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r237, 237 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r238, 238 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r239, 239 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r240, 240 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r241, 241 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r242, 242 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r243, 243 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r244, 244 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r245, 245 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r246, 246 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r247, 247 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r248, 248 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r249, 249 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r250, 250 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r251, 251 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r252, 252 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r253, 253 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r254, 254 | GPR| Arch_cuda, "cuda"); + DEF_REGISTER(r255, 255 | GPR| Arch_cuda, "cuda"); + + // uniform registers + DEF_REGISTER(ur0, 0 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur1, 1 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur2, 2 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur3, 3 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur4, 4 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur5, 5 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur6, 6 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur7, 7 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur8, 8 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur9, 9 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur10, 10 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur11, 11 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur12, 12 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur13, 13 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur14, 14 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur15, 15 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur16, 16 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur17, 17 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur18, 18 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur19, 19 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur20, 20 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur21, 21 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur22, 22 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur23, 23 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur24, 24 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur25, 25 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur26, 26 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur27, 27 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur28, 28 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur29, 29 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur30, 30 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur31, 31 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur32, 32 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur33, 33 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur34, 34 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur35, 35 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur36, 36 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur37, 37 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur38, 38 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur39, 39 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur40, 40 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur41, 41 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur42, 42 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur43, 43 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur44, 44 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur45, 45 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur46, 46 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur47, 47 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur48, 48 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur49, 49 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur50, 50 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur51, 51 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur52, 52 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur53, 53 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur54, 54 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur55, 55 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur56, 56 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur57, 57 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur58, 58 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur59, 59 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur60, 60 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur61, 61 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur62, 62 | UR | Arch_cuda, "cuda"); + DEF_REGISTER(ur63, 63 | UR | Arch_cuda, "cuda"); + + // Placeholder for a pc register, so that we don't assert + DEF_REGISTER(pc, 256 | GPR| Arch_cuda, "cuda"); + + // Predicate registers used as source or dest operands + // Different from a predicate register used as instruction predicate, + // which is handle by operand::isTruePredicate and operand::isFalsePredicate + DEF_REGISTER(p0, 0 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p1, 1 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p2, 2 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p3, 3 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p4, 4 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p5, 5 | PR | Arch_cuda, "cuda"); + DEF_REGISTER(p6, 6 | PR | Arch_cuda, "cuda"); + + DEF_REGISTER(b1, 1 | BR | Arch_cuda, "cuda"); + DEF_REGISTER(b2, 2 | BR | Arch_cuda, "cuda"); + DEF_REGISTER(b3, 3 | BR | Arch_cuda, "cuda"); + DEF_REGISTER(b4, 4 | BR | Arch_cuda, "cuda"); + DEF_REGISTER(b5, 5 | BR | Arch_cuda, "cuda"); + DEF_REGISTER(b6, 6 | BR | Arch_cuda, "cuda"); + + // XXX(Keren): not sure how many uprs, use 16 for safety + DEF_REGISTER(up0, 0 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up1, 1 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up2, 2 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up3, 3 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up4, 4 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up5, 5 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up6, 6 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up7, 7 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up8, 8 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up9, 9 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up10, 10 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up11, 11 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up12, 12 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up13, 13 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up14, 14 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER(up15, 15 | UPR | Arch_cuda, "cuda"); + } //end of cuda namespace } #endif diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index 60a7843197..f812f84045 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -3008,6 +3008,8 @@ power_op_dxex, aarch64_op_zip2_advsimd, amdgpu_op_sop1_nop, #include "amdgpu_op_table.h" +#include "amdgpu_cdna_op_table.h" +#include "amdgpu_cdna2_op_table.h" cuda_op_general, cuda_op_call, intel_gpu_op_general, diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index ab433db538..9ecddaa534 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -109,6 +109,27 @@ MachRegister MachRegister::getBaseRegister() const { default: return *this; } + case Arch_amdgpu_cdna2: + switch (category){ + case amdgpu_cdna2::SGPR: + case amdgpu_cdna2::SGPR_VEC2: + case amdgpu_cdna2::SGPR_VEC4: + case amdgpu_cdna2::SGPR_VEC8: + case amdgpu_cdna2::SGPR_VEC16: + return MachRegister( (reg & 0x000000ff) | amdgpu_cdna2::s0); + case amdgpu_cdna2::VGPR: + case amdgpu_cdna2::VGPR_VEC2: + case amdgpu_cdna2::VGPR_VEC4: + case amdgpu_cdna2::VGPR_VEC8: + case amdgpu_cdna2::VGPR_VEC16: + return MachRegister( (reg & 0x000000ff) | amdgpu_cdna2::v0); + case amdgpu_cdna2::HWR: + return MachRegister(reg); + + default: + return *this; + } + case Arch_aarch32: case Arch_aarch64: case Arch_intelGen9: @@ -116,11 +137,12 @@ MachRegister MachRegister::getBaseRegister() const { //not verified return *this; default: - return InvalidReg; + return InvalidReg; } return InvalidReg; } + Architecture MachRegister::getArchitecture() const { return (Architecture) (reg & 0xff000000); } @@ -160,41 +182,51 @@ std::string MachRegister::name() const { switch(category){ case amdgpu_vega::SGPR_VEC2: base_val -= (amdgpu_vega::sgpr_vec2_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+1)+"]"); + ret = "SGPR["+std::to_string(base_val)+":"+std::to_string(base_val+1)+"]"; break; case amdgpu_vega::VGPR_VEC2: base_val -= (amdgpu_vega::vgpr_vec2_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+1)+"]"); + ret = "VGPR["+std::to_string(base_val)+":"+std::to_string(base_val+1)+"]"; break; case amdgpu_vega::SGPR_VEC4: base_val -= (amdgpu_vega::sgpr_vec4_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+3)+"]"); + ret = "SGPR["+std::to_string(base_val)+":"+std::to_string(base_val+3)+"]"; break; case amdgpu_vega::VGPR_VEC4: base_val -= (amdgpu_vega::vgpr_vec4_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+3)+"]"); + ret = "VGPR["+std::to_string(base_val)+":"+std::to_string(base_val+3)+"]"; break; case amdgpu_vega::SGPR_VEC8: base_val -= (amdgpu_vega::sgpr_vec8_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+7)+"]"); + ret = "SGPR["+std::to_string(base_val)+":"+std::to_string(base_val+7)+"]"; break; case amdgpu_vega::VGPR_VEC8: base_val -= (amdgpu_vega::vgpr_vec8_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+7)+"]"); + ret = "VGPR["+std::to_string(base_val)+":"+std::to_string(base_val+7)+"]"; break; case amdgpu_vega::SGPR_VEC16: base_val -= (amdgpu_vega::sgpr_vec16_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+15)+"]"); + ret = "SGPR["+std::to_string(base_val)+":"+std::to_string(base_val+15)+"]"; break; case amdgpu_vega::VGPR_VEC16: base_val -= (amdgpu_vega::vgpr_vec16_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+15)+"]"); + ret = "VGPR["+std::to_string(base_val)+":"+std::to_string(base_val+15)+"]"; + break; + default: + ret = iter->second; break; + } + return ret; + }else if(getArchitecture() == Arch_amdgpu_cdna2){ + signed int category = reg & 0x00ff0000; + signed int base_val = reg & 0x000000ff; + switch(category){ default: ret = iter->second; break; } return ret; + }else{ return iter->second; } @@ -271,91 +303,134 @@ unsigned int MachRegister::size() const { return 8; } case Arch_aarch32: - assert(0); - break; - + assert(0); + break; + case Arch_cuda: - return 8; + return 8; case Arch_amdgpu_vega:{ - int reg_class = (reg&0x00ff0000 ) ; - if ( reg_class == amdgpu_vega::SGPR || reg_class == amdgpu_vega::VGPR){ - return 4; - }else if (reg_class == amdgpu_vega::SGPR_VEC2 || reg_class == amdgpu_vega::VGPR_VEC2){ - return 8; - }else if (reg_class == amdgpu_vega::SGPR_VEC4 || reg_class == amdgpu_vega::VGPR_VEC4){ - return 16; - }else if (reg_class == amdgpu_vega::SGPR_VEC8 || reg_class == amdgpu_vega::VGPR_VEC8){ - return 32; - }else if (reg_class == amdgpu_vega::SGPR_VEC16 || reg_class == amdgpu_vega::VGPR_VEC16){ - return 64; - }else{ - switch(reg & 0x00007f00){ - case amdgpu_vega::BITS_1: - case amdgpu_vega::BITS_2: - case amdgpu_vega::BITS_3: - case amdgpu_vega::BITS_4: - case amdgpu_vega::BITS_6: - case amdgpu_vega::BITS_7: - case amdgpu_vega::BITS_8: - return 1; - case amdgpu_vega::BITS_9: - case amdgpu_vega::BITS_15: - case amdgpu_vega::BITS_16: - return 2; - case amdgpu_vega::BITS_32: - return 4; - case amdgpu_vega::BITS_48: - case amdgpu_vega::BITS_64: - return 8; - case amdgpu_vega::BITS_128: - return 16; - case amdgpu_vega::BITS_256: - return 32; - case amdgpu_vega::BITS_512: - return 64; - } - common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); - assert(0); - } - } + int reg_class = (reg&0x00ff0000 ) ; + if ( reg_class == amdgpu_vega::SGPR || reg_class == amdgpu_vega::VGPR){ + return 4; + }else if (reg_class == amdgpu_vega::SGPR_VEC2 || reg_class == amdgpu_vega::VGPR_VEC2){ + return 8; + }else if (reg_class == amdgpu_vega::SGPR_VEC4 || reg_class == amdgpu_vega::VGPR_VEC4){ + return 16; + }else if (reg_class == amdgpu_vega::SGPR_VEC8 || reg_class == amdgpu_vega::VGPR_VEC8){ + return 32; + }else if (reg_class == amdgpu_vega::SGPR_VEC16 || reg_class == amdgpu_vega::VGPR_VEC16){ + return 64; + }else{ + switch(reg & 0x00007f00){ + case amdgpu_vega::BITS_1: + case amdgpu_vega::BITS_2: + case amdgpu_vega::BITS_3: + case amdgpu_vega::BITS_4: + case amdgpu_vega::BITS_6: + case amdgpu_vega::BITS_7: + case amdgpu_vega::BITS_8: + return 1; + case amdgpu_vega::BITS_9: + case amdgpu_vega::BITS_15: + case amdgpu_vega::BITS_16: + return 2; + case amdgpu_vega::BITS_32: + return 4; + case amdgpu_vega::BITS_48: + case amdgpu_vega::BITS_64: + return 8; + case amdgpu_vega::BITS_128: + return 16; + case amdgpu_vega::BITS_256: + return 32; + case amdgpu_vega::BITS_512: + return 64; + } + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + case Arch_amdgpu_cdna2:{ + int reg_class = (reg&0x00ff0000 ) ; + if ( reg_class == amdgpu_cdna2::SGPR || reg_class == amdgpu_cdna2::VGPR){ + return 4; + }else if (reg_class == amdgpu_cdna2::SGPR_VEC2 || reg_class == amdgpu_cdna2::VGPR_VEC2){ + return 8; + }else if (reg_class == amdgpu_cdna2::SGPR_VEC4 || reg_class == amdgpu_cdna2::VGPR_VEC4){ + return 16; + }else if (reg_class == amdgpu_cdna2::SGPR_VEC8 || reg_class == amdgpu_cdna2::VGPR_VEC8){ + return 32; + }else if (reg_class == amdgpu_cdna2::SGPR_VEC16 || reg_class == amdgpu_cdna2::VGPR_VEC16){ + return 64; + }else{ + switch(reg & 0x00007f00){ + case amdgpu_cdna2::BITS_1: + case amdgpu_cdna2::BITS_2: + case amdgpu_cdna2::BITS_3: + case amdgpu_cdna2::BITS_4: + case amdgpu_cdna2::BITS_6: + case amdgpu_cdna2::BITS_7: + case amdgpu_cdna2::BITS_8: + return 1; + case amdgpu_cdna2::BITS_9: + case amdgpu_cdna2::BITS_15: + case amdgpu_cdna2::BITS_16: + return 2; + case amdgpu_cdna2::BITS_32: + return 4; + case amdgpu_cdna2::BITS_48: + return 6; + case amdgpu_cdna2::BITS_64: + return 8; + case amdgpu_cdna2::BITS_128: + return 16; + case amdgpu_cdna2::BITS_256: + return 32; + case amdgpu_cdna2::BITS_512: + return 64; + } + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + case Arch_aarch64:{ - if((reg & 0x00ff0000) == aarch64::FPR) - { - switch(reg & 0x0000ff00) - { - case aarch64::B_REG: return 1; - case aarch64::W_REG: return 2; - case aarch64::D_REG: return 4; - case aarch64::FULL: - case aarch64::HQ_REG: return 8; - case aarch64::Q_REG: return 16; - default: - assert(0); - return 0; - } - } - else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR || - (reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG) - switch(reg & 0x0000ff00) - { - case aarch64::FULL : return 8; - case aarch64::D_REG: return 4; - case aarch64::BIT: return 0; - default: return 0; - } - else - return 4; - break; - } - case Arch_amdgpu_rdna: + if((reg & 0x00ff0000) == aarch64::FPR) + { + switch(reg & 0x0000ff00) + { + case aarch64::B_REG: return 1; + case aarch64::W_REG: return 2; + case aarch64::D_REG: return 4; + case aarch64::FULL: + case aarch64::HQ_REG: return 8; + case aarch64::Q_REG: return 16; + default: + assert(0); + return 0; + } + } + else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR || + (reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG) + switch(reg & 0x0000ff00) + { + case aarch64::FULL : return 8; + case aarch64::D_REG: return 4; + case aarch64::BIT: return 0; + default: return 0; + } + else + return 4; + break; + } case Arch_intelGen9: - { - assert(0); - break; - } - + { + assert(0); + break; + } + case Arch_none: - return 0; + return 0; } return 0; //Unreachable, but disable warnings } @@ -399,7 +474,8 @@ MachRegister MachRegister::getPC(Dyninst::Architecture arch) return InvalidReg; case Arch_amdgpu_vega: return amdgpu_vega::pc; - case Arch_amdgpu_rdna: + case Arch_amdgpu_cdna2: + return amdgpu_cdna2::pc_all; case Arch_none: return InvalidReg; } @@ -424,7 +500,7 @@ MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch) case Arch_aarch32: case Arch_cuda: case Arch_amdgpu_vega: // TODO:Since amdgpu functions are all inlined, the return address is highly likely in sgpr[30:31] - case Arch_amdgpu_rdna: + case Arch_amdgpu_cdna2: case Arch_intelGen9: assert(0); case Arch_none: @@ -449,6 +525,7 @@ MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch) return aarch64::x29; //aarch64: frame pointer is X29 by convention case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: case Arch_none: return InvalidReg; @@ -478,6 +555,8 @@ MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch) assert(0); case Arch_none: case Arch_amdgpu_vega: + + case Arch_amdgpu_cdna2: return InvalidReg; default: assert(0); @@ -503,6 +582,7 @@ MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch) case Arch_aarch32: case Arch_cuda: case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: assert(0); case Arch_none: return InvalidReg; @@ -598,6 +678,7 @@ MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch) return ppc64::cr0e; case Arch_cuda: case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: assert(0); case Arch_none: return InvalidReg; @@ -613,7 +694,7 @@ bool MachRegister::isPC() const { return (*this == x86_64::rip || *this == x86::eip || *this == ppc32::pc || *this == ppc64::pc || - *this == aarch64::pc ); + *this == aarch64::pc || *this == amdgpu_cdna2::pc_all ); } bool MachRegister::isFramePointer() const @@ -667,14 +748,16 @@ bool MachRegister::isFlag() const int baseID = reg & 0x0000FFFF; return (baseID <= 731 && baseID >= 700) || (baseID <= 629 && baseID >= 621); } - case Arch_amdgpu_vega:{ - return (reg & 0x0000F000); - } + case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: + { + return (reg & 0x0000F000); + } case Arch_cuda: - return false; + return false; default: - assert(!"Not implemented!"); + assert(!"Not implemented!"); } return false; } @@ -721,26 +804,26 @@ void MachRegister::getAMDGPUROSERegister(int ®_class, int ®_idx, int &offs reg_idx = baseID; switch(category){ case amdgpu_vega::SGPR:{ - reg_class = amdgpu_regclass_sgpr; - break; - } + reg_class = amdgpu_regclass_sgpr; + break; + } case amdgpu_vega::VGPR: { - reg_class = amdgpu_regclass_vgpr; - break; - } + reg_class = amdgpu_regclass_vgpr; + break; + } case amdgpu_vega::PC: { - reg_class = amdgpu_regclass_pc; - reg_idx = amdgpu_pc; - break; - } + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } case amdgpu_vega::SGPR_VEC2:{ - reg_class = amdgpu_regclass_sgpr_vec2; - break; - } + reg_class = amdgpu_regclass_sgpr_vec2; + break; + } default:{ - assert(0 && "un suppoprted register type for amdgpu "); - } - + assert(0 && "un suppoprted register type for amdgpu "); + } + } return; } @@ -762,7 +845,8 @@ void MachRegister::getROSERegister(int &c, int &n, int &p) { // Rose: class, number, position // Dyninst: category, base id, subrange - if (getArchitecture()==Arch_amdgpu_vega){ + Architecture maybe_amdgpu = getArchitecture(); + if (maybe_amdgpu==Arch_amdgpu_vega || maybe_amdgpu == Arch_amdgpu_cdna2){ getAMDGPUROSERegister(c,n,p); return; } @@ -1069,75 +1153,75 @@ void MachRegister::getROSERegister(int &c, int &n, int &p) } break; case Arch_ppc32: - { - baseID = reg & 0x0000FFFF; - n = baseID; - switch(category) { - case ppc32::GPR: - c = powerpc_regclass_gpr; - break; - case ppc32::FPR: - case ppc32::FSR: - c = powerpc_regclass_fpr; - break; - case ppc32::SPR: - { - if(baseID < 613) { - c = powerpc_regclass_spr; - } else if(baseID < 621 ) { - c = powerpc_regclass_sr; - } else { - c = powerpc_regclass_cr; - n = 0; - p = baseID - 621; - /* n = baseID - 621; - if(n > 7) { - n = 0; - p = powerpc_condreggranularity_whole; - } else { - p = powerpc_condreggranularity_field; - } - */ + baseID = reg & 0x0000FFFF; + n = baseID; + switch(category) + { + case ppc32::GPR: + c = powerpc_regclass_gpr; + break; + case ppc32::FPR: + case ppc32::FSR: + c = powerpc_regclass_fpr; + break; + case ppc32::SPR: + { + if(baseID < 613) { + c = powerpc_regclass_spr; + } else if(baseID < 621 ) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + /* n = baseID - 621; + if(n > 7) { + n = 0; + p = powerpc_condreggranularity_whole; + } else { + p = powerpc_condreggranularity_field; + } + */ + } } - } - break; - default: - c = -1; - return; + break; + default: + c = -1; + return; + } + return; } - return; - } - break; + break; case Arch_ppc64: { - baseID = reg & 0x0000FFFF; - n = baseID; - switch (category) { - case ppc64::GPR: - c = powerpc_regclass_gpr; - break; - case ppc64::FPR: - case ppc64::FSR: - c = powerpc_regclass_fpr; - break; - case ppc64::SPR: { - if (baseID < 613) { - c = powerpc_regclass_spr; - } else if (baseID < 621) { - c = powerpc_regclass_sr; - } else { - c = powerpc_regclass_cr; - n = 0; - p = baseID - 621; - } - } break; - default: - c = -1; - return; - } - return; - } - break; + baseID = reg & 0x0000FFFF; + n = baseID; + switch (category) { + case ppc64::GPR: + c = powerpc_regclass_gpr; + break; + case ppc64::FPR: + case ppc64::FSR: + c = powerpc_regclass_fpr; + break; + case ppc64::SPR: { + if (baseID < 613) { + c = powerpc_regclass_spr; + } else if (baseID < 621) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + } + } break; + default: + c = -1; + return; + } + return; + } + break; case Arch_aarch64: { p = 0; switch (category) { @@ -1220,10 +1304,10 @@ void MachRegister::getROSERegister(int &c, int &n, int &p) return; } break; - default: - c = x86_regclass_unknown; - n = 0; - break; + default: + c = x86_regclass_unknown; + n = 0; + break; } switch (getArchitecture()) { @@ -1757,6 +1841,7 @@ MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arc return Dyninst::InvalidReg; break; case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: // ignore CUDA register encodings for now return Dyninst::InvalidReg; break; @@ -2210,6 +2295,7 @@ unsigned Dyninst::getArchAddressWidth(Dyninst::Architecture arch) case Arch_cuda: case Arch_intelGen9: case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: return 8; default: assert(0); diff --git a/dwarf/src/dwarfHandle.C b/dwarf/src/dwarfHandle.C index 2a6efd03f8..937d08a913 100644 --- a/dwarf/src/dwarfHandle.C +++ b/dwarf/src/dwarfHandle.C @@ -197,11 +197,11 @@ bool DwarfHandle::init_dbg() case EM_CUDA: arch = Dyninst::Arch_cuda; break; - case EM_AMDGPU: { + case EM_AMDGPU: { // TODO: This part of logic needs to be updated to reflect the table on the llvm website unsigned int ef_amdgpu_mach = 0x000000ff & file->e_flags(); switch(ef_amdgpu_mach){ - case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: case 0x38: - arch = Dyninst::Arch_amdgpu_rdna; + case 0x3f: + arch = Dyninst::Arch_amdgpu_cdna2; break; case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: arch = Dyninst::Arch_amdgpu_vega; diff --git a/elf/src/Elf_X.C b/elf/src/Elf_X.C index 404926a733..25a2bb0bda 100644 --- a/elf/src/Elf_X.C +++ b/elf/src/Elf_X.C @@ -1829,9 +1829,8 @@ Dyninst::Architecture Elf_X::getArch() const unsigned int ef_amdgpu_mach = 0x000000ff & e_flags(); //cerr << " dealing with amd gpu , mach = " << std::hex << ef_amdgpu_mach << endl; switch(ef_amdgpu_mach){ - case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: case 0x38: - return Dyninst::Arch_amdgpu_rdna; - assert( 0 && "rdna not supported yet " ); + case 0x3f: + return Dyninst::Arch_amdgpu_cdna2; case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: return Dyninst::Arch_amdgpu_vega; case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: @@ -1840,6 +1839,7 @@ Dyninst::Architecture Elf_X::getArch() const case 0x27: case 0x32 : case 0x39: assert(0 && "reserved"); default: + //cerr << "unsupported amdgpu architecture , value = " << ef_amdgpu_mach << endl; assert(0 && "probabily won't be supported"); } diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index b55de862ff..baf647eb03 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -2,6 +2,8 @@ include_directories ( ${PROJECT_SOURCE_DIR}/instructionAPI/src + ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/cdna2 + ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/vega ) @@ -21,7 +23,8 @@ set (SRC_LIST src/InstructionDecoder-x86.C src/InstructionDecoder-power.C src/InstructionDecoder-aarch64.C - src/InstructionDecoder-amdgpu-vega.C + src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C + src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C src/InstructionDecoderImpl.C ) SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) diff --git a/instructionAPI/h/Instruction.h b/instructionAPI/h/Instruction.h index 2119eb3ca1..2782c9f1fa 100644 --- a/instructionAPI/h/Instruction.h +++ b/instructionAPI/h/Instruction.h @@ -92,6 +92,8 @@ namespace Dyninst friend class InstructionDecoder_power; friend class InstructionDecoder_aarch64; friend class InstructionDecoder_amdgpu_vega; + friend class InstructionDecoder_amdgpu_cdna; + friend class InstructionDecoder_amdgpu_cdna2; struct CFT { diff --git a/instructionAPI/h/Operation_impl.h b/instructionAPI/h/Operation_impl.h index 7cc6f20471..34902f3041 100644 --- a/instructionAPI/h/Operation_impl.h +++ b/instructionAPI/h/Operation_impl.h @@ -102,6 +102,9 @@ namespace Dyninst friend class InstructionDecoder_power; // for editing mnemonics after creation friend class InstructionDecoder_aarch64; friend class InstructionDecoder_amdgpu_vega; + friend class InstructionDecoder_amdgpu_cdna; + friend class InstructionDecoder_amdgpu_cdna2; + friend class Instruction; // to make use of the update size function public: INSTRUCTION_EXPORT Operation_impl(NS_x86::ia32_entry* e, NS_x86::ia32_prefixes* p = NULL, ia32_locations* l = NULL, diff --git a/instructionAPI/h/Result.h b/instructionAPI/h/Result.h index 8c5ba6993d..b6f0421388 100644 --- a/instructionAPI/h/Result.h +++ b/instructionAPI/h/Result.h @@ -36,12 +36,12 @@ #if !defined(_MSC_VER) #include #else - typedef __int64 int64_t; - typedef __int32 int32_t; - typedef __int16 int16_t; - typedef unsigned __int64 uint64_t; - typedef unsigned __int32 uint32_t; - typedef unsigned __int16 uint16_t; +typedef __int64 int64_t; +typedef __int32 int32_t; +typedef __int16 int16_t; +typedef unsigned __int64 uint64_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int16 uint16_t; #endif #include #include @@ -50,557 +50,580 @@ namespace Dyninst { - namespace InstructionAPI - { - union Result_Value + namespace InstructionAPI { - unsigned char bitval : 1; - unsigned char u8val; - char s8val; - uint16_t u16val; - int16_t s16val; - uint32_t u24val:24; - uint32_t u32val; - int32_t s32val; - uint64_t u64val; - int64_t s64val; - float floatval; - double dblval; - uint64_t u48val : 48; - int64_t s48val : 48; - void * m14val; - void * m96val; - void * dbl128val; - void * m192val; - void * m256val; - void * m384val; - void * m512val; - }; - enum Result_Type - { - bit_flag = 0, - s8, - u8, - s16, - u16, - u24, - s32, - u32, - s48, - u48, - s64, - u64, - sp_float, - dp_float, - // 48-bit pointers...yay Intel - m14, - m96, - dbl128, - m192, - m256, - m384, - m512, - invalid_type - }; + union Result_Value + { + unsigned char bitval : 1; + unsigned char u8val; + char s8val; + uint16_t u16val; + int16_t s16val; + uint32_t u24val:24; + uint32_t u32val; + int32_t s32val; + uint64_t u64val; + int64_t s64val; + float floatval; + double dblval; + uint64_t u48val : 48; + int64_t s48val : 48; + void * m14val; + void * dbl128val; + void * m32val; + void * m64val; + void * m96val; + void * m128val; + void * m160val; + void * m192val; + void * m224val; + void * m256val; + void * m288val; + void * m320val; + void * m352val; + void * m384val; + void * m416val; + void * m448val; + void * m480val; + void * m512val; + }; + enum Result_Type + { + bit_flag = 0, + s8, + u8, + s16, + u16, + u24, + s32, + u32, + s48, + u48, + s64, + u64, + sp_float, + dp_float, + // 48-bit pointers...yay Intel + m14, + dbl128, + m32, + m64, + m96, + m128, + m160, + m192, + m224, + m256, + m288, + m320, + m352, + m384, + m416, + m448, + m480, + m512, - template < Result_Type t > struct Result_type2type - { - typedef void* type; - }; - template < > struct Result_type2type - { - typedef char type; - }; - template < > struct Result_type2type - { - typedef unsigned char type; - }; - template < > struct Result_type2type - { - typedef int16_t type; - }; - template < > struct Result_type2type - { - typedef uint16_t type; - }; - template < > struct Result_type2type - { - typedef uint32_t type; - }; - template < > struct Result_type2type - { - typedef int32_t type; - }; - template < > struct Result_type2type - { - typedef uint32_t type; - }; - template < > struct Result_type2type - { - typedef int64_t type; - }; - template < > struct Result_type2type - { - typedef uint64_t type; - }; - template < > struct Result_type2type - { - typedef int64_t type; - }; - template < > struct Result_type2type - { - typedef uint64_t type; - }; - template < > struct Result_type2type - { - typedef float type; - }; - template < > struct Result_type2type - { - typedef double type; - }; - template < > struct Result_type2type - { - typedef unsigned char type; - }; - /// A %Result object represents a value computed by a %Expression AST. - /// - /// The %Result class is a tagged-union representation of the results that - /// %Expressions can produce. It includes 8, 16, 32, 48, and 64 bit integers - /// (signed and unsigned), bit values, and single and double precision floating point values. - /// For each of these types, the value of a %Result may be undefined, or it may be a value within - /// the range of the type. - /// - /// The \c type field is an enum that may contain any of the following values: - /// - \c u8: an unsigned 8-bit integer - /// - \c s8: a signed 8-bit integer - /// - \c u16: an unsigned 16-bit integer - /// - \c s16: a signed 16-bit integer - /// - \c u32: an unsigned 32-bit integer - /// - \c s32: a signed 32-bit integer - /// - \c u48: an unsigned 48-bit integer (IA32 pointers) - /// - \c s48: a signed 48-bit integer (IA32 pointers) - /// - \c u64: an unsigned 64-bit integer - /// - \c s64: a signed 64-bit integer - /// - \c sp_float: a single-precision float - /// - \c dp_float: a double-precision float - /// - \c bit_flag: a single bit (individual flags) - /// - \c m512: a 512-bit memory value - /// - \c dbl128: a 128-bit integer, which often contains packed floating point values - /// - \c m14: a 14 byte memory value - /// - // The %Instruction API's model of %Results is a simple one, and may seem overly aggressive about - // making an %Expression's %Result undefined. It follows the same basic rule as the rest of the API: - // a decoded %Instruction object represents only the information that may be obtained from the machine - // instruction that was decoded. As discussed in the Expression section, the \c setValue - // and \c eval interface allows you to determine the possible %Results of an %Expression when evaluated over various - // machine states. From this, you may construct abstractions to represent the set of possible results. - // Alternately, you may use instrumentation to determine the exact machine state at the time an - // instruction executes, which will allow you to evaluate the %Result of an %Expression in its actual context. - class INSTRUCTION_EXPORT Result - { - public: - Result_Value val; - Result_Type type; - bool defined; + invalid_type + }; + + template < Result_Type t > struct Result_type2type + { + typedef void* type; + }; + template < > struct Result_type2type + { + typedef char type; + }; + template < > struct Result_type2type + { + typedef unsigned char type; + }; + template < > struct Result_type2type + { + typedef int16_t type; + }; + template < > struct Result_type2type + { + typedef uint16_t type; + }; + template < > struct Result_type2type + { + typedef uint32_t type; + }; + template < > struct Result_type2type + { + typedef int32_t type; + }; + template < > struct Result_type2type + { + typedef uint32_t type; + }; + template < > struct Result_type2type + { + typedef int64_t type; + }; + template < > struct Result_type2type + { + typedef uint64_t type; + }; + template < > struct Result_type2type + { + typedef int64_t type; + }; + template < > struct Result_type2type + { + typedef uint64_t type; + }; + template < > struct Result_type2type + { + typedef float type; + }; + template < > struct Result_type2type + { + typedef double type; + }; + template < > struct Result_type2type + { + typedef unsigned char type; + }; + /// A %Result object represents a value computed by a %Expression AST. + /// + /// The %Result class is a tagged-union representation of the results that + /// %Expressions can produce. It includes 8, 16, 32, 48, and 64 bit integers + /// (signed and unsigned), bit values, and single and double precision floating point values. + /// For each of these types, the value of a %Result may be undefined, or it may be a value within + /// the range of the type. + /// + /// The \c type field is an enum that may contain any of the following values: + /// - \c u8: an unsigned 8-bit integer + /// - \c s8: a signed 8-bit integer + /// - \c u16: an unsigned 16-bit integer + /// - \c s16: a signed 16-bit integer + /// - \c u32: an unsigned 32-bit integer + /// - \c s32: a signed 32-bit integer + /// - \c u48: an unsigned 48-bit integer (IA32 pointers) + /// - \c s48: a signed 48-bit integer (IA32 pointers) + /// - \c u64: an unsigned 64-bit integer + /// - \c s64: a signed 64-bit integer + /// - \c sp_float: a single-precision float + /// - \c dp_float: a double-precision float + /// - \c bit_flag: a single bit (individual flags) + /// - \c m512: a 512-bit memory value + /// - \c dbl128: a 128-bit integer, which often contains packed floating point values + /// - \c m14: a 14 byte memory value + /// + // The %Instruction API's model of %Results is a simple one, and may seem overly aggressive about + // making an %Expression's %Result undefined. It follows the same basic rule as the rest of the API: + // a decoded %Instruction object represents only the information that may be obtained from the machine + // instruction that was decoded. As discussed in the Expression section, the \c setValue + // and \c eval interface allows you to determine the possible %Results of an %Expression when evaluated over various + // machine states. From this, you may construct abstractions to represent the set of possible results. + // Alternately, you may use instrumentation to determine the exact machine state at the time an + // instruction executes, which will allow you to evaluate the %Result of an %Expression in its actual context. + class INSTRUCTION_EXPORT Result + { + public: + Result_Value val; + Result_Type type; + bool defined; - Result() : - type(u32), defined(false) - { - val.u32val = 0; - } - Result(const Result& o) : - val(o.val), type(o.type), defined(o.defined) - { - } + Result() : + type(u32), defined(false) + { + val.u32val = 0; + } + Result(const Result& o) : + val(o.val), type(o.type), defined(o.defined) + { + } - const Result& operator=(const Result& rhs) - { - val = rhs.val; - type = rhs.type; - defined = rhs.defined; - return *this; - } + const Result& operator=(const Result& rhs) + { + val = rhs.val; + type = rhs.type; + defined = rhs.defined; + return *this; + } - /// A %Result may be constructed from a type without providing a value. - /// This constructor creates a %Result of type \c t with undefined contents. - Result(Result_Type t) : - type(t), defined(false) - { - val.u32val = 0; - } + /// A %Result may be constructed from a type without providing a value. + /// This constructor creates a %Result of type \c t with undefined contents. + Result(Result_Type t) : + type(t), defined(false) + { + val.u32val = 0; + } - /// A %Result may be constructed from a type and any value convertible to the type that the - /// tag represents. - /// This constructor creates a %Result of type \c t and contents \c v for any \c v that is implicitly - /// convertible to type \c t. Attempting to construct a %Result with a value that is incompatible with - /// its type will result in a compile-time error. - template - Result(Result_Type t, T v) : - type(t), defined(true) - { - switch(type) - { - case u8: - val.u8val = (unsigned char)(v); - break; - case s8: - val.s8val = (char)(v); - break; - case u16: - val.u16val = (uint16_t)(v); - break; - case s16: - val.s16val = (int16_t)(v); - break; - case u24: - val.u24val = (uint32_t)(v & 0xFFFFFF); - break; - case u32: - val.u32val = (uint32_t)(v ); - break; - case s32: - val.s32val = (int32_t)(v); - break; - case u64: - val.u64val = (uint64_t)(v); - break; - case s64: - val.s64val = (int64_t)(v); - break; - case bit_flag: - val.bitval = (v != 0) ? 1 : 0; - break; - case u48: - val.u48val = (uint64_t)(v & 0x0000FFFFFFFFFFFFLL); - break; - case s48: - val.s48val = (int64_t)(v & 0x0000FFFFFFFFFFFFLL); - break; - case m512: - val.m512val = (void *)(intptr_t) v; - break; - case dbl128: - val.dbl128val = (void*)(intptr_t) v; - break; - case m14: - val.m14val = (void*)(intptr_t) v; - break; - case m96: - val.m96val = (void *)(intptr_t) v; - break; - case m192: - val.m192val = (void *)(intptr_t) v; - break; - case m256: - val.m256val = (void *)(intptr_t) v; - break; - case m384: - val.m384val = (void *)(intptr_t) v; - break; - // Floats should be constructed with float types - default: - case sp_float: - case dp_float: - assert(!"Invalid type!"); - break; - } - } - Result(Result_Type t, float v) : - type(t), defined(true) - { - assert(t == sp_float || t == dp_float); - val.dblval = (double)v; - } - Result(Result_Type t, double v) : - type(t), defined(true) - { - assert(t == sp_float || t == dp_float); - val.dblval = v; - } - ~Result() - { - } + /// A %Result may be constructed from a type and any value convertible to the type that the + /// tag represents. + /// This constructor creates a %Result of type \c t and contents \c v for any \c v that is implicitly + /// convertible to type \c t. Attempting to construct a %Result with a value that is incompatible with + /// its type will result in a compile-time error. + template + Result(Result_Type t, T v) : + type(t), defined(true) + { + switch(type) + { + case u8: + val.u8val = (unsigned char)(v); + break; + case s8: + val.s8val = (char)(v); + break; + case u16: + val.u16val = (uint16_t)(v); + break; + case s16: + val.s16val = (int16_t)(v); + break; + case u24: + val.u24val = (uint32_t)(v & 0xFFFFFF); + break; + case u32: + val.u32val = (uint32_t)(v ); + break; + case s32: + val.s32val = (int32_t)(v); + break; + case u64: + val.u64val = (uint64_t)(v); + break; + case s64: + val.s64val = (int64_t)(v); + break; + case bit_flag: + val.bitval = (v != 0) ? 1 : 0; + break; + case u48: + val.u48val = (uint64_t)(v & 0x0000FFFFFFFFFFFFLL); + break; + case s48: + val.s48val = (int64_t)(v & 0x0000FFFFFFFFFFFFLL); + break; + case m512: + val.m512val = (void *)(intptr_t) v; + break; + case dbl128: + val.dbl128val = (void*)(intptr_t) v; + break; + case m14: + val.m14val = (void*)(intptr_t) v; + break; + case m96: + val.m96val = (void *)(intptr_t) v; + break; + case m192: + val.m192val = (void *)(intptr_t) v; + break; + case m256: + val.m256val = (void *)(intptr_t) v; + break; + case m384: + val.m384val = (void *)(intptr_t) v; + break; + // Floats should be constructed with float types + default: + case sp_float: + case dp_float: + assert(!"Invalid type!"); + break; + } + } + Result(Result_Type t, float v) : + type(t), defined(true) + { + assert(t == sp_float || t == dp_float); + val.dblval = (double)v; + } + Result(Result_Type t, double v) : + type(t), defined(true) + { + assert(t == sp_float || t == dp_float); + val.dblval = v; + } + ~Result() + { + } - bool operator<(const Result& o) const - { - if(type < o.type) return true; - if(!defined) return false; - if(!o.defined) return true; + bool operator<(const Result& o) const + { + if(type < o.type) return true; + if(!defined) return false; + if(!o.defined) return true; - switch(type) - { - case u8: - return val.u8val < o.val.u8val; - break; - case s8: - return val.s8val < o.val.s8val; - break; - case u16: - return val.u16val < o.val.u16val; - break; - case s16: - return val.s16val < o.val.s16val; - break; - case u24: - return val.u24val < o.val.u24val; - break; - case u32: - return val.u32val < o.val.u32val; - break; - case s32: - return val.s32val < o.val.s32val; - break; - case u64: - return val.u64val < o.val.u64val; - break; - case s64: - return val.s64val < o.val.s64val; - break; - case sp_float: - return val.floatval < o.val.floatval; - break; - case dp_float: - return val.dblval < o.val.dblval; - break; - case bit_flag: - return val.bitval < o.val.bitval; - break; - case u48: - return val.u48val < o.val.u48val; - break; - case s48: - return val.s48val < o.val.s48val; - break; - case m512: - return memcmp(val.m512val, o.val.m512val, 512) < 0; - break; - case dbl128: - return memcmp(val.dbl128val, o.val.dbl128val, 128 / 8) < 0; - break; - case m14: - return memcmp(val.m14val, o.val.m14val, 14) < 0; - break; - case m96: - return memcmp(val.m96val, o.val.m96val, 96) < 0; - break; - case m192: - return memcmp(val.m192val, o.val.m192val, 192) < 0; - break; - case m256: - return memcmp(val.m256val, o.val.m256val, 256) < 0; - break; - case m384: - return memcmp(val.m384val, o.val.m384val, 384) < 0; - break; - default: - assert(!"Invalid type!"); - break; - } - return false; - } + switch(type) + { + case u8: + return val.u8val < o.val.u8val; + break; + case s8: + return val.s8val < o.val.s8val; + break; + case u16: + return val.u16val < o.val.u16val; + break; + case s16: + return val.s16val < o.val.s16val; + break; + case u24: + return val.u24val < o.val.u24val; + break; + case u32: + return val.u32val < o.val.u32val; + break; + case s32: + return val.s32val < o.val.s32val; + break; + case u64: + return val.u64val < o.val.u64val; + break; + case s64: + return val.s64val < o.val.s64val; + break; + case sp_float: + return val.floatval < o.val.floatval; + break; + case dp_float: + return val.dblval < o.val.dblval; + break; + case bit_flag: + return val.bitval < o.val.bitval; + break; + case u48: + return val.u48val < o.val.u48val; + break; + case s48: + return val.s48val < o.val.s48val; + break; + case m512: + return memcmp(val.m512val, o.val.m512val, 512) < 0; + break; + case dbl128: + return memcmp(val.dbl128val, o.val.dbl128val, 128 / 8) < 0; + break; + case m14: + return memcmp(val.m14val, o.val.m14val, 14) < 0; + break; + case m96: + return memcmp(val.m96val, o.val.m96val, 96) < 0; + break; + case m192: + return memcmp(val.m192val, o.val.m192val, 192) < 0; + break; + case m256: + return memcmp(val.m256val, o.val.m256val, 256) < 0; + break; + case m384: + return memcmp(val.m384val, o.val.m384val, 384) < 0; + break; + default: + assert(!"Invalid type!"); + break; + } + return false; + } - /// Two %Results are equal if any of the following hold: - /// - Both %Results are of the same type and undefined - /// - Both %Results are of the same type, defined, and have the same value - /// - /// Otherwise, they are unequal (due to having different types, an undefined %Result compared to a defined %Result, - /// or different values). + /// Two %Results are equal if any of the following hold: + /// - Both %Results are of the same type and undefined + /// - Both %Results are of the same type, defined, and have the same value + /// + /// Otherwise, they are unequal (due to having different types, an undefined %Result compared to a defined %Result, + /// or different values). - bool operator==(const Result& o) const - { - return !((*this < o) || (o < *this)); + bool operator==(const Result& o) const + { + return !((*this < o) || (o < *this)); - } - /// %Results are formatted as strings containing their contents, represented as hexadecimal. - /// The type of the %Result is not included in the output. - std::string format() const - { - if(!defined) - { - return "[empty]"; - } - else - { - char hex[20]; - switch(type) - { - case u8: - snprintf(hex, 20, "%x", val.u8val); - break; - case s8: - snprintf(hex, 20, "%x", (unsigned int)val.s8val); - break; - case u16: - snprintf(hex, 20, "%x", val.u16val); - break; - case s16: - snprintf(hex, 20, "%x", (unsigned int)val.s16val); - break; - case u24: - snprintf(hex, 20, "%x", (unsigned int)val.u24val); - break; - case u32: - snprintf(hex, 20, "%x", val.u32val); - break; - case s32: - snprintf(hex, 20, "%x", (unsigned int)val.s32val); - break; - case u64: - return std::to_string(val.u64val); - case s64: - return std::to_string(val.s64val); - break; - case sp_float: - snprintf(hex, 20, "%f", (double)val.floatval); - break; - case dp_float: - snprintf(hex, 20, "%lf", val.dblval); - break; - case bit_flag: - snprintf(hex, 20, "%x", (unsigned int)val.bitval); - break; - case u48: - return std::to_string(val.s48val); - break; - case s48: - return std::to_string(val.s48val); - break; - case m512: - snprintf(hex, 20, "%p", val.m512val); - break; - case m14: - snprintf(hex, 20, "%p", val.m14val); - break; - case m96: - snprintf(hex, 20, "%p", val.m96val); - break; - case dbl128: - snprintf(hex, 20, "%p", val.dbl128val); - break; - case m192: - snprintf(hex, 20, "%p", val.m192val); - break; - case m256: - snprintf(hex, 20, "%p", val.m256val); - break; - case m384: - snprintf(hex, 20, "%p", val.m384val); - break; - default: - snprintf(hex, 20, "[invalid type]"); - break; - }; - return std::string(hex); - } - } + } + /// %Results are formatted as strings containing their contents, represented as hexadecimal. + /// The type of the %Result is not included in the output. + std::string format() const + { + if(!defined) + { + return "[empty]"; + } + else + { + char hex[20]; + switch(type) + { + case u8: + snprintf(hex, 20, "%x", val.u8val); + break; + case s8: + snprintf(hex, 20, "%x", (unsigned int)val.s8val); + break; + case u16: + snprintf(hex, 20, "%x", val.u16val); + break; + case s16: + snprintf(hex, 20, "%x", (unsigned int)val.s16val); + break; + case u24: + snprintf(hex, 20, "%x", (unsigned int)val.u24val); + break; + case u32: + snprintf(hex, 20, "%x", val.u32val); + break; + case s32: + snprintf(hex, 20, "%x", (unsigned int)val.s32val); + break; + case u64: + return std::to_string(val.u64val); + case s64: + return std::to_string(val.s64val); + break; + case sp_float: + snprintf(hex, 20, "%f", (double)val.floatval); + break; + case dp_float: + snprintf(hex, 20, "%lf", val.dblval); + break; + case bit_flag: + snprintf(hex, 20, "%x", (unsigned int)val.bitval); + break; + case u48: + return std::to_string(val.s48val); + break; + case s48: + return std::to_string(val.s48val); + break; + case m512: + snprintf(hex, 20, "%p", val.m512val); + break; + case m14: + snprintf(hex, 20, "%p", val.m14val); + break; + case m96: + snprintf(hex, 20, "%p", val.m96val); + break; + case dbl128: + snprintf(hex, 20, "%p", val.dbl128val); + break; + case m192: + snprintf(hex, 20, "%p", val.m192val); + break; + case m256: + snprintf(hex, 20, "%p", val.m256val); + break; + case m384: + snprintf(hex, 20, "%p", val.m384val); + break; + default: + snprintf(hex, 20, "[invalid type]"); + break; + }; + return std::string(hex); + } + } - template< typename to_type > - to_type convert() const - { - switch(type) - { - case s8: - return to_type(val.s8val); - case u8: - return to_type(val.u8val); - case s16: - return to_type(val.s16val); - case u16: - return to_type(val.u16val); - case u24: - return to_type(val.u24val); - case s32: - return to_type(val.s32val); - case u32: - return to_type(val.u32val); - case s48: - return to_type(val.s48val); - case u48: - return to_type(val.u48val); - case s64: - return to_type(val.s64val); - case u64: - return to_type(val.u64val); - case sp_float: - return to_type(val.floatval); - case dp_float: - return to_type(val.dblval); - case bit_flag: - return to_type(val.bitval); - case m512: - case dbl128: - case m192: - case m256: - case m384: - case m96: - assert(!"M512 and DBL128 types cannot be converted yet"); - return to_type(0); - default: - assert(!"Invalid type in result!"); - return to_type(0); - } - } + template< typename to_type > + to_type convert() const + { + switch(type) + { + case s8: + return to_type(val.s8val); + case u8: + return to_type(val.u8val); + case s16: + return to_type(val.s16val); + case u16: + return to_type(val.u16val); + case u24: + return to_type(val.u24val); + case s32: + return to_type(val.s32val); + case u32: + return to_type(val.u32val); + case s48: + return to_type(val.s48val); + case u48: + return to_type(val.u48val); + case s64: + return to_type(val.s64val); + case u64: + return to_type(val.u64val); + case sp_float: + return to_type(val.floatval); + case dp_float: + return to_type(val.dblval); + case bit_flag: + return to_type(val.bitval); + case m512: + case dbl128: + case m192: + case m256: + case m384: + case m96: + assert(!"M512 and DBL128 types cannot be converted yet"); + return to_type(0); + default: + assert(!"Invalid type in result!"); + return to_type(0); + } + } - /// Returns the size of the contained type, in bytes - int size() const - { - switch(type) - { - case u8: - case s8: - return 1; - case u16: - case s16: - return 2; - case u24: - return 3; - case u32: - case s32: - return 4; - case u64: - case s64: - return 8; - case u48: - case s48: - return 6; - case sp_float: - return sizeof(float); - case dp_float: - return sizeof(double); - case bit_flag: - return 1; - case m512: - return 64; - case dbl128: - return 16; - case m192: - return 24; - case m256: - return 32; - default: - // In probabilistic gap parsing, - // we could start to decode at any byte and reach here. - // It is a sign for junk bytes - return 0; - }; - } - }; + /// Returns the size of the contained type, in bytes + int size() const + { + switch(type) + { + case u8: + case s8: + return 1; + case u16: + case s16: + return 2; + case u24: + return 3; + case u32: + case s32: + return 4; + case u64: + case s64: + return 8; + case u48: + case s48: + return 6; + case sp_float: + return sizeof(float); + case dp_float: + return sizeof(double); + case bit_flag: + return 1; + case m512: + return 64; + case dbl128: + return 16; + case m192: + return 24; + case m256: + return 32; + default: + // In probabilistic gap parsing, + // we could start to decode at any byte and reach here. + // It is a sign for junk bytes + return 0; + }; + } + }; - INSTRUCTION_EXPORT Result operator+(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator*(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator<<(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator>>(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator&(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator|(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator+(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator*(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator<<(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator>>(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator&(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator|(const Result& arg1, const Result& arg2); - } + } } diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C new file mode 100644 index 0000000000..46e999577e --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -0,0 +1,310 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Ternary.h" +#include "InstructionDecoder-amdgpu-cdna2.h" + +namespace Dyninst { + namespace InstructionAPI { + typedef void (InstructionDecoder_amdgpu_cdna2::*operandFactory)(); + + typedef amdgpu_cdna2_insn_entry amdgpu_cdna2_insn_table[]; + typedef amdgpu_mask_entry amdgpu_decoder_table[]; + + const std::array InstructionDecoder_amdgpu_cdna2::condNames = { { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", + "lt", "gt", "le", "al", "nv", + } }; + + const char* InstructionDecoder_amdgpu_cdna2::bitfieldInsnAliasMap(entryID e) { + switch(e) { + default: assert(!"no alias for entryID"); + }; + } + const char* InstructionDecoder_amdgpu_cdna2::condInsnAliasMap(entryID e) { + switch(e) { + default: assert(!"no alias for entryID"); + }; + } + +#include "amdgpu_cdna2_insn_entry.h" + struct amdgpu_mask_entry { + unsigned int mask; + std::size_t branchCnt; + const std::pair* nodeBranches; + int insnTableIndex; + + static const amdgpu_decoder_table main_decoder_table; + static const std::pair branchTable[]; + }; + +#include "amdgpu_cdna2_opcode_tables.C" + + InstructionDecoder_amdgpu_cdna2::InstructionDecoder_amdgpu_cdna2(Architecture a) + : InstructionDecoderImpl(a), + insn_size(0), immLen(0) , num_elements(1) , isSMEM(false), isLoad(false), isStore(false),isBuffer(false), + isScratch(false) , isBranch(false), isConditional(false) ,isCall(false), isModifyPC(false) + { + } + + InstructionDecoder_amdgpu_cdna2::~InstructionDecoder_amdgpu_cdna2() { + } + + + using namespace std; + void InstructionDecoder_amdgpu_cdna2::NOTHING() { + } + + Result_Type InstructionDecoder_amdgpu_cdna2::makeSizeType(unsigned int) { + assert(0); //not implemented + return u32; + } + + // **************** + // decoding opcodes + // **************** + + MachRegister InstructionDecoder_amdgpu_cdna2::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int len) { + MachRegister realBase = base; + /*if (base == amdgpu_cdna2::s0){ + switch(len){ + case 2: + realBase = amdgpu_cdna2::sgpr_vec2_0; + break; + case 4: + realBase = amdgpu_cdna2::sgpr_vec4_0; + break; + case 8: + realBase = amdgpu_cdna2::sgpr_vec8_0; + break; + case 16: + realBase = amdgpu_cdna2::sgpr_vec16_0; + break; + } + }else if (base == amdgpu_cdna2::v0){ + switch(len){ + case 2: + realBase = amdgpu_cdna2::vgpr_vec2_0; + break; + case 4: + realBase = amdgpu_cdna2::vgpr_vec4_0; + break; + case 8: + realBase = amdgpu_cdna2::vgpr_vec8_0; + break; + case 16: + realBase = amdgpu_cdna2::vgpr_vec16_0; + break; + } + + }*/ + return MachRegister(realBase.val() + encoding); + + } + + Expression::Ptr InstructionDecoder_amdgpu_cdna2::makePCExpr() { + MachRegister baseReg = amdgpu_cdna2::pc_all; + return makeRegisterExpression(baseReg); + } + + void InstructionDecoder_amdgpu_cdna2::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, + int immLen_ = 16) { + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + int64_t offset = sign_extend64(immLen_, immVal * 4); + + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + + insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, + false); + if (bIsConditional || branchIsCall) { + insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); + } + + } + + Expression::Ptr InstructionDecoder_amdgpu_cdna2::makeFallThroughExpr() { + // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long + return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); + } + + + bool InstructionDecoder_amdgpu_cdna2::decodeOperands(const Instruction *) { + assert(0 && "decodeOperands deprecated for amdgpu"); + return true; + } + + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeSGPRorM0(unsigned int offset){ + if( offset <= 104) + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_cdna2::s0,offset)); + if (offset == 124) + return makeRegisterExpression(amdgpu_cdna2::m0); + cerr << " unknown offset in sgpr or m0 " << offset << endl; + assert(0 && "shouldn't reach here"); + } + + + uint32_t InstructionDecoder_amdgpu_cdna2::decodeOPR_LITERAL(){ + if (!useImm){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + + } + return immLiteral; + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_LABEL(uint64_t input){ + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + int64_t offset = sign_extend64(immLen, input * 4); + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + return makeAddExpression(lhs, rhs, s64); + + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SIMM4(uint64_t input){ + return Immediate::makeImmediate(Result(s8, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SIMM8(uint64_t input){ + return Immediate::makeImmediate(Result(s8, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SIMM16(uint64_t input){ + return Immediate::makeImmediate(Result(s16, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SIMM32(uint64_t input){ + return Immediate::makeImmediate(Result(s32, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_WAITCNT(uint64_t input){ + return Immediate::makeImmediate(Result(s16, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::makeRegisterExpression(MachRegister registerID){ + if(registerID == amdgpu_cdna2::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID); + } + Expression::Ptr InstructionDecoder_amdgpu_cdna2::makeRegisterExpression(MachRegister registerID, uint32_t low, uint32_t high ){ + if(registerID == amdgpu_cdna2::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID, low, high ); + } + + + + void Dyninst::InstructionAPI::InstructionDecoder_amdgpu_cdna2::finalizeENC_VINTRPOperands(){ + + } +#include "amdgpu_cdna2_decoder_impl.C" +#include "decodeOperands.C" +#include "finalizeOperands.C" + inline unsigned int InstructionDecoder_amdgpu_cdna2::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ + assert(offset %4 ==0 ); + if(b.start + offset + 4 < b.end) + return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; + return 0; + } + + + void InstructionDecoder_amdgpu_cdna2::reset(){ + immLen = 0; + insn_size = 0; + num_elements =1; + isBranch = false; + isConditional = false; + isModifyPC =false; + isSMEM = false; + isLoad = false ; + isStore =false; + isBuffer =false ; + isScratch = false; + insn = insn_high = insn_long = 0; + useImm = false; + isCall = false; + if (!getenv("DEBUG_DECODE")) + cout.setstate(ios_base::badbit); + } + // here we assemble the first 64 bit (if available) as an instruction + + void InstructionDecoder_amdgpu_cdna2::setupInsnWord(InstructionDecoder::buffer &b) { + reset(); + if (b.start > b.end) + return; + insn = get32bit(b,0); + + imm_at_32 = insn_high = get32bit(b,4); + imm_at_64 = get32bit(b,8); + + insn_long = ( ((uint64_t) insn_high) << 32) | insn; + cout << " setup insn_long = " << std::hex << insn_long << endl; + + } + void InstructionDecoder_amdgpu_cdna2::decodeOpcode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + } + + void InstructionDecoder_amdgpu_cdna2::debug_instr(){ + cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family + << " length = " << insn_in_progress->size()<< endl << endl; + + } + + Instruction InstructionDecoder_amdgpu_cdna2::decode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){ + //cout << "Is Branch Instruction !! , name = " << insn_in_progress -> getOperation().mnemonic << endl; + //std::mem_fun(decode_lookup_table[instr_family])(this); + } + debug_instr(); + cout.clear(); + b.start += insn_in_progress->size(); + return *insn_in_progress; + } + + void InstructionDecoder_amdgpu_cdna2::doDelayedDecode(const Instruction *insn_to_complete) { + + InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); + setupInsnWord(b); + mainDecode(); + debug_instr(); + cout.clear(); + Instruction* iptr = const_cast(insn_to_complete); + *iptr = *(insn_in_progress.get()); + } + } +} + + + diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h new file mode 100644 index 0000000000..7acd5e0a2b --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h @@ -0,0 +1,317 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "InstructionDecoderImpl.h" +#include +#include "Immediate.h" +#include "dyn_regs.h" + +namespace Dyninst { + namespace InstructionAPI { + +#define insn_printf(format, ...) \ + do{ \ + printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ + }while(0) + + struct amdgpu_cdna2_insn_entry; + struct amdgpu_mask_entry; + + class InstructionDecoder_amdgpu_cdna2 : public InstructionDecoderImpl { + friend struct amdgpu_cdna2_insn_entry; + friend struct amdgpu_mask_entry; + enum DecodeFamily {sopp}; + + public: + InstructionDecoder_amdgpu_cdna2(Architecture a); + + virtual ~InstructionDecoder_amdgpu_cdna2(); + + virtual void decodeOpcode(InstructionDecoder::buffer &b); + + // decode one instruction starting from b.start + // will advance b.start whenver a instruction is successfully decoded + virtual Instruction decode(InstructionDecoder::buffer &b); + + virtual void setMode(bool) { } + + virtual bool decodeOperands(const Instruction *insn_to_complete); + + bool decodeOperands(const amdgpu_cdna2_insn_entry & insn_entry); + + virtual void doDelayedDecode(const Instruction *insn_to_complete); + + static const std::array condNames; + static MachRegister sysRegMap(unsigned int); + static const char* bitfieldInsnAliasMap(entryID); + static const char* condInsnAliasMap(entryID); + + + + private: + virtual Result_Type makeSizeType(unsigned int opType); + + bool is64Bit; + + unsigned int insn_size; // size of the instruction that we are currently working on + unsigned int insn; // the first 32 bit + unsigned int insn_high; // the second 32 bit + unsigned long long int insn_long; // the combined 64 bit: insn_high << 32 | insn + + // the main process of decoding an instruciton, won't advance buffer + void mainDecode(); + + void mainDecodeOpcode(); + + + void setupInsnWord(InstructionDecoder::buffer &b); + // pointer to the instruction that we are currently working on + boost::shared_ptr insn_in_progress; + + template + int field(unsigned int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFF >> (31 - (end - start)))) << " "; +#endif + return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); + } + + template + int longfield(unsigned long long int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; +#endif + return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); + } + + int32_t sign_extend32(int size_, int in) { + int32_t val = 0 | in; + + return (val << (32 - size_)) >> (32 - size_); + } + + int64_t sign_extend64(int size_, int in) { + int64_t val = 0 | in; + + return (val << (64 - size_)) >> (64 - size_); + } + + uint32_t unsign_extend32(int size_, int in) { + uint32_t mask = ~0; + + return (mask >> (32 - size_)) & in; + } + + uint64_t unsign_extend64(int size_, int in) { + uint64_t mask = ~0; + + return (mask >> (64 - size_)) & in; + } + + int highest_set_bit(int32_t val) { + for (int bit_index = 31; bit_index >= 0; bit_index--) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + int lowest_set_bit(int32_t val) { + for (int bit_index = 0; bit_index <= 31; bit_index++) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + + bool hasHw; + int hwField; + + void processHwFieldInsn(int, int); + + bool hasShift; + int shiftField; + + void makeBranchTarget(bool, bool, int, int); + + Expression::Ptr makeFallThroughExpr(); + + int _szField, size; + int _typeField; + int cmode; + int op; + int simdAlphabetImm; + + void processAlphabetImm(); + + void NOTHING(); + bool fix_bitfieldinsn_alias(int, int); + void fix_condinsn_alias_and_cond(int &); + void modify_mnemonic_simd_upperhalf_insns(); + + MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); + + MachRegister getLoadStoreSimdRegister(int encoding); + + Expression::Ptr makePCExpr(); + + + template + Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); + + + //for load store + void insnSize(unsigned int insn_size ); + + Expression::Ptr decodeSSRC(unsigned int index); + Expression::Ptr decodeVSRC(unsigned int index); + Expression::Ptr decodeVDST(unsigned int index); + + Expression::Ptr decodeSGPRorM0(unsigned int offset); + + + bool useImm; + uint32_t immLen; + uint32_t immLiteral; + uint32_t imm_at_32; + uint32_t imm_at_64; + uint32_t imm_at_96; + + bool setSCC; + +#define IS_LD_ST() (isLoad || isStore ) + + unsigned int num_elements ; // the number of elements that will be load or store by each instruction + bool isSMEM; // this is set when using smem instruction + bool isLoad; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time + bool isStore; // similar to isLoad, but for store instructions + bool isBuffer; // + bool isScratch; + + bool isBranch; // this is set for all branch instructions, + bool isConditional; // this is set for all conditional branch instruction, will set branchCond + bool isCall; // this is a call function + + + + // this is set for instructions that directly modify pc + // namely s_setpc and s_swappc + bool isModifyPC; + + // reset the decoder internal state for decoding the next instruction + void reset(); + + Expression::Ptr branchCond; + Expression::Ptr branchTarget; + + void setBranch(){ + isBranch = true; + } + + void setConditionalBranch(){ + isConditional = true; + // TODO : set conditional branch + } + void setModifyPC(){ + isModifyPC = true; + } + + void setCall(){ + isCall = true; + } + + inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ); + + template + void setUseImm(InstructionDecoder::buffer & b, unsigned int offset){ + if ( longfield(insn_long) == candidate ){ + useImm = true; + immLen = 4; + immLiteral = get32bit(b,offset); + } + + } + + void setSMEM() {isSMEM = true;} + + + + template + void setLoad(){isLoad = true; this->num_elements = num_elements; } + + template + void setStore() {isStore = true;this->num_elements = num_elements;} + + void setScratch() {isScratch = true;} + + void setBuffer() {isBuffer = true;} + + typedef struct buffer_resource_desc{ + unsigned long long base_address; + unsigned stride; + unsigned cache_swizzle; + unsigned swizzle_enable; + unsigned num_records; + unsigned dst_sel_x; + unsigned dst_sel_y; + unsigned dst_sel_z; + unsigned dst_sel_w; + unsigned num_format; + unsigned data_format; + unsigned user_vm_enable; + unsigned user_vm_mode; + unsigned index_stride; + unsigned add_tid_enable; + unsigned non_volatile; + unsigned type; + }buffer_resource_desc; + + void debug_instr(); + + uint32_t decodeOPR_LITERAL(); + Expression::Ptr decodeOPR_LABEL(uint64_t input); + Expression::Ptr decodeOPR_SIMM4(uint64_t input); + Expression::Ptr decodeOPR_SIMM8(uint64_t input); + Expression::Ptr decodeOPR_SIMM16(uint64_t input); + Expression::Ptr decodeOPR_SIMM32(uint64_t input); + Expression::Ptr decodeOPR_WAITCNT(uint64_t input); + using InstructionDecoderImpl::makeRegisterExpression; + Expression::Ptr makeRegisterExpression(MachRegister registerID); + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high ); + void specialHandle(); + #include "amdgpu_cdna2_decoder_impl.h" + #include "decodeOperands.h" + }; + } +} + diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C new file mode 100644 index 0000000000..66947766d8 --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C @@ -0,0 +1,2195 @@ +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SOP1(uint64_t I){ + switch( I & 4286643968 ){ + case 3196059648: + case 3196059904: + case 3196060672: + case 3196060160: + case 3196060416: + case 3196060928: + case 3196061184: + case 3196061440: + case 3196061696: + case 3196061952: + case 3196063744: + case 3196064000: + case 3196068096: + case 3196067840: + case 3196064256: + case 3196068352: + case 3196071936: + case 3196072448: + case 3196064512: + case 3196068608: + case 3196072704: + case 3196064768: + case 3196068864: + case 3196072960: + case 3196065024: + case 3196069120: + case 3196073216: + case 3196065280: + case 3196069376: + case 3196073472: + case 3196065536: + case 3196069632: + case 3196073728: + case 3196065792: + case 3196069888: + case 3196066048: + case 3196070144: + case 3196062208: + case 3196066304: + case 3196070400: + case 3196062464: + case 3196066560: + case 3196070656: + case 3196062720: + case 3196066816: + case 3196070912: + case 3196067584: + case 3196062976: + case 3196067072: + case 3196071168: + case 3196063232: + case 3196067328: + case 3196071424: + case 3196063488: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SOPC(uint64_t I){ + switch( I & 4294901760 ){ + case 3204448256: + case 3204513792: + case 3204644864: + case 3204579328: + case 3204710400: + case 3204775936: + case 3204841472: + case 3204907008: + case 3204972544: + case 3205038080: + case 3205103616: + case 3205169152: + case 3205234688: + case 3205300224: + case 3205365760: + case 3205431296: + case 3205693440: + case 3205562368: + case 3205627904: + case 3205496832: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SOPP(uint64_t I){ + switch( I & 4294901760 ){ + case 3212836864: + case 3212902400: + case 3213033472: + case 3212967936: + case 3213099008: + case 3213164544: + case 3213230080: + case 3213295616: + case 3213361152: + case 3213426688: + case 3213492224: + case 3213623296: + case 3213754368: + case 3214016512: + case 3214147584: + case 3213885440: + case 3214606336: + case 3214737408: + case 3213557760: + case 3213688832: + case 3213819904: + case 3214082048: + case 3213950976: + case 3214213120: + case 3214278656: + case 3214344192: + case 3214475264: + case 3214409728: + case 3214540800: + case 3214671872: + case 3214802944: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SOPK(uint64_t I){ + switch( I & 4286578688 ){ + case 2952790016: + case 2961178624: + case 2986344448: + case 2969567232: + case 2977955840: + case 2994733056: + case 3003121664: + case 3011510272: + case 3019898880: + case 3028287488: + case 3036676096: + case 3045064704: + case 3053453312: + case 3061841920: + case 3070230528: + case 3078619136: + case 3103784960: + case 3095396352: + case 3128950784: + case 3120562176: + case 3087007744: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SOP2(uint64_t I){ + switch( I & 4286578688 ){ + case 2147483648: + case 2155872256: + case 2181038080: + case 2164260864: + case 2172649472: + case 2189426688: + case 2197815296: + case 2206203904: + case 2214592512: + case 2222981120: + case 2231369728: + case 2239758336: + case 2248146944: + case 2256535552: + case 2264924160: + case 2273312768: + case 2399141888: + case 2533359616: + case 2407530496: + case 2541748224: + case 2415919104: + case 2550136832: + case 2298478592: + case 2306867200: + case 2290089984: + case 2315255808: + case 2281701376: + case 2323644416: + case 2332033024: + case 2340421632: + case 2348810240: + case 2357198848: + case 2424307712: + case 2558525440: + case 2432696320: + case 2566914048: + case 2441084928: + case 2575302656: + case 2516582400: + case 2449473536: + case 2583691264: + case 2457862144: + case 2466250752: + case 2474639360: + case 2390753280: + case 2483027968: + case 2524971008: + case 2491416576: + case 2365587456: + case 2499805184: + case 2373976064: + case 2508193792: + case 2382364672: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_SMEM(uint64_t I){ + switch( I & 4294705152 ){ + case 3221225472: + case 3221487616: + case 3222274048: + case 3221749760: + case 3222011904: + case 3222536192: + case 3222798336: + case 3223060480: + case 3223322624: + case 3223584768: + case 3223846912: + case 3224109056: + case 3224371200: + case 3225419776: + case 3225681920: + case 3225944064: + case 3249537024: + case 3229614080: + case 3238002688: + case 3246391296: + case 3254779904: + case 3257925632: + case 3263168512: + case 3229876224: + case 3238264832: + case 3246653440: + case 3255042048: + case 3263430656: + case 3266314240: + case 3230138368: + case 3238526976: + case 3246915584: + case 3255304192: + case 3263692800: + case 3230400512: + case 3238789120: + case 3247177728: + case 3255566336: + case 3263954944: + case 3230662656: + case 3239051264: + case 3247439872: + case 3255828480: + case 3264217088: + case 3226730496: + case 3230924800: + case 3239313408: + case 3247702016: + case 3256090624: + case 3264479232: + case 3226992640: + case 3231186944: + case 3239575552: + case 3247964160: + case 3256352768: + case 3264741376: + case 3227254784: + case 3231449088: + case 3239837696: + case 3248226304: + case 3256614912: + case 3265003520: + case 3227516928: + case 3231711232: + case 3240099840: + case 3248488448: + case 3256877056: + case 3265265664: + case 3227779072: + case 3231973376: + case 3240361984: + case 3248750592: + case 3257139200: + case 3265527808: + case 3249274880: + case 3228041216: + case 3240624128: + case 3249012736: + case 3257401344: + case 3265789952: + case 3257663488: + case 3240886272: + case 3266052096: + case 3241148416: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP1(uint64_t I){ + switch( I & 4261543424 ){ + case 2113929216: + case 2113929728: + case 2113930752: + case 2113931264: + case 2113930240: + case 2113931776: + case 2113932288: + case 2113932800: + case 2113933312: + case 2113934336: + case 2113937408: + case 2113937920: + case 2113941504: + case 2113942016: + case 2113946112: + case 2113950208: + case 2113945600: + case 2113954304: + case 2113958400: + case 2113962496: + case 2113949696: + case 2113953792: + case 2113938432: + case 2113942528: + case 2113946624: + case 2113950720: + case 2113954816: + case 2113958912: + case 2113961984: + case 2113963008: + case 2113967104: + case 2113966080: + case 2113934848: + case 2113938944: + case 2113943040: + case 2113947136: + case 2113951232: + case 2113955328: + case 2113959424: + case 2113963520: + case 2113967616: + case 2113935360: + case 2113939456: + case 2113943552: + case 2113947648: + case 2113951744: + case 2113955840: + case 2113959936: + case 2113964032: + case 2113968128: + case 2113971200: + case 2113935872: + case 2113939968: + case 2113944064: + case 2113948160: + case 2113952256: + case 2113956352: + case 2113960448: + case 2113964544: + case 2113968640: + case 2113936384: + case 2113940480: + case 2113944576: + case 2113948672: + case 2113952768: + case 2113960960: + case 2113965056: + case 2113969152: + case 2113936896: + case 2113940992: + case 2113945088: + case 2113949184: + case 2113953280: + case 2113957376: + case 2113961472: + case 2113965568: + case 2113969664: + case 2113966592: + case 2113970688: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOPC(uint64_t I){ + switch( I & 4294836224 ){ + case 2082471936: + case 2082603008: + case 2082865152: + case 2082734080: + case 2082996224: + case 2083127296: + case 2084569088: + case 2084700160: + case 2084831232: + case 2084962304: + case 2085093376: + case 2085617664: + case 2088239104: + case 2092433408: + case 2088763392: + case 2092957696: + case 2096627712: + case 2113404928: + case 2109341696: + case 2105278464: + case 2109865984: + case 2105802752: + case 2101739520: + case 2110390272: + case 2106327040: + case 2102263808: + case 2110914560: + case 2090074112: + case 2106851328: + case 2086010880: + case 2102788096: + case 2094661632: + case 2111438848: + case 2090598400: + case 2107375616: + case 2086535168: + case 2103312384: + case 2095185920: + case 2111963136: + case 2091122688: + case 2107899904: + case 2087059456: + case 2103836672: + case 2095710208: + case 2112487424: + case 2108424192: + case 2087583744: + case 2104360960: + case 2108948480: + case 2096234496: + case 2113011712: + case 2085224448: + case 2085748736: + case 2088370176: + case 2092564480: + case 2088894464: + case 2093088768: + case 2089418752: + case 2093613056: + case 2089943040: + case 2094137344: + case 2092171264: + case 2104885248: + case 2096758784: + case 2113536000: + case 2109472768: + case 2105409536: + case 2101346304: + case 2109997056: + case 2105933824: + case 2101870592: + case 2110521344: + case 2106458112: + case 2102394880: + case 2094268416: + case 2111045632: + case 2090205184: + case 2106982400: + case 2086141952: + case 2102919168: + case 2094792704: + case 2111569920: + case 2090729472: + case 2107506688: + case 2086666240: + case 2103443456: + case 2095316992: + case 2112094208: + case 2091253760: + case 2108030976: + case 2087190528: + case 2103967744: + case 2095841280: + case 2112618496: + case 2108555264: + case 2087714816: + case 2104492032: + case 2113142784: + case 2085355520: + case 2087976960: + case 2088501248: + case 2092695552: + case 2091646976: + case 2089025536: + case 2093219840: + case 2089549824: + case 2093744128: + case 2085879808: + case 2096365568: + case 2105016320: + case 2109079552: + case 2096889856: + case 2113667072: + case 2109603840: + case 2105540608: + case 2101477376: + case 2110128128: + case 2089287680: + case 2106064896: + case 2102001664: + case 2110652416: + case 2089811968: + case 2106589184: + case 2102525952: + case 2094399488: + case 2111176704: + case 2090336256: + case 2107113472: + case 2086273024: + case 2103050240: + case 2094923776: + case 2111700992: + case 2090860544: + case 2107637760: + case 2086797312: + case 2103574528: + case 2095448064: + case 2112225280: + case 2091384832: + case 2108162048: + case 2087321600: + case 2104098816: + case 2095972352: + case 2112749568: + case 2091909120: + case 2108686336: + case 2087845888: + case 2104623104: + case 2085486592: + case 2088108032: + case 2092302336: + case 2088632320: + case 2092826624: + case 2089156608: + case 2093350912: + case 2091778048: + case 2089680896: + case 2093875200: + case 2096496640: + case 2109210624: + case 2113273856: + case 2105147392: + case 2097020928: + case 2113798144: + case 2109734912: + case 2105671680: + case 2101608448: + case 2104229888: + case 2093481984: + case 2110259200: + case 2106195968: + case 2102132736: + case 2094006272: + case 2110783488: + case 2106720256: + case 2102657024: + case 2094530560: + case 2111307776: + case 2090467328: + case 2107244544: + case 2086404096: + case 2103181312: + case 2092040192: + case 2112880640: + case 2095054848: + case 2111832064: + case 2090991616: + case 2107768832: + case 2086928384: + case 2103705600: + case 2108817408: + case 2095579136: + case 2112356352: + case 2091515904: + case 2108293120: + case 2087452672: + case 2104754176: + case 2096103424: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP2(uint64_t I){ + switch( I & 4261412864 ){ + case 0: + case 33554432: + case 134217728: + case 67108864: + case 100663296: + case 167772160: + case 201326592: + case 234881024: + case 268435456: + case 301989888: + case 335544320: + case 369098752: + case 402653184: + case 436207616: + case 469762048: + case 503316480: + case 1174405120: + case 1577058304: + case 1308622848: + case 1442840576: + case 939524096: + case 1073741824: + case 1342177280: + case 603979776: + case 637534208: + case 671088640: + case 570425344: + case 536870912: + case 704643072: + case 738197504: + case 838860800: + case 872415232: + case 905969664: + case 1711276032: + case 1845493760: + case 1979711488: + case 1476395008: + case 973078528: + case 1107296256: + case 1375731712: + case 1509949440: + case 1610612736: + case 1644167168: + case 1744830464: + case 1778384896: + case 1912602624: + case 1879048192: + case 2013265920: + case 1006632960: + case 1140850688: + case 1275068416: + case 1409286144: + case 1543503872: + case 1677721600: + case 1811939328: + case 1946157056: + case 2046820352: + case 1040187392: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VINTRP(uint64_t I){ + switch( I & 4227858432 ){ + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP3P(uint64_t I){ + switch( I & 4294901760 ){ + case 3548381184: + case 3548446720: + case 3548577792: + case 3548512256: + case 3548643328: + case 3548708864: + case 3548774400: + case 3548839936: + case 3548905472: + case 3548971008: + case 3549036544: + case 3549167616: + case 3549298688: + case 3549560832: + case 3550478336: + case 3549429760: + case 3554213888: + case 3551723520: + case 3549102080: + case 3549233152: + case 3549364224: + case 3550543872: + case 3549495296: + case 3550674944: + case 3550937088: + case 3551068160: + case 3551199232: + case 3551592448: + case 3551657984: + case 3554148352: + case 3550609408: + case 3550871552: + case 3551002624: + case 3551133696: + case 3551526912: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP3(uint64_t I){ + switch( I & 4294901760 ){ + case 3510632448: + case 3510697984: + case 3510829056: + case 3510763520: + case 3510894592: + case 3510960128: + case 3511025664: + case 3511091200: + case 3511156736: + case 3511287808: + case 3511353344: + case 3514826752: + case 3506438144: + case 3523215360: + case 3508535296: + case 3491758080: + case 3505913856: + case 3504668672: + case 3503423488: + case 3496017920: + case 3512795136: + case 3514892288: + case 3506503680: + case 3531669504: + case 3533766656: + case 3500212224: + case 3519086592: + case 3523280896: + case 3508600832: + case 3500933120: + case 3505520640: + case 3519152128: + case 3521249280: + case 3514957824: + case 3506569216: + case 3512860672: + case 3523346432: + case 3508666368: + case 3491889152: + case 3493986304: + case 3496083456: + case 3504275456: + case 3493855232: + case 3503030272: + case 3508731904: + case 3491954688: + case 3494051840: + case 3496148992: + case 3512926208: + case 3515023360: + case 3506634752: + case 3531800576: + case 3500343296: + case 3519217664: + case 3506372608: + case 3495952384: + case 3505127424: + case 3531866112: + case 3500408832: + case 3519283200: + case 3521380352: + case 3515088896: + case 3506700288: + case 3512991744: + case 3523477504: + case 3492020224: + case 3494117376: + case 3503882240: + case 3502637056: + case 3501391872: + case 3521445888: + case 3523543040: + case 3492085760: + case 3494182912: + case 3496280064: + case 3513057280: + case 3515154432: + case 3506765824: + case 3531931648: + case 3500474368: + case 3505979392: + case 3500146688: + case 3504734208: + case 3503489024: + case 3494248448: + case 3496345600: + case 3531997184: + case 3500539904: + case 3519414272: + case 3521511424: + case 3515219968: + case 3513122816: + case 3506831360: + case 3523608576: + case 3502243840: + case 3491823616: + case 3532259328: + case 3500998656: + case 3505586176: + case 3500605440: + case 3519479808: + case 3521576960: + case 3523674112: + case 3508994048: + case 3492216832: + case 3494313984: + case 3496411136: + case 3513188352: + case 3515285504: + case 3495165952: + case 3504340992: + case 3493920768: + case 3519348736: + case 3508928512: + case 3503095808: + case 3515351040: + case 3506962432: + case 3509059584: + case 3492282368: + case 3494379520: + case 3513253888: + case 3496476672: + case 3532128256: + case 3519545344: + case 3500670976: + case 3505192960: + case 3496542208: + case 3513319424: + case 3515416576: + case 3532193792: + case 3519610880: + case 3507027968: + case 3509125120: + case 3492347904: + case 3494445056: + case 3500736512: + case 3503947776: + case 3502702592: + case 3519676416: + case 3521773568: + case 3515482112: + case 3513384960: + case 3507093504: + case 3509190656: + case 3492413440: + case 3494510592: + case 3496607744: + case 3491037184: + case 3501457408: + case 3506044928: + case 3504799744: + case 3509256192: + case 3492478976: + case 3494576128: + case 3496673280: + case 3513450496: + case 3515547648: + case 3507159040: + case 3532324864: + case 3519741952: + case 3521839104: + case 3503554560: + case 3512729600: + case 3502309376: + case 3506896896: + case 3501064192: + case 3532390400: + case 3519807488: + case 3521904640: + case 3511418880: + case 3515613184: + case 3513516032: + case 3507224576: + case 3509321728: + case 3492544512: + case 3494641664: + case 3505651712: + case 3504406528: + case 3503161344: + case 3521970176: + case 3507290112: + case 3509387264: + case 3492610048: + case 3494707200: + case 3496804352: + case 3513581568: + case 3511484416: + case 3515678720: + case 3532455936: + case 3505258496: + case 3494772736: + case 3496869888: + case 3492675584: + case 3519938560: + case 3522035712: + case 3511549952: + case 3515744256: + case 3513647104: + case 3507355648: + case 3509452800: + case 3519021056: + case 3502768128: + case 3532783616: + case 3522363392: + case 3520004096: + case 3522101248: + case 3507421184: + case 3509518336: + case 3492741120: + case 3494838272: + case 3496935424: + case 3513712640: + case 3511615488: + case 3515809792: + case 3501522944: + case 3506110464: + case 3500277760: + case 3504865280: + case 3519873024: + case 3511681024: + case 3507486720: + case 3490709504: + case 3509583872: + case 3492806656: + case 3494903808: + case 3513778176: + case 3497000960: + case 3532652544: + case 3520069632: + case 3503620096: + case 3502374912: + case 3501129728: + case 3497066496: + case 3515940864: + case 3513843712: + case 3511746560: + case 3532718080: + case 3520135168: + case 3494969344: + case 3522232320: + case 3507552256: + case 3490775040: + case 3505717248: + case 3504472064: + case 3503226880: + case 3520200704: + case 3522297856: + case 3511812096: + case 3513909248: + case 3516006400: + case 3507617792: + case 3490840576: + case 3509714944: + case 3492937728: + case 3495034880: + case 3505324032: + case 3509780480: + case 3493003264: + case 3495100416: + case 3497197568: + case 3513974784: + case 3511877632: + case 3532849152: + case 3490906112: + case 3507683328: + case 3520266240: + case 3504078848: + case 3502833664: + case 3532914688: + case 3493068800: + case 3520331776: + case 3511943168: + case 3514040320: + case 3522428928: + case 3497263104: + case 3507748864: + case 3490971648: + case 3509846016: + case 3506176000: + case 3501326336: + case 3531603968: + case 3504930816: + case 3520397312: + case 3495231488: + case 3522494464: + case 3507814400: + case 3509911552: + case 3493134336: + case 3512008704: + case 3514105856: + case 3497328640: + case 3532980224: + case 3503685632: + case 3533701120: + case 3502440448: + case 3501195264: + case 3509977088: + case 3493199872: + case 3495297024: + case 3533045760: + case 3520462848: + case 3512074240: + case 3522560000: + case 3497394176: + case 3507879936: + case 3501588480: + case 3505782784: + case 3504537600: + case 3503292416: + case 3492872192: + case 3533111296: + case 3520528384: + case 3522625536: + case 3510042624: + case 3493265408: + case 3495362560: + case 3512139776: + case 3514236928: + case 3497459712: + case 3501654016: + case 3496214528: + case 3532062720: + case 3500802048: + case 3505389568: + case 3512205312: + case 3522691072: + case 3510108160: + case 3493330944: + case 3495428096: + case 3497525248: + case 3533176832: + case 3520593920: + case 3501719552: + case 3503816704: + case 3504144384: + case 3502899200: + case 3495493632: + case 3512270848: + case 3514368000: + case 3497590784: + case 3533242368: + case 3520659456: + case 3522756608: + case 3510173696: + case 3493396480: + case 3501785088: + case 3506241536: + case 3504996352: + case 3520724992: + case 3514433536: + case 3512336384: + case 3522822144: + case 3510239232: + case 3493462016: + case 3495559168: + case 3497656320: + case 3533307904: + case 3501850624: + case 3503751168: + case 3502505984: + case 3501260800: + case 3510304768: + case 3493527552: + case 3495624704: + case 3512401920: + case 3514499072: + case 3497721856: + case 3520790528: + case 3522887680: + case 3501916160: + case 3504013312: + case 3505848320: + case 3504603136: + case 3503357952: + case 3497787392: + case 3533438976: + case 3520856064: + case 3514564608: + case 3512467456: + case 3522953216: + case 3510370304: + case 3493593088: + case 3495690240: + case 3501981696: + case 3500867584: + case 3505455104: + case 3520921600: + case 3523018752: + case 3510435840: + case 3493658624: + case 3495755776: + case 3512532992: + case 3514630144: + case 3497852928: + case 3533504512: + case 3502047232: + case 3502964736: + case 3497132032: + case 3493724160: + case 3495821312: + case 3497918464: + case 3533570048: + case 3520987136: + case 3514695680: + case 3512598528: + case 3523084288: + case 3502112768: + case 3504209920: + case 3506307072: + case 3531735040: + case 3521314816: + case 3505061888: + case 3509649408: + case 3533635584: + case 3521052672: + case 3523149824: + case 3508469760: + case 3493789696: + case 3495886848: + case 3512664064: + case 3514761216: + case 3497984000: + case 3502178304: + case 3523411968: + case 3502571520: + case 3492151296: + case 3496738816: + case 3532587008: + case 3522166784: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_DS(uint64_t I){ + switch( I & 4261281792 ){ + case 3623878656: + case 3624009728: + case 3624271872: + case 3624140800: + case 3624402944: + case 3624534016: + case 3624665088: + case 3624796160: + case 3624927232: + case 3625058304: + case 3625189376: + case 3625451520: + case 3631742976: + case 3635412992: + case 3628072960: + case 3632267264: + case 3640131584: + case 3644194816: + case 3648782336: + case 3636592640: + case 3637116928: + case 3637641216: + case 3633577984: + case 3629514752: + case 3638165504: + case 3634102272: + case 3630039040: + case 3625975808: + case 3638689792: + case 3634626560: + case 3630563328: + case 3626500096: + case 3635150848: + case 3631087616: + case 3643801600: + case 3625582592: + case 3627679744: + case 3631874048: + case 3631349760: + case 3635544064: + case 3628204032: + case 3632398336: + case 3628728320: + case 3632922624: + case 3629252608: + case 3644325888: + case 3652976640: + case 3636723712: + case 3628597248: + case 3637248000: + case 3629121536: + case 3637772288: + case 3633709056: + case 3629645824: + case 3638296576: + case 3634233344: + case 3630170112: + case 3626106880: + case 3638820864: + case 3634757632: + case 3630694400: + case 3626631168: + case 3639345152: + case 3635281920: + case 3631218688: + case 3643932672: + case 3625713664: + case 3631480832: + case 3627810816: + case 3632005120: + case 3628335104: + case 3632529408: + case 3635675136: + case 3628859392: + case 3633053696: + case 3629383680: + case 3644456960: + case 3640393728: + case 3657170944: + case 3653107712: + case 3636854784: + case 3632791552: + case 3644063744: + case 3637379072: + case 3633315840: + case 3637903360: + case 3633840128: + case 3629776896: + case 3638427648: + case 3634364416: + case 3630301184: + case 3626237952: + case 3647733760: + case 3638951936: + case 3634888704: + case 3630825472: + case 3639476224: + case 3625320448: + case 3625844736: + case 3631611904: + case 3627941888: + case 3632136192: + case 3628466176: + case 3632660480: + case 3628990464: + case 3633184768: + case 3635806208: + case 3635937280: + case 3648651264: + case 3657302016: + case 3636461568: + case 3636985856: + case 3637510144: + case 3633446912: + case 3638034432: + case 3633971200: + case 3629907968: + case 3638558720: + case 3634495488: + case 3630432256: + case 3626369024: + case 3635019776: + case 3630956544: + case 3639607296: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_MUBUF(uint64_t I){ + switch( I & 4261150720 ){ + case 3758096384: + case 3758358528: + case 3759144960: + case 3758620672: + case 3758882816: + case 3759407104: + case 3759669248: + case 3759931392: + case 3760193536: + case 3760455680: + case 3760717824: + case 3760979968: + case 3761242112: + case 3761504256: + case 3761766400: + case 3762028544: + case 3765698560: + case 3765960704: + case 3774349312: + case 3778019328: + case 3778543616: + case 3766222848: + case 3774611456: + case 3778805760: + case 3786407936: + case 3762290688: + case 3766484992: + case 3774873600: + case 3779067904: + case 3783262208: + case 3762552832: + case 3766747136: + case 3775135744: + case 3779330048: + case 3783524352: + case 3762814976: + case 3767009280: + case 3775397888: + case 3783786496: + case 3774087168: + case 3763077120: + case 3767271424: + case 3775660032: + case 3778281472: + case 3784048640: + case 3763339264: + case 3767533568: + case 3775922176: + case 3784310784: + case 3763601408: + case 3767795712: + case 3776184320: + case 3784572928: + case 3763863552: + case 3768057856: + case 3776446464: + case 3784835072: + case 3764125696: + case 3768320000: + case 3776708608: + case 3785097216: + case 3764387840: + case 3768582144: + case 3776970752: + case 3785359360: + case 3777757184: + case 3764649984: + case 3768844288: + case 3777232896: + case 3785621504: + case 3786145792: + case 3764912128: + case 3777495040: + case 3785883648: + case 3765174272: + case 3765436416: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_MTBUF(uint64_t I){ + switch( I & 4228349952 ){ + case 3892314112: + case 3892346880: + case 3892412416: + case 3892445184: + case 3892379648: + case 3892477952: + case 3892510720: + case 3892543488: + case 3892576256: + case 3892609024: + case 3892641792: + case 3892674560: + case 3892707328: + case 3892740096: + case 3892772864: + case 3892805632: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_MIMG(uint64_t I){ + switch( I & 4261150720 ){ + case 4026531840: + case 4026793984: + case 4027580416: + case 4027056128: + case 4027318272: + case 4027842560: + case 4028628992: + case 4028891136: + case 4029153280: + case 4029415424: + case 4030201856: + case 4030726144: + case 4030988288: + case 4031250432: + case 4031512576: + case 4031774720: + case 4034920448: + case 4032036864: + case 4032299008: + case 4032561152: + case 4032823296: + case 4033085440: + case 4033347584: + case 4033609728: + case 4033871872: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_FLAT(uint64_t I){ + switch( I & 4261199872 ){ + case 3695181824: + case 3695443968: + case 3696230400: + case 3695706112: + case 3695968256: + case 3696492544: + case 3696754688: + case 3697016832: + case 3697278976: + case 3697541120: + case 3697803264: + case 3698065408: + case 3698327552: + case 3698589696: + case 3698851840: + case 3699113984: + case 3711696896: + case 3699376128: + case 3707764736: + case 3711959040: + case 3716153344: + case 3699638272: + case 3708026880: + case 3712221184: + case 3716415488: + case 3719036928: + case 3699900416: + case 3708289024: + case 3716677632: + case 3700162560: + case 3708551168: + case 3716939776: + case 3700424704: + case 3708813312: + case 3717201920: + case 3700686848: + case 3709075456: + case 3717464064: + case 3709337600: + case 3717726208: + case 3709599744: + case 3717988352: + case 3719299072: + case 3709861888: + case 3718250496: + case 3710124032: + case 3718512640: + case 3710386176: + case 3718774784: + case 3710648320: + case 3710910464: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_FLAT_GLBL(uint64_t I){ + switch( I & 4261199872 ){ + case 3695214592: + case 3695476736: + case 3696263168: + case 3696001024: + case 3695738880: + case 3696525312: + case 3696787456: + case 3697049600: + case 3697311744: + case 3697573888: + case 3697836032: + case 3710156800: + case 3718545408: + case 3710418944: + case 3718807552: + case 3710681088: + case 3719069696: + case 3710943232: + case 3719331840: + case 3698098176: + case 3698360320: + case 3698622464: + case 3698884608: + case 3699146752: + case 3699408896: + case 3699671040: + case 3699933184: + case 3700457472: + case 3700195328: + case 3711205376: + case 3711467520: + case 3718021120: + case 3711729664: + case 3707797504: + case 3711991808: + case 3716186112: + case 3708059648: + case 3712253952: + case 3716448256: + case 3708321792: + case 3716710400: + case 3709894656: + case 3708583936: + case 3716972544: + case 3718283264: + case 3708846080: + case 3717234688: + case 3700719616: + case 3709108224: + case 3717496832: + case 3709370368: + case 3717758976: + case 3709632512: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_FLAT_SCRATCH(uint64_t I){ + switch( I & 4261199872 ){ + case 3695198208: + case 3695460352: + case 3696246784: + case 3695722496: + case 3695984640: + case 3696508928: + case 3696771072: + case 3697033216: + case 3697295360: + case 3697557504: + case 3697819648: + case 3698081792: + case 3698343936: + case 3698606080: + case 3698868224: + case 3699130368: + case 3699392512: + case 3699654656: + case 3699916800: + case 3700178944: + case 3700441088: + case 3700703232: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP2_LITERAL(uint64_t I){ + switch( I & 4261412864 ){ + case 771751936: + case 805306368: + case 1207959552: + case 1241513984: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP3B(uint64_t I){ + switch( I & 4294901760 ){ + case 3508076544: + case 3508142080: + case 3508338688: + case 3508207616: + case 3508273152: + case 3508404224: + case 3521118208: + case 3521183744: + case 3521642496: + case 3521708032: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_cdna2::IS_ENC_VOP3P_MFMA(uint64_t I){ + switch( I & 4294901760 ){ + case 3552575488: + case 3552641024: + case 3552903168: + case 3552706560: + case 3552837632: + case 3553099776: + case 3553165312: + case 3553230848: + case 3553361920: + case 3553427456: + case 3553624064: + case 3553755136: + case 3553886208: + case 3554934784: + case 3555065856: + case 3555196928: + case 3553689600: + case 3553951744: + case 3554869248: + case 3555000320: + case 3555131392: + case 3555262464: + case 3555393536: + case 3555524608: + case 3555655680: + case 3555459072: + case 3555590144: + return true; + default: + return false; + } +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SOP1(){ + insn_size = 4; + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<8,15>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPC(){ + insn_size = 4; + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPP(){ + insn_size = 4; + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPK(){ + insn_size = 4; + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPKOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SOP2(){ + insn_size = 4; + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + layout.ENCODING = longfield<30,31>(insn_long); + layout.OP = longfield<23,29>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_SMEM(){ + insn_size = 8; + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.IMM = longfield<17,17>(insn_long); + layout.NV = longfield<15,15>(insn_long); + layout.OFFSET = longfield<32,52>(insn_long); + layout.OP = longfield<18,25>(insn_long); + layout.SBASE = (longfield<0,5>(insn_long) << 1 ) | 0 ; + layout.SDATA = longfield<6,12>(insn_long); + layout.SOFFSET = longfield<57,63>(insn_long); + layout.SOFFSET_EN = longfield<14,14>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SMEMOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP1(){ + insn_size = 4; + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<9,16>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOPC(){ + insn_size = 4; + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2(){ + insn_size = 4; + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VINTRP(){ + insn_size = 4; + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + layout.ATTR = longfield<10,15>(insn_long); + layout.ATTRCHAN = longfield<8,9>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.OP = longfield<16,17>(insn_long); + layout.VDST = longfield<18,25>(insn_long); + layout.VSRC = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VINTRPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P(){ + insn_size = 8; + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.NEG_HI = longfield<8,10>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.OP_SEL = longfield<11,13>(insn_long); + layout.OP_SEL_HI = longfield<59,60>(insn_long); + layout.OP_SEL_HI_2 = longfield<14,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3POperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3(){ + insn_size = 8; + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + layout.ABS = longfield<8,10>(insn_long); + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.OP_SEL = longfield<11,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_DS(){ + insn_size = 8; + layout_ENC_DS & layout = insn_layout.ENC_DS; + layout.ACC = longfield<25,25>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA0 = longfield<40,47>(insn_long); + layout.DATA1 = longfield<48,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GDS = longfield<16,16>(insn_long); + layout.OFFSET0 = longfield<0,7>(insn_long); + layout.OFFSET1 = longfield<8,15>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_DS_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_DSOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_MUBUF(){ + insn_size = 8; + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.LDS = longfield<16,16>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SCC = longfield<15,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MUBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_MTBUF(){ + insn_size = 8; + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.DFMT = longfield<19,22>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.NFMT = longfield<23,25>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<15,18>(insn_long); + layout.SCC = longfield<53,53>(insn_long); + layout.SLC = longfield<54,54>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MTBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_MIMG(){ + insn_size = 8; + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + layout.A16 = longfield<15,15>(insn_long); + layout.ACC = longfield<16,16>(insn_long); + layout.D16 = longfield<63,63>(insn_long); + layout.DA = longfield<14,14>(insn_long); + layout.DMASK = longfield<8,11>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<13,13>(insn_long); + layout.LWE = longfield<17,17>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.OPM = longfield<0,0>(insn_long); + layout.SCC = longfield<7,7>(insn_long); + layout.SLC = longfield<25,25>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.SSAMP = (longfield<53,57>(insn_long) << 2 ) | 0 ; + layout.UNORM = longfield<12,12>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MIMGOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT(){ + insn_size = 8; + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLATOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_GLBL(){ + insn_size = 8; + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_GLBLOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_SCRATCH(){ + insn_size = 8; + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_SCRATCHOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2_LITERAL(){ + insn_size = 8; + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2_LITERALOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3B(){ + insn_size = 8; + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.SDST = longfield<8,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3BOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P_MFMA(){ + insn_size = 8; + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + layout.ABID = longfield<11,14>(insn_long); + layout.ACC = longfield<59,60>(insn_long); + layout.ACC_CD = longfield<15,15>(insn_long); + layout.BLGP = longfield<61,63>(insn_long); + layout.CBSZ = longfield<8,10>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3P_MFMAOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_cdna2::mainDecodeOpcode(){ + if(IS_ENC_SOP1(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[longfield<8,15>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP1; + } + else if(IS_ENC_SOPC(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[longfield<16,22>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPC; + } + else if(IS_ENC_SOPP(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[longfield<16,22>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPP; + } + else if(IS_ENC_SOPK(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[longfield<23,27>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPK; + } + else if(IS_ENC_SOP2(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[longfield<23,29>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP2; + } + else if(IS_ENC_SMEM(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[longfield<18,25>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SMEM; + } + else if(IS_ENC_VOP1(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[longfield<9,16>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP1; + } + else if(IS_ENC_VOPC(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[longfield<17,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOPC; + } + else if(IS_ENC_VOP2(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[longfield<25,30>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2; + } + else if(IS_ENC_VINTRP(insn_long)){ + insn_size = 4; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[longfield<16,17>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VINTRP; + } + else if(IS_ENC_VOP3P(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[longfield<16,22>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P; + } + else if(IS_ENC_VOP3(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[longfield<16,25>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3; + } + else if(IS_ENC_DS(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_DS_insn_table[longfield<17,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_DS; + } + else if(IS_ENC_MUBUF(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[longfield<18,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MUBUF; + } + else if(IS_ENC_MTBUF(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[longfield<15,18>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MTBUF; + } + else if(IS_ENC_MIMG(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[longfield<18,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MIMG; + } + else if(IS_ENC_FLAT(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[longfield<18,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT; + } + else if(IS_ENC_FLAT_GLBL(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[longfield<18,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_GLBL; + } + else if(IS_ENC_FLAT_SCRATCH(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[longfield<18,24>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_SCRATCH; + } + else if(IS_ENC_VOP2_LITERAL(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[longfield<25,30>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2_LITERAL; + } + else if(IS_ENC_VOP3B(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[longfield<16,25>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3B; + } + else if(IS_ENC_VOP3P_MFMA(insn_long)){ + insn_size = 8; + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[longfield<16,22>(insn_long)]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P_MFMA; + } +} +void InstructionDecoder_amdgpu_cdna2::mainDecode(){ + if(IS_ENC_SOP1(insn_long)){ + decodeENC_SOP1(); + } + else if(IS_ENC_SOPC(insn_long)){ + decodeENC_SOPC(); + } + else if(IS_ENC_SOPP(insn_long)){ + decodeENC_SOPP(); + } + else if(IS_ENC_SOPK(insn_long)){ + decodeENC_SOPK(); + } + else if(IS_ENC_SOP2(insn_long)){ + decodeENC_SOP2(); + } + else if(IS_ENC_SMEM(insn_long)){ + decodeENC_SMEM(); + } + else if(IS_ENC_VOP1(insn_long)){ + decodeENC_VOP1(); + } + else if(IS_ENC_VOPC(insn_long)){ + decodeENC_VOPC(); + } + else if(IS_ENC_VOP2(insn_long)){ + decodeENC_VOP2(); + } + else if(IS_ENC_VINTRP(insn_long)){ + decodeENC_VINTRP(); + } + else if(IS_ENC_VOP3P(insn_long)){ + decodeENC_VOP3P(); + } + else if(IS_ENC_VOP3(insn_long)){ + decodeENC_VOP3(); + } + else if(IS_ENC_DS(insn_long)){ + decodeENC_DS(); + } + else if(IS_ENC_MUBUF(insn_long)){ + decodeENC_MUBUF(); + } + else if(IS_ENC_MTBUF(insn_long)){ + decodeENC_MTBUF(); + } + else if(IS_ENC_MIMG(insn_long)){ + decodeENC_MIMG(); + } + else if(IS_ENC_FLAT(insn_long)){ + decodeENC_FLAT(); + } + else if(IS_ENC_FLAT_GLBL(insn_long)){ + decodeENC_FLAT_GLBL(); + } + else if(IS_ENC_FLAT_SCRATCH(insn_long)){ + decodeENC_FLAT_SCRATCH(); + } + else if(IS_ENC_VOP2_LITERAL(insn_long)){ + decodeENC_VOP2_LITERAL(); + } + else if(IS_ENC_VOP3B(insn_long)){ + decodeENC_VOP3B(); + } + else if(IS_ENC_VOP3P_MFMA(insn_long)){ + decodeENC_VOP3P_MFMA(); + } +} diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h new file mode 100644 index 0000000000..aad5a985a4 --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h @@ -0,0 +1,378 @@ +static bool IS_ENC_SOP1(uint64_t I); +static bool IS_ENC_SOPC(uint64_t I); +static bool IS_ENC_SOPP(uint64_t I); +static bool IS_ENC_SOPK(uint64_t I); +static bool IS_ENC_SOP2(uint64_t I); +static bool IS_ENC_SMEM(uint64_t I); +static bool IS_ENC_VOP1(uint64_t I); +static bool IS_ENC_VOPC(uint64_t I); +static bool IS_ENC_VOP2(uint64_t I); +static bool IS_ENC_VINTRP(uint64_t I); +static bool IS_ENC_VOP3P(uint64_t I); +static bool IS_ENC_VOP3(uint64_t I); +static bool IS_ENC_DS(uint64_t I); +static bool IS_ENC_MUBUF(uint64_t I); +static bool IS_ENC_MTBUF(uint64_t I); +static bool IS_ENC_MIMG(uint64_t I); +static bool IS_ENC_FLAT(uint64_t I); +static bool IS_ENC_FLAT_GLBL(uint64_t I); +static bool IS_ENC_FLAT_SCRATCH(uint64_t I); +static bool IS_ENC_VOP2_LITERAL(uint64_t I); +static bool IS_ENC_VOP3B(uint64_t I); +static bool IS_ENC_VOP3P_MFMA(uint64_t I); +enum InstructionFamily{ + ENC_SOP1 = -1, + ENC_SOPC = 0, + ENC_SOPP = 1, + ENC_SOPK = 2, + ENC_SOP2 = 3, + ENC_SMEM = 4, + ENC_VOP1 = 5, + ENC_VOPC = 6, + ENC_VOP2 = 7, + ENC_VINTRP = 8, + ENC_VOP3P = 9, + ENC_VOP3 = 10, + ENC_DS = 11, + ENC_MUBUF = 12, + ENC_MTBUF = 13, + ENC_MIMG = 14, + ENC_FLAT = 16, + ENC_FLAT_GLBL = 17, + ENC_FLAT_SCRATCH = 18, + ENC_VOP2_LITERAL = 19, + ENC_VOP3B = 20, + ENC_VOP3P_MFMA = 21, +}; +InstructionFamily instr_family; +typedef void (InstructionDecoder_amdgpu_cdna2::*func_ptr)(void); +func_ptr decode_lookup_table [22] = { + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOP1), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOPC), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOPP), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOPK), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOP2), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_SMEM), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP1), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOPC), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VINTRP), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_DS), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_MUBUF), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_MTBUF), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_MIMG), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_GLBL), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_SCRATCH), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2_LITERAL), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3B), + (&InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P_MFMA), +}; +typedef struct layout_ENC_SOP1{ + uint16_t ENCODING : 9 ; + uint8_t OP : 8 ; + uint8_t SDST : 7 ; + uint8_t SSRC0 : 8 ; +}layout_ENC_SOP1; +typedef struct layout_ENC_SOPC{ + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint8_t SSRC0 : 8 ; + uint8_t SSRC1 : 8 ; +}layout_ENC_SOPC; +typedef struct layout_ENC_SOPP{ + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint16_t SIMM16 : 16 ; +}layout_ENC_SOPP; +typedef struct layout_ENC_SOPK{ + uint8_t ENCODING : 4 ; + uint8_t OP : 5 ; + uint8_t SDST : 7 ; + uint16_t SIMM16 : 16 ; +}layout_ENC_SOPK; +typedef struct layout_ENC_SOP2{ + uint8_t ENCODING : 2 ; + uint8_t OP : 7 ; + uint8_t SDST : 7 ; + uint8_t SSRC0 : 8 ; + uint8_t SSRC1 : 8 ; +}layout_ENC_SOP2; +typedef struct layout_ENC_SMEM{ + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IMM : 1 ; + uint8_t NV : 1 ; + uint32_t OFFSET : 21 ; + uint8_t OP : 8 ; + uint8_t SBASE : 6 ; + uint8_t SDATA : 7 ; + uint8_t SOFFSET : 7 ; + uint8_t SOFFSET_EN : 1 ; +}layout_ENC_SMEM; +typedef struct layout_ENC_VOP1{ + uint8_t ENCODING : 7 ; + uint8_t OP : 8 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP1; +typedef struct layout_ENC_VOPC{ + uint8_t ENCODING : 7 ; + uint8_t OP : 8 ; + uint16_t SRC0 : 9 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOPC; +typedef struct layout_ENC_VOP2{ + uint8_t ENCODING : 1 ; + uint8_t OP : 6 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOP2; +typedef struct layout_ENC_VINTRP{ + uint8_t ATTR : 6 ; + uint8_t ATTRCHAN : 2 ; + uint8_t ENCODING : 6 ; + uint8_t OP : 2 ; + uint8_t VDST : 8 ; + uint8_t VSRC : 8 ; +}layout_ENC_VINTRP; +typedef struct layout_ENC_VOP3P{ + uint8_t CLAMP : 1 ; + uint16_t ENCODING : 9 ; + uint8_t NEG : 3 ; + uint8_t NEG_HI : 3 ; + uint8_t OP : 7 ; + uint8_t OP_SEL : 3 ; + uint8_t OP_SEL_HI : 2 ; + uint8_t OP_SEL_HI_2 : 1 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3P; +typedef struct layout_ENC_VOP3{ + uint8_t ABS : 3 ; + uint8_t CLAMP : 1 ; + uint8_t ENCODING : 6 ; + uint8_t NEG : 3 ; + uint8_t OMOD : 2 ; + uint16_t OP : 10 ; + uint8_t OP_SEL : 4 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3; +typedef struct layout_ENC_DS{ + uint8_t ACC : 1 ; + uint8_t ADDR : 8 ; + uint8_t DATA0 : 8 ; + uint8_t DATA1 : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GDS : 1 ; + uint8_t OFFSET0 : 8 ; + uint8_t OFFSET1 : 8 ; + uint8_t OP : 8 ; + uint8_t VDST : 8 ; +}layout_ENC_DS; +typedef struct layout_ENC_MUBUF{ + uint8_t ACC : 1 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IDXEN : 1 ; + uint8_t LDS : 1 ; + uint8_t OFFEN : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 7 ; + uint8_t SCC : 1 ; + uint8_t SLC : 1 ; + uint8_t SOFFSET : 8 ; + uint8_t SRSRC : 5 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MUBUF; +typedef struct layout_ENC_MTBUF{ + uint8_t ACC : 1 ; + uint8_t DFMT : 4 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IDXEN : 1 ; + uint8_t NFMT : 3 ; + uint8_t OFFEN : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 4 ; + uint8_t SCC : 1 ; + uint8_t SLC : 1 ; + uint8_t SOFFSET : 8 ; + uint8_t SRSRC : 5 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MTBUF; +typedef struct layout_ENC_MIMG{ + uint8_t A16 : 1 ; + uint8_t ACC : 1 ; + uint8_t D16 : 1 ; + uint8_t DA : 1 ; + uint8_t DMASK : 4 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LWE : 1 ; + uint8_t OP : 7 ; + uint8_t OPM : 1 ; + uint8_t SCC : 1 ; + uint8_t SLC : 1 ; + uint8_t SRSRC : 5 ; + uint8_t SSAMP : 5 ; + uint8_t UNORM : 1 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MIMG; +typedef struct layout_ENC_FLAT{ + uint8_t ACC : 1 ; + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SCC : 1 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT; +typedef struct layout_ENC_FLAT_GLBL{ + uint8_t ACC : 1 ; + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint16_t OFFSET : 13 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SCC : 1 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT_GLBL; +typedef struct layout_ENC_FLAT_SCRATCH{ + uint8_t ACC : 1 ; + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint16_t OFFSET : 13 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SCC : 1 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT_SCRATCH; +typedef struct layout_ENC_VOP2_LITERAL{ + uint8_t ENCODING : 1 ; + uint8_t OP : 6 ; + uint32_t SIMM32 : 32 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOP2_LITERAL; +typedef struct layout_ENC_VOP3B{ + uint8_t CLAMP : 1 ; + uint8_t ENCODING : 6 ; + uint8_t NEG : 3 ; + uint8_t OMOD : 2 ; + uint16_t OP : 10 ; + uint8_t SDST : 7 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3B; +typedef struct layout_ENC_VOP3P_MFMA{ + uint8_t ABID : 4 ; + uint8_t ACC : 2 ; + uint8_t ACC_CD : 1 ; + uint8_t BLGP : 3 ; + uint8_t CBSZ : 3 ; + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3P_MFMA; +union insn_layout{ + layout_ENC_SOP1 ENC_SOP1; + layout_ENC_SOPC ENC_SOPC; + layout_ENC_SOPP ENC_SOPP; + layout_ENC_SOPK ENC_SOPK; + layout_ENC_SOP2 ENC_SOP2; + layout_ENC_SMEM ENC_SMEM; + layout_ENC_VOP1 ENC_VOP1; + layout_ENC_VOPC ENC_VOPC; + layout_ENC_VOP2 ENC_VOP2; + layout_ENC_VINTRP ENC_VINTRP; + layout_ENC_VOP3P ENC_VOP3P; + layout_ENC_VOP3 ENC_VOP3; + layout_ENC_DS ENC_DS; + layout_ENC_MUBUF ENC_MUBUF; + layout_ENC_MTBUF ENC_MTBUF; + layout_ENC_MIMG ENC_MIMG; + layout_ENC_FLAT ENC_FLAT; + layout_ENC_FLAT_GLBL ENC_FLAT_GLBL; + layout_ENC_FLAT_SCRATCH ENC_FLAT_SCRATCH; + layout_ENC_VOP2_LITERAL ENC_VOP2_LITERAL; + layout_ENC_VOP3B ENC_VOP3B; + layout_ENC_VOP3P_MFMA ENC_VOP3P_MFMA; +}insn_layout; +void decodeENC_SOP1(); +void finalizeENC_SOP1Operands(); +void decodeENC_SOPC(); +void finalizeENC_SOPCOperands(); +void decodeENC_SOPP(); +void finalizeENC_SOPPOperands(); +void decodeENC_SOPK(); +void finalizeENC_SOPKOperands(); +void decodeENC_SOP2(); +void finalizeENC_SOP2Operands(); +void decodeENC_SMEM(); +void finalizeENC_SMEMOperands(); +void decodeENC_VOP1(); +void finalizeENC_VOP1Operands(); +void decodeENC_VOPC(); +void finalizeENC_VOPCOperands(); +void decodeENC_VOP2(); +void finalizeENC_VOP2Operands(); +void decodeENC_VINTRP(); +void finalizeENC_VINTRPOperands(); +void decodeENC_VOP3P(); +void finalizeENC_VOP3POperands(); +void decodeENC_VOP3(); +void finalizeENC_VOP3Operands(); +void decodeENC_DS(); +void finalizeENC_DSOperands(); +void decodeENC_MUBUF(); +void finalizeENC_MUBUFOperands(); +void decodeENC_MTBUF(); +void finalizeENC_MTBUFOperands(); +void decodeENC_MIMG(); +void finalizeENC_MIMGOperands(); +void decodeENC_FLAT(); +void finalizeENC_FLATOperands(); +void decodeENC_FLAT_GLBL(); +void finalizeENC_FLAT_GLBLOperands(); +void decodeENC_FLAT_SCRATCH(); +void finalizeENC_FLAT_SCRATCHOperands(); +void decodeENC_VOP2_LITERAL(); +void finalizeENC_VOP2_LITERALOperands(); +void decodeENC_VOP3B(); +void finalizeENC_VOP3BOperands(); +void decodeENC_VOP3P_MFMA(); +void finalizeENC_VOP3P_MFMAOperands(); diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h new file mode 100644 index 0000000000..35ddd6bcdc --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h @@ -0,0 +1,30 @@ +struct amdgpu_cdna2_insn_entry { + entryID op; + const char *mnemonic; + std::size_t operandCnt; + const operandFactory *operands; + static const amdgpu_cdna2_insn_table main_insn_table ; + static const operandFactory operandTable[] ; + static const amdgpu_cdna2_insn_table ENC_DS_insn_table ; + static const amdgpu_cdna2_insn_table ENC_FLAT_insn_table ; + static const amdgpu_cdna2_insn_table ENC_FLAT_GLBL_insn_table ; + static const amdgpu_cdna2_insn_table ENC_FLAT_SCRATCH_insn_table ; + static const amdgpu_cdna2_insn_table ENC_MIMG_insn_table ; + static const amdgpu_cdna2_insn_table ENC_MTBUF_insn_table ; + static const amdgpu_cdna2_insn_table ENC_MUBUF_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SMEM_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SOP1_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SOP2_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SOPC_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SOPK_insn_table ; + static const amdgpu_cdna2_insn_table ENC_SOPP_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP1_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP3_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP2_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP2_LITERAL_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP3B_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP3P_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOP3P_MFMA_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VOPC_insn_table ; + static const amdgpu_cdna2_insn_table ENC_VINTRP_insn_table ; +}; diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h new file mode 100644 index 0000000000..90eb1cb315 --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h @@ -0,0 +1,1135 @@ +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_AND, +amdgpu_cdna2_op_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_DEC, +amdgpu_cdna2_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_INC, +amdgpu_cdna2_op_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_MAX_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_MIN_F64, +amdgpu_cdna2_op_BUFFER_ATOMIC_OR, +amdgpu_cdna2_op_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN, +amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SUB, +amdgpu_cdna2_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP, +amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN, +amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_BUFFER_ATOMIC_XOR, +amdgpu_cdna2_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna2_op_BUFFER_INVL2, +amdgpu_cdna2_op_BUFFER_LOAD_DWORD, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX2, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX3, +amdgpu_cdna2_op_BUFFER_LOAD_DWORDX4, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_X, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16, +amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_SSHORT, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_LOAD_USHORT, +amdgpu_cdna2_op_BUFFER_STORE_BYTE, +amdgpu_cdna2_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_BUFFER_STORE_DWORD, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX2, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX3, +amdgpu_cdna2_op_BUFFER_STORE_DWORDX4, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_X, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XY, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna2_op_BUFFER_STORE_LDS_DWORD, +amdgpu_cdna2_op_BUFFER_STORE_SHORT, +amdgpu_cdna2_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_BUFFER_WBINVL1, +amdgpu_cdna2_op_BUFFER_WBINVL1_VOL, +amdgpu_cdna2_op_BUFFER_WBL2, +amdgpu_cdna2_op_DS_ADD_F32, +amdgpu_cdna2_op_DS_ADD_F64, +amdgpu_cdna2_op_DS_ADD_RTN_F32, +amdgpu_cdna2_op_DS_ADD_RTN_F64, +amdgpu_cdna2_op_DS_ADD_RTN_U32, +amdgpu_cdna2_op_DS_ADD_RTN_U64, +amdgpu_cdna2_op_DS_ADD_U32, +amdgpu_cdna2_op_DS_ADD_U64, +amdgpu_cdna2_op_DS_AND_B32, +amdgpu_cdna2_op_DS_AND_B64, +amdgpu_cdna2_op_DS_AND_RTN_B32, +amdgpu_cdna2_op_DS_AND_RTN_B64, +amdgpu_cdna2_op_DS_APPEND, +amdgpu_cdna2_op_DS_BPERMUTE_B32, +amdgpu_cdna2_op_DS_CMPST_B32, +amdgpu_cdna2_op_DS_CMPST_B64, +amdgpu_cdna2_op_DS_CMPST_F32, +amdgpu_cdna2_op_DS_CMPST_F64, +amdgpu_cdna2_op_DS_CMPST_RTN_B32, +amdgpu_cdna2_op_DS_CMPST_RTN_B64, +amdgpu_cdna2_op_DS_CMPST_RTN_F32, +amdgpu_cdna2_op_DS_CMPST_RTN_F64, +amdgpu_cdna2_op_DS_CONDXCHG32_RTN_B64, +amdgpu_cdna2_op_DS_CONSUME, +amdgpu_cdna2_op_DS_DEC_RTN_U32, +amdgpu_cdna2_op_DS_DEC_RTN_U64, +amdgpu_cdna2_op_DS_DEC_U32, +amdgpu_cdna2_op_DS_DEC_U64, +amdgpu_cdna2_op_DS_GWS_BARRIER, +amdgpu_cdna2_op_DS_GWS_INIT, +amdgpu_cdna2_op_DS_GWS_SEMA_BR, +amdgpu_cdna2_op_DS_GWS_SEMA_P, +amdgpu_cdna2_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_cdna2_op_DS_GWS_SEMA_V, +amdgpu_cdna2_op_DS_INC_RTN_U32, +amdgpu_cdna2_op_DS_INC_RTN_U64, +amdgpu_cdna2_op_DS_INC_U32, +amdgpu_cdna2_op_DS_INC_U64, +amdgpu_cdna2_op_DS_MAX_F32, +amdgpu_cdna2_op_DS_MAX_F64, +amdgpu_cdna2_op_DS_MAX_I32, +amdgpu_cdna2_op_DS_MAX_I64, +amdgpu_cdna2_op_DS_MAX_RTN_F32, +amdgpu_cdna2_op_DS_MAX_RTN_F64, +amdgpu_cdna2_op_DS_MAX_RTN_I32, +amdgpu_cdna2_op_DS_MAX_RTN_I64, +amdgpu_cdna2_op_DS_MAX_RTN_U32, +amdgpu_cdna2_op_DS_MAX_RTN_U64, +amdgpu_cdna2_op_DS_MAX_U32, +amdgpu_cdna2_op_DS_MAX_U64, +amdgpu_cdna2_op_DS_MIN_F32, +amdgpu_cdna2_op_DS_MIN_F64, +amdgpu_cdna2_op_DS_MIN_I32, +amdgpu_cdna2_op_DS_MIN_I64, +amdgpu_cdna2_op_DS_MIN_RTN_F32, +amdgpu_cdna2_op_DS_MIN_RTN_F64, +amdgpu_cdna2_op_DS_MIN_RTN_I32, +amdgpu_cdna2_op_DS_MIN_RTN_I64, +amdgpu_cdna2_op_DS_MIN_RTN_U32, +amdgpu_cdna2_op_DS_MIN_RTN_U64, +amdgpu_cdna2_op_DS_MIN_U32, +amdgpu_cdna2_op_DS_MIN_U64, +amdgpu_cdna2_op_DS_MSKOR_B32, +amdgpu_cdna2_op_DS_MSKOR_B64, +amdgpu_cdna2_op_DS_MSKOR_RTN_B32, +amdgpu_cdna2_op_DS_MSKOR_RTN_B64, +amdgpu_cdna2_op_DS_NOP, +amdgpu_cdna2_op_DS_OR_B32, +amdgpu_cdna2_op_DS_OR_B64, +amdgpu_cdna2_op_DS_OR_RTN_B32, +amdgpu_cdna2_op_DS_OR_RTN_B64, +amdgpu_cdna2_op_DS_PERMUTE_B32, +amdgpu_cdna2_op_DS_READ2ST64_B32, +amdgpu_cdna2_op_DS_READ2ST64_B64, +amdgpu_cdna2_op_DS_READ2_B32, +amdgpu_cdna2_op_DS_READ2_B64, +amdgpu_cdna2_op_DS_READ_ADDTID_B32, +amdgpu_cdna2_op_DS_READ_B128, +amdgpu_cdna2_op_DS_READ_B32, +amdgpu_cdna2_op_DS_READ_B64, +amdgpu_cdna2_op_DS_READ_B96, +amdgpu_cdna2_op_DS_READ_I16, +amdgpu_cdna2_op_DS_READ_I8, +amdgpu_cdna2_op_DS_READ_I8_D16, +amdgpu_cdna2_op_DS_READ_I8_D16_HI, +amdgpu_cdna2_op_DS_READ_U16, +amdgpu_cdna2_op_DS_READ_U16_D16, +amdgpu_cdna2_op_DS_READ_U16_D16_HI, +amdgpu_cdna2_op_DS_READ_U8, +amdgpu_cdna2_op_DS_READ_U8_D16, +amdgpu_cdna2_op_DS_READ_U8_D16_HI, +amdgpu_cdna2_op_DS_RSUB_RTN_U32, +amdgpu_cdna2_op_DS_RSUB_RTN_U64, +amdgpu_cdna2_op_DS_RSUB_U32, +amdgpu_cdna2_op_DS_RSUB_U64, +amdgpu_cdna2_op_DS_SUB_RTN_U32, +amdgpu_cdna2_op_DS_SUB_RTN_U64, +amdgpu_cdna2_op_DS_SUB_U32, +amdgpu_cdna2_op_DS_SUB_U64, +amdgpu_cdna2_op_DS_SWIZZLE_B32, +amdgpu_cdna2_op_DS_WRAP_RTN_B32, +amdgpu_cdna2_op_DS_WRITE2ST64_B32, +amdgpu_cdna2_op_DS_WRITE2ST64_B64, +amdgpu_cdna2_op_DS_WRITE2_B32, +amdgpu_cdna2_op_DS_WRITE2_B64, +amdgpu_cdna2_op_DS_WRITE_ADDTID_B32, +amdgpu_cdna2_op_DS_WRITE_B128, +amdgpu_cdna2_op_DS_WRITE_B16, +amdgpu_cdna2_op_DS_WRITE_B16_D16_HI, +amdgpu_cdna2_op_DS_WRITE_B32, +amdgpu_cdna2_op_DS_WRITE_B64, +amdgpu_cdna2_op_DS_WRITE_B8, +amdgpu_cdna2_op_DS_WRITE_B8_D16_HI, +amdgpu_cdna2_op_DS_WRITE_B96, +amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_cdna2_op_DS_WRXCHG2_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG2_RTN_B64, +amdgpu_cdna2_op_DS_WRXCHG_RTN_B32, +amdgpu_cdna2_op_DS_WRXCHG_RTN_B64, +amdgpu_cdna2_op_DS_XOR_B32, +amdgpu_cdna2_op_DS_XOR_B64, +amdgpu_cdna2_op_DS_XOR_RTN_B32, +amdgpu_cdna2_op_DS_XOR_RTN_B64, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_ADD_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_AND, +amdgpu_cdna2_op_FLAT_ATOMIC_AND_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_DEC, +amdgpu_cdna2_op_FLAT_ATOMIC_DEC_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_INC, +amdgpu_cdna2_op_FLAT_ATOMIC_INC_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_MAX_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_MIN_F64, +amdgpu_cdna2_op_FLAT_ATOMIC_OR, +amdgpu_cdna2_op_FLAT_ATOMIC_OR_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SMAX, +amdgpu_cdna2_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SMIN, +amdgpu_cdna2_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SUB, +amdgpu_cdna2_op_FLAT_ATOMIC_SUB_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_SWAP, +amdgpu_cdna2_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_UMAX, +amdgpu_cdna2_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_UMIN, +amdgpu_cdna2_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_FLAT_ATOMIC_XOR, +amdgpu_cdna2_op_FLAT_ATOMIC_XOR_X2, +amdgpu_cdna2_op_FLAT_LOAD_DWORD, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX2, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX3, +amdgpu_cdna2_op_FLAT_LOAD_DWORDX4, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16, +amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16, +amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_SSHORT, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16, +amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_FLAT_LOAD_USHORT, +amdgpu_cdna2_op_FLAT_STORE_BYTE, +amdgpu_cdna2_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_FLAT_STORE_DWORD, +amdgpu_cdna2_op_FLAT_STORE_DWORDX2, +amdgpu_cdna2_op_FLAT_STORE_DWORDX3, +amdgpu_cdna2_op_FLAT_STORE_DWORDX4, +amdgpu_cdna2_op_FLAT_STORE_SHORT, +amdgpu_cdna2_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_AND, +amdgpu_cdna2_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC, +amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_INC, +amdgpu_cdna2_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_MAX_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_MIN_F64, +amdgpu_cdna2_op_GLOBAL_ATOMIC_OR, +amdgpu_cdna2_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP, +amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN, +amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR, +amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORD, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX2, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX3, +amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX4, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_SSHORT, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_LOAD_USHORT, +amdgpu_cdna2_op_GLOBAL_STORE_BYTE, +amdgpu_cdna2_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_GLOBAL_STORE_DWORD, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX2, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX3, +amdgpu_cdna2_op_GLOBAL_STORE_DWORDX4, +amdgpu_cdna2_op_GLOBAL_STORE_SHORT, +amdgpu_cdna2_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_IMAGE_ATOMIC_ADD, +amdgpu_cdna2_op_IMAGE_ATOMIC_AND, +amdgpu_cdna2_op_IMAGE_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_IMAGE_ATOMIC_DEC, +amdgpu_cdna2_op_IMAGE_ATOMIC_INC, +amdgpu_cdna2_op_IMAGE_ATOMIC_OR, +amdgpu_cdna2_op_IMAGE_ATOMIC_SMAX, +amdgpu_cdna2_op_IMAGE_ATOMIC_SMIN, +amdgpu_cdna2_op_IMAGE_ATOMIC_SUB, +amdgpu_cdna2_op_IMAGE_ATOMIC_SWAP, +amdgpu_cdna2_op_IMAGE_ATOMIC_UMAX, +amdgpu_cdna2_op_IMAGE_ATOMIC_UMIN, +amdgpu_cdna2_op_IMAGE_ATOMIC_XOR, +amdgpu_cdna2_op_IMAGE_GET_RESINFO, +amdgpu_cdna2_op_IMAGE_LOAD, +amdgpu_cdna2_op_IMAGE_LOAD_MIP, +amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK, +amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK_SGN, +amdgpu_cdna2_op_IMAGE_LOAD_PCK, +amdgpu_cdna2_op_IMAGE_LOAD_PCK_SGN, +amdgpu_cdna2_op_IMAGE_SAMPLE, +amdgpu_cdna2_op_IMAGE_STORE, +amdgpu_cdna2_op_IMAGE_STORE_MIP, +amdgpu_cdna2_op_IMAGE_STORE_MIP_PCK, +amdgpu_cdna2_op_IMAGE_STORE_PCK, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORD, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX3, +amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_SSHORT, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_LOAD_USHORT, +amdgpu_cdna2_op_SCRATCH_STORE_BYTE, +amdgpu_cdna2_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_cdna2_op_SCRATCH_STORE_DWORD, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX2, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX3, +amdgpu_cdna2_op_SCRATCH_STORE_DWORDX4, +amdgpu_cdna2_op_SCRATCH_STORE_SHORT, +amdgpu_cdna2_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_cdna2_op_S_ABSDIFF_I32, +amdgpu_cdna2_op_S_ABS_I32, +amdgpu_cdna2_op_S_ADDC_U32, +amdgpu_cdna2_op_S_ADDK_I32, +amdgpu_cdna2_op_S_ADD_I32, +amdgpu_cdna2_op_S_ADD_U32, +amdgpu_cdna2_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ANDN1_WREXEC_B64, +amdgpu_cdna2_op_S_ANDN2_B32, +amdgpu_cdna2_op_S_ANDN2_B64, +amdgpu_cdna2_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ANDN2_WREXEC_B64, +amdgpu_cdna2_op_S_AND_B32, +amdgpu_cdna2_op_S_AND_B64, +amdgpu_cdna2_op_S_AND_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ASHR_I32, +amdgpu_cdna2_op_S_ASHR_I64, +amdgpu_cdna2_op_S_ATC_PROBE, +amdgpu_cdna2_op_S_ATC_PROBE_BUFFER, +amdgpu_cdna2_op_S_ATOMIC_ADD, +amdgpu_cdna2_op_S_ATOMIC_ADD_X2, +amdgpu_cdna2_op_S_ATOMIC_AND, +amdgpu_cdna2_op_S_ATOMIC_AND_X2, +amdgpu_cdna2_op_S_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_S_ATOMIC_DEC, +amdgpu_cdna2_op_S_ATOMIC_DEC_X2, +amdgpu_cdna2_op_S_ATOMIC_INC, +amdgpu_cdna2_op_S_ATOMIC_INC_X2, +amdgpu_cdna2_op_S_ATOMIC_OR, +amdgpu_cdna2_op_S_ATOMIC_OR_X2, +amdgpu_cdna2_op_S_ATOMIC_SMAX, +amdgpu_cdna2_op_S_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_S_ATOMIC_SMIN, +amdgpu_cdna2_op_S_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_S_ATOMIC_SUB, +amdgpu_cdna2_op_S_ATOMIC_SUB_X2, +amdgpu_cdna2_op_S_ATOMIC_SWAP, +amdgpu_cdna2_op_S_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_S_ATOMIC_UMAX, +amdgpu_cdna2_op_S_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_S_ATOMIC_UMIN, +amdgpu_cdna2_op_S_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_S_ATOMIC_XOR, +amdgpu_cdna2_op_S_ATOMIC_XOR_X2, +amdgpu_cdna2_op_S_BARRIER, +amdgpu_cdna2_op_S_BCNT0_I32_B32, +amdgpu_cdna2_op_S_BCNT0_I32_B64, +amdgpu_cdna2_op_S_BCNT1_I32_B32, +amdgpu_cdna2_op_S_BCNT1_I32_B64, +amdgpu_cdna2_op_S_BFE_I32, +amdgpu_cdna2_op_S_BFE_I64, +amdgpu_cdna2_op_S_BFE_U32, +amdgpu_cdna2_op_S_BFE_U64, +amdgpu_cdna2_op_S_BFM_B32, +amdgpu_cdna2_op_S_BFM_B64, +amdgpu_cdna2_op_S_BITCMP0_B32, +amdgpu_cdna2_op_S_BITCMP0_B64, +amdgpu_cdna2_op_S_BITCMP1_B32, +amdgpu_cdna2_op_S_BITCMP1_B64, +amdgpu_cdna2_op_S_BITREPLICATE_B64_B32, +amdgpu_cdna2_op_S_BITSET0_B32, +amdgpu_cdna2_op_S_BITSET0_B64, +amdgpu_cdna2_op_S_BITSET1_B32, +amdgpu_cdna2_op_S_BITSET1_B64, +amdgpu_cdna2_op_S_BRANCH, +amdgpu_cdna2_op_S_BREV_B32, +amdgpu_cdna2_op_S_BREV_B64, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR, +amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORD, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORD, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX2, +amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX4, +amdgpu_cdna2_op_S_CALL_B64, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_cdna2_op_S_CBRANCH_CDBGUSER, +amdgpu_cdna2_op_S_CBRANCH_EXECNZ, +amdgpu_cdna2_op_S_CBRANCH_EXECZ, +amdgpu_cdna2_op_S_CBRANCH_G_FORK, +amdgpu_cdna2_op_S_CBRANCH_I_FORK, +amdgpu_cdna2_op_S_CBRANCH_JOIN, +amdgpu_cdna2_op_S_CBRANCH_SCC0, +amdgpu_cdna2_op_S_CBRANCH_SCC1, +amdgpu_cdna2_op_S_CBRANCH_VCCNZ, +amdgpu_cdna2_op_S_CBRANCH_VCCZ, +amdgpu_cdna2_op_S_CMOVK_I32, +amdgpu_cdna2_op_S_CMOV_B32, +amdgpu_cdna2_op_S_CMOV_B64, +amdgpu_cdna2_op_S_CMPK_EQ_I32, +amdgpu_cdna2_op_S_CMPK_EQ_U32, +amdgpu_cdna2_op_S_CMPK_GE_I32, +amdgpu_cdna2_op_S_CMPK_GE_U32, +amdgpu_cdna2_op_S_CMPK_GT_I32, +amdgpu_cdna2_op_S_CMPK_GT_U32, +amdgpu_cdna2_op_S_CMPK_LE_I32, +amdgpu_cdna2_op_S_CMPK_LE_U32, +amdgpu_cdna2_op_S_CMPK_LG_I32, +amdgpu_cdna2_op_S_CMPK_LG_U32, +amdgpu_cdna2_op_S_CMPK_LT_I32, +amdgpu_cdna2_op_S_CMPK_LT_U32, +amdgpu_cdna2_op_S_CMP_EQ_I32, +amdgpu_cdna2_op_S_CMP_EQ_U32, +amdgpu_cdna2_op_S_CMP_EQ_U64, +amdgpu_cdna2_op_S_CMP_GE_I32, +amdgpu_cdna2_op_S_CMP_GE_U32, +amdgpu_cdna2_op_S_CMP_GT_I32, +amdgpu_cdna2_op_S_CMP_GT_U32, +amdgpu_cdna2_op_S_CMP_LE_I32, +amdgpu_cdna2_op_S_CMP_LE_U32, +amdgpu_cdna2_op_S_CMP_LG_I32, +amdgpu_cdna2_op_S_CMP_LG_U32, +amdgpu_cdna2_op_S_CMP_LG_U64, +amdgpu_cdna2_op_S_CMP_LT_I32, +amdgpu_cdna2_op_S_CMP_LT_U32, +amdgpu_cdna2_op_S_CSELECT_B32, +amdgpu_cdna2_op_S_CSELECT_B64, +amdgpu_cdna2_op_S_DCACHE_DISCARD, +amdgpu_cdna2_op_S_DCACHE_DISCARD_X2, +amdgpu_cdna2_op_S_DCACHE_INV, +amdgpu_cdna2_op_S_DCACHE_INV_VOL, +amdgpu_cdna2_op_S_DCACHE_WB, +amdgpu_cdna2_op_S_DCACHE_WB_VOL, +amdgpu_cdna2_op_S_DECPERFLEVEL, +amdgpu_cdna2_op_S_ENDPGM, +amdgpu_cdna2_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_cdna2_op_S_ENDPGM_SAVED, +amdgpu_cdna2_op_S_FF0_I32_B32, +amdgpu_cdna2_op_S_FF0_I32_B64, +amdgpu_cdna2_op_S_FF1_I32_B32, +amdgpu_cdna2_op_S_FF1_I32_B64, +amdgpu_cdna2_op_S_FLBIT_I32, +amdgpu_cdna2_op_S_FLBIT_I32_B32, +amdgpu_cdna2_op_S_FLBIT_I32_B64, +amdgpu_cdna2_op_S_FLBIT_I32_I64, +amdgpu_cdna2_op_S_GETPC_B64, +amdgpu_cdna2_op_S_GETREG_B32, +amdgpu_cdna2_op_S_ICACHE_INV, +amdgpu_cdna2_op_S_INCPERFLEVEL, +amdgpu_cdna2_op_S_LOAD_DWORD, +amdgpu_cdna2_op_S_LOAD_DWORDX16, +amdgpu_cdna2_op_S_LOAD_DWORDX2, +amdgpu_cdna2_op_S_LOAD_DWORDX4, +amdgpu_cdna2_op_S_LOAD_DWORDX8, +amdgpu_cdna2_op_S_LSHL1_ADD_U32, +amdgpu_cdna2_op_S_LSHL2_ADD_U32, +amdgpu_cdna2_op_S_LSHL3_ADD_U32, +amdgpu_cdna2_op_S_LSHL4_ADD_U32, +amdgpu_cdna2_op_S_LSHL_B32, +amdgpu_cdna2_op_S_LSHL_B64, +amdgpu_cdna2_op_S_LSHR_B32, +amdgpu_cdna2_op_S_LSHR_B64, +amdgpu_cdna2_op_S_MAX_I32, +amdgpu_cdna2_op_S_MAX_U32, +amdgpu_cdna2_op_S_MEMREALTIME, +amdgpu_cdna2_op_S_MEMTIME, +amdgpu_cdna2_op_S_MIN_I32, +amdgpu_cdna2_op_S_MIN_U32, +amdgpu_cdna2_op_S_MOVK_I32, +amdgpu_cdna2_op_S_MOVRELD_B32, +amdgpu_cdna2_op_S_MOVRELD_B64, +amdgpu_cdna2_op_S_MOVRELS_B32, +amdgpu_cdna2_op_S_MOVRELS_B64, +amdgpu_cdna2_op_S_MOV_B32, +amdgpu_cdna2_op_S_MOV_B64, +amdgpu_cdna2_op_S_MULK_I32, +amdgpu_cdna2_op_S_MUL_HI_I32, +amdgpu_cdna2_op_S_MUL_HI_U32, +amdgpu_cdna2_op_S_MUL_I32, +amdgpu_cdna2_op_S_NAND_B32, +amdgpu_cdna2_op_S_NAND_B64, +amdgpu_cdna2_op_S_NAND_SAVEEXEC_B64, +amdgpu_cdna2_op_S_NOP, +amdgpu_cdna2_op_S_NOR_B32, +amdgpu_cdna2_op_S_NOR_B64, +amdgpu_cdna2_op_S_NOR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_NOT_B32, +amdgpu_cdna2_op_S_NOT_B64, +amdgpu_cdna2_op_S_ORN1_SAVEEXEC_B64, +amdgpu_cdna2_op_S_ORN2_B32, +amdgpu_cdna2_op_S_ORN2_B64, +amdgpu_cdna2_op_S_ORN2_SAVEEXEC_B64, +amdgpu_cdna2_op_S_OR_B32, +amdgpu_cdna2_op_S_OR_B64, +amdgpu_cdna2_op_S_OR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_PACK_HH_B32_B16, +amdgpu_cdna2_op_S_PACK_LH_B32_B16, +amdgpu_cdna2_op_S_PACK_LL_B32_B16, +amdgpu_cdna2_op_S_QUADMASK_B32, +amdgpu_cdna2_op_S_QUADMASK_B64, +amdgpu_cdna2_op_S_RFE_B64, +amdgpu_cdna2_op_S_RFE_RESTORE_B64, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORD, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORD, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_cdna2_op_S_SENDMSG, +amdgpu_cdna2_op_S_SENDMSGHALT, +amdgpu_cdna2_op_S_SETHALT, +amdgpu_cdna2_op_S_SETKILL, +amdgpu_cdna2_op_S_SETPC_B64, +amdgpu_cdna2_op_S_SETPRIO, +amdgpu_cdna2_op_S_SETREG_B32, +amdgpu_cdna2_op_S_SETREG_IMM32_B32, +amdgpu_cdna2_op_S_SETVSKIP, +amdgpu_cdna2_op_S_SET_GPR_IDX_IDX, +amdgpu_cdna2_op_S_SET_GPR_IDX_MODE, +amdgpu_cdna2_op_S_SET_GPR_IDX_OFF, +amdgpu_cdna2_op_S_SET_GPR_IDX_ON, +amdgpu_cdna2_op_S_SEXT_I32_I16, +amdgpu_cdna2_op_S_SEXT_I32_I8, +amdgpu_cdna2_op_S_SLEEP, +amdgpu_cdna2_op_S_STORE_DWORD, +amdgpu_cdna2_op_S_STORE_DWORDX2, +amdgpu_cdna2_op_S_STORE_DWORDX4, +amdgpu_cdna2_op_S_SUBB_U32, +amdgpu_cdna2_op_S_SUB_I32, +amdgpu_cdna2_op_S_SUB_U32, +amdgpu_cdna2_op_S_SWAPPC_B64, +amdgpu_cdna2_op_S_TRAP, +amdgpu_cdna2_op_S_TTRACEDATA, +amdgpu_cdna2_op_S_WAITCNT, +amdgpu_cdna2_op_S_WAKEUP, +amdgpu_cdna2_op_S_WQM_B32, +amdgpu_cdna2_op_S_WQM_B64, +amdgpu_cdna2_op_S_XNOR_B32, +amdgpu_cdna2_op_S_XNOR_B64, +amdgpu_cdna2_op_S_XNOR_SAVEEXEC_B64, +amdgpu_cdna2_op_S_XOR_B32, +amdgpu_cdna2_op_S_XOR_B64, +amdgpu_cdna2_op_S_XOR_SAVEEXEC_B64, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_X, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_cdna2_op_V_ACCVGPR_MOV_B32, +amdgpu_cdna2_op_V_ACCVGPR_READ, +amdgpu_cdna2_op_V_ACCVGPR_WRITE, +amdgpu_cdna2_op_V_ADD3_U32, +amdgpu_cdna2_op_V_ADDC_CO_U32, +amdgpu_cdna2_op_V_ADD_CO_U32, +amdgpu_cdna2_op_V_ADD_F16, +amdgpu_cdna2_op_V_ADD_F32, +amdgpu_cdna2_op_V_ADD_F64, +amdgpu_cdna2_op_V_ADD_I16, +amdgpu_cdna2_op_V_ADD_I32, +amdgpu_cdna2_op_V_ADD_LSHL_U32, +amdgpu_cdna2_op_V_ADD_U16, +amdgpu_cdna2_op_V_ADD_U32, +amdgpu_cdna2_op_V_ALIGNBIT_B32, +amdgpu_cdna2_op_V_ALIGNBYTE_B32, +amdgpu_cdna2_op_V_AND_B32, +amdgpu_cdna2_op_V_AND_OR_B32, +amdgpu_cdna2_op_V_ASHRREV_I16, +amdgpu_cdna2_op_V_ASHRREV_I32, +amdgpu_cdna2_op_V_ASHRREV_I64, +amdgpu_cdna2_op_V_BCNT_U32_B32, +amdgpu_cdna2_op_V_BFE_I32, +amdgpu_cdna2_op_V_BFE_U32, +amdgpu_cdna2_op_V_BFI_B32, +amdgpu_cdna2_op_V_BFM_B32, +amdgpu_cdna2_op_V_BFREV_B32, +amdgpu_cdna2_op_V_CEIL_F16, +amdgpu_cdna2_op_V_CEIL_F32, +amdgpu_cdna2_op_V_CEIL_F64, +amdgpu_cdna2_op_V_CLREXCP, +amdgpu_cdna2_op_V_CMPX_CLASS_F16, +amdgpu_cdna2_op_V_CMPX_CLASS_F32, +amdgpu_cdna2_op_V_CMPX_CLASS_F64, +amdgpu_cdna2_op_V_CMPX_EQ_F16, +amdgpu_cdna2_op_V_CMPX_EQ_F32, +amdgpu_cdna2_op_V_CMPX_EQ_F64, +amdgpu_cdna2_op_V_CMPX_EQ_I16, +amdgpu_cdna2_op_V_CMPX_EQ_I32, +amdgpu_cdna2_op_V_CMPX_EQ_I64, +amdgpu_cdna2_op_V_CMPX_EQ_U16, +amdgpu_cdna2_op_V_CMPX_EQ_U32, +amdgpu_cdna2_op_V_CMPX_EQ_U64, +amdgpu_cdna2_op_V_CMPX_F_F16, +amdgpu_cdna2_op_V_CMPX_F_F32, +amdgpu_cdna2_op_V_CMPX_F_F64, +amdgpu_cdna2_op_V_CMPX_F_I16, +amdgpu_cdna2_op_V_CMPX_F_I32, +amdgpu_cdna2_op_V_CMPX_F_I64, +amdgpu_cdna2_op_V_CMPX_F_U16, +amdgpu_cdna2_op_V_CMPX_F_U32, +amdgpu_cdna2_op_V_CMPX_F_U64, +amdgpu_cdna2_op_V_CMPX_GE_F16, +amdgpu_cdna2_op_V_CMPX_GE_F32, +amdgpu_cdna2_op_V_CMPX_GE_F64, +amdgpu_cdna2_op_V_CMPX_GE_I16, +amdgpu_cdna2_op_V_CMPX_GE_I32, +amdgpu_cdna2_op_V_CMPX_GE_I64, +amdgpu_cdna2_op_V_CMPX_GE_U16, +amdgpu_cdna2_op_V_CMPX_GE_U32, +amdgpu_cdna2_op_V_CMPX_GE_U64, +amdgpu_cdna2_op_V_CMPX_GT_F16, +amdgpu_cdna2_op_V_CMPX_GT_F32, +amdgpu_cdna2_op_V_CMPX_GT_F64, +amdgpu_cdna2_op_V_CMPX_GT_I16, +amdgpu_cdna2_op_V_CMPX_GT_I32, +amdgpu_cdna2_op_V_CMPX_GT_I64, +amdgpu_cdna2_op_V_CMPX_GT_U16, +amdgpu_cdna2_op_V_CMPX_GT_U32, +amdgpu_cdna2_op_V_CMPX_GT_U64, +amdgpu_cdna2_op_V_CMPX_LE_F16, +amdgpu_cdna2_op_V_CMPX_LE_F32, +amdgpu_cdna2_op_V_CMPX_LE_F64, +amdgpu_cdna2_op_V_CMPX_LE_I16, +amdgpu_cdna2_op_V_CMPX_LE_I32, +amdgpu_cdna2_op_V_CMPX_LE_I64, +amdgpu_cdna2_op_V_CMPX_LE_U16, +amdgpu_cdna2_op_V_CMPX_LE_U32, +amdgpu_cdna2_op_V_CMPX_LE_U64, +amdgpu_cdna2_op_V_CMPX_LG_F16, +amdgpu_cdna2_op_V_CMPX_LG_F32, +amdgpu_cdna2_op_V_CMPX_LG_F64, +amdgpu_cdna2_op_V_CMPX_LT_F16, +amdgpu_cdna2_op_V_CMPX_LT_F32, +amdgpu_cdna2_op_V_CMPX_LT_F64, +amdgpu_cdna2_op_V_CMPX_LT_I16, +amdgpu_cdna2_op_V_CMPX_LT_I32, +amdgpu_cdna2_op_V_CMPX_LT_I64, +amdgpu_cdna2_op_V_CMPX_LT_U16, +amdgpu_cdna2_op_V_CMPX_LT_U32, +amdgpu_cdna2_op_V_CMPX_LT_U64, +amdgpu_cdna2_op_V_CMPX_NEQ_F16, +amdgpu_cdna2_op_V_CMPX_NEQ_F32, +amdgpu_cdna2_op_V_CMPX_NEQ_F64, +amdgpu_cdna2_op_V_CMPX_NE_I16, +amdgpu_cdna2_op_V_CMPX_NE_I32, +amdgpu_cdna2_op_V_CMPX_NE_I64, +amdgpu_cdna2_op_V_CMPX_NE_U16, +amdgpu_cdna2_op_V_CMPX_NE_U32, +amdgpu_cdna2_op_V_CMPX_NE_U64, +amdgpu_cdna2_op_V_CMPX_NGE_F16, +amdgpu_cdna2_op_V_CMPX_NGE_F32, +amdgpu_cdna2_op_V_CMPX_NGE_F64, +amdgpu_cdna2_op_V_CMPX_NGT_F16, +amdgpu_cdna2_op_V_CMPX_NGT_F32, +amdgpu_cdna2_op_V_CMPX_NGT_F64, +amdgpu_cdna2_op_V_CMPX_NLE_F16, +amdgpu_cdna2_op_V_CMPX_NLE_F32, +amdgpu_cdna2_op_V_CMPX_NLE_F64, +amdgpu_cdna2_op_V_CMPX_NLG_F16, +amdgpu_cdna2_op_V_CMPX_NLG_F32, +amdgpu_cdna2_op_V_CMPX_NLG_F64, +amdgpu_cdna2_op_V_CMPX_NLT_F16, +amdgpu_cdna2_op_V_CMPX_NLT_F32, +amdgpu_cdna2_op_V_CMPX_NLT_F64, +amdgpu_cdna2_op_V_CMPX_O_F16, +amdgpu_cdna2_op_V_CMPX_O_F32, +amdgpu_cdna2_op_V_CMPX_O_F64, +amdgpu_cdna2_op_V_CMPX_TRU_F16, +amdgpu_cdna2_op_V_CMPX_TRU_F32, +amdgpu_cdna2_op_V_CMPX_TRU_F64, +amdgpu_cdna2_op_V_CMPX_T_I16, +amdgpu_cdna2_op_V_CMPX_T_I32, +amdgpu_cdna2_op_V_CMPX_T_I64, +amdgpu_cdna2_op_V_CMPX_T_U16, +amdgpu_cdna2_op_V_CMPX_T_U32, +amdgpu_cdna2_op_V_CMPX_T_U64, +amdgpu_cdna2_op_V_CMPX_U_F16, +amdgpu_cdna2_op_V_CMPX_U_F32, +amdgpu_cdna2_op_V_CMPX_U_F64, +amdgpu_cdna2_op_V_CMP_CLASS_F16, +amdgpu_cdna2_op_V_CMP_CLASS_F32, +amdgpu_cdna2_op_V_CMP_CLASS_F64, +amdgpu_cdna2_op_V_CMP_EQ_F16, +amdgpu_cdna2_op_V_CMP_EQ_F32, +amdgpu_cdna2_op_V_CMP_EQ_F64, +amdgpu_cdna2_op_V_CMP_EQ_I16, +amdgpu_cdna2_op_V_CMP_EQ_I32, +amdgpu_cdna2_op_V_CMP_EQ_I64, +amdgpu_cdna2_op_V_CMP_EQ_U16, +amdgpu_cdna2_op_V_CMP_EQ_U32, +amdgpu_cdna2_op_V_CMP_EQ_U64, +amdgpu_cdna2_op_V_CMP_F_F16, +amdgpu_cdna2_op_V_CMP_F_F32, +amdgpu_cdna2_op_V_CMP_F_F64, +amdgpu_cdna2_op_V_CMP_F_I16, +amdgpu_cdna2_op_V_CMP_F_I32, +amdgpu_cdna2_op_V_CMP_F_I64, +amdgpu_cdna2_op_V_CMP_F_U16, +amdgpu_cdna2_op_V_CMP_F_U32, +amdgpu_cdna2_op_V_CMP_F_U64, +amdgpu_cdna2_op_V_CMP_GE_F16, +amdgpu_cdna2_op_V_CMP_GE_F32, +amdgpu_cdna2_op_V_CMP_GE_F64, +amdgpu_cdna2_op_V_CMP_GE_I16, +amdgpu_cdna2_op_V_CMP_GE_I32, +amdgpu_cdna2_op_V_CMP_GE_I64, +amdgpu_cdna2_op_V_CMP_GE_U16, +amdgpu_cdna2_op_V_CMP_GE_U32, +amdgpu_cdna2_op_V_CMP_GE_U64, +amdgpu_cdna2_op_V_CMP_GT_F16, +amdgpu_cdna2_op_V_CMP_GT_F32, +amdgpu_cdna2_op_V_CMP_GT_F64, +amdgpu_cdna2_op_V_CMP_GT_I16, +amdgpu_cdna2_op_V_CMP_GT_I32, +amdgpu_cdna2_op_V_CMP_GT_I64, +amdgpu_cdna2_op_V_CMP_GT_U16, +amdgpu_cdna2_op_V_CMP_GT_U32, +amdgpu_cdna2_op_V_CMP_GT_U64, +amdgpu_cdna2_op_V_CMP_LE_F16, +amdgpu_cdna2_op_V_CMP_LE_F32, +amdgpu_cdna2_op_V_CMP_LE_F64, +amdgpu_cdna2_op_V_CMP_LE_I16, +amdgpu_cdna2_op_V_CMP_LE_I32, +amdgpu_cdna2_op_V_CMP_LE_I64, +amdgpu_cdna2_op_V_CMP_LE_U16, +amdgpu_cdna2_op_V_CMP_LE_U32, +amdgpu_cdna2_op_V_CMP_LE_U64, +amdgpu_cdna2_op_V_CMP_LG_F16, +amdgpu_cdna2_op_V_CMP_LG_F32, +amdgpu_cdna2_op_V_CMP_LG_F64, +amdgpu_cdna2_op_V_CMP_LT_F16, +amdgpu_cdna2_op_V_CMP_LT_F32, +amdgpu_cdna2_op_V_CMP_LT_F64, +amdgpu_cdna2_op_V_CMP_LT_I16, +amdgpu_cdna2_op_V_CMP_LT_I32, +amdgpu_cdna2_op_V_CMP_LT_I64, +amdgpu_cdna2_op_V_CMP_LT_U16, +amdgpu_cdna2_op_V_CMP_LT_U32, +amdgpu_cdna2_op_V_CMP_LT_U64, +amdgpu_cdna2_op_V_CMP_NEQ_F16, +amdgpu_cdna2_op_V_CMP_NEQ_F32, +amdgpu_cdna2_op_V_CMP_NEQ_F64, +amdgpu_cdna2_op_V_CMP_NE_I16, +amdgpu_cdna2_op_V_CMP_NE_I32, +amdgpu_cdna2_op_V_CMP_NE_I64, +amdgpu_cdna2_op_V_CMP_NE_U16, +amdgpu_cdna2_op_V_CMP_NE_U32, +amdgpu_cdna2_op_V_CMP_NE_U64, +amdgpu_cdna2_op_V_CMP_NGE_F16, +amdgpu_cdna2_op_V_CMP_NGE_F32, +amdgpu_cdna2_op_V_CMP_NGE_F64, +amdgpu_cdna2_op_V_CMP_NGT_F16, +amdgpu_cdna2_op_V_CMP_NGT_F32, +amdgpu_cdna2_op_V_CMP_NGT_F64, +amdgpu_cdna2_op_V_CMP_NLE_F16, +amdgpu_cdna2_op_V_CMP_NLE_F32, +amdgpu_cdna2_op_V_CMP_NLE_F64, +amdgpu_cdna2_op_V_CMP_NLG_F16, +amdgpu_cdna2_op_V_CMP_NLG_F32, +amdgpu_cdna2_op_V_CMP_NLG_F64, +amdgpu_cdna2_op_V_CMP_NLT_F16, +amdgpu_cdna2_op_V_CMP_NLT_F32, +amdgpu_cdna2_op_V_CMP_NLT_F64, +amdgpu_cdna2_op_V_CMP_O_F16, +amdgpu_cdna2_op_V_CMP_O_F32, +amdgpu_cdna2_op_V_CMP_O_F64, +amdgpu_cdna2_op_V_CMP_TRU_F16, +amdgpu_cdna2_op_V_CMP_TRU_F32, +amdgpu_cdna2_op_V_CMP_TRU_F64, +amdgpu_cdna2_op_V_CMP_T_I16, +amdgpu_cdna2_op_V_CMP_T_I32, +amdgpu_cdna2_op_V_CMP_T_I64, +amdgpu_cdna2_op_V_CMP_T_U16, +amdgpu_cdna2_op_V_CMP_T_U32, +amdgpu_cdna2_op_V_CMP_T_U64, +amdgpu_cdna2_op_V_CMP_U_F16, +amdgpu_cdna2_op_V_CMP_U_F32, +amdgpu_cdna2_op_V_CMP_U_F64, +amdgpu_cdna2_op_V_CNDMASK_B32, +amdgpu_cdna2_op_V_COS_F16, +amdgpu_cdna2_op_V_COS_F32, +amdgpu_cdna2_op_V_CUBEID_F32, +amdgpu_cdna2_op_V_CUBEMA_F32, +amdgpu_cdna2_op_V_CUBESC_F32, +amdgpu_cdna2_op_V_CUBETC_F32, +amdgpu_cdna2_op_V_CVT_F16_F32, +amdgpu_cdna2_op_V_CVT_F16_I16, +amdgpu_cdna2_op_V_CVT_F16_U16, +amdgpu_cdna2_op_V_CVT_F32_F16, +amdgpu_cdna2_op_V_CVT_F32_F64, +amdgpu_cdna2_op_V_CVT_F32_I32, +amdgpu_cdna2_op_V_CVT_F32_U32, +amdgpu_cdna2_op_V_CVT_F32_UBYTE0, +amdgpu_cdna2_op_V_CVT_F32_UBYTE1, +amdgpu_cdna2_op_V_CVT_F32_UBYTE2, +amdgpu_cdna2_op_V_CVT_F32_UBYTE3, +amdgpu_cdna2_op_V_CVT_F64_F32, +amdgpu_cdna2_op_V_CVT_F64_I32, +amdgpu_cdna2_op_V_CVT_F64_U32, +amdgpu_cdna2_op_V_CVT_FLR_I32_F32, +amdgpu_cdna2_op_V_CVT_I16_F16, +amdgpu_cdna2_op_V_CVT_I32_F32, +amdgpu_cdna2_op_V_CVT_I32_F64, +amdgpu_cdna2_op_V_CVT_NORM_I16_F16, +amdgpu_cdna2_op_V_CVT_NORM_U16_F16, +amdgpu_cdna2_op_V_CVT_OFF_F32_I4, +amdgpu_cdna2_op_V_CVT_PKACCUM_U8_F32, +amdgpu_cdna2_op_V_CVT_PKNORM_I16_F16, +amdgpu_cdna2_op_V_CVT_PKNORM_I16_F32, +amdgpu_cdna2_op_V_CVT_PKNORM_U16_F16, +amdgpu_cdna2_op_V_CVT_PKNORM_U16_F32, +amdgpu_cdna2_op_V_CVT_PKRTZ_F16_F32, +amdgpu_cdna2_op_V_CVT_PK_I16_I32, +amdgpu_cdna2_op_V_CVT_PK_U16_U32, +amdgpu_cdna2_op_V_CVT_PK_U8_F32, +amdgpu_cdna2_op_V_CVT_RPI_I32_F32, +amdgpu_cdna2_op_V_CVT_U16_F16, +amdgpu_cdna2_op_V_CVT_U32_F32, +amdgpu_cdna2_op_V_CVT_U32_F64, +amdgpu_cdna2_op_V_DIV_FIXUP_F16, +amdgpu_cdna2_op_V_DIV_FIXUP_F32, +amdgpu_cdna2_op_V_DIV_FIXUP_F64, +amdgpu_cdna2_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_cdna2_op_V_DIV_FMAS_F32, +amdgpu_cdna2_op_V_DIV_FMAS_F64, +amdgpu_cdna2_op_V_DIV_SCALE_F32, +amdgpu_cdna2_op_V_DIV_SCALE_F64, +amdgpu_cdna2_op_V_DOT2C_F32_F16, +amdgpu_cdna2_op_V_DOT2C_I32_I16, +amdgpu_cdna2_op_V_DOT2_F32_F16, +amdgpu_cdna2_op_V_DOT2_I32_I16, +amdgpu_cdna2_op_V_DOT2_U32_U16, +amdgpu_cdna2_op_V_DOT4C_I32_I8, +amdgpu_cdna2_op_V_DOT4_I32_I8, +amdgpu_cdna2_op_V_DOT4_U32_U8, +amdgpu_cdna2_op_V_DOT8C_I32_I4, +amdgpu_cdna2_op_V_DOT8_I32_I4, +amdgpu_cdna2_op_V_DOT8_U32_U4, +amdgpu_cdna2_op_V_EXP_F16, +amdgpu_cdna2_op_V_EXP_F32, +amdgpu_cdna2_op_V_EXP_LEGACY_F32, +amdgpu_cdna2_op_V_FFBH_I32, +amdgpu_cdna2_op_V_FFBH_U32, +amdgpu_cdna2_op_V_FFBL_B32, +amdgpu_cdna2_op_V_FLOOR_F16, +amdgpu_cdna2_op_V_FLOOR_F32, +amdgpu_cdna2_op_V_FLOOR_F64, +amdgpu_cdna2_op_V_FMAC_F32, +amdgpu_cdna2_op_V_FMAC_F64, +amdgpu_cdna2_op_V_FMA_F16, +amdgpu_cdna2_op_V_FMA_F32, +amdgpu_cdna2_op_V_FMA_F64, +amdgpu_cdna2_op_V_FMA_LEGACY_F16, +amdgpu_cdna2_op_V_FRACT_F16, +amdgpu_cdna2_op_V_FRACT_F32, +amdgpu_cdna2_op_V_FRACT_F64, +amdgpu_cdna2_op_V_FREXP_EXP_I16_F16, +amdgpu_cdna2_op_V_FREXP_EXP_I32_F32, +amdgpu_cdna2_op_V_FREXP_EXP_I32_F64, +amdgpu_cdna2_op_V_FREXP_MANT_F16, +amdgpu_cdna2_op_V_FREXP_MANT_F32, +amdgpu_cdna2_op_V_FREXP_MANT_F64, +amdgpu_cdna2_op_V_LDEXP_F16, +amdgpu_cdna2_op_V_LDEXP_F32, +amdgpu_cdna2_op_V_LDEXP_F64, +amdgpu_cdna2_op_V_LERP_U8, +amdgpu_cdna2_op_V_LOG_F16, +amdgpu_cdna2_op_V_LOG_F32, +amdgpu_cdna2_op_V_LOG_LEGACY_F32, +amdgpu_cdna2_op_V_LSHLREV_B16, +amdgpu_cdna2_op_V_LSHLREV_B32, +amdgpu_cdna2_op_V_LSHLREV_B64, +amdgpu_cdna2_op_V_LSHL_ADD_U32, +amdgpu_cdna2_op_V_LSHL_OR_B32, +amdgpu_cdna2_op_V_LSHRREV_B16, +amdgpu_cdna2_op_V_LSHRREV_B32, +amdgpu_cdna2_op_V_LSHRREV_B64, +amdgpu_cdna2_op_V_MAC_F16, +amdgpu_cdna2_op_V_MAC_F32, +amdgpu_cdna2_op_V_MADAK_F16, +amdgpu_cdna2_op_V_MADAK_F32, +amdgpu_cdna2_op_V_MADMK_F16, +amdgpu_cdna2_op_V_MADMK_F32, +amdgpu_cdna2_op_V_MAD_F16, +amdgpu_cdna2_op_V_MAD_F32, +amdgpu_cdna2_op_V_MAD_I16, +amdgpu_cdna2_op_V_MAD_I32_I16, +amdgpu_cdna2_op_V_MAD_I32_I24, +amdgpu_cdna2_op_V_MAD_I64_I32, +amdgpu_cdna2_op_V_MAD_LEGACY_F16, +amdgpu_cdna2_op_V_MAD_LEGACY_F32, +amdgpu_cdna2_op_V_MAD_LEGACY_I16, +amdgpu_cdna2_op_V_MAD_LEGACY_U16, +amdgpu_cdna2_op_V_MAD_MIXHI_F16, +amdgpu_cdna2_op_V_MAD_MIXLO_F16, +amdgpu_cdna2_op_V_MAD_MIX_F32, +amdgpu_cdna2_op_V_MAD_U16, +amdgpu_cdna2_op_V_MAD_U32_U16, +amdgpu_cdna2_op_V_MAD_U32_U24, +amdgpu_cdna2_op_V_MAD_U64_U32, +amdgpu_cdna2_op_V_MAX3_F16, +amdgpu_cdna2_op_V_MAX3_F32, +amdgpu_cdna2_op_V_MAX3_I16, +amdgpu_cdna2_op_V_MAX3_I32, +amdgpu_cdna2_op_V_MAX3_U16, +amdgpu_cdna2_op_V_MAX3_U32, +amdgpu_cdna2_op_V_MAX_F16, +amdgpu_cdna2_op_V_MAX_F32, +amdgpu_cdna2_op_V_MAX_F64, +amdgpu_cdna2_op_V_MAX_I16, +amdgpu_cdna2_op_V_MAX_I32, +amdgpu_cdna2_op_V_MAX_U16, +amdgpu_cdna2_op_V_MAX_U32, +amdgpu_cdna2_op_V_MBCNT_HI_U32_B32, +amdgpu_cdna2_op_V_MBCNT_LO_U32_B32, +amdgpu_cdna2_op_V_MED3_F16, +amdgpu_cdna2_op_V_MED3_F32, +amdgpu_cdna2_op_V_MED3_I16, +amdgpu_cdna2_op_V_MED3_I32, +amdgpu_cdna2_op_V_MED3_U16, +amdgpu_cdna2_op_V_MED3_U32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X16BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_16X16X16F16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X1F32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4F16, +amdgpu_cdna2_op_V_MFMA_F32_16X16X4F32, +amdgpu_cdna2_op_V_MFMA_F32_16X16X8BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X1F32, +amdgpu_cdna2_op_V_MFMA_F32_32X32X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X2F32, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_32X32X4F16, +amdgpu_cdna2_op_V_MFMA_F32_32X32X8BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_32X32X8F16, +amdgpu_cdna2_op_V_MFMA_F32_4X4X1F32, +amdgpu_cdna2_op_V_MFMA_F32_4X4X2BF16, +amdgpu_cdna2_op_V_MFMA_F32_4X4X4BF16_1K, +amdgpu_cdna2_op_V_MFMA_F32_4X4X4F16, +amdgpu_cdna2_op_V_MFMA_F64_16X16X4F64, +amdgpu_cdna2_op_V_MFMA_F64_4X4X4F64, +amdgpu_cdna2_op_V_MFMA_I32_16X16X16I8, +amdgpu_cdna2_op_V_MFMA_I32_16X16X4I8, +amdgpu_cdna2_op_V_MFMA_I32_32X32X4I8, +amdgpu_cdna2_op_V_MFMA_I32_32X32X8I8, +amdgpu_cdna2_op_V_MFMA_I32_4X4X4I8, +amdgpu_cdna2_op_V_MIN3_F16, +amdgpu_cdna2_op_V_MIN3_F32, +amdgpu_cdna2_op_V_MIN3_I16, +amdgpu_cdna2_op_V_MIN3_I32, +amdgpu_cdna2_op_V_MIN3_U16, +amdgpu_cdna2_op_V_MIN3_U32, +amdgpu_cdna2_op_V_MIN_F16, +amdgpu_cdna2_op_V_MIN_F32, +amdgpu_cdna2_op_V_MIN_F64, +amdgpu_cdna2_op_V_MIN_I16, +amdgpu_cdna2_op_V_MIN_I32, +amdgpu_cdna2_op_V_MIN_U16, +amdgpu_cdna2_op_V_MIN_U32, +amdgpu_cdna2_op_V_MOV_B32, +amdgpu_cdna2_op_V_MQSAD_PK_U16_U8, +amdgpu_cdna2_op_V_MQSAD_U32_U8, +amdgpu_cdna2_op_V_MSAD_U8, +amdgpu_cdna2_op_V_MUL_F16, +amdgpu_cdna2_op_V_MUL_F32, +amdgpu_cdna2_op_V_MUL_F64, +amdgpu_cdna2_op_V_MUL_HI_I32, +amdgpu_cdna2_op_V_MUL_HI_I32_I24, +amdgpu_cdna2_op_V_MUL_HI_U32, +amdgpu_cdna2_op_V_MUL_HI_U32_U24, +amdgpu_cdna2_op_V_MUL_I32_I24, +amdgpu_cdna2_op_V_MUL_LEGACY_F32, +amdgpu_cdna2_op_V_MUL_LO_U16, +amdgpu_cdna2_op_V_MUL_LO_U32, +amdgpu_cdna2_op_V_MUL_U32_U24, +amdgpu_cdna2_op_V_NOP, +amdgpu_cdna2_op_V_NOT_B32, +amdgpu_cdna2_op_V_OR3_B32, +amdgpu_cdna2_op_V_OR_B32, +amdgpu_cdna2_op_V_PACK_B32_F16, +amdgpu_cdna2_op_V_PERM_B32, +amdgpu_cdna2_op_V_PK_ADD_F16, +amdgpu_cdna2_op_V_PK_ADD_F32, +amdgpu_cdna2_op_V_PK_ADD_I16, +amdgpu_cdna2_op_V_PK_ADD_U16, +amdgpu_cdna2_op_V_PK_ASHRREV_I16, +amdgpu_cdna2_op_V_PK_FMAC_F16, +amdgpu_cdna2_op_V_PK_FMA_F16, +amdgpu_cdna2_op_V_PK_FMA_F32, +amdgpu_cdna2_op_V_PK_LSHLREV_B16, +amdgpu_cdna2_op_V_PK_LSHRREV_B16, +amdgpu_cdna2_op_V_PK_MAD_I16, +amdgpu_cdna2_op_V_PK_MAD_U16, +amdgpu_cdna2_op_V_PK_MAX_F16, +amdgpu_cdna2_op_V_PK_MAX_I16, +amdgpu_cdna2_op_V_PK_MAX_U16, +amdgpu_cdna2_op_V_PK_MIN_F16, +amdgpu_cdna2_op_V_PK_MIN_I16, +amdgpu_cdna2_op_V_PK_MIN_U16, +amdgpu_cdna2_op_V_PK_MOV_B32, +amdgpu_cdna2_op_V_PK_MUL_F16, +amdgpu_cdna2_op_V_PK_MUL_F32, +amdgpu_cdna2_op_V_PK_MUL_LO_U16, +amdgpu_cdna2_op_V_PK_SUB_I16, +amdgpu_cdna2_op_V_PK_SUB_U16, +amdgpu_cdna2_op_V_QSAD_PK_U16_U8, +amdgpu_cdna2_op_V_RCP_F16, +amdgpu_cdna2_op_V_RCP_F32, +amdgpu_cdna2_op_V_RCP_F64, +amdgpu_cdna2_op_V_RCP_IFLAG_F32, +amdgpu_cdna2_op_V_READFIRSTLANE_B32, +amdgpu_cdna2_op_V_READLANE_B32, +amdgpu_cdna2_op_V_RNDNE_F16, +amdgpu_cdna2_op_V_RNDNE_F32, +amdgpu_cdna2_op_V_RNDNE_F64, +amdgpu_cdna2_op_V_RSQ_F16, +amdgpu_cdna2_op_V_RSQ_F32, +amdgpu_cdna2_op_V_RSQ_F64, +amdgpu_cdna2_op_V_SAD_HI_U8, +amdgpu_cdna2_op_V_SAD_U16, +amdgpu_cdna2_op_V_SAD_U32, +amdgpu_cdna2_op_V_SAD_U8, +amdgpu_cdna2_op_V_SAT_PK_U8_I16, +amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_cdna2_op_V_SIN_F16, +amdgpu_cdna2_op_V_SIN_F32, +amdgpu_cdna2_op_V_SQRT_F16, +amdgpu_cdna2_op_V_SQRT_F32, +amdgpu_cdna2_op_V_SQRT_F64, +amdgpu_cdna2_op_V_SUBBREV_CO_U32, +amdgpu_cdna2_op_V_SUBB_CO_U32, +amdgpu_cdna2_op_V_SUBREV_CO_U32, +amdgpu_cdna2_op_V_SUBREV_F16, +amdgpu_cdna2_op_V_SUBREV_F32, +amdgpu_cdna2_op_V_SUBREV_U16, +amdgpu_cdna2_op_V_SUBREV_U32, +amdgpu_cdna2_op_V_SUB_CO_U32, +amdgpu_cdna2_op_V_SUB_F16, +amdgpu_cdna2_op_V_SUB_F32, +amdgpu_cdna2_op_V_SUB_I16, +amdgpu_cdna2_op_V_SUB_I32, +amdgpu_cdna2_op_V_SUB_U16, +amdgpu_cdna2_op_V_SUB_U32, +amdgpu_cdna2_op_V_SWAP_B32, +amdgpu_cdna2_op_V_TRIG_PREOP_F64, +amdgpu_cdna2_op_V_TRUNC_F16, +amdgpu_cdna2_op_V_TRUNC_F32, +amdgpu_cdna2_op_V_TRUNC_F64, +amdgpu_cdna2_op_V_WRITELANE_B32, +amdgpu_cdna2_op_V_XAD_U32, +amdgpu_cdna2_op_V_XNOR_B32, +amdgpu_cdna2_op_V_XOR_B32, diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C new file mode 100644 index 0000000000..c5a67bdb42 --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C @@ -0,0 +1,2879 @@ +#define fn(...) (&InstructionDecoder_amdgpu_cdna2::__VA_ARGS__) +const operandFactory amdgpu_cdna2_insn_entry::operandTable[] = { + fn(NOTHING), +}; +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_DS_insn_table = { +{amdgpu_cdna2_op_DS_ADD_U32,"DS_ADD_U32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_DS_SUB_U32,"DS_SUB_U32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_DS_RSUB_U32,"DS_RSUB_U32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_DS_INC_U32,"DS_INC_U32",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_DS_DEC_U32,"DS_DEC_U32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_DS_MIN_I32,"DS_MIN_I32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_DS_MAX_I32,"DS_MAX_I32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_DS_MIN_U32,"DS_MIN_U32",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_DS_MAX_U32,"DS_MAX_U32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_DS_AND_B32,"DS_AND_B32",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_DS_OR_B32,"DS_OR_B32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_DS_XOR_B32,"DS_XOR_B32",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_DS_MSKOR_B32,"DS_MSKOR_B32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_DS_WRITE_B32,"DS_WRITE_B32",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_DS_WRITE2_B32,"DS_WRITE2_B32",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_DS_CMPST_B32,"DS_CMPST_B32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_DS_CMPST_F32,"DS_CMPST_F32",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_DS_MIN_F32,"DS_MIN_F32",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_DS_MAX_F32,"DS_MAX_F32",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_DS_NOP,"DS_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_DS_ADD_F32,"DS_ADD_F32",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_DS_WRITE_B8,"DS_WRITE_B8",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_DS_WRITE_B16,"DS_WRITE_B16",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_DS_INC_RTN_U32,"DS_INC_RTN_U32",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_DS_AND_RTN_B32,"DS_AND_RTN_B32",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_DS_OR_RTN_B32,"DS_OR_RTN_B32",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_DS_READ_B32,"DS_READ_B32",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_DS_READ2_B32,"DS_READ2_B32",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_DS_READ2ST64_B32,"DS_READ2ST64_B32",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_DS_READ_I8,"DS_READ_I8",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_DS_READ_U8,"DS_READ_U8",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_DS_READ_I16,"DS_READ_I16",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_DS_READ_U16,"DS_READ_U16",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_DS_PERMUTE_B32,"DS_PERMUTE_B32",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_DS_ADD_U64,"DS_ADD_U64",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_DS_SUB_U64,"DS_SUB_U64",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_DS_RSUB_U64,"DS_RSUB_U64",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_DS_INC_U64,"DS_INC_U64",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_DS_DEC_U64,"DS_DEC_U64",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_DS_MIN_I64,"DS_MIN_I64",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_DS_MAX_I64,"DS_MAX_I64",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_DS_MIN_U64,"DS_MIN_U64",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_DS_MAX_U64,"DS_MAX_U64",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_DS_AND_B64,"DS_AND_B64",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_DS_OR_B64,"DS_OR_B64",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_DS_XOR_B64,"DS_XOR_B64",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_DS_MSKOR_B64,"DS_MSKOR_B64",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_DS_WRITE_B64,"DS_WRITE_B64",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_DS_WRITE2_B64,"DS_WRITE2_B64",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_DS_CMPST_B64,"DS_CMPST_B64",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_DS_CMPST_F64,"DS_CMPST_F64",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_DS_MIN_F64,"DS_MIN_F64",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_DS_MAX_F64,"DS_MAX_F64",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_DS_READ_U8_D16,"DS_READ_U8_D16",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_DS_READ_I8_D16,"DS_READ_I8_D16",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_DS_READ_U16_D16,"DS_READ_U16_D16",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_DS_ADD_F64,"DS_ADD_F64",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_DS_INC_RTN_U64,"DS_INC_RTN_U64",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_DS_AND_RTN_B64,"DS_AND_RTN_B64",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_DS_OR_RTN_B64,"DS_OR_RTN_B64",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64",0,&operandTable[0]} ,//111 +{amdgpu_cdna2_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64",0,&operandTable[0]} ,//112 +{amdgpu_cdna2_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64",0,&operandTable[0]} ,//113 +{amdgpu_cdna2_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64",0,&operandTable[0]} ,//114 +{amdgpu_cdna2_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64",0,&operandTable[0]} ,//115 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_cdna2_op_DS_READ_B64,"DS_READ_B64",0,&operandTable[0]} ,//118 +{amdgpu_cdna2_op_DS_READ2_B64,"DS_READ2_B64",0,&operandTable[0]} ,//119 +{amdgpu_cdna2_op_DS_READ2ST64_B64,"DS_READ2ST64_B64",0,&operandTable[0]} ,//120 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_cdna2_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64",0,&operandTable[0]} ,//124 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_cdna2_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64",0,&operandTable[0]} ,//126 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_cdna2_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL",0,&operandTable[0]} ,//152 +{amdgpu_cdna2_op_DS_GWS_INIT,"DS_GWS_INIT",0,&operandTable[0]} ,//153 +{amdgpu_cdna2_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V",0,&operandTable[0]} ,//154 +{amdgpu_cdna2_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR",0,&operandTable[0]} ,//155 +{amdgpu_cdna2_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P",0,&operandTable[0]} ,//156 +{amdgpu_cdna2_op_DS_GWS_BARRIER,"DS_GWS_BARRIER",0,&operandTable[0]} ,//157 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181 +{amdgpu_cdna2_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32",0,&operandTable[0]} ,//182 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188 +{amdgpu_cdna2_op_DS_CONSUME,"DS_CONSUME",0,&operandTable[0]} ,//189 +{amdgpu_cdna2_op_DS_APPEND,"DS_APPEND",0,&operandTable[0]} ,//190 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//191 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//192 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//193 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//194 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//195 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//196 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//197 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//198 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//199 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//200 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//201 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//202 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//203 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//205 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//210 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//211 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221 +{amdgpu_cdna2_op_DS_WRITE_B96,"DS_WRITE_B96",0,&operandTable[0]} ,//222 +{amdgpu_cdna2_op_DS_WRITE_B128,"DS_WRITE_B128",0,&operandTable[0]} ,//223 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253 +{amdgpu_cdna2_op_DS_READ_B96,"DS_READ_B96",0,&operandTable[0]} ,//254 +{amdgpu_cdna2_op_DS_READ_B128,"DS_READ_B128",0,&operandTable[0]} ,//255 +}; // end ENC_DS_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_FLAT_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_FLAT_GLBL_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +}; // end ENC_FLAT_SCRATCH_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table = { +{amdgpu_cdna2_op_IMAGE_LOAD,"IMAGE_LOAD",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_IMAGE_STORE,"IMAGE_STORE",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_IMAGE_SAMPLE,"IMAGE_SAMPLE",0,&operandTable[0]} ,//32 +}; // end ENC_MIMG_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table = { +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15 +}; // end ENC_MTBUF_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table = { +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_BUFFER_WBL2,"BUFFER_WBL2",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_BUFFER_INVL2,"BUFFER_INVL2",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_BUFFER_WBINVL1,"BUFFER_WBINVL1",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_MUBUF_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table = { +{amdgpu_cdna2_op_S_LOAD_DWORD,"S_LOAD_DWORD",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_STORE_DWORD,"S_STORE_DWORD",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_STORE_DWORDX2,"S_STORE_DWORDX2",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_STORE_DWORDX4,"S_STORE_DWORDX4",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_DCACHE_INV,"S_DCACHE_INV",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_DCACHE_WB,"S_DCACHE_WB",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_MEMTIME,"S_MEMTIME",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_MEMREALTIME,"S_MEMREALTIME",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_ATC_PROBE,"S_ATC_PROBE",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_cdna2_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP",0,&operandTable[0]} ,//128 +{amdgpu_cdna2_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//129 +{amdgpu_cdna2_op_S_ATOMIC_ADD,"S_ATOMIC_ADD",0,&operandTable[0]} ,//130 +{amdgpu_cdna2_op_S_ATOMIC_SUB,"S_ATOMIC_SUB",0,&operandTable[0]} ,//131 +{amdgpu_cdna2_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN",0,&operandTable[0]} ,//132 +{amdgpu_cdna2_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN",0,&operandTable[0]} ,//133 +{amdgpu_cdna2_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX",0,&operandTable[0]} ,//134 +{amdgpu_cdna2_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX",0,&operandTable[0]} ,//135 +{amdgpu_cdna2_op_S_ATOMIC_AND,"S_ATOMIC_AND",0,&operandTable[0]} ,//136 +{amdgpu_cdna2_op_S_ATOMIC_OR,"S_ATOMIC_OR",0,&operandTable[0]} ,//137 +{amdgpu_cdna2_op_S_ATOMIC_XOR,"S_ATOMIC_XOR",0,&operandTable[0]} ,//138 +{amdgpu_cdna2_op_S_ATOMIC_INC,"S_ATOMIC_INC",0,&operandTable[0]} ,//139 +{amdgpu_cdna2_op_S_ATOMIC_DEC,"S_ATOMIC_DEC",0,&operandTable[0]} ,//140 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_cdna2_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//160 +{amdgpu_cdna2_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//161 +{amdgpu_cdna2_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2",0,&operandTable[0]} ,//162 +{amdgpu_cdna2_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2",0,&operandTable[0]} ,//163 +{amdgpu_cdna2_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//164 +{amdgpu_cdna2_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//165 +{amdgpu_cdna2_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//166 +{amdgpu_cdna2_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//167 +{amdgpu_cdna2_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2",0,&operandTable[0]} ,//168 +{amdgpu_cdna2_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2",0,&operandTable[0]} ,//169 +{amdgpu_cdna2_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2",0,&operandTable[0]} ,//170 +{amdgpu_cdna2_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2",0,&operandTable[0]} ,//171 +{amdgpu_cdna2_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2",0,&operandTable[0]} ,//172 +}; // end ENC_SMEM_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table = { +{amdgpu_cdna2_op_S_MOV_B32,"S_MOV_B32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_MOV_B64,"S_MOV_B64",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_CMOV_B32,"S_CMOV_B32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_CMOV_B64,"S_CMOV_B64",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOT_B32,"S_NOT_B32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOT_B64,"S_NOT_B64",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_WQM_B32,"S_WQM_B32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_WQM_B64,"S_WQM_B64",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_BREV_B32,"S_BREV_B32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_BREV_B64,"S_BREV_B64",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_FF0_I32_B32,"S_FF0_I32_B32",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_FF0_I32_B64,"S_FF0_I32_B64",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_FF1_I32_B32,"S_FF1_I32_B32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_FF1_I32_B64,"S_FF1_I32_B64",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_FLBIT_I32,"S_FLBIT_I32",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_SEXT_I32_I8,"S_SEXT_I32_I8",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_SEXT_I32_I16,"S_SEXT_I32_I16",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_BITSET0_B32,"S_BITSET0_B32",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_BITSET0_B64,"S_BITSET0_B64",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_BITSET1_B32,"S_BITSET1_B32",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_BITSET1_B64,"S_BITSET1_B64",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_GETPC_B64,"S_GETPC_B64",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_SETPC_B64,"S_SETPC_B64",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_SWAPPC_B64,"S_SWAPPC_B64",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_RFE_B64,"S_RFE_B64",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_QUADMASK_B32,"S_QUADMASK_B32",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_QUADMASK_B64,"S_QUADMASK_B64",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_MOVRELS_B32,"S_MOVRELS_B32",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_MOVRELS_B64,"S_MOVRELS_B64",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_MOVRELD_B32,"S_MOVRELD_B32",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_MOVRELD_B64,"S_MOVRELD_B64",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_ABS_I32,"S_ABS_I32",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32",0,&operandTable[0]} ,//55 +}; // end ENC_SOP1_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table = { +{amdgpu_cdna2_op_S_ADD_U32,"S_ADD_U32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_SUB_U32,"S_SUB_U32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_ADD_I32,"S_ADD_I32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_SUB_I32,"S_SUB_I32",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_ADDC_U32,"S_ADDC_U32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_SUBB_U32,"S_SUBB_U32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_MIN_I32,"S_MIN_I32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_MIN_U32,"S_MIN_U32",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_MAX_I32,"S_MAX_I32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_MAX_U32,"S_MAX_U32",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_CSELECT_B32,"S_CSELECT_B32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_CSELECT_B64,"S_CSELECT_B64",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_AND_B32,"S_AND_B32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_AND_B64,"S_AND_B64",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_OR_B32,"S_OR_B32",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_OR_B64,"S_OR_B64",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_XOR_B32,"S_XOR_B32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_XOR_B64,"S_XOR_B64",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_ANDN2_B32,"S_ANDN2_B32",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_ANDN2_B64,"S_ANDN2_B64",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_ORN2_B32,"S_ORN2_B32",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_ORN2_B64,"S_ORN2_B64",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NAND_B32,"S_NAND_B32",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NAND_B64,"S_NAND_B64",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOR_B32,"S_NOR_B32",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOR_B64,"S_NOR_B64",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_XNOR_B32,"S_XNOR_B32",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_XNOR_B64,"S_XNOR_B64",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_LSHL_B32,"S_LSHL_B32",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_LSHL_B64,"S_LSHL_B64",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_LSHR_B32,"S_LSHR_B32",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_LSHR_B64,"S_LSHR_B64",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_ASHR_I32,"S_ASHR_I32",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_ASHR_I64,"S_ASHR_I64",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_BFM_B32,"S_BFM_B32",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_BFM_B64,"S_BFM_B64",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_MUL_I32,"S_MUL_I32",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_BFE_U32,"S_BFE_U32",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_BFE_I32,"S_BFE_I32",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_BFE_U64,"S_BFE_U64",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_BFE_I64,"S_BFE_I64",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_ABSDIFF_I32,"S_ABSDIFF_I32",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_MUL_HI_U32,"S_MUL_HI_U32",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_MUL_HI_I32,"S_MUL_HI_I32",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16",0,&operandTable[0]} ,//52 +}; // end ENC_SOP2_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table = { +{amdgpu_cdna2_op_S_CMP_EQ_I32,"S_CMP_EQ_I32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_CMP_LG_I32,"S_CMP_LG_I32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_CMP_GT_I32,"S_CMP_GT_I32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_CMP_GE_I32,"S_CMP_GE_I32",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_CMP_LT_I32,"S_CMP_LT_I32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_CMP_LE_I32,"S_CMP_LE_I32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_CMP_EQ_U32,"S_CMP_EQ_U32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_CMP_LG_U32,"S_CMP_LG_U32",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_CMP_GT_U32,"S_CMP_GT_U32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_CMP_GE_U32,"S_CMP_GE_U32",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_CMP_LT_U32,"S_CMP_LT_U32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_CMP_LE_U32,"S_CMP_LE_U32",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_BITCMP0_B32,"S_BITCMP0_B32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_BITCMP1_B32,"S_BITCMP1_B32",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_BITCMP0_B64,"S_BITCMP0_B64",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_BITCMP1_B64,"S_BITCMP1_B64",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_SETVSKIP,"S_SETVSKIP",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_CMP_EQ_U64,"S_CMP_EQ_U64",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_CMP_LG_U64,"S_CMP_LG_U64",0,&operandTable[0]} ,//19 +}; // end ENC_SOPC_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table = { +{amdgpu_cdna2_op_S_MOVK_I32,"S_MOVK_I32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_CMOVK_I32,"S_CMOVK_I32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_CMPK_LG_I32,"S_CMPK_LG_I32",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_CMPK_GT_I32,"S_CMPK_GT_I32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_CMPK_GE_I32,"S_CMPK_GE_I32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_CMPK_LT_I32,"S_CMPK_LT_I32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_CMPK_LE_I32,"S_CMPK_LE_I32",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_CMPK_LG_U32,"S_CMPK_LG_U32",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_CMPK_GT_U32,"S_CMPK_GT_U32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_CMPK_GE_U32,"S_CMPK_GE_U32",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_CMPK_LT_U32,"S_CMPK_LT_U32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_CMPK_LE_U32,"S_CMPK_LE_U32",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_ADDK_I32,"S_ADDK_I32",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_MULK_I32,"S_MULK_I32",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_GETREG_B32,"S_GETREG_B32",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_SETREG_B32,"S_SETREG_B32",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_CALL_B64,"S_CALL_B64",0,&operandTable[0]} ,//21 +}; // end ENC_SOPK_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_ENDPGM,"S_ENDPGM",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_BRANCH,"S_BRANCH",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_WAKEUP,"S_WAKEUP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_BARRIER,"S_BARRIER",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_SETKILL,"S_SETKILL",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_WAITCNT,"S_WAITCNT",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_SETHALT,"S_SETHALT",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_SLEEP,"S_SLEEP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_SETPRIO,"S_SETPRIO",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_SENDMSG,"S_SENDMSG",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_SENDMSGHALT,"S_SENDMSGHALT",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_TRAP,"S_TRAP",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_ICACHE_INV,"S_ICACHE_INV",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_INCPERFLEVEL,"S_INCPERFLEVEL",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_DECPERFLEVEL,"S_DECPERFLEVEL",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_TTRACEDATA,"S_TTRACEDATA",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE",0,&operandTable[0]} ,//30 +}; // end ENC_SOPP_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table = { +{amdgpu_cdna2_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32",0,&operandTable[0]} ,//82 +}; // end ENC_VOP1_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111 +{amdgpu_cdna2_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112 +{amdgpu_cdna2_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113 +{amdgpu_cdna2_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114 +{amdgpu_cdna2_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115 +{amdgpu_cdna2_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116 +{amdgpu_cdna2_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117 +{amdgpu_cdna2_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118 +{amdgpu_cdna2_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119 +{amdgpu_cdna2_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120 +{amdgpu_cdna2_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121 +{amdgpu_cdna2_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122 +{amdgpu_cdna2_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123 +{amdgpu_cdna2_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124 +{amdgpu_cdna2_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125 +{amdgpu_cdna2_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126 +{amdgpu_cdna2_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_cdna2_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160 +{amdgpu_cdna2_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161 +{amdgpu_cdna2_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162 +{amdgpu_cdna2_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163 +{amdgpu_cdna2_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164 +{amdgpu_cdna2_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165 +{amdgpu_cdna2_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166 +{amdgpu_cdna2_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167 +{amdgpu_cdna2_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168 +{amdgpu_cdna2_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169 +{amdgpu_cdna2_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170 +{amdgpu_cdna2_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171 +{amdgpu_cdna2_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172 +{amdgpu_cdna2_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173 +{amdgpu_cdna2_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174 +{amdgpu_cdna2_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175 +{amdgpu_cdna2_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176 +{amdgpu_cdna2_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177 +{amdgpu_cdna2_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178 +{amdgpu_cdna2_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179 +{amdgpu_cdna2_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180 +{amdgpu_cdna2_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181 +{amdgpu_cdna2_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182 +{amdgpu_cdna2_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183 +{amdgpu_cdna2_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184 +{amdgpu_cdna2_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185 +{amdgpu_cdna2_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186 +{amdgpu_cdna2_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187 +{amdgpu_cdna2_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188 +{amdgpu_cdna2_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189 +{amdgpu_cdna2_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190 +{amdgpu_cdna2_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191 +{amdgpu_cdna2_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192 +{amdgpu_cdna2_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193 +{amdgpu_cdna2_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194 +{amdgpu_cdna2_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195 +{amdgpu_cdna2_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196 +{amdgpu_cdna2_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197 +{amdgpu_cdna2_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198 +{amdgpu_cdna2_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199 +{amdgpu_cdna2_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200 +{amdgpu_cdna2_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201 +{amdgpu_cdna2_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202 +{amdgpu_cdna2_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203 +{amdgpu_cdna2_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204 +{amdgpu_cdna2_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205 +{amdgpu_cdna2_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206 +{amdgpu_cdna2_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207 +{amdgpu_cdna2_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208 +{amdgpu_cdna2_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209 +{amdgpu_cdna2_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210 +{amdgpu_cdna2_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211 +{amdgpu_cdna2_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212 +{amdgpu_cdna2_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213 +{amdgpu_cdna2_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214 +{amdgpu_cdna2_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215 +{amdgpu_cdna2_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216 +{amdgpu_cdna2_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217 +{amdgpu_cdna2_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218 +{amdgpu_cdna2_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219 +{amdgpu_cdna2_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220 +{amdgpu_cdna2_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221 +{amdgpu_cdna2_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222 +{amdgpu_cdna2_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223 +{amdgpu_cdna2_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224 +{amdgpu_cdna2_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225 +{amdgpu_cdna2_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226 +{amdgpu_cdna2_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227 +{amdgpu_cdna2_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228 +{amdgpu_cdna2_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229 +{amdgpu_cdna2_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230 +{amdgpu_cdna2_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231 +{amdgpu_cdna2_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232 +{amdgpu_cdna2_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233 +{amdgpu_cdna2_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234 +{amdgpu_cdna2_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235 +{amdgpu_cdna2_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236 +{amdgpu_cdna2_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237 +{amdgpu_cdna2_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238 +{amdgpu_cdna2_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239 +{amdgpu_cdna2_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240 +{amdgpu_cdna2_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241 +{amdgpu_cdna2_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242 +{amdgpu_cdna2_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243 +{amdgpu_cdna2_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244 +{amdgpu_cdna2_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245 +{amdgpu_cdna2_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246 +{amdgpu_cdna2_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247 +{amdgpu_cdna2_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248 +{amdgpu_cdna2_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249 +{amdgpu_cdna2_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250 +{amdgpu_cdna2_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251 +{amdgpu_cdna2_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252 +{amdgpu_cdna2_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253 +{amdgpu_cdna2_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254 +{amdgpu_cdna2_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255 +{amdgpu_cdna2_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//256 +{amdgpu_cdna2_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//257 +{amdgpu_cdna2_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//258 +{amdgpu_cdna2_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//259 +{amdgpu_cdna2_op_V_FMAC_F64,"V_FMAC_F64",0,&operandTable[0]} ,//260 +{amdgpu_cdna2_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//261 +{amdgpu_cdna2_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//262 +{amdgpu_cdna2_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//263 +{amdgpu_cdna2_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//264 +{amdgpu_cdna2_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//265 +{amdgpu_cdna2_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//266 +{amdgpu_cdna2_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//267 +{amdgpu_cdna2_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//268 +{amdgpu_cdna2_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//269 +{amdgpu_cdna2_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//270 +{amdgpu_cdna2_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//271 +{amdgpu_cdna2_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//272 +{amdgpu_cdna2_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//273 +{amdgpu_cdna2_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//274 +{amdgpu_cdna2_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//275 +{amdgpu_cdna2_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//276 +{amdgpu_cdna2_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//277 +{amdgpu_cdna2_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//278 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//281 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//282 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//283 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//284 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//285 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//286 +{amdgpu_cdna2_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//287 +{amdgpu_cdna2_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//288 +{amdgpu_cdna2_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//289 +{amdgpu_cdna2_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//290 +{amdgpu_cdna2_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//291 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293 +{amdgpu_cdna2_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//294 +{amdgpu_cdna2_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//295 +{amdgpu_cdna2_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//296 +{amdgpu_cdna2_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//297 +{amdgpu_cdna2_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//298 +{amdgpu_cdna2_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//299 +{amdgpu_cdna2_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//300 +{amdgpu_cdna2_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//301 +{amdgpu_cdna2_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//302 +{amdgpu_cdna2_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//303 +{amdgpu_cdna2_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//304 +{amdgpu_cdna2_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//305 +{amdgpu_cdna2_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//306 +{amdgpu_cdna2_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//307 +{amdgpu_cdna2_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//308 +{amdgpu_cdna2_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//309 +{amdgpu_cdna2_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//310 +{amdgpu_cdna2_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//311 +{amdgpu_cdna2_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//312 +{amdgpu_cdna2_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//313 +{amdgpu_cdna2_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//314 +{amdgpu_cdna2_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//315 +{amdgpu_cdna2_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//316 +{amdgpu_cdna2_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//317 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319 +{amdgpu_cdna2_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//320 +{amdgpu_cdna2_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//321 +{amdgpu_cdna2_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//322 +{amdgpu_cdna2_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//323 +{amdgpu_cdna2_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//324 +{amdgpu_cdna2_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//325 +{amdgpu_cdna2_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//326 +{amdgpu_cdna2_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//327 +{amdgpu_cdna2_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//328 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329 +{amdgpu_cdna2_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//330 +{amdgpu_cdna2_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//331 +{amdgpu_cdna2_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//332 +{amdgpu_cdna2_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//333 +{amdgpu_cdna2_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//334 +{amdgpu_cdna2_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//335 +{amdgpu_cdna2_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//336 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//337 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//338 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//339 +{amdgpu_cdna2_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//340 +{amdgpu_cdna2_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//341 +{amdgpu_cdna2_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//342 +{amdgpu_cdna2_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//343 +{amdgpu_cdna2_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//344 +{amdgpu_cdna2_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//345 +{amdgpu_cdna2_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//346 +{amdgpu_cdna2_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//347 +{amdgpu_cdna2_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//348 +{amdgpu_cdna2_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//349 +{amdgpu_cdna2_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//350 +{amdgpu_cdna2_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//351 +{amdgpu_cdna2_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//352 +{amdgpu_cdna2_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//353 +{amdgpu_cdna2_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//354 +{amdgpu_cdna2_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//355 +{amdgpu_cdna2_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//356 +{amdgpu_cdna2_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//357 +{amdgpu_cdna2_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//358 +{amdgpu_cdna2_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//359 +{amdgpu_cdna2_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//360 +{amdgpu_cdna2_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//361 +{amdgpu_cdna2_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//362 +{amdgpu_cdna2_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//363 +{amdgpu_cdna2_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//364 +{amdgpu_cdna2_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//365 +{amdgpu_cdna2_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//366 +{amdgpu_cdna2_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//367 +{amdgpu_cdna2_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//368 +{amdgpu_cdna2_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//369 +{amdgpu_cdna2_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//370 +{amdgpu_cdna2_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//371 +{amdgpu_cdna2_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//372 +{amdgpu_cdna2_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//373 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374 +{amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//375 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376 +{amdgpu_cdna2_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//377 +{amdgpu_cdna2_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//378 +{amdgpu_cdna2_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//379 +{amdgpu_cdna2_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//380 +{amdgpu_cdna2_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//381 +{amdgpu_cdna2_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//382 +{amdgpu_cdna2_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//383 +{amdgpu_cdna2_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//384 +{amdgpu_cdna2_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//385 +{amdgpu_cdna2_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//386 +{amdgpu_cdna2_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//387 +{amdgpu_cdna2_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//388 +{amdgpu_cdna2_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//389 +{amdgpu_cdna2_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//390 +{amdgpu_cdna2_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//391 +{amdgpu_cdna2_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//392 +{amdgpu_cdna2_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//393 +{amdgpu_cdna2_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//394 +{amdgpu_cdna2_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//395 +{amdgpu_cdna2_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//396 +{amdgpu_cdna2_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//397 +{amdgpu_cdna2_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//398 +{amdgpu_cdna2_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//399 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400 +{amdgpu_cdna2_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//401 +{amdgpu_cdna2_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32",0,&operandTable[0]} ,//402 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447 +{amdgpu_cdna2_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32",0,&operandTable[0]} ,//448 +{amdgpu_cdna2_op_V_MAD_F32,"V_MAD_F32",0,&operandTable[0]} ,//449 +{amdgpu_cdna2_op_V_MAD_I32_I24,"V_MAD_I32_I24",0,&operandTable[0]} ,//450 +{amdgpu_cdna2_op_V_MAD_U32_U24,"V_MAD_U32_U24",0,&operandTable[0]} ,//451 +{amdgpu_cdna2_op_V_CUBEID_F32,"V_CUBEID_F32",0,&operandTable[0]} ,//452 +{amdgpu_cdna2_op_V_CUBESC_F32,"V_CUBESC_F32",0,&operandTable[0]} ,//453 +{amdgpu_cdna2_op_V_CUBETC_F32,"V_CUBETC_F32",0,&operandTable[0]} ,//454 +{amdgpu_cdna2_op_V_CUBEMA_F32,"V_CUBEMA_F32",0,&operandTable[0]} ,//455 +{amdgpu_cdna2_op_V_BFE_U32,"V_BFE_U32",0,&operandTable[0]} ,//456 +{amdgpu_cdna2_op_V_BFE_I32,"V_BFE_I32",0,&operandTable[0]} ,//457 +{amdgpu_cdna2_op_V_BFI_B32,"V_BFI_B32",0,&operandTable[0]} ,//458 +{amdgpu_cdna2_op_V_FMA_F32,"V_FMA_F32",0,&operandTable[0]} ,//459 +{amdgpu_cdna2_op_V_FMA_F64,"V_FMA_F64",0,&operandTable[0]} ,//460 +{amdgpu_cdna2_op_V_LERP_U8,"V_LERP_U8",0,&operandTable[0]} ,//461 +{amdgpu_cdna2_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32",0,&operandTable[0]} ,//462 +{amdgpu_cdna2_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32",0,&operandTable[0]} ,//463 +{amdgpu_cdna2_op_V_MIN3_F32,"V_MIN3_F32",0,&operandTable[0]} ,//464 +{amdgpu_cdna2_op_V_MIN3_I32,"V_MIN3_I32",0,&operandTable[0]} ,//465 +{amdgpu_cdna2_op_V_MIN3_U32,"V_MIN3_U32",0,&operandTable[0]} ,//466 +{amdgpu_cdna2_op_V_MAX3_F32,"V_MAX3_F32",0,&operandTable[0]} ,//467 +{amdgpu_cdna2_op_V_MAX3_I32,"V_MAX3_I32",0,&operandTable[0]} ,//468 +{amdgpu_cdna2_op_V_MAX3_U32,"V_MAX3_U32",0,&operandTable[0]} ,//469 +{amdgpu_cdna2_op_V_MED3_F32,"V_MED3_F32",0,&operandTable[0]} ,//470 +{amdgpu_cdna2_op_V_MED3_I32,"V_MED3_I32",0,&operandTable[0]} ,//471 +{amdgpu_cdna2_op_V_MED3_U32,"V_MED3_U32",0,&operandTable[0]} ,//472 +{amdgpu_cdna2_op_V_SAD_U8,"V_SAD_U8",0,&operandTable[0]} ,//473 +{amdgpu_cdna2_op_V_SAD_HI_U8,"V_SAD_HI_U8",0,&operandTable[0]} ,//474 +{amdgpu_cdna2_op_V_SAD_U16,"V_SAD_U16",0,&operandTable[0]} ,//475 +{amdgpu_cdna2_op_V_SAD_U32,"V_SAD_U32",0,&operandTable[0]} ,//476 +{amdgpu_cdna2_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32",0,&operandTable[0]} ,//477 +{amdgpu_cdna2_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32",0,&operandTable[0]} ,//478 +{amdgpu_cdna2_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64",0,&operandTable[0]} ,//479 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//480 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//481 +{amdgpu_cdna2_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32",0,&operandTable[0]} ,//482 +{amdgpu_cdna2_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64",0,&operandTable[0]} ,//483 +{amdgpu_cdna2_op_V_MSAD_U8,"V_MSAD_U8",0,&operandTable[0]} ,//484 +{amdgpu_cdna2_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8",0,&operandTable[0]} ,//485 +{amdgpu_cdna2_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8",0,&operandTable[0]} ,//486 +{amdgpu_cdna2_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8",0,&operandTable[0]} ,//487 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//488 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//489 +{amdgpu_cdna2_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16",0,&operandTable[0]} ,//490 +{amdgpu_cdna2_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16",0,&operandTable[0]} ,//491 +{amdgpu_cdna2_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16",0,&operandTable[0]} ,//492 +{amdgpu_cdna2_op_V_PERM_B32,"V_PERM_B32",0,&operandTable[0]} ,//493 +{amdgpu_cdna2_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16",0,&operandTable[0]} ,//494 +{amdgpu_cdna2_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16",0,&operandTable[0]} ,//495 +{amdgpu_cdna2_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32",0,&operandTable[0]} ,//496 +{amdgpu_cdna2_op_V_MAD_U32_U16,"V_MAD_U32_U16",0,&operandTable[0]} ,//497 +{amdgpu_cdna2_op_V_MAD_I32_I16,"V_MAD_I32_I16",0,&operandTable[0]} ,//498 +{amdgpu_cdna2_op_V_XAD_U32,"V_XAD_U32",0,&operandTable[0]} ,//499 +{amdgpu_cdna2_op_V_MIN3_F16,"V_MIN3_F16",0,&operandTable[0]} ,//500 +{amdgpu_cdna2_op_V_MIN3_I16,"V_MIN3_I16",0,&operandTable[0]} ,//501 +{amdgpu_cdna2_op_V_MIN3_U16,"V_MIN3_U16",0,&operandTable[0]} ,//502 +{amdgpu_cdna2_op_V_MAX3_F16,"V_MAX3_F16",0,&operandTable[0]} ,//503 +{amdgpu_cdna2_op_V_MAX3_I16,"V_MAX3_I16",0,&operandTable[0]} ,//504 +{amdgpu_cdna2_op_V_MAX3_U16,"V_MAX3_U16",0,&operandTable[0]} ,//505 +{amdgpu_cdna2_op_V_MED3_F16,"V_MED3_F16",0,&operandTable[0]} ,//506 +{amdgpu_cdna2_op_V_MED3_I16,"V_MED3_I16",0,&operandTable[0]} ,//507 +{amdgpu_cdna2_op_V_MED3_U16,"V_MED3_U16",0,&operandTable[0]} ,//508 +{amdgpu_cdna2_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32",0,&operandTable[0]} ,//509 +{amdgpu_cdna2_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32",0,&operandTable[0]} ,//510 +{amdgpu_cdna2_op_V_ADD3_U32,"V_ADD3_U32",0,&operandTable[0]} ,//511 +{amdgpu_cdna2_op_V_LSHL_OR_B32,"V_LSHL_OR_B32",0,&operandTable[0]} ,//512 +{amdgpu_cdna2_op_V_AND_OR_B32,"V_AND_OR_B32",0,&operandTable[0]} ,//513 +{amdgpu_cdna2_op_V_OR3_B32,"V_OR3_B32",0,&operandTable[0]} ,//514 +{amdgpu_cdna2_op_V_MAD_F16,"V_MAD_F16",0,&operandTable[0]} ,//515 +{amdgpu_cdna2_op_V_MAD_U16,"V_MAD_U16",0,&operandTable[0]} ,//516 +{amdgpu_cdna2_op_V_MAD_I16,"V_MAD_I16",0,&operandTable[0]} ,//517 +{amdgpu_cdna2_op_V_FMA_F16,"V_FMA_F16",0,&operandTable[0]} ,//518 +{amdgpu_cdna2_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16",0,&operandTable[0]} ,//519 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//520 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//521 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//522 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//523 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//524 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//525 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//526 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//527 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//528 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//529 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//530 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//531 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//532 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//533 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//534 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//535 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//536 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//537 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//538 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//539 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//540 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//541 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//542 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//543 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//544 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//545 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//546 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//547 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//548 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//549 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//550 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//551 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//552 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//553 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//554 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//555 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//556 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//557 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//558 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//559 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//560 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//561 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//562 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//563 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//564 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//565 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//566 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//567 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//568 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//569 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//570 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//571 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//572 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//573 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//574 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//575 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//576 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//577 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//578 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//579 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//580 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//581 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//582 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//583 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//584 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//585 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//586 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//587 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//588 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//589 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//590 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//591 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//592 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//593 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//594 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//595 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//596 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//597 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//598 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//599 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//600 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//601 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//602 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//603 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//604 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//605 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//606 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//607 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//608 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//609 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//610 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//611 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//612 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//613 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//614 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//615 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//616 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//617 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//618 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//619 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//620 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//621 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//622 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//623 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//624 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//625 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//626 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//627 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//628 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//629 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//630 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//631 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//632 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//633 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//634 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//635 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//636 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//637 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//638 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//639 +{amdgpu_cdna2_op_V_ADD_F64,"V_ADD_F64",0,&operandTable[0]} ,//640 +{amdgpu_cdna2_op_V_MUL_F64,"V_MUL_F64",0,&operandTable[0]} ,//641 +{amdgpu_cdna2_op_V_MIN_F64,"V_MIN_F64",0,&operandTable[0]} ,//642 +{amdgpu_cdna2_op_V_MAX_F64,"V_MAX_F64",0,&operandTable[0]} ,//643 +{amdgpu_cdna2_op_V_LDEXP_F64,"V_LDEXP_F64",0,&operandTable[0]} ,//644 +{amdgpu_cdna2_op_V_MUL_LO_U32,"V_MUL_LO_U32",0,&operandTable[0]} ,//645 +{amdgpu_cdna2_op_V_MUL_HI_U32,"V_MUL_HI_U32",0,&operandTable[0]} ,//646 +{amdgpu_cdna2_op_V_MUL_HI_I32,"V_MUL_HI_I32",0,&operandTable[0]} ,//647 +{amdgpu_cdna2_op_V_LDEXP_F32,"V_LDEXP_F32",0,&operandTable[0]} ,//648 +{amdgpu_cdna2_op_V_READLANE_B32,"V_READLANE_B32",0,&operandTable[0]} ,//649 +{amdgpu_cdna2_op_V_WRITELANE_B32,"V_WRITELANE_B32",0,&operandTable[0]} ,//650 +{amdgpu_cdna2_op_V_BCNT_U32_B32,"V_BCNT_U32_B32",0,&operandTable[0]} ,//651 +{amdgpu_cdna2_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32",0,&operandTable[0]} ,//652 +{amdgpu_cdna2_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32",0,&operandTable[0]} ,//653 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//654 +{amdgpu_cdna2_op_V_LSHLREV_B64,"V_LSHLREV_B64",0,&operandTable[0]} ,//655 +{amdgpu_cdna2_op_V_LSHRREV_B64,"V_LSHRREV_B64",0,&operandTable[0]} ,//656 +{amdgpu_cdna2_op_V_ASHRREV_I64,"V_ASHRREV_I64",0,&operandTable[0]} ,//657 +{amdgpu_cdna2_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64",0,&operandTable[0]} ,//658 +{amdgpu_cdna2_op_V_BFM_B32,"V_BFM_B32",0,&operandTable[0]} ,//659 +{amdgpu_cdna2_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32",0,&operandTable[0]} ,//660 +{amdgpu_cdna2_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32",0,&operandTable[0]} ,//661 +{amdgpu_cdna2_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32",0,&operandTable[0]} ,//662 +{amdgpu_cdna2_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32",0,&operandTable[0]} ,//663 +{amdgpu_cdna2_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32",0,&operandTable[0]} ,//664 +{amdgpu_cdna2_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16",0,&operandTable[0]} ,//665 +{amdgpu_cdna2_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16",0,&operandTable[0]} ,//666 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//667 +{amdgpu_cdna2_op_V_ADD_I32,"V_ADD_I32",0,&operandTable[0]} ,//668 +{amdgpu_cdna2_op_V_SUB_I32,"V_SUB_I32",0,&operandTable[0]} ,//669 +{amdgpu_cdna2_op_V_ADD_I16,"V_ADD_I16",0,&operandTable[0]} ,//670 +{amdgpu_cdna2_op_V_SUB_I16,"V_SUB_I16",0,&operandTable[0]} ,//671 +{amdgpu_cdna2_op_V_PACK_B32_F16,"V_PACK_B32_F16",0,&operandTable[0]} ,//672 +{amdgpu_cdna2_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32",0,&operandTable[0]} ,//673 +}; // end ENC_VOP3_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table = { +{amdgpu_cdna2_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_V_FMAC_F64,"V_FMAC_F64",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//61 +}; // end ENC_VOP2_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_V_MADMK_F32,"V_MADMK_F32",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_V_MADAK_F32,"V_MADAK_F32",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_V_MADMK_F16,"V_MADMK_F16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_V_MADAK_F16,"V_MADAK_F16",0,&operandTable[0]} ,//37 +}; // end ENC_VOP2_LITERAL_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//182 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//189 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//190 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//191 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//192 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//193 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//194 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//195 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//196 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//197 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//198 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//199 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//200 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//201 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//202 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//203 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//205 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//210 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//211 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//222 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//223 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//254 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//255 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//256 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//257 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//258 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//259 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//260 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//261 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//262 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//263 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//264 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//265 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//266 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//267 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//268 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//269 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//270 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//271 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//272 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//273 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//274 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//275 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//276 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//277 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//278 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280 +{amdgpu_cdna2_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//281 +{amdgpu_cdna2_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//282 +{amdgpu_cdna2_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//283 +{amdgpu_cdna2_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//284 +{amdgpu_cdna2_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//285 +{amdgpu_cdna2_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//286 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//287 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//288 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//289 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//290 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//291 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//294 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//295 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//296 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//297 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//298 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//299 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//300 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//301 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//302 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//303 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//304 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//305 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//306 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//307 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//308 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//309 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//310 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//311 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//312 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//313 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//314 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//315 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//316 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//317 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//320 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//321 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//322 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//323 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//324 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//325 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//326 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//327 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//328 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//330 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//331 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//332 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//333 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//334 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//335 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//336 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//337 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//338 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//339 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//340 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//341 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//342 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//343 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//344 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//345 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//346 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//347 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//348 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//349 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//350 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//351 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//352 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//353 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//354 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//355 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//356 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//357 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//358 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//359 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//360 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//361 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//362 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//363 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//364 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//365 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//366 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//367 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//368 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//369 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//370 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//371 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//372 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//373 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//375 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//377 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//378 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//379 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//380 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//381 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//382 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//383 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//384 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//385 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//386 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//387 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//388 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//389 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//390 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//391 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//392 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//393 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//394 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//395 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//396 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//397 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//398 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//399 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//401 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//402 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//448 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//449 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//450 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//451 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//452 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//453 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//454 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//455 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//456 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//457 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//458 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//459 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//460 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//461 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//462 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//463 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//464 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//465 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//466 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//467 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//468 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//469 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//470 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//471 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//472 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//473 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//474 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//475 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//476 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//477 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//478 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//479 +{amdgpu_cdna2_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32",0,&operandTable[0]} ,//480 +{amdgpu_cdna2_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64",0,&operandTable[0]} ,//481 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//482 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//483 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//484 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//485 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//486 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//487 +{amdgpu_cdna2_op_V_MAD_U64_U32,"V_MAD_U64_U32",0,&operandTable[0]} ,//488 +{amdgpu_cdna2_op_V_MAD_I64_I32,"V_MAD_I64_I32",0,&operandTable[0]} ,//489 +}; // end ENC_VOP3B_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table = { +{amdgpu_cdna2_op_V_PK_MAD_I16,"V_PK_MAD_I16",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_V_PK_ADD_I16,"V_PK_ADD_I16",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_V_PK_SUB_I16,"V_PK_SUB_I16",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_V_PK_MAX_I16,"V_PK_MAX_I16",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_V_PK_MIN_I16,"V_PK_MIN_I16",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_V_PK_MAD_U16,"V_PK_MAD_U16",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_V_PK_ADD_U16,"V_PK_ADD_U16",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_V_PK_SUB_U16,"V_PK_SUB_U16",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_V_PK_MAX_U16,"V_PK_MAX_U16",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_V_PK_MIN_U16,"V_PK_MIN_U16",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_V_PK_FMA_F16,"V_PK_FMA_F16",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_V_PK_ADD_F16,"V_PK_ADD_F16",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_V_PK_MUL_F16,"V_PK_MUL_F16",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_V_PK_MIN_F16,"V_PK_MIN_F16",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_V_PK_MAX_F16,"V_PK_MAX_F16",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_V_MAD_MIX_F32,"V_MAD_MIX_F32",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_V_DOT2_F32_F16,"V_DOT2_F32_F16",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_V_DOT2_I32_I16,"V_DOT2_I32_I16",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_V_DOT2_U32_U16,"V_DOT2_U32_U16",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_V_DOT4_I32_I8,"V_DOT4_I32_I8",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_V_DOT4_U32_U8,"V_DOT4_U32_U8",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_V_DOT8_I32_I4,"V_DOT8_I32_I4",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_V_DOT8_U32_U4,"V_DOT8_U32_U4",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_V_PK_FMA_F32,"V_PK_FMA_F32",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_V_PK_MUL_F32,"V_PK_MUL_F32",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_V_PK_ADD_F32,"V_PK_ADD_F32",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_V_PK_MOV_B32,"V_PK_MOV_B32",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_V_ACCVGPR_READ,"V_ACCVGPR_READ",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE",0,&operandTable[0]} ,//89 +}; // end ENC_VOP3P_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16_1K,"V_MFMA_F32_32X32X4BF16_1K",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X4BF16_1K,"V_MFMA_F32_16X16X4BF16_1K",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_V_MFMA_F32_4X4X4BF16_1K,"V_MFMA_F32_4X4X4BF16_1K",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X8BF16_1K,"V_MFMA_F32_32X32X8BF16_1K",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X16BF16_1K,"V_MFMA_F32_16X16X16BF16_1K",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_V_MFMA_F64_16X16X4F64,"V_MFMA_F64_16X16X4F64",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_V_MFMA_F64_4X4X4F64,"V_MFMA_F64_4X4X4F64",0,&operandTable[0]} ,//111 +}; // end ENC_VOP3P_MFMA_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_cdna2_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16 +{amdgpu_cdna2_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17 +{amdgpu_cdna2_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18 +{amdgpu_cdna2_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19 +{amdgpu_cdna2_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20 +{amdgpu_cdna2_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_cdna2_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32 +{amdgpu_cdna2_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33 +{amdgpu_cdna2_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34 +{amdgpu_cdna2_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35 +{amdgpu_cdna2_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36 +{amdgpu_cdna2_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37 +{amdgpu_cdna2_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38 +{amdgpu_cdna2_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39 +{amdgpu_cdna2_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40 +{amdgpu_cdna2_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41 +{amdgpu_cdna2_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42 +{amdgpu_cdna2_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43 +{amdgpu_cdna2_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44 +{amdgpu_cdna2_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45 +{amdgpu_cdna2_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46 +{amdgpu_cdna2_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47 +{amdgpu_cdna2_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48 +{amdgpu_cdna2_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49 +{amdgpu_cdna2_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50 +{amdgpu_cdna2_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51 +{amdgpu_cdna2_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52 +{amdgpu_cdna2_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53 +{amdgpu_cdna2_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54 +{amdgpu_cdna2_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55 +{amdgpu_cdna2_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56 +{amdgpu_cdna2_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57 +{amdgpu_cdna2_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58 +{amdgpu_cdna2_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59 +{amdgpu_cdna2_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60 +{amdgpu_cdna2_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61 +{amdgpu_cdna2_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62 +{amdgpu_cdna2_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63 +{amdgpu_cdna2_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64 +{amdgpu_cdna2_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65 +{amdgpu_cdna2_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66 +{amdgpu_cdna2_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67 +{amdgpu_cdna2_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68 +{amdgpu_cdna2_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69 +{amdgpu_cdna2_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70 +{amdgpu_cdna2_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71 +{amdgpu_cdna2_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72 +{amdgpu_cdna2_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73 +{amdgpu_cdna2_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74 +{amdgpu_cdna2_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75 +{amdgpu_cdna2_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76 +{amdgpu_cdna2_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77 +{amdgpu_cdna2_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78 +{amdgpu_cdna2_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79 +{amdgpu_cdna2_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80 +{amdgpu_cdna2_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81 +{amdgpu_cdna2_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82 +{amdgpu_cdna2_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83 +{amdgpu_cdna2_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84 +{amdgpu_cdna2_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85 +{amdgpu_cdna2_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86 +{amdgpu_cdna2_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87 +{amdgpu_cdna2_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88 +{amdgpu_cdna2_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89 +{amdgpu_cdna2_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90 +{amdgpu_cdna2_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91 +{amdgpu_cdna2_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92 +{amdgpu_cdna2_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93 +{amdgpu_cdna2_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94 +{amdgpu_cdna2_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95 +{amdgpu_cdna2_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96 +{amdgpu_cdna2_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97 +{amdgpu_cdna2_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98 +{amdgpu_cdna2_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99 +{amdgpu_cdna2_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100 +{amdgpu_cdna2_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101 +{amdgpu_cdna2_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102 +{amdgpu_cdna2_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103 +{amdgpu_cdna2_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104 +{amdgpu_cdna2_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105 +{amdgpu_cdna2_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106 +{amdgpu_cdna2_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107 +{amdgpu_cdna2_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108 +{amdgpu_cdna2_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109 +{amdgpu_cdna2_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110 +{amdgpu_cdna2_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111 +{amdgpu_cdna2_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112 +{amdgpu_cdna2_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113 +{amdgpu_cdna2_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114 +{amdgpu_cdna2_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115 +{amdgpu_cdna2_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116 +{amdgpu_cdna2_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117 +{amdgpu_cdna2_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118 +{amdgpu_cdna2_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119 +{amdgpu_cdna2_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120 +{amdgpu_cdna2_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121 +{amdgpu_cdna2_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122 +{amdgpu_cdna2_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123 +{amdgpu_cdna2_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124 +{amdgpu_cdna2_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125 +{amdgpu_cdna2_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126 +{amdgpu_cdna2_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_cdna2_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160 +{amdgpu_cdna2_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161 +{amdgpu_cdna2_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162 +{amdgpu_cdna2_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163 +{amdgpu_cdna2_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164 +{amdgpu_cdna2_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165 +{amdgpu_cdna2_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166 +{amdgpu_cdna2_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167 +{amdgpu_cdna2_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168 +{amdgpu_cdna2_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169 +{amdgpu_cdna2_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170 +{amdgpu_cdna2_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171 +{amdgpu_cdna2_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172 +{amdgpu_cdna2_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173 +{amdgpu_cdna2_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174 +{amdgpu_cdna2_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175 +{amdgpu_cdna2_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176 +{amdgpu_cdna2_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177 +{amdgpu_cdna2_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178 +{amdgpu_cdna2_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179 +{amdgpu_cdna2_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180 +{amdgpu_cdna2_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181 +{amdgpu_cdna2_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182 +{amdgpu_cdna2_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183 +{amdgpu_cdna2_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184 +{amdgpu_cdna2_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185 +{amdgpu_cdna2_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186 +{amdgpu_cdna2_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187 +{amdgpu_cdna2_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188 +{amdgpu_cdna2_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189 +{amdgpu_cdna2_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190 +{amdgpu_cdna2_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191 +{amdgpu_cdna2_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192 +{amdgpu_cdna2_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193 +{amdgpu_cdna2_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194 +{amdgpu_cdna2_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195 +{amdgpu_cdna2_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196 +{amdgpu_cdna2_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197 +{amdgpu_cdna2_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198 +{amdgpu_cdna2_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199 +{amdgpu_cdna2_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200 +{amdgpu_cdna2_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201 +{amdgpu_cdna2_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202 +{amdgpu_cdna2_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203 +{amdgpu_cdna2_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204 +{amdgpu_cdna2_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205 +{amdgpu_cdna2_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206 +{amdgpu_cdna2_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207 +{amdgpu_cdna2_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208 +{amdgpu_cdna2_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209 +{amdgpu_cdna2_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210 +{amdgpu_cdna2_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211 +{amdgpu_cdna2_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212 +{amdgpu_cdna2_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213 +{amdgpu_cdna2_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214 +{amdgpu_cdna2_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215 +{amdgpu_cdna2_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216 +{amdgpu_cdna2_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217 +{amdgpu_cdna2_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218 +{amdgpu_cdna2_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219 +{amdgpu_cdna2_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220 +{amdgpu_cdna2_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221 +{amdgpu_cdna2_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222 +{amdgpu_cdna2_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223 +{amdgpu_cdna2_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224 +{amdgpu_cdna2_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225 +{amdgpu_cdna2_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226 +{amdgpu_cdna2_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227 +{amdgpu_cdna2_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228 +{amdgpu_cdna2_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229 +{amdgpu_cdna2_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230 +{amdgpu_cdna2_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231 +{amdgpu_cdna2_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232 +{amdgpu_cdna2_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233 +{amdgpu_cdna2_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234 +{amdgpu_cdna2_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235 +{amdgpu_cdna2_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236 +{amdgpu_cdna2_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237 +{amdgpu_cdna2_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238 +{amdgpu_cdna2_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239 +{amdgpu_cdna2_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240 +{amdgpu_cdna2_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241 +{amdgpu_cdna2_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242 +{amdgpu_cdna2_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243 +{amdgpu_cdna2_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244 +{amdgpu_cdna2_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245 +{amdgpu_cdna2_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246 +{amdgpu_cdna2_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247 +{amdgpu_cdna2_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248 +{amdgpu_cdna2_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249 +{amdgpu_cdna2_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250 +{amdgpu_cdna2_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251 +{amdgpu_cdna2_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252 +{amdgpu_cdna2_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253 +{amdgpu_cdna2_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254 +{amdgpu_cdna2_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255 +}; // end ENC_VOPC_insn_table +const amdgpu_cdna2_insn_table amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table = { +{amdgpu_cdna2_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +}; // end ENC_VINTRP_insn_table diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h new file mode 100644 index 0000000000..8515f8630b --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h @@ -0,0 +1,617 @@ +#ifndef DYNINST_AMDGPU_CDNA2_SYS_REGS_H +#define DYNINST_AMDGPU_CDNA2_SYS_REGS_H +DEF_REGISTER(s0, Arch_amdgpu_cdna2| SGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(s1, Arch_amdgpu_cdna2| SGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(s2, Arch_amdgpu_cdna2| SGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(s3, Arch_amdgpu_cdna2| SGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(s4, Arch_amdgpu_cdna2| SGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(s5, Arch_amdgpu_cdna2| SGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(s6, Arch_amdgpu_cdna2| SGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(s7, Arch_amdgpu_cdna2| SGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(s8, Arch_amdgpu_cdna2| SGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(s9, Arch_amdgpu_cdna2| SGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(s10, Arch_amdgpu_cdna2| SGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(s11, Arch_amdgpu_cdna2| SGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(s12, Arch_amdgpu_cdna2| SGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(s13, Arch_amdgpu_cdna2| SGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(s14, Arch_amdgpu_cdna2| SGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(s15, Arch_amdgpu_cdna2| SGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(s16, Arch_amdgpu_cdna2| SGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(s17, Arch_amdgpu_cdna2| SGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(s18, Arch_amdgpu_cdna2| SGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(s19, Arch_amdgpu_cdna2| SGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(s20, Arch_amdgpu_cdna2| SGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(s21, Arch_amdgpu_cdna2| SGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(s22, Arch_amdgpu_cdna2| SGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(s23, Arch_amdgpu_cdna2| SGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(s24, Arch_amdgpu_cdna2| SGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(s25, Arch_amdgpu_cdna2| SGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(s26, Arch_amdgpu_cdna2| SGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(s27, Arch_amdgpu_cdna2| SGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(s28, Arch_amdgpu_cdna2| SGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(s29, Arch_amdgpu_cdna2| SGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(s30, Arch_amdgpu_cdna2| SGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(s31, Arch_amdgpu_cdna2| SGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(s32, Arch_amdgpu_cdna2| SGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(s33, Arch_amdgpu_cdna2| SGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(s34, Arch_amdgpu_cdna2| SGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(s35, Arch_amdgpu_cdna2| SGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(s36, Arch_amdgpu_cdna2| SGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(s37, Arch_amdgpu_cdna2| SGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(s38, Arch_amdgpu_cdna2| SGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(s39, Arch_amdgpu_cdna2| SGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(s40, Arch_amdgpu_cdna2| SGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(s41, Arch_amdgpu_cdna2| SGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(s42, Arch_amdgpu_cdna2| SGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(s43, Arch_amdgpu_cdna2| SGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(s44, Arch_amdgpu_cdna2| SGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(s45, Arch_amdgpu_cdna2| SGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(s46, Arch_amdgpu_cdna2| SGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(s47, Arch_amdgpu_cdna2| SGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(s48, Arch_amdgpu_cdna2| SGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(s49, Arch_amdgpu_cdna2| SGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(s50, Arch_amdgpu_cdna2| SGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(s51, Arch_amdgpu_cdna2| SGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(s52, Arch_amdgpu_cdna2| SGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(s53, Arch_amdgpu_cdna2| SGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(s54, Arch_amdgpu_cdna2| SGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(s55, Arch_amdgpu_cdna2| SGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(s56, Arch_amdgpu_cdna2| SGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(s57, Arch_amdgpu_cdna2| SGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(s58, Arch_amdgpu_cdna2| SGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(s59, Arch_amdgpu_cdna2| SGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(s60, Arch_amdgpu_cdna2| SGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(s61, Arch_amdgpu_cdna2| SGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(s62, Arch_amdgpu_cdna2| SGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(s63, Arch_amdgpu_cdna2| SGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(s64, Arch_amdgpu_cdna2| SGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(s65, Arch_amdgpu_cdna2| SGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(s66, Arch_amdgpu_cdna2| SGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(s67, Arch_amdgpu_cdna2| SGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(s68, Arch_amdgpu_cdna2| SGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(s69, Arch_amdgpu_cdna2| SGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(s70, Arch_amdgpu_cdna2| SGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(s71, Arch_amdgpu_cdna2| SGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(s72, Arch_amdgpu_cdna2| SGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(s73, Arch_amdgpu_cdna2| SGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(s74, Arch_amdgpu_cdna2| SGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(s75, Arch_amdgpu_cdna2| SGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(s76, Arch_amdgpu_cdna2| SGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(s77, Arch_amdgpu_cdna2| SGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(s78, Arch_amdgpu_cdna2| SGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(s79, Arch_amdgpu_cdna2| SGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(s80, Arch_amdgpu_cdna2| SGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(s81, Arch_amdgpu_cdna2| SGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(s82, Arch_amdgpu_cdna2| SGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(s83, Arch_amdgpu_cdna2| SGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(s84, Arch_amdgpu_cdna2| SGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(s85, Arch_amdgpu_cdna2| SGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(s86, Arch_amdgpu_cdna2| SGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(s87, Arch_amdgpu_cdna2| SGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(s88, Arch_amdgpu_cdna2| SGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(s89, Arch_amdgpu_cdna2| SGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(s90, Arch_amdgpu_cdna2| SGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(s91, Arch_amdgpu_cdna2| SGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(s92, Arch_amdgpu_cdna2| SGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(s93, Arch_amdgpu_cdna2| SGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(s94, Arch_amdgpu_cdna2| SGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(s95, Arch_amdgpu_cdna2| SGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(s96, Arch_amdgpu_cdna2| SGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(s97, Arch_amdgpu_cdna2| SGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(s98, Arch_amdgpu_cdna2| SGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(s99, Arch_amdgpu_cdna2| SGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(s100, Arch_amdgpu_cdna2| SGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(s101, Arch_amdgpu_cdna2| SGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(v0, Arch_amdgpu_cdna2| VGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(v1, Arch_amdgpu_cdna2| VGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(v2, Arch_amdgpu_cdna2| VGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(v3, Arch_amdgpu_cdna2| VGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(v4, Arch_amdgpu_cdna2| VGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(v5, Arch_amdgpu_cdna2| VGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(v6, Arch_amdgpu_cdna2| VGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(v7, Arch_amdgpu_cdna2| VGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(v8, Arch_amdgpu_cdna2| VGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(v9, Arch_amdgpu_cdna2| VGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(v10, Arch_amdgpu_cdna2| VGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(v11, Arch_amdgpu_cdna2| VGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(v12, Arch_amdgpu_cdna2| VGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(v13, Arch_amdgpu_cdna2| VGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(v14, Arch_amdgpu_cdna2| VGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(v15, Arch_amdgpu_cdna2| VGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(v16, Arch_amdgpu_cdna2| VGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(v17, Arch_amdgpu_cdna2| VGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(v18, Arch_amdgpu_cdna2| VGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(v19, Arch_amdgpu_cdna2| VGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(v20, Arch_amdgpu_cdna2| VGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(v21, Arch_amdgpu_cdna2| VGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(v22, Arch_amdgpu_cdna2| VGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(v23, Arch_amdgpu_cdna2| VGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(v24, Arch_amdgpu_cdna2| VGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(v25, Arch_amdgpu_cdna2| VGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(v26, Arch_amdgpu_cdna2| VGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(v27, Arch_amdgpu_cdna2| VGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(v28, Arch_amdgpu_cdna2| VGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(v29, Arch_amdgpu_cdna2| VGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(v30, Arch_amdgpu_cdna2| VGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(v31, Arch_amdgpu_cdna2| VGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(v32, Arch_amdgpu_cdna2| VGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(v33, Arch_amdgpu_cdna2| VGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(v34, Arch_amdgpu_cdna2| VGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(v35, Arch_amdgpu_cdna2| VGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(v36, Arch_amdgpu_cdna2| VGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(v37, Arch_amdgpu_cdna2| VGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(v38, Arch_amdgpu_cdna2| VGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(v39, Arch_amdgpu_cdna2| VGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(v40, Arch_amdgpu_cdna2| VGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(v41, Arch_amdgpu_cdna2| VGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(v42, Arch_amdgpu_cdna2| VGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(v43, Arch_amdgpu_cdna2| VGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(v44, Arch_amdgpu_cdna2| VGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(v45, Arch_amdgpu_cdna2| VGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(v46, Arch_amdgpu_cdna2| VGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(v47, Arch_amdgpu_cdna2| VGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(v48, Arch_amdgpu_cdna2| VGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(v49, Arch_amdgpu_cdna2| VGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(v50, Arch_amdgpu_cdna2| VGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(v51, Arch_amdgpu_cdna2| VGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(v52, Arch_amdgpu_cdna2| VGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(v53, Arch_amdgpu_cdna2| VGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(v54, Arch_amdgpu_cdna2| VGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(v55, Arch_amdgpu_cdna2| VGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(v56, Arch_amdgpu_cdna2| VGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(v57, Arch_amdgpu_cdna2| VGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(v58, Arch_amdgpu_cdna2| VGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(v59, Arch_amdgpu_cdna2| VGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(v60, Arch_amdgpu_cdna2| VGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(v61, Arch_amdgpu_cdna2| VGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(v62, Arch_amdgpu_cdna2| VGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(v63, Arch_amdgpu_cdna2| VGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(v64, Arch_amdgpu_cdna2| VGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(v65, Arch_amdgpu_cdna2| VGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(v66, Arch_amdgpu_cdna2| VGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(v67, Arch_amdgpu_cdna2| VGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(v68, Arch_amdgpu_cdna2| VGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(v69, Arch_amdgpu_cdna2| VGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(v70, Arch_amdgpu_cdna2| VGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(v71, Arch_amdgpu_cdna2| VGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(v72, Arch_amdgpu_cdna2| VGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(v73, Arch_amdgpu_cdna2| VGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(v74, Arch_amdgpu_cdna2| VGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(v75, Arch_amdgpu_cdna2| VGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(v76, Arch_amdgpu_cdna2| VGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(v77, Arch_amdgpu_cdna2| VGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(v78, Arch_amdgpu_cdna2| VGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(v79, Arch_amdgpu_cdna2| VGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(v80, Arch_amdgpu_cdna2| VGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(v81, Arch_amdgpu_cdna2| VGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(v82, Arch_amdgpu_cdna2| VGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(v83, Arch_amdgpu_cdna2| VGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(v84, Arch_amdgpu_cdna2| VGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(v85, Arch_amdgpu_cdna2| VGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(v86, Arch_amdgpu_cdna2| VGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(v87, Arch_amdgpu_cdna2| VGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(v88, Arch_amdgpu_cdna2| VGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(v89, Arch_amdgpu_cdna2| VGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(v90, Arch_amdgpu_cdna2| VGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(v91, Arch_amdgpu_cdna2| VGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(v92, Arch_amdgpu_cdna2| VGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(v93, Arch_amdgpu_cdna2| VGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(v94, Arch_amdgpu_cdna2| VGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(v95, Arch_amdgpu_cdna2| VGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(v96, Arch_amdgpu_cdna2| VGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(v97, Arch_amdgpu_cdna2| VGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(v98, Arch_amdgpu_cdna2| VGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(v99, Arch_amdgpu_cdna2| VGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(v100, Arch_amdgpu_cdna2| VGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(v101, Arch_amdgpu_cdna2| VGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(v102, Arch_amdgpu_cdna2| VGPR | BITS_32 | 102 , "amdgpu_cdna2"); +DEF_REGISTER(v103, Arch_amdgpu_cdna2| VGPR | BITS_32 | 103 , "amdgpu_cdna2"); +DEF_REGISTER(v104, Arch_amdgpu_cdna2| VGPR | BITS_32 | 104 , "amdgpu_cdna2"); +DEF_REGISTER(v105, Arch_amdgpu_cdna2| VGPR | BITS_32 | 105 , "amdgpu_cdna2"); +DEF_REGISTER(v106, Arch_amdgpu_cdna2| VGPR | BITS_32 | 106 , "amdgpu_cdna2"); +DEF_REGISTER(v107, Arch_amdgpu_cdna2| VGPR | BITS_32 | 107 , "amdgpu_cdna2"); +DEF_REGISTER(v108, Arch_amdgpu_cdna2| VGPR | BITS_32 | 108 , "amdgpu_cdna2"); +DEF_REGISTER(v109, Arch_amdgpu_cdna2| VGPR | BITS_32 | 109 , "amdgpu_cdna2"); +DEF_REGISTER(v110, Arch_amdgpu_cdna2| VGPR | BITS_32 | 110 , "amdgpu_cdna2"); +DEF_REGISTER(v111, Arch_amdgpu_cdna2| VGPR | BITS_32 | 111 , "amdgpu_cdna2"); +DEF_REGISTER(v112, Arch_amdgpu_cdna2| VGPR | BITS_32 | 112 , "amdgpu_cdna2"); +DEF_REGISTER(v113, Arch_amdgpu_cdna2| VGPR | BITS_32 | 113 , "amdgpu_cdna2"); +DEF_REGISTER(v114, Arch_amdgpu_cdna2| VGPR | BITS_32 | 114 , "amdgpu_cdna2"); +DEF_REGISTER(v115, Arch_amdgpu_cdna2| VGPR | BITS_32 | 115 , "amdgpu_cdna2"); +DEF_REGISTER(v116, Arch_amdgpu_cdna2| VGPR | BITS_32 | 116 , "amdgpu_cdna2"); +DEF_REGISTER(v117, Arch_amdgpu_cdna2| VGPR | BITS_32 | 117 , "amdgpu_cdna2"); +DEF_REGISTER(v118, Arch_amdgpu_cdna2| VGPR | BITS_32 | 118 , "amdgpu_cdna2"); +DEF_REGISTER(v119, Arch_amdgpu_cdna2| VGPR | BITS_32 | 119 , "amdgpu_cdna2"); +DEF_REGISTER(v120, Arch_amdgpu_cdna2| VGPR | BITS_32 | 120 , "amdgpu_cdna2"); +DEF_REGISTER(v121, Arch_amdgpu_cdna2| VGPR | BITS_32 | 121 , "amdgpu_cdna2"); +DEF_REGISTER(v122, Arch_amdgpu_cdna2| VGPR | BITS_32 | 122 , "amdgpu_cdna2"); +DEF_REGISTER(v123, Arch_amdgpu_cdna2| VGPR | BITS_32 | 123 , "amdgpu_cdna2"); +DEF_REGISTER(v124, Arch_amdgpu_cdna2| VGPR | BITS_32 | 124 , "amdgpu_cdna2"); +DEF_REGISTER(v125, Arch_amdgpu_cdna2| VGPR | BITS_32 | 125 , "amdgpu_cdna2"); +DEF_REGISTER(v126, Arch_amdgpu_cdna2| VGPR | BITS_32 | 126 , "amdgpu_cdna2"); +DEF_REGISTER(v127, Arch_amdgpu_cdna2| VGPR | BITS_32 | 127 , "amdgpu_cdna2"); +DEF_REGISTER(v128, Arch_amdgpu_cdna2| VGPR | BITS_32 | 128 , "amdgpu_cdna2"); +DEF_REGISTER(v129, Arch_amdgpu_cdna2| VGPR | BITS_32 | 129 , "amdgpu_cdna2"); +DEF_REGISTER(v130, Arch_amdgpu_cdna2| VGPR | BITS_32 | 130 , "amdgpu_cdna2"); +DEF_REGISTER(v131, Arch_amdgpu_cdna2| VGPR | BITS_32 | 131 , "amdgpu_cdna2"); +DEF_REGISTER(v132, Arch_amdgpu_cdna2| VGPR | BITS_32 | 132 , "amdgpu_cdna2"); +DEF_REGISTER(v133, Arch_amdgpu_cdna2| VGPR | BITS_32 | 133 , "amdgpu_cdna2"); +DEF_REGISTER(v134, Arch_amdgpu_cdna2| VGPR | BITS_32 | 134 , "amdgpu_cdna2"); +DEF_REGISTER(v135, Arch_amdgpu_cdna2| VGPR | BITS_32 | 135 , "amdgpu_cdna2"); +DEF_REGISTER(v136, Arch_amdgpu_cdna2| VGPR | BITS_32 | 136 , "amdgpu_cdna2"); +DEF_REGISTER(v137, Arch_amdgpu_cdna2| VGPR | BITS_32 | 137 , "amdgpu_cdna2"); +DEF_REGISTER(v138, Arch_amdgpu_cdna2| VGPR | BITS_32 | 138 , "amdgpu_cdna2"); +DEF_REGISTER(v139, Arch_amdgpu_cdna2| VGPR | BITS_32 | 139 , "amdgpu_cdna2"); +DEF_REGISTER(v140, Arch_amdgpu_cdna2| VGPR | BITS_32 | 140 , "amdgpu_cdna2"); +DEF_REGISTER(v141, Arch_amdgpu_cdna2| VGPR | BITS_32 | 141 , "amdgpu_cdna2"); +DEF_REGISTER(v142, Arch_amdgpu_cdna2| VGPR | BITS_32 | 142 , "amdgpu_cdna2"); +DEF_REGISTER(v143, Arch_amdgpu_cdna2| VGPR | BITS_32 | 143 , "amdgpu_cdna2"); +DEF_REGISTER(v144, Arch_amdgpu_cdna2| VGPR | BITS_32 | 144 , "amdgpu_cdna2"); +DEF_REGISTER(v145, Arch_amdgpu_cdna2| VGPR | BITS_32 | 145 , "amdgpu_cdna2"); +DEF_REGISTER(v146, Arch_amdgpu_cdna2| VGPR | BITS_32 | 146 , "amdgpu_cdna2"); +DEF_REGISTER(v147, Arch_amdgpu_cdna2| VGPR | BITS_32 | 147 , "amdgpu_cdna2"); +DEF_REGISTER(v148, Arch_amdgpu_cdna2| VGPR | BITS_32 | 148 , "amdgpu_cdna2"); +DEF_REGISTER(v149, Arch_amdgpu_cdna2| VGPR | BITS_32 | 149 , "amdgpu_cdna2"); +DEF_REGISTER(v150, Arch_amdgpu_cdna2| VGPR | BITS_32 | 150 , "amdgpu_cdna2"); +DEF_REGISTER(v151, Arch_amdgpu_cdna2| VGPR | BITS_32 | 151 , "amdgpu_cdna2"); +DEF_REGISTER(v152, Arch_amdgpu_cdna2| VGPR | BITS_32 | 152 , "amdgpu_cdna2"); +DEF_REGISTER(v153, Arch_amdgpu_cdna2| VGPR | BITS_32 | 153 , "amdgpu_cdna2"); +DEF_REGISTER(v154, Arch_amdgpu_cdna2| VGPR | BITS_32 | 154 , "amdgpu_cdna2"); +DEF_REGISTER(v155, Arch_amdgpu_cdna2| VGPR | BITS_32 | 155 , "amdgpu_cdna2"); +DEF_REGISTER(v156, Arch_amdgpu_cdna2| VGPR | BITS_32 | 156 , "amdgpu_cdna2"); +DEF_REGISTER(v157, Arch_amdgpu_cdna2| VGPR | BITS_32 | 157 , "amdgpu_cdna2"); +DEF_REGISTER(v158, Arch_amdgpu_cdna2| VGPR | BITS_32 | 158 , "amdgpu_cdna2"); +DEF_REGISTER(v159, Arch_amdgpu_cdna2| VGPR | BITS_32 | 159 , "amdgpu_cdna2"); +DEF_REGISTER(v160, Arch_amdgpu_cdna2| VGPR | BITS_32 | 160 , "amdgpu_cdna2"); +DEF_REGISTER(v161, Arch_amdgpu_cdna2| VGPR | BITS_32 | 161 , "amdgpu_cdna2"); +DEF_REGISTER(v162, Arch_amdgpu_cdna2| VGPR | BITS_32 | 162 , "amdgpu_cdna2"); +DEF_REGISTER(v163, Arch_amdgpu_cdna2| VGPR | BITS_32 | 163 , "amdgpu_cdna2"); +DEF_REGISTER(v164, Arch_amdgpu_cdna2| VGPR | BITS_32 | 164 , "amdgpu_cdna2"); +DEF_REGISTER(v165, Arch_amdgpu_cdna2| VGPR | BITS_32 | 165 , "amdgpu_cdna2"); +DEF_REGISTER(v166, Arch_amdgpu_cdna2| VGPR | BITS_32 | 166 , "amdgpu_cdna2"); +DEF_REGISTER(v167, Arch_amdgpu_cdna2| VGPR | BITS_32 | 167 , "amdgpu_cdna2"); +DEF_REGISTER(v168, Arch_amdgpu_cdna2| VGPR | BITS_32 | 168 , "amdgpu_cdna2"); +DEF_REGISTER(v169, Arch_amdgpu_cdna2| VGPR | BITS_32 | 169 , "amdgpu_cdna2"); +DEF_REGISTER(v170, Arch_amdgpu_cdna2| VGPR | BITS_32 | 170 , "amdgpu_cdna2"); +DEF_REGISTER(v171, Arch_amdgpu_cdna2| VGPR | BITS_32 | 171 , "amdgpu_cdna2"); +DEF_REGISTER(v172, Arch_amdgpu_cdna2| VGPR | BITS_32 | 172 , "amdgpu_cdna2"); +DEF_REGISTER(v173, Arch_amdgpu_cdna2| VGPR | BITS_32 | 173 , "amdgpu_cdna2"); +DEF_REGISTER(v174, Arch_amdgpu_cdna2| VGPR | BITS_32 | 174 , "amdgpu_cdna2"); +DEF_REGISTER(v175, Arch_amdgpu_cdna2| VGPR | BITS_32 | 175 , "amdgpu_cdna2"); +DEF_REGISTER(v176, Arch_amdgpu_cdna2| VGPR | BITS_32 | 176 , "amdgpu_cdna2"); +DEF_REGISTER(v177, Arch_amdgpu_cdna2| VGPR | BITS_32 | 177 , "amdgpu_cdna2"); +DEF_REGISTER(v178, Arch_amdgpu_cdna2| VGPR | BITS_32 | 178 , "amdgpu_cdna2"); +DEF_REGISTER(v179, Arch_amdgpu_cdna2| VGPR | BITS_32 | 179 , "amdgpu_cdna2"); +DEF_REGISTER(v180, Arch_amdgpu_cdna2| VGPR | BITS_32 | 180 , "amdgpu_cdna2"); +DEF_REGISTER(v181, Arch_amdgpu_cdna2| VGPR | BITS_32 | 181 , "amdgpu_cdna2"); +DEF_REGISTER(v182, Arch_amdgpu_cdna2| VGPR | BITS_32 | 182 , "amdgpu_cdna2"); +DEF_REGISTER(v183, Arch_amdgpu_cdna2| VGPR | BITS_32 | 183 , "amdgpu_cdna2"); +DEF_REGISTER(v184, Arch_amdgpu_cdna2| VGPR | BITS_32 | 184 , "amdgpu_cdna2"); +DEF_REGISTER(v185, Arch_amdgpu_cdna2| VGPR | BITS_32 | 185 , "amdgpu_cdna2"); +DEF_REGISTER(v186, Arch_amdgpu_cdna2| VGPR | BITS_32 | 186 , "amdgpu_cdna2"); +DEF_REGISTER(v187, Arch_amdgpu_cdna2| VGPR | BITS_32 | 187 , "amdgpu_cdna2"); +DEF_REGISTER(v188, Arch_amdgpu_cdna2| VGPR | BITS_32 | 188 , "amdgpu_cdna2"); +DEF_REGISTER(v189, Arch_amdgpu_cdna2| VGPR | BITS_32 | 189 , "amdgpu_cdna2"); +DEF_REGISTER(v190, Arch_amdgpu_cdna2| VGPR | BITS_32 | 190 , "amdgpu_cdna2"); +DEF_REGISTER(v191, Arch_amdgpu_cdna2| VGPR | BITS_32 | 191 , "amdgpu_cdna2"); +DEF_REGISTER(v192, Arch_amdgpu_cdna2| VGPR | BITS_32 | 192 , "amdgpu_cdna2"); +DEF_REGISTER(v193, Arch_amdgpu_cdna2| VGPR | BITS_32 | 193 , "amdgpu_cdna2"); +DEF_REGISTER(v194, Arch_amdgpu_cdna2| VGPR | BITS_32 | 194 , "amdgpu_cdna2"); +DEF_REGISTER(v195, Arch_amdgpu_cdna2| VGPR | BITS_32 | 195 , "amdgpu_cdna2"); +DEF_REGISTER(v196, Arch_amdgpu_cdna2| VGPR | BITS_32 | 196 , "amdgpu_cdna2"); +DEF_REGISTER(v197, Arch_amdgpu_cdna2| VGPR | BITS_32 | 197 , "amdgpu_cdna2"); +DEF_REGISTER(v198, Arch_amdgpu_cdna2| VGPR | BITS_32 | 198 , "amdgpu_cdna2"); +DEF_REGISTER(v199, Arch_amdgpu_cdna2| VGPR | BITS_32 | 199 , "amdgpu_cdna2"); +DEF_REGISTER(v200, Arch_amdgpu_cdna2| VGPR | BITS_32 | 200 , "amdgpu_cdna2"); +DEF_REGISTER(v201, Arch_amdgpu_cdna2| VGPR | BITS_32 | 201 , "amdgpu_cdna2"); +DEF_REGISTER(v202, Arch_amdgpu_cdna2| VGPR | BITS_32 | 202 , "amdgpu_cdna2"); +DEF_REGISTER(v203, Arch_amdgpu_cdna2| VGPR | BITS_32 | 203 , "amdgpu_cdna2"); +DEF_REGISTER(v204, Arch_amdgpu_cdna2| VGPR | BITS_32 | 204 , "amdgpu_cdna2"); +DEF_REGISTER(v205, Arch_amdgpu_cdna2| VGPR | BITS_32 | 205 , "amdgpu_cdna2"); +DEF_REGISTER(v206, Arch_amdgpu_cdna2| VGPR | BITS_32 | 206 , "amdgpu_cdna2"); +DEF_REGISTER(v207, Arch_amdgpu_cdna2| VGPR | BITS_32 | 207 , "amdgpu_cdna2"); +DEF_REGISTER(v208, Arch_amdgpu_cdna2| VGPR | BITS_32 | 208 , "amdgpu_cdna2"); +DEF_REGISTER(v209, Arch_amdgpu_cdna2| VGPR | BITS_32 | 209 , "amdgpu_cdna2"); +DEF_REGISTER(v210, Arch_amdgpu_cdna2| VGPR | BITS_32 | 210 , "amdgpu_cdna2"); +DEF_REGISTER(v211, Arch_amdgpu_cdna2| VGPR | BITS_32 | 211 , "amdgpu_cdna2"); +DEF_REGISTER(v212, Arch_amdgpu_cdna2| VGPR | BITS_32 | 212 , "amdgpu_cdna2"); +DEF_REGISTER(v213, Arch_amdgpu_cdna2| VGPR | BITS_32 | 213 , "amdgpu_cdna2"); +DEF_REGISTER(v214, Arch_amdgpu_cdna2| VGPR | BITS_32 | 214 , "amdgpu_cdna2"); +DEF_REGISTER(v215, Arch_amdgpu_cdna2| VGPR | BITS_32 | 215 , "amdgpu_cdna2"); +DEF_REGISTER(v216, Arch_amdgpu_cdna2| VGPR | BITS_32 | 216 , "amdgpu_cdna2"); +DEF_REGISTER(v217, Arch_amdgpu_cdna2| VGPR | BITS_32 | 217 , "amdgpu_cdna2"); +DEF_REGISTER(v218, Arch_amdgpu_cdna2| VGPR | BITS_32 | 218 , "amdgpu_cdna2"); +DEF_REGISTER(v219, Arch_amdgpu_cdna2| VGPR | BITS_32 | 219 , "amdgpu_cdna2"); +DEF_REGISTER(v220, Arch_amdgpu_cdna2| VGPR | BITS_32 | 220 , "amdgpu_cdna2"); +DEF_REGISTER(v221, Arch_amdgpu_cdna2| VGPR | BITS_32 | 221 , "amdgpu_cdna2"); +DEF_REGISTER(v222, Arch_amdgpu_cdna2| VGPR | BITS_32 | 222 , "amdgpu_cdna2"); +DEF_REGISTER(v223, Arch_amdgpu_cdna2| VGPR | BITS_32 | 223 , "amdgpu_cdna2"); +DEF_REGISTER(v224, Arch_amdgpu_cdna2| VGPR | BITS_32 | 224 , "amdgpu_cdna2"); +DEF_REGISTER(v225, Arch_amdgpu_cdna2| VGPR | BITS_32 | 225 , "amdgpu_cdna2"); +DEF_REGISTER(v226, Arch_amdgpu_cdna2| VGPR | BITS_32 | 226 , "amdgpu_cdna2"); +DEF_REGISTER(v227, Arch_amdgpu_cdna2| VGPR | BITS_32 | 227 , "amdgpu_cdna2"); +DEF_REGISTER(v228, Arch_amdgpu_cdna2| VGPR | BITS_32 | 228 , "amdgpu_cdna2"); +DEF_REGISTER(v229, Arch_amdgpu_cdna2| VGPR | BITS_32 | 229 , "amdgpu_cdna2"); +DEF_REGISTER(v230, Arch_amdgpu_cdna2| VGPR | BITS_32 | 230 , "amdgpu_cdna2"); +DEF_REGISTER(v231, Arch_amdgpu_cdna2| VGPR | BITS_32 | 231 , "amdgpu_cdna2"); +DEF_REGISTER(v232, Arch_amdgpu_cdna2| VGPR | BITS_32 | 232 , "amdgpu_cdna2"); +DEF_REGISTER(v233, Arch_amdgpu_cdna2| VGPR | BITS_32 | 233 , "amdgpu_cdna2"); +DEF_REGISTER(v234, Arch_amdgpu_cdna2| VGPR | BITS_32 | 234 , "amdgpu_cdna2"); +DEF_REGISTER(v235, Arch_amdgpu_cdna2| VGPR | BITS_32 | 235 , "amdgpu_cdna2"); +DEF_REGISTER(v236, Arch_amdgpu_cdna2| VGPR | BITS_32 | 236 , "amdgpu_cdna2"); +DEF_REGISTER(v237, Arch_amdgpu_cdna2| VGPR | BITS_32 | 237 , "amdgpu_cdna2"); +DEF_REGISTER(v238, Arch_amdgpu_cdna2| VGPR | BITS_32 | 238 , "amdgpu_cdna2"); +DEF_REGISTER(v239, Arch_amdgpu_cdna2| VGPR | BITS_32 | 239 , "amdgpu_cdna2"); +DEF_REGISTER(v240, Arch_amdgpu_cdna2| VGPR | BITS_32 | 240 , "amdgpu_cdna2"); +DEF_REGISTER(v241, Arch_amdgpu_cdna2| VGPR | BITS_32 | 241 , "amdgpu_cdna2"); +DEF_REGISTER(v242, Arch_amdgpu_cdna2| VGPR | BITS_32 | 242 , "amdgpu_cdna2"); +DEF_REGISTER(v243, Arch_amdgpu_cdna2| VGPR | BITS_32 | 243 , "amdgpu_cdna2"); +DEF_REGISTER(v244, Arch_amdgpu_cdna2| VGPR | BITS_32 | 244 , "amdgpu_cdna2"); +DEF_REGISTER(v245, Arch_amdgpu_cdna2| VGPR | BITS_32 | 245 , "amdgpu_cdna2"); +DEF_REGISTER(v246, Arch_amdgpu_cdna2| VGPR | BITS_32 | 246 , "amdgpu_cdna2"); +DEF_REGISTER(v247, Arch_amdgpu_cdna2| VGPR | BITS_32 | 247 , "amdgpu_cdna2"); +DEF_REGISTER(v248, Arch_amdgpu_cdna2| VGPR | BITS_32 | 248 , "amdgpu_cdna2"); +DEF_REGISTER(v249, Arch_amdgpu_cdna2| VGPR | BITS_32 | 249 , "amdgpu_cdna2"); +DEF_REGISTER(v250, Arch_amdgpu_cdna2| VGPR | BITS_32 | 250 , "amdgpu_cdna2"); +DEF_REGISTER(v251, Arch_amdgpu_cdna2| VGPR | BITS_32 | 251 , "amdgpu_cdna2"); +DEF_REGISTER(v252, Arch_amdgpu_cdna2| VGPR | BITS_32 | 252 , "amdgpu_cdna2"); +DEF_REGISTER(v253, Arch_amdgpu_cdna2| VGPR | BITS_32 | 253 , "amdgpu_cdna2"); +DEF_REGISTER(v254, Arch_amdgpu_cdna2| VGPR | BITS_32 | 254 , "amdgpu_cdna2"); +DEF_REGISTER(v255, Arch_amdgpu_cdna2| VGPR | BITS_32 | 255 , "amdgpu_cdna2"); +DEF_REGISTER(acc0, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 0 , "amdgpu_cdna2"); +DEF_REGISTER(acc1, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 1 , "amdgpu_cdna2"); +DEF_REGISTER(acc2, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 2 , "amdgpu_cdna2"); +DEF_REGISTER(acc3, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 3 , "amdgpu_cdna2"); +DEF_REGISTER(acc4, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 4 , "amdgpu_cdna2"); +DEF_REGISTER(acc5, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 5 , "amdgpu_cdna2"); +DEF_REGISTER(acc6, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 6 , "amdgpu_cdna2"); +DEF_REGISTER(acc7, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 7 , "amdgpu_cdna2"); +DEF_REGISTER(acc8, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 8 , "amdgpu_cdna2"); +DEF_REGISTER(acc9, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 9 , "amdgpu_cdna2"); +DEF_REGISTER(acc10, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 10 , "amdgpu_cdna2"); +DEF_REGISTER(acc11, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 11 , "amdgpu_cdna2"); +DEF_REGISTER(acc12, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 12 , "amdgpu_cdna2"); +DEF_REGISTER(acc13, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 13 , "amdgpu_cdna2"); +DEF_REGISTER(acc14, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 14 , "amdgpu_cdna2"); +DEF_REGISTER(acc15, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 15 , "amdgpu_cdna2"); +DEF_REGISTER(acc16, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 16 , "amdgpu_cdna2"); +DEF_REGISTER(acc17, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 17 , "amdgpu_cdna2"); +DEF_REGISTER(acc18, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 18 , "amdgpu_cdna2"); +DEF_REGISTER(acc19, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 19 , "amdgpu_cdna2"); +DEF_REGISTER(acc20, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 20 , "amdgpu_cdna2"); +DEF_REGISTER(acc21, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 21 , "amdgpu_cdna2"); +DEF_REGISTER(acc22, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 22 , "amdgpu_cdna2"); +DEF_REGISTER(acc23, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 23 , "amdgpu_cdna2"); +DEF_REGISTER(acc24, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 24 , "amdgpu_cdna2"); +DEF_REGISTER(acc25, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 25 , "amdgpu_cdna2"); +DEF_REGISTER(acc26, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 26 , "amdgpu_cdna2"); +DEF_REGISTER(acc27, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 27 , "amdgpu_cdna2"); +DEF_REGISTER(acc28, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 28 , "amdgpu_cdna2"); +DEF_REGISTER(acc29, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 29 , "amdgpu_cdna2"); +DEF_REGISTER(acc30, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 30 , "amdgpu_cdna2"); +DEF_REGISTER(acc31, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 31 , "amdgpu_cdna2"); +DEF_REGISTER(acc32, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 32 , "amdgpu_cdna2"); +DEF_REGISTER(acc33, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 33 , "amdgpu_cdna2"); +DEF_REGISTER(acc34, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 34 , "amdgpu_cdna2"); +DEF_REGISTER(acc35, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 35 , "amdgpu_cdna2"); +DEF_REGISTER(acc36, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 36 , "amdgpu_cdna2"); +DEF_REGISTER(acc37, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 37 , "amdgpu_cdna2"); +DEF_REGISTER(acc38, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 38 , "amdgpu_cdna2"); +DEF_REGISTER(acc39, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 39 , "amdgpu_cdna2"); +DEF_REGISTER(acc40, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 40 , "amdgpu_cdna2"); +DEF_REGISTER(acc41, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 41 , "amdgpu_cdna2"); +DEF_REGISTER(acc42, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 42 , "amdgpu_cdna2"); +DEF_REGISTER(acc43, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 43 , "amdgpu_cdna2"); +DEF_REGISTER(acc44, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 44 , "amdgpu_cdna2"); +DEF_REGISTER(acc45, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 45 , "amdgpu_cdna2"); +DEF_REGISTER(acc46, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 46 , "amdgpu_cdna2"); +DEF_REGISTER(acc47, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 47 , "amdgpu_cdna2"); +DEF_REGISTER(acc48, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 48 , "amdgpu_cdna2"); +DEF_REGISTER(acc49, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 49 , "amdgpu_cdna2"); +DEF_REGISTER(acc50, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 50 , "amdgpu_cdna2"); +DEF_REGISTER(acc51, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 51 , "amdgpu_cdna2"); +DEF_REGISTER(acc52, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 52 , "amdgpu_cdna2"); +DEF_REGISTER(acc53, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 53 , "amdgpu_cdna2"); +DEF_REGISTER(acc54, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 54 , "amdgpu_cdna2"); +DEF_REGISTER(acc55, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 55 , "amdgpu_cdna2"); +DEF_REGISTER(acc56, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 56 , "amdgpu_cdna2"); +DEF_REGISTER(acc57, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 57 , "amdgpu_cdna2"); +DEF_REGISTER(acc58, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 58 , "amdgpu_cdna2"); +DEF_REGISTER(acc59, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 59 , "amdgpu_cdna2"); +DEF_REGISTER(acc60, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 60 , "amdgpu_cdna2"); +DEF_REGISTER(acc61, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 61 , "amdgpu_cdna2"); +DEF_REGISTER(acc62, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 62 , "amdgpu_cdna2"); +DEF_REGISTER(acc63, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 63 , "amdgpu_cdna2"); +DEF_REGISTER(acc64, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 64 , "amdgpu_cdna2"); +DEF_REGISTER(acc65, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 65 , "amdgpu_cdna2"); +DEF_REGISTER(acc66, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 66 , "amdgpu_cdna2"); +DEF_REGISTER(acc67, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 67 , "amdgpu_cdna2"); +DEF_REGISTER(acc68, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 68 , "amdgpu_cdna2"); +DEF_REGISTER(acc69, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 69 , "amdgpu_cdna2"); +DEF_REGISTER(acc70, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 70 , "amdgpu_cdna2"); +DEF_REGISTER(acc71, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 71 , "amdgpu_cdna2"); +DEF_REGISTER(acc72, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 72 , "amdgpu_cdna2"); +DEF_REGISTER(acc73, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 73 , "amdgpu_cdna2"); +DEF_REGISTER(acc74, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 74 , "amdgpu_cdna2"); +DEF_REGISTER(acc75, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 75 , "amdgpu_cdna2"); +DEF_REGISTER(acc76, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 76 , "amdgpu_cdna2"); +DEF_REGISTER(acc77, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 77 , "amdgpu_cdna2"); +DEF_REGISTER(acc78, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 78 , "amdgpu_cdna2"); +DEF_REGISTER(acc79, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 79 , "amdgpu_cdna2"); +DEF_REGISTER(acc80, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 80 , "amdgpu_cdna2"); +DEF_REGISTER(acc81, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 81 , "amdgpu_cdna2"); +DEF_REGISTER(acc82, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 82 , "amdgpu_cdna2"); +DEF_REGISTER(acc83, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 83 , "amdgpu_cdna2"); +DEF_REGISTER(acc84, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 84 , "amdgpu_cdna2"); +DEF_REGISTER(acc85, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 85 , "amdgpu_cdna2"); +DEF_REGISTER(acc86, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 86 , "amdgpu_cdna2"); +DEF_REGISTER(acc87, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 87 , "amdgpu_cdna2"); +DEF_REGISTER(acc88, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 88 , "amdgpu_cdna2"); +DEF_REGISTER(acc89, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 89 , "amdgpu_cdna2"); +DEF_REGISTER(acc90, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 90 , "amdgpu_cdna2"); +DEF_REGISTER(acc91, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 91 , "amdgpu_cdna2"); +DEF_REGISTER(acc92, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 92 , "amdgpu_cdna2"); +DEF_REGISTER(acc93, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 93 , "amdgpu_cdna2"); +DEF_REGISTER(acc94, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 94 , "amdgpu_cdna2"); +DEF_REGISTER(acc95, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 95 , "amdgpu_cdna2"); +DEF_REGISTER(acc96, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 96 , "amdgpu_cdna2"); +DEF_REGISTER(acc97, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 97 , "amdgpu_cdna2"); +DEF_REGISTER(acc98, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 98 , "amdgpu_cdna2"); +DEF_REGISTER(acc99, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 99 , "amdgpu_cdna2"); +DEF_REGISTER(acc100, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 100 , "amdgpu_cdna2"); +DEF_REGISTER(acc101, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 101 , "amdgpu_cdna2"); +DEF_REGISTER(acc102, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 102 , "amdgpu_cdna2"); +DEF_REGISTER(acc103, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 103 , "amdgpu_cdna2"); +DEF_REGISTER(acc104, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 104 , "amdgpu_cdna2"); +DEF_REGISTER(acc105, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 105 , "amdgpu_cdna2"); +DEF_REGISTER(acc106, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 106 , "amdgpu_cdna2"); +DEF_REGISTER(acc107, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 107 , "amdgpu_cdna2"); +DEF_REGISTER(acc108, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 108 , "amdgpu_cdna2"); +DEF_REGISTER(acc109, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 109 , "amdgpu_cdna2"); +DEF_REGISTER(acc110, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 110 , "amdgpu_cdna2"); +DEF_REGISTER(acc111, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 111 , "amdgpu_cdna2"); +DEF_REGISTER(acc112, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 112 , "amdgpu_cdna2"); +DEF_REGISTER(acc113, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 113 , "amdgpu_cdna2"); +DEF_REGISTER(acc114, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 114 , "amdgpu_cdna2"); +DEF_REGISTER(acc115, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 115 , "amdgpu_cdna2"); +DEF_REGISTER(acc116, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 116 , "amdgpu_cdna2"); +DEF_REGISTER(acc117, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 117 , "amdgpu_cdna2"); +DEF_REGISTER(acc118, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 118 , "amdgpu_cdna2"); +DEF_REGISTER(acc119, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 119 , "amdgpu_cdna2"); +DEF_REGISTER(acc120, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 120 , "amdgpu_cdna2"); +DEF_REGISTER(acc121, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 121 , "amdgpu_cdna2"); +DEF_REGISTER(acc122, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 122 , "amdgpu_cdna2"); +DEF_REGISTER(acc123, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 123 , "amdgpu_cdna2"); +DEF_REGISTER(acc124, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 124 , "amdgpu_cdna2"); +DEF_REGISTER(acc125, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 125 , "amdgpu_cdna2"); +DEF_REGISTER(acc126, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 126 , "amdgpu_cdna2"); +DEF_REGISTER(acc127, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 127 , "amdgpu_cdna2"); +DEF_REGISTER(acc128, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 128 , "amdgpu_cdna2"); +DEF_REGISTER(acc129, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 129 , "amdgpu_cdna2"); +DEF_REGISTER(acc130, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 130 , "amdgpu_cdna2"); +DEF_REGISTER(acc131, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 131 , "amdgpu_cdna2"); +DEF_REGISTER(acc132, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 132 , "amdgpu_cdna2"); +DEF_REGISTER(acc133, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 133 , "amdgpu_cdna2"); +DEF_REGISTER(acc134, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 134 , "amdgpu_cdna2"); +DEF_REGISTER(acc135, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 135 , "amdgpu_cdna2"); +DEF_REGISTER(acc136, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 136 , "amdgpu_cdna2"); +DEF_REGISTER(acc137, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 137 , "amdgpu_cdna2"); +DEF_REGISTER(acc138, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 138 , "amdgpu_cdna2"); +DEF_REGISTER(acc139, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 139 , "amdgpu_cdna2"); +DEF_REGISTER(acc140, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 140 , "amdgpu_cdna2"); +DEF_REGISTER(acc141, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 141 , "amdgpu_cdna2"); +DEF_REGISTER(acc142, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 142 , "amdgpu_cdna2"); +DEF_REGISTER(acc143, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 143 , "amdgpu_cdna2"); +DEF_REGISTER(acc144, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 144 , "amdgpu_cdna2"); +DEF_REGISTER(acc145, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 145 , "amdgpu_cdna2"); +DEF_REGISTER(acc146, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 146 , "amdgpu_cdna2"); +DEF_REGISTER(acc147, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 147 , "amdgpu_cdna2"); +DEF_REGISTER(acc148, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 148 , "amdgpu_cdna2"); +DEF_REGISTER(acc149, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 149 , "amdgpu_cdna2"); +DEF_REGISTER(acc150, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 150 , "amdgpu_cdna2"); +DEF_REGISTER(acc151, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 151 , "amdgpu_cdna2"); +DEF_REGISTER(acc152, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 152 , "amdgpu_cdna2"); +DEF_REGISTER(acc153, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 153 , "amdgpu_cdna2"); +DEF_REGISTER(acc154, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 154 , "amdgpu_cdna2"); +DEF_REGISTER(acc155, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 155 , "amdgpu_cdna2"); +DEF_REGISTER(acc156, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 156 , "amdgpu_cdna2"); +DEF_REGISTER(acc157, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 157 , "amdgpu_cdna2"); +DEF_REGISTER(acc158, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 158 , "amdgpu_cdna2"); +DEF_REGISTER(acc159, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 159 , "amdgpu_cdna2"); +DEF_REGISTER(acc160, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 160 , "amdgpu_cdna2"); +DEF_REGISTER(acc161, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 161 , "amdgpu_cdna2"); +DEF_REGISTER(acc162, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 162 , "amdgpu_cdna2"); +DEF_REGISTER(acc163, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 163 , "amdgpu_cdna2"); +DEF_REGISTER(acc164, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 164 , "amdgpu_cdna2"); +DEF_REGISTER(acc165, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 165 , "amdgpu_cdna2"); +DEF_REGISTER(acc166, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 166 , "amdgpu_cdna2"); +DEF_REGISTER(acc167, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 167 , "amdgpu_cdna2"); +DEF_REGISTER(acc168, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 168 , "amdgpu_cdna2"); +DEF_REGISTER(acc169, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 169 , "amdgpu_cdna2"); +DEF_REGISTER(acc170, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 170 , "amdgpu_cdna2"); +DEF_REGISTER(acc171, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 171 , "amdgpu_cdna2"); +DEF_REGISTER(acc172, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 172 , "amdgpu_cdna2"); +DEF_REGISTER(acc173, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 173 , "amdgpu_cdna2"); +DEF_REGISTER(acc174, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 174 , "amdgpu_cdna2"); +DEF_REGISTER(acc175, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 175 , "amdgpu_cdna2"); +DEF_REGISTER(acc176, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 176 , "amdgpu_cdna2"); +DEF_REGISTER(acc177, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 177 , "amdgpu_cdna2"); +DEF_REGISTER(acc178, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 178 , "amdgpu_cdna2"); +DEF_REGISTER(acc179, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 179 , "amdgpu_cdna2"); +DEF_REGISTER(acc180, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 180 , "amdgpu_cdna2"); +DEF_REGISTER(acc181, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 181 , "amdgpu_cdna2"); +DEF_REGISTER(acc182, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 182 , "amdgpu_cdna2"); +DEF_REGISTER(acc183, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 183 , "amdgpu_cdna2"); +DEF_REGISTER(acc184, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 184 , "amdgpu_cdna2"); +DEF_REGISTER(acc185, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 185 , "amdgpu_cdna2"); +DEF_REGISTER(acc186, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 186 , "amdgpu_cdna2"); +DEF_REGISTER(acc187, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 187 , "amdgpu_cdna2"); +DEF_REGISTER(acc188, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 188 , "amdgpu_cdna2"); +DEF_REGISTER(acc189, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 189 , "amdgpu_cdna2"); +DEF_REGISTER(acc190, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 190 , "amdgpu_cdna2"); +DEF_REGISTER(acc191, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 191 , "amdgpu_cdna2"); +DEF_REGISTER(acc192, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 192 , "amdgpu_cdna2"); +DEF_REGISTER(acc193, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 193 , "amdgpu_cdna2"); +DEF_REGISTER(acc194, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 194 , "amdgpu_cdna2"); +DEF_REGISTER(acc195, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 195 , "amdgpu_cdna2"); +DEF_REGISTER(acc196, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 196 , "amdgpu_cdna2"); +DEF_REGISTER(acc197, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 197 , "amdgpu_cdna2"); +DEF_REGISTER(acc198, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 198 , "amdgpu_cdna2"); +DEF_REGISTER(acc199, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 199 , "amdgpu_cdna2"); +DEF_REGISTER(acc200, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 200 , "amdgpu_cdna2"); +DEF_REGISTER(acc201, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 201 , "amdgpu_cdna2"); +DEF_REGISTER(acc202, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 202 , "amdgpu_cdna2"); +DEF_REGISTER(acc203, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 203 , "amdgpu_cdna2"); +DEF_REGISTER(acc204, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 204 , "amdgpu_cdna2"); +DEF_REGISTER(acc205, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 205 , "amdgpu_cdna2"); +DEF_REGISTER(acc206, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 206 , "amdgpu_cdna2"); +DEF_REGISTER(acc207, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 207 , "amdgpu_cdna2"); +DEF_REGISTER(acc208, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 208 , "amdgpu_cdna2"); +DEF_REGISTER(acc209, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 209 , "amdgpu_cdna2"); +DEF_REGISTER(acc210, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 210 , "amdgpu_cdna2"); +DEF_REGISTER(acc211, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 211 , "amdgpu_cdna2"); +DEF_REGISTER(acc212, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 212 , "amdgpu_cdna2"); +DEF_REGISTER(acc213, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 213 , "amdgpu_cdna2"); +DEF_REGISTER(acc214, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 214 , "amdgpu_cdna2"); +DEF_REGISTER(acc215, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 215 , "amdgpu_cdna2"); +DEF_REGISTER(acc216, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 216 , "amdgpu_cdna2"); +DEF_REGISTER(acc217, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 217 , "amdgpu_cdna2"); +DEF_REGISTER(acc218, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 218 , "amdgpu_cdna2"); +DEF_REGISTER(acc219, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 219 , "amdgpu_cdna2"); +DEF_REGISTER(acc220, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 220 , "amdgpu_cdna2"); +DEF_REGISTER(acc221, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 221 , "amdgpu_cdna2"); +DEF_REGISTER(acc222, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 222 , "amdgpu_cdna2"); +DEF_REGISTER(acc223, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 223 , "amdgpu_cdna2"); +DEF_REGISTER(acc224, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 224 , "amdgpu_cdna2"); +DEF_REGISTER(acc225, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 225 , "amdgpu_cdna2"); +DEF_REGISTER(acc226, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 226 , "amdgpu_cdna2"); +DEF_REGISTER(acc227, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 227 , "amdgpu_cdna2"); +DEF_REGISTER(acc228, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 228 , "amdgpu_cdna2"); +DEF_REGISTER(acc229, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 229 , "amdgpu_cdna2"); +DEF_REGISTER(acc230, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 230 , "amdgpu_cdna2"); +DEF_REGISTER(acc231, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 231 , "amdgpu_cdna2"); +DEF_REGISTER(acc232, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 232 , "amdgpu_cdna2"); +DEF_REGISTER(acc233, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 233 , "amdgpu_cdna2"); +DEF_REGISTER(acc234, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 234 , "amdgpu_cdna2"); +DEF_REGISTER(acc235, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 235 , "amdgpu_cdna2"); +DEF_REGISTER(acc236, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 236 , "amdgpu_cdna2"); +DEF_REGISTER(acc237, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 237 , "amdgpu_cdna2"); +DEF_REGISTER(acc238, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 238 , "amdgpu_cdna2"); +DEF_REGISTER(acc239, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 239 , "amdgpu_cdna2"); +DEF_REGISTER(acc240, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 240 , "amdgpu_cdna2"); +DEF_REGISTER(acc241, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 241 , "amdgpu_cdna2"); +DEF_REGISTER(acc242, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 242 , "amdgpu_cdna2"); +DEF_REGISTER(acc243, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 243 , "amdgpu_cdna2"); +DEF_REGISTER(acc244, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 244 , "amdgpu_cdna2"); +DEF_REGISTER(acc245, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 245 , "amdgpu_cdna2"); +DEF_REGISTER(acc246, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 246 , "amdgpu_cdna2"); +DEF_REGISTER(acc247, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 247 , "amdgpu_cdna2"); +DEF_REGISTER(acc248, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 248 , "amdgpu_cdna2"); +DEF_REGISTER(acc249, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 249 , "amdgpu_cdna2"); +DEF_REGISTER(acc250, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 250 , "amdgpu_cdna2"); +DEF_REGISTER(acc251, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 251 , "amdgpu_cdna2"); +DEF_REGISTER(acc252, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 252 , "amdgpu_cdna2"); +DEF_REGISTER(acc253, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 253 , "amdgpu_cdna2"); +DEF_REGISTER(acc254, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 254 , "amdgpu_cdna2"); +DEF_REGISTER(acc255, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 255 , "amdgpu_cdna2"); +#endif diff --git a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C new file mode 100644 index 0000000000..d170f06d0c --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C @@ -0,0 +1,6648 @@ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 512 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); +case 513 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); +case 514 : return makeRegisterExpression(amdgpu_cdna2::acc2,0,opr_size); +case 515 : return makeRegisterExpression(amdgpu_cdna2::acc3,0,opr_size); +case 516 : return makeRegisterExpression(amdgpu_cdna2::acc4,0,opr_size); +case 517 : return makeRegisterExpression(amdgpu_cdna2::acc5,0,opr_size); +case 518 : return makeRegisterExpression(amdgpu_cdna2::acc6,0,opr_size); +case 519 : return makeRegisterExpression(amdgpu_cdna2::acc7,0,opr_size); +case 520 : return makeRegisterExpression(amdgpu_cdna2::acc8,0,opr_size); +case 521 : return makeRegisterExpression(amdgpu_cdna2::acc9,0,opr_size); +case 522 : return makeRegisterExpression(amdgpu_cdna2::acc10,0,opr_size); +case 523 : return makeRegisterExpression(amdgpu_cdna2::acc11,0,opr_size); +case 524 : return makeRegisterExpression(amdgpu_cdna2::acc12,0,opr_size); +case 525 : return makeRegisterExpression(amdgpu_cdna2::acc13,0,opr_size); +case 526 : return makeRegisterExpression(amdgpu_cdna2::acc14,0,opr_size); +case 527 : return makeRegisterExpression(amdgpu_cdna2::acc15,0,opr_size); +case 528 : return makeRegisterExpression(amdgpu_cdna2::acc16,0,opr_size); +case 529 : return makeRegisterExpression(amdgpu_cdna2::acc17,0,opr_size); +case 530 : return makeRegisterExpression(amdgpu_cdna2::acc18,0,opr_size); +case 531 : return makeRegisterExpression(amdgpu_cdna2::acc19,0,opr_size); +case 532 : return makeRegisterExpression(amdgpu_cdna2::acc20,0,opr_size); +case 533 : return makeRegisterExpression(amdgpu_cdna2::acc21,0,opr_size); +case 534 : return makeRegisterExpression(amdgpu_cdna2::acc22,0,opr_size); +case 535 : return makeRegisterExpression(amdgpu_cdna2::acc23,0,opr_size); +case 536 : return makeRegisterExpression(amdgpu_cdna2::acc24,0,opr_size); +case 537 : return makeRegisterExpression(amdgpu_cdna2::acc25,0,opr_size); +case 538 : return makeRegisterExpression(amdgpu_cdna2::acc26,0,opr_size); +case 539 : return makeRegisterExpression(amdgpu_cdna2::acc27,0,opr_size); +case 540 : return makeRegisterExpression(amdgpu_cdna2::acc28,0,opr_size); +case 541 : return makeRegisterExpression(amdgpu_cdna2::acc29,0,opr_size); +case 542 : return makeRegisterExpression(amdgpu_cdna2::acc30,0,opr_size); +case 543 : return makeRegisterExpression(amdgpu_cdna2::acc31,0,opr_size); +case 544 : return makeRegisterExpression(amdgpu_cdna2::acc32,0,opr_size); +case 545 : return makeRegisterExpression(amdgpu_cdna2::acc33,0,opr_size); +case 546 : return makeRegisterExpression(amdgpu_cdna2::acc34,0,opr_size); +case 547 : return makeRegisterExpression(amdgpu_cdna2::acc35,0,opr_size); +case 548 : return makeRegisterExpression(amdgpu_cdna2::acc36,0,opr_size); +case 549 : return makeRegisterExpression(amdgpu_cdna2::acc37,0,opr_size); +case 550 : return makeRegisterExpression(amdgpu_cdna2::acc38,0,opr_size); +case 551 : return makeRegisterExpression(amdgpu_cdna2::acc39,0,opr_size); +case 552 : return makeRegisterExpression(amdgpu_cdna2::acc40,0,opr_size); +case 553 : return makeRegisterExpression(amdgpu_cdna2::acc41,0,opr_size); +case 554 : return makeRegisterExpression(amdgpu_cdna2::acc42,0,opr_size); +case 555 : return makeRegisterExpression(amdgpu_cdna2::acc43,0,opr_size); +case 556 : return makeRegisterExpression(amdgpu_cdna2::acc44,0,opr_size); +case 557 : return makeRegisterExpression(amdgpu_cdna2::acc45,0,opr_size); +case 558 : return makeRegisterExpression(amdgpu_cdna2::acc46,0,opr_size); +case 559 : return makeRegisterExpression(amdgpu_cdna2::acc47,0,opr_size); +case 560 : return makeRegisterExpression(amdgpu_cdna2::acc48,0,opr_size); +case 561 : return makeRegisterExpression(amdgpu_cdna2::acc49,0,opr_size); +case 562 : return makeRegisterExpression(amdgpu_cdna2::acc50,0,opr_size); +case 563 : return makeRegisterExpression(amdgpu_cdna2::acc51,0,opr_size); +case 564 : return makeRegisterExpression(amdgpu_cdna2::acc52,0,opr_size); +case 565 : return makeRegisterExpression(amdgpu_cdna2::acc53,0,opr_size); +case 566 : return makeRegisterExpression(amdgpu_cdna2::acc54,0,opr_size); +case 567 : return makeRegisterExpression(amdgpu_cdna2::acc55,0,opr_size); +case 568 : return makeRegisterExpression(amdgpu_cdna2::acc56,0,opr_size); +case 569 : return makeRegisterExpression(amdgpu_cdna2::acc57,0,opr_size); +case 570 : return makeRegisterExpression(amdgpu_cdna2::acc58,0,opr_size); +case 571 : return makeRegisterExpression(amdgpu_cdna2::acc59,0,opr_size); +case 572 : return makeRegisterExpression(amdgpu_cdna2::acc60,0,opr_size); +case 573 : return makeRegisterExpression(amdgpu_cdna2::acc61,0,opr_size); +case 574 : return makeRegisterExpression(amdgpu_cdna2::acc62,0,opr_size); +case 575 : return makeRegisterExpression(amdgpu_cdna2::acc63,0,opr_size); +case 576 : return makeRegisterExpression(amdgpu_cdna2::acc64,0,opr_size); +case 577 : return makeRegisterExpression(amdgpu_cdna2::acc65,0,opr_size); +case 578 : return makeRegisterExpression(amdgpu_cdna2::acc66,0,opr_size); +case 579 : return makeRegisterExpression(amdgpu_cdna2::acc67,0,opr_size); +case 580 : return makeRegisterExpression(amdgpu_cdna2::acc68,0,opr_size); +case 581 : return makeRegisterExpression(amdgpu_cdna2::acc69,0,opr_size); +case 582 : return makeRegisterExpression(amdgpu_cdna2::acc70,0,opr_size); +case 583 : return makeRegisterExpression(amdgpu_cdna2::acc71,0,opr_size); +case 584 : return makeRegisterExpression(amdgpu_cdna2::acc72,0,opr_size); +case 585 : return makeRegisterExpression(amdgpu_cdna2::acc73,0,opr_size); +case 586 : return makeRegisterExpression(amdgpu_cdna2::acc74,0,opr_size); +case 587 : return makeRegisterExpression(amdgpu_cdna2::acc75,0,opr_size); +case 588 : return makeRegisterExpression(amdgpu_cdna2::acc76,0,opr_size); +case 589 : return makeRegisterExpression(amdgpu_cdna2::acc77,0,opr_size); +case 590 : return makeRegisterExpression(amdgpu_cdna2::acc78,0,opr_size); +case 591 : return makeRegisterExpression(amdgpu_cdna2::acc79,0,opr_size); +case 592 : return makeRegisterExpression(amdgpu_cdna2::acc80,0,opr_size); +case 593 : return makeRegisterExpression(amdgpu_cdna2::acc81,0,opr_size); +case 594 : return makeRegisterExpression(amdgpu_cdna2::acc82,0,opr_size); +case 595 : return makeRegisterExpression(amdgpu_cdna2::acc83,0,opr_size); +case 596 : return makeRegisterExpression(amdgpu_cdna2::acc84,0,opr_size); +case 597 : return makeRegisterExpression(amdgpu_cdna2::acc85,0,opr_size); +case 598 : return makeRegisterExpression(amdgpu_cdna2::acc86,0,opr_size); +case 599 : return makeRegisterExpression(amdgpu_cdna2::acc87,0,opr_size); +case 600 : return makeRegisterExpression(amdgpu_cdna2::acc88,0,opr_size); +case 601 : return makeRegisterExpression(amdgpu_cdna2::acc89,0,opr_size); +case 602 : return makeRegisterExpression(amdgpu_cdna2::acc90,0,opr_size); +case 603 : return makeRegisterExpression(amdgpu_cdna2::acc91,0,opr_size); +case 604 : return makeRegisterExpression(amdgpu_cdna2::acc92,0,opr_size); +case 605 : return makeRegisterExpression(amdgpu_cdna2::acc93,0,opr_size); +case 606 : return makeRegisterExpression(amdgpu_cdna2::acc94,0,opr_size); +case 607 : return makeRegisterExpression(amdgpu_cdna2::acc95,0,opr_size); +case 608 : return makeRegisterExpression(amdgpu_cdna2::acc96,0,opr_size); +case 609 : return makeRegisterExpression(amdgpu_cdna2::acc97,0,opr_size); +case 610 : return makeRegisterExpression(amdgpu_cdna2::acc98,0,opr_size); +case 611 : return makeRegisterExpression(amdgpu_cdna2::acc99,0,opr_size); +case 612 : return makeRegisterExpression(amdgpu_cdna2::acc100,0,opr_size); +case 613 : return makeRegisterExpression(amdgpu_cdna2::acc101,0,opr_size); +case 614 : return makeRegisterExpression(amdgpu_cdna2::acc102,0,opr_size); +case 615 : return makeRegisterExpression(amdgpu_cdna2::acc103,0,opr_size); +case 616 : return makeRegisterExpression(amdgpu_cdna2::acc104,0,opr_size); +case 617 : return makeRegisterExpression(amdgpu_cdna2::acc105,0,opr_size); +case 618 : return makeRegisterExpression(amdgpu_cdna2::acc106,0,opr_size); +case 619 : return makeRegisterExpression(amdgpu_cdna2::acc107,0,opr_size); +case 620 : return makeRegisterExpression(amdgpu_cdna2::acc108,0,opr_size); +case 621 : return makeRegisterExpression(amdgpu_cdna2::acc109,0,opr_size); +case 622 : return makeRegisterExpression(amdgpu_cdna2::acc110,0,opr_size); +case 623 : return makeRegisterExpression(amdgpu_cdna2::acc111,0,opr_size); +case 624 : return makeRegisterExpression(amdgpu_cdna2::acc112,0,opr_size); +case 625 : return makeRegisterExpression(amdgpu_cdna2::acc113,0,opr_size); +case 626 : return makeRegisterExpression(amdgpu_cdna2::acc114,0,opr_size); +case 627 : return makeRegisterExpression(amdgpu_cdna2::acc115,0,opr_size); +case 628 : return makeRegisterExpression(amdgpu_cdna2::acc116,0,opr_size); +case 629 : return makeRegisterExpression(amdgpu_cdna2::acc117,0,opr_size); +case 630 : return makeRegisterExpression(amdgpu_cdna2::acc118,0,opr_size); +case 631 : return makeRegisterExpression(amdgpu_cdna2::acc119,0,opr_size); +case 632 : return makeRegisterExpression(amdgpu_cdna2::acc120,0,opr_size); +case 633 : return makeRegisterExpression(amdgpu_cdna2::acc121,0,opr_size); +case 634 : return makeRegisterExpression(amdgpu_cdna2::acc122,0,opr_size); +case 635 : return makeRegisterExpression(amdgpu_cdna2::acc123,0,opr_size); +case 636 : return makeRegisterExpression(amdgpu_cdna2::acc124,0,opr_size); +case 637 : return makeRegisterExpression(amdgpu_cdna2::acc125,0,opr_size); +case 638 : return makeRegisterExpression(amdgpu_cdna2::acc126,0,opr_size); +case 639 : return makeRegisterExpression(amdgpu_cdna2::acc127,0,opr_size); +case 640 : return makeRegisterExpression(amdgpu_cdna2::acc128,0,opr_size); +case 641 : return makeRegisterExpression(amdgpu_cdna2::acc129,0,opr_size); +case 642 : return makeRegisterExpression(amdgpu_cdna2::acc130,0,opr_size); +case 643 : return makeRegisterExpression(amdgpu_cdna2::acc131,0,opr_size); +case 644 : return makeRegisterExpression(amdgpu_cdna2::acc132,0,opr_size); +case 645 : return makeRegisterExpression(amdgpu_cdna2::acc133,0,opr_size); +case 646 : return makeRegisterExpression(amdgpu_cdna2::acc134,0,opr_size); +case 647 : return makeRegisterExpression(amdgpu_cdna2::acc135,0,opr_size); +case 648 : return makeRegisterExpression(amdgpu_cdna2::acc136,0,opr_size); +case 649 : return makeRegisterExpression(amdgpu_cdna2::acc137,0,opr_size); +case 650 : return makeRegisterExpression(amdgpu_cdna2::acc138,0,opr_size); +case 651 : return makeRegisterExpression(amdgpu_cdna2::acc139,0,opr_size); +case 652 : return makeRegisterExpression(amdgpu_cdna2::acc140,0,opr_size); +case 653 : return makeRegisterExpression(amdgpu_cdna2::acc141,0,opr_size); +case 654 : return makeRegisterExpression(amdgpu_cdna2::acc142,0,opr_size); +case 655 : return makeRegisterExpression(amdgpu_cdna2::acc143,0,opr_size); +case 656 : return makeRegisterExpression(amdgpu_cdna2::acc144,0,opr_size); +case 657 : return makeRegisterExpression(amdgpu_cdna2::acc145,0,opr_size); +case 658 : return makeRegisterExpression(amdgpu_cdna2::acc146,0,opr_size); +case 659 : return makeRegisterExpression(amdgpu_cdna2::acc147,0,opr_size); +case 660 : return makeRegisterExpression(amdgpu_cdna2::acc148,0,opr_size); +case 661 : return makeRegisterExpression(amdgpu_cdna2::acc149,0,opr_size); +case 662 : return makeRegisterExpression(amdgpu_cdna2::acc150,0,opr_size); +case 663 : return makeRegisterExpression(amdgpu_cdna2::acc151,0,opr_size); +case 664 : return makeRegisterExpression(amdgpu_cdna2::acc152,0,opr_size); +case 665 : return makeRegisterExpression(amdgpu_cdna2::acc153,0,opr_size); +case 666 : return makeRegisterExpression(amdgpu_cdna2::acc154,0,opr_size); +case 667 : return makeRegisterExpression(amdgpu_cdna2::acc155,0,opr_size); +case 668 : return makeRegisterExpression(amdgpu_cdna2::acc156,0,opr_size); +case 669 : return makeRegisterExpression(amdgpu_cdna2::acc157,0,opr_size); +case 670 : return makeRegisterExpression(amdgpu_cdna2::acc158,0,opr_size); +case 671 : return makeRegisterExpression(amdgpu_cdna2::acc159,0,opr_size); +case 672 : return makeRegisterExpression(amdgpu_cdna2::acc160,0,opr_size); +case 673 : return makeRegisterExpression(amdgpu_cdna2::acc161,0,opr_size); +case 674 : return makeRegisterExpression(amdgpu_cdna2::acc162,0,opr_size); +case 675 : return makeRegisterExpression(amdgpu_cdna2::acc163,0,opr_size); +case 676 : return makeRegisterExpression(amdgpu_cdna2::acc164,0,opr_size); +case 677 : return makeRegisterExpression(amdgpu_cdna2::acc165,0,opr_size); +case 678 : return makeRegisterExpression(amdgpu_cdna2::acc166,0,opr_size); +case 679 : return makeRegisterExpression(amdgpu_cdna2::acc167,0,opr_size); +case 680 : return makeRegisterExpression(amdgpu_cdna2::acc168,0,opr_size); +case 681 : return makeRegisterExpression(amdgpu_cdna2::acc169,0,opr_size); +case 682 : return makeRegisterExpression(amdgpu_cdna2::acc170,0,opr_size); +case 683 : return makeRegisterExpression(amdgpu_cdna2::acc171,0,opr_size); +case 684 : return makeRegisterExpression(amdgpu_cdna2::acc172,0,opr_size); +case 685 : return makeRegisterExpression(amdgpu_cdna2::acc173,0,opr_size); +case 686 : return makeRegisterExpression(amdgpu_cdna2::acc174,0,opr_size); +case 687 : return makeRegisterExpression(amdgpu_cdna2::acc175,0,opr_size); +case 688 : return makeRegisterExpression(amdgpu_cdna2::acc176,0,opr_size); +case 689 : return makeRegisterExpression(amdgpu_cdna2::acc177,0,opr_size); +case 690 : return makeRegisterExpression(amdgpu_cdna2::acc178,0,opr_size); +case 691 : return makeRegisterExpression(amdgpu_cdna2::acc179,0,opr_size); +case 692 : return makeRegisterExpression(amdgpu_cdna2::acc180,0,opr_size); +case 693 : return makeRegisterExpression(amdgpu_cdna2::acc181,0,opr_size); +case 694 : return makeRegisterExpression(amdgpu_cdna2::acc182,0,opr_size); +case 695 : return makeRegisterExpression(amdgpu_cdna2::acc183,0,opr_size); +case 696 : return makeRegisterExpression(amdgpu_cdna2::acc184,0,opr_size); +case 697 : return makeRegisterExpression(amdgpu_cdna2::acc185,0,opr_size); +case 698 : return makeRegisterExpression(amdgpu_cdna2::acc186,0,opr_size); +case 699 : return makeRegisterExpression(amdgpu_cdna2::acc187,0,opr_size); +case 700 : return makeRegisterExpression(amdgpu_cdna2::acc188,0,opr_size); +case 701 : return makeRegisterExpression(amdgpu_cdna2::acc189,0,opr_size); +case 702 : return makeRegisterExpression(amdgpu_cdna2::acc190,0,opr_size); +case 703 : return makeRegisterExpression(amdgpu_cdna2::acc191,0,opr_size); +case 704 : return makeRegisterExpression(amdgpu_cdna2::acc192,0,opr_size); +case 705 : return makeRegisterExpression(amdgpu_cdna2::acc193,0,opr_size); +case 706 : return makeRegisterExpression(amdgpu_cdna2::acc194,0,opr_size); +case 707 : return makeRegisterExpression(amdgpu_cdna2::acc195,0,opr_size); +case 708 : return makeRegisterExpression(amdgpu_cdna2::acc196,0,opr_size); +case 709 : return makeRegisterExpression(amdgpu_cdna2::acc197,0,opr_size); +case 710 : return makeRegisterExpression(amdgpu_cdna2::acc198,0,opr_size); +case 711 : return makeRegisterExpression(amdgpu_cdna2::acc199,0,opr_size); +case 712 : return makeRegisterExpression(amdgpu_cdna2::acc200,0,opr_size); +case 713 : return makeRegisterExpression(amdgpu_cdna2::acc201,0,opr_size); +case 714 : return makeRegisterExpression(amdgpu_cdna2::acc202,0,opr_size); +case 715 : return makeRegisterExpression(amdgpu_cdna2::acc203,0,opr_size); +case 716 : return makeRegisterExpression(amdgpu_cdna2::acc204,0,opr_size); +case 717 : return makeRegisterExpression(amdgpu_cdna2::acc205,0,opr_size); +case 718 : return makeRegisterExpression(amdgpu_cdna2::acc206,0,opr_size); +case 719 : return makeRegisterExpression(amdgpu_cdna2::acc207,0,opr_size); +case 720 : return makeRegisterExpression(amdgpu_cdna2::acc208,0,opr_size); +case 721 : return makeRegisterExpression(amdgpu_cdna2::acc209,0,opr_size); +case 722 : return makeRegisterExpression(amdgpu_cdna2::acc210,0,opr_size); +case 723 : return makeRegisterExpression(amdgpu_cdna2::acc211,0,opr_size); +case 724 : return makeRegisterExpression(amdgpu_cdna2::acc212,0,opr_size); +case 725 : return makeRegisterExpression(amdgpu_cdna2::acc213,0,opr_size); +case 726 : return makeRegisterExpression(amdgpu_cdna2::acc214,0,opr_size); +case 727 : return makeRegisterExpression(amdgpu_cdna2::acc215,0,opr_size); +case 728 : return makeRegisterExpression(amdgpu_cdna2::acc216,0,opr_size); +case 729 : return makeRegisterExpression(amdgpu_cdna2::acc217,0,opr_size); +case 730 : return makeRegisterExpression(amdgpu_cdna2::acc218,0,opr_size); +case 731 : return makeRegisterExpression(amdgpu_cdna2::acc219,0,opr_size); +case 732 : return makeRegisterExpression(amdgpu_cdna2::acc220,0,opr_size); +case 733 : return makeRegisterExpression(amdgpu_cdna2::acc221,0,opr_size); +case 734 : return makeRegisterExpression(amdgpu_cdna2::acc222,0,opr_size); +case 735 : return makeRegisterExpression(amdgpu_cdna2::acc223,0,opr_size); +case 736 : return makeRegisterExpression(amdgpu_cdna2::acc224,0,opr_size); +case 737 : return makeRegisterExpression(amdgpu_cdna2::acc225,0,opr_size); +case 738 : return makeRegisterExpression(amdgpu_cdna2::acc226,0,opr_size); +case 739 : return makeRegisterExpression(amdgpu_cdna2::acc227,0,opr_size); +case 740 : return makeRegisterExpression(amdgpu_cdna2::acc228,0,opr_size); +case 741 : return makeRegisterExpression(amdgpu_cdna2::acc229,0,opr_size); +case 742 : return makeRegisterExpression(amdgpu_cdna2::acc230,0,opr_size); +case 743 : return makeRegisterExpression(amdgpu_cdna2::acc231,0,opr_size); +case 744 : return makeRegisterExpression(amdgpu_cdna2::acc232,0,opr_size); +case 745 : return makeRegisterExpression(amdgpu_cdna2::acc233,0,opr_size); +case 746 : return makeRegisterExpression(amdgpu_cdna2::acc234,0,opr_size); +case 747 : return makeRegisterExpression(amdgpu_cdna2::acc235,0,opr_size); +case 748 : return makeRegisterExpression(amdgpu_cdna2::acc236,0,opr_size); +case 749 : return makeRegisterExpression(amdgpu_cdna2::acc237,0,opr_size); +case 750 : return makeRegisterExpression(amdgpu_cdna2::acc238,0,opr_size); +case 751 : return makeRegisterExpression(amdgpu_cdna2::acc239,0,opr_size); +case 752 : return makeRegisterExpression(amdgpu_cdna2::acc240,0,opr_size); +case 753 : return makeRegisterExpression(amdgpu_cdna2::acc241,0,opr_size); +case 754 : return makeRegisterExpression(amdgpu_cdna2::acc242,0,opr_size); +case 755 : return makeRegisterExpression(amdgpu_cdna2::acc243,0,opr_size); +case 756 : return makeRegisterExpression(amdgpu_cdna2::acc244,0,opr_size); +case 757 : return makeRegisterExpression(amdgpu_cdna2::acc245,0,opr_size); +case 758 : return makeRegisterExpression(amdgpu_cdna2::acc246,0,opr_size); +case 759 : return makeRegisterExpression(amdgpu_cdna2::acc247,0,opr_size); +case 760 : return makeRegisterExpression(amdgpu_cdna2::acc248,0,opr_size); +case 761 : return makeRegisterExpression(amdgpu_cdna2::acc249,0,opr_size); +case 762 : return makeRegisterExpression(amdgpu_cdna2::acc250,0,opr_size); +case 763 : return makeRegisterExpression(amdgpu_cdna2::acc251,0,opr_size); +case 764 : return makeRegisterExpression(amdgpu_cdna2::acc252,0,opr_size); +case 765 : return makeRegisterExpression(amdgpu_cdna2::acc253,0,opr_size); +case 766 : return makeRegisterExpression(amdgpu_cdna2::acc254,0,opr_size); +case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ATTR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::attr0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::attr1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::attr2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::attr3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::attr4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::attr5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::attr6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::attr7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::attr8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::attr9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::attr10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::attr11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::attr12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::attr13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::attr14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::attr15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::attr16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::attr17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::attr18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::attr19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::attr20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::attr21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::attr22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::attr23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::attr24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::attr25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::attr26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::attr27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::attr28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::attr29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::attr30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::attr31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::attr32,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_all,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PARAM(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::p10,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::p20,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::p0,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::pc_all); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_EXEC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_M0(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SMEM_OFFSET(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 768 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_cdna2::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_cdna2::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_cdna2::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_cdna2::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_cdna2::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_cdna2::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_cdna2::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_cdna2::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_cdna2::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_cdna2::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_cdna2::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_cdna2::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_cdna2::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_cdna2::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_cdna2::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_cdna2::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_cdna2::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_cdna2::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_cdna2::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_cdna2::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_cdna2::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_cdna2::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_cdna2::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_cdna2::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_cdna2::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_cdna2::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_cdna2::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_cdna2::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_cdna2::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_cdna2::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_cdna2::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_cdna2::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_cdna2::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_cdna2::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_cdna2::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_cdna2::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_cdna2::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_cdna2::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_cdna2::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_cdna2::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_cdna2::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_cdna2::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_cdna2::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_cdna2::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_cdna2::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_cdna2::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_cdna2::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_cdna2::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_cdna2::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_cdna2::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_cdna2::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_cdna2::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_cdna2::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_cdna2::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_cdna2::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_cdna2::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_cdna2::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_cdna2::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_cdna2::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_cdna2::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_cdna2::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_cdna2::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_cdna2::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_cdna2::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_cdna2::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_cdna2::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_cdna2::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_cdna2::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_cdna2::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_cdna2::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_cdna2::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_cdna2::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_cdna2::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_cdna2::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_cdna2::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_cdna2::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_cdna2::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_cdna2::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_cdna2::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_cdna2::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_cdna2::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_cdna2::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_cdna2::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_cdna2::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_cdna2::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_cdna2::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_cdna2::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_cdna2::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_cdna2::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_cdna2::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_cdna2::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_cdna2::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_cdna2::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_cdna2::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_cdna2::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_cdna2::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_cdna2::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_cdna2::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_cdna2::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_cdna2::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_cdna2::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_cdna2::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_cdna2::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_cdna2::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_cdna2::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_cdna2::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_cdna2::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_cdna2::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_cdna2::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_cdna2::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_cdna2::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_cdna2::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_cdna2::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_cdna2::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_cdna2::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_cdna2::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_cdna2::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_cdna2::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_cdna2::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_cdna2::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_cdna2::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_cdna2::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_cdna2::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_cdna2::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_cdna2::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_cdna2::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_cdna2::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_cdna2::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_cdna2::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_cdna2::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_cdna2::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_cdna2::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_cdna2::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_cdna2::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_cdna2::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_cdna2::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_cdna2::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_cdna2::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_cdna2::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_cdna2::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_cdna2::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_cdna2::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_cdna2::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_cdna2::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_cdna2::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_cdna2::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_cdna2::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_cdna2::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_cdna2::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_cdna2::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_cdna2::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_cdna2::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_cdna2::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_cdna2::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_cdna2::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_cdna2::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_cdna2::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_cdna2::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_cdna2::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_cdna2::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_cdna2::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_cdna2::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_cdna2::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_cdna2::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_cdna2::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_cdna2::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_cdna2::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_cdna2::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_cdna2::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_cdna2::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_cdna2::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_cdna2::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_cdna2::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_cdna2::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_cdna2::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_cdna2::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_cdna2::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_cdna2::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_cdna2::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_cdna2::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_cdna2::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_cdna2::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_cdna2::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_cdna2::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_cdna2::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_cdna2::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_cdna2::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_cdna2::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_cdna2::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_cdna2::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_cdna2::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_cdna2::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_cdna2::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_cdna2::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_cdna2::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_cdna2::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_cdna2::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_cdna2::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_cdna2::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_cdna2::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_cdna2::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_cdna2::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_cdna2::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_cdna2::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_cdna2::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_cdna2::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_cdna2::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_cdna2::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_cdna2::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_cdna2::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_cdna2::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_cdna2::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_cdna2::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_cdna2::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_cdna2::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_cdna2::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_cdna2::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_cdna2::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_cdna2::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_cdna2::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_cdna2::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_cdna2::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_cdna2::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_cdna2::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_cdna2::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_cdna2::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_cdna2::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_cdna2::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_cdna2::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_cdna2::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_cdna2::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_cdna2::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_cdna2::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_cdna2::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_cdna2::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_cdna2::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_cdna2::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_cdna2::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_cdna2::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_cdna2::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_cdna2::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_cdna2::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_cdna2::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_cdna2::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_cdna2::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_cdna2::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_cdna2::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_cdna2::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_cdna2::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_cdna2::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_cdna2::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_cdna2::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_cdna2::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLDS(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_SIMPLE(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_cdna2::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_cdna2::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_cdna2::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_cdna2::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_cdna2::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_cdna2::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_cdna2::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_cdna2::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_cdna2::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_cdna2::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_cdna2::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_cdna2::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_cdna2::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_cdna2::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_cdna2::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_cdna2::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_cdna2::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_cdna2::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_cdna2::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_cdna2::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_cdna2::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_cdna2::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_cdna2::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_cdna2::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_cdna2::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_cdna2::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_cdna2::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_cdna2::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_cdna2::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_cdna2::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_cdna2::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_cdna2::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_cdna2::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_cdna2::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_cdna2::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_cdna2::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_cdna2::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_cdna2::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_cdna2::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_cdna2::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_cdna2::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_cdna2::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_cdna2::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_cdna2::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_cdna2::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_cdna2::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_cdna2::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_cdna2::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_cdna2::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_cdna2::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_cdna2::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_cdna2::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_cdna2::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_cdna2::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_cdna2::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_cdna2::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_cdna2::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_cdna2::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_cdna2::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_cdna2::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_cdna2::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_cdna2::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_cdna2::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_cdna2::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_cdna2::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_cdna2::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_cdna2::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_cdna2::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_cdna2::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_cdna2::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_cdna2::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_cdna2::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_cdna2::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_cdna2::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_cdna2::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_cdna2::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_cdna2::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_cdna2::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_cdna2::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_cdna2::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_cdna2::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_cdna2::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_cdna2::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_cdna2::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_cdna2::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_cdna2::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_cdna2::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_cdna2::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_cdna2::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_cdna2::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_cdna2::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_cdna2::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_cdna2::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_cdna2::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_cdna2::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_cdna2::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_cdna2::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_cdna2::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_cdna2::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_cdna2::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_cdna2::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_cdna2::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_cdna2::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_cdna2::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_cdna2::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_cdna2::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_cdna2::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_cdna2::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_cdna2::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_cdna2::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_cdna2::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_cdna2::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_cdna2::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_cdna2::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_cdna2::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_cdna2::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_cdna2::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_cdna2::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_cdna2::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_cdna2::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_cdna2::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_cdna2::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_cdna2::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_cdna2::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_cdna2::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_cdna2::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_cdna2::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_cdna2::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_cdna2::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_cdna2::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_cdna2::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_cdna2::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_cdna2::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_cdna2::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_cdna2::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_cdna2::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_cdna2::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_cdna2::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_cdna2::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_cdna2::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_cdna2::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_cdna2::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_cdna2::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_cdna2::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_cdna2::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_cdna2::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_cdna2::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_cdna2::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_cdna2::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_cdna2::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_cdna2::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_cdna2::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_cdna2::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_cdna2::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_cdna2::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_cdna2::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_cdna2::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_cdna2::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_cdna2::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_cdna2::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_cdna2::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_cdna2::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_cdna2::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_cdna2::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_cdna2::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_cdna2::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_cdna2::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_cdna2::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_cdna2::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_cdna2::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_cdna2::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_cdna2::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_cdna2::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_cdna2::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_cdna2::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_cdna2::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_cdna2::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_cdna2::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_cdna2::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_cdna2::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_cdna2::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_cdna2::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_cdna2::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_cdna2::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_cdna2::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_cdna2::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_cdna2::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_cdna2::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_cdna2::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_cdna2::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_cdna2::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_cdna2::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_cdna2::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_cdna2::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_cdna2::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_cdna2::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_cdna2::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_cdna2::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_cdna2::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_cdna2::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_cdna2::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_cdna2::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_cdna2::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_cdna2::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_cdna2::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_cdna2::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_cdna2::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_cdna2::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_cdna2::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_cdna2::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_cdna2::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_cdna2::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_cdna2::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_cdna2::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_cdna2::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_cdna2::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_cdna2::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_cdna2::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_cdna2::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_cdna2::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_cdna2::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_cdna2::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_cdna2::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_cdna2::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_cdna2::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_cdna2::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_cdna2::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_cdna2::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_cdna2::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_cdna2::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_cdna2::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_cdna2::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_cdna2::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_cdna2::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_cdna2::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_cdna2::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_cdna2::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_cdna2::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_cdna2::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_cdna2::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_cdna2::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_cdna2::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_cdna2::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_cdna2::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_cdna2::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_cdna2::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_cdna2::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_cdna2::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_cdna2::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_cdna2::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_cdna2::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_cdna2::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_cdna2::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_cdna2::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_cdna2::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_cdna2::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_cdna2::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_cdna2::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_cdna2::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_cdna2::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_cdna2::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_cdna2::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_cdna2::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_cdna2::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_cdna2::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_cdna2::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_cdna2::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_cdna2::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_cdna2::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_cdna2::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_cdna2::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_cdna2::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_cdna2::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_cdna2::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_cdna2::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_cdna2::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_cdna2::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_cdna2::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_cdna2::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_cdna2::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_cdna2::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_cdna2::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_cdna2::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_cdna2::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_cdna2::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_cdna2::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_cdna2::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_cdna2::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_cdna2::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_cdna2::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_cdna2::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_cdna2::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_cdna2::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_cdna2::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_cdna2::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_cdna2::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_cdna2::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_cdna2::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_cdna2::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_cdna2::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_cdna2::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_cdna2::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_cdna2::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_cdna2::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_cdna2::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_cdna2::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_cdna2::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_cdna2::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_cdna2::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_cdna2::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_cdna2::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_cdna2::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_cdna2::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_cdna2::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_cdna2::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_cdna2::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_cdna2::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_cdna2::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_cdna2::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_cdna2::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_cdna2::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_cdna2::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_cdna2::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_cdna2::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_cdna2::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_cdna2::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_cdna2::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_cdna2::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_cdna2::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_cdna2::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_cdna2::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_cdna2::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_cdna2::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_cdna2::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_cdna2::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_cdna2::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_cdna2::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_cdna2::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_cdna2::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_cdna2::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_cdna2::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_cdna2::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_cdna2::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_cdna2::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_cdna2::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_cdna2::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_cdna2::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_cdna2::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_cdna2::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_cdna2::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_cdna2::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_cdna2::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_cdna2::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_cdna2::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_cdna2::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_cdna2::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_cdna2::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_cdna2::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_cdna2::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_cdna2::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_cdna2::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_cdna2::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_cdna2::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_cdna2::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_cdna2::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_cdna2::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_cdna2::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_cdna2::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_cdna2::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_cdna2::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_cdna2::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_cdna2::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_cdna2::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_cdna2::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_cdna2::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_cdna2::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_cdna2::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_cdna2::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_cdna2::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_cdna2::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_cdna2::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_cdna2::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_cdna2::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_cdna2::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_cdna2::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_cdna2::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_cdna2::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_cdna2::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_cdna2::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_cdna2::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_cdna2::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_cdna2::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_cdna2::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_cdna2::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_cdna2::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_cdna2::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_cdna2::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_cdna2::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_cdna2::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_cdna2::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_cdna2::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_cdna2::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_cdna2::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_cdna2::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_cdna2::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_cdna2::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_cdna2::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_cdna2::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_cdna2::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_cdna2::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_cdna2::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_cdna2::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_cdna2::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_cdna2::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_cdna2::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_cdna2::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_cdna2::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_cdna2::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_cdna2::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_cdna2::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_cdna2::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_cdna2::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_cdna2::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_cdna2::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_cdna2::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_cdna2::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_cdna2::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_cdna2::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_cdna2::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_cdna2::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_cdna2::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_cdna2::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_cdna2::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_cdna2::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_cdna2::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_cdna2::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_cdna2::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_cdna2::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_cdna2::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_cdna2::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_cdna2::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_cdna2::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_cdna2::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_cdna2::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_cdna2::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_cdna2::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_cdna2::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_cdna2::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_cdna2::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_cdna2::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_cdna2::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_cdna2::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_cdna2::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_cdna2::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_cdna2::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_cdna2::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_cdna2::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_cdna2::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_cdna2::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_cdna2::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_cdna2::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_cdna2::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_cdna2::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_cdna2::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_cdna2::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_cdna2::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_cdna2::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_cdna2::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_cdna2::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_cdna2::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_cdna2::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_cdna2::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_cdna2::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_cdna2::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_cdna2::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_cdna2::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_cdna2::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_cdna2::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_cdna2::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_cdna2::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_cdna2::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_cdna2::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_cdna2::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_cdna2::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_cdna2::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_cdna2::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_cdna2::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_cdna2::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_cdna2::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_cdna2::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_cdna2::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_cdna2::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_cdna2::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_cdna2::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_cdna2::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_cdna2::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_cdna2::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_cdna2::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_cdna2::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_cdna2::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_cdna2::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_cdna2::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_cdna2::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_cdna2::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_cdna2::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_cdna2::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG_NOVCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_LANESEL(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TGT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::mrt0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::mrt1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::mrt2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::mrt3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::mrt4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::mrt5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::mrt6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::mrt7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::mrtz,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::null,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::pos0,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::pos1,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::pos2,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::pos3,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::param0,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::param1,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::param2,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::param3,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::param4,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::param5,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::param6,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::param7,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::param8,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::param9,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::param10,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::param11,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::param12,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::param13,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::param14,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::param15,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::param16,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::param17,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::param18,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::param19,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::param20,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::param21,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::param22,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::param23,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::param24,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::param25,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::param26,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::param27,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::param28,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::param29,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::param30,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::param31,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TRAP(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::vcc); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 125 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 128 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 129 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 130 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 131 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 132 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 133 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 134 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 135 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 136 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 137 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 138 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 139 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 140 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 141 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 142 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 143 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 144 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 145 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 146 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 147 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 148 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 149 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 150 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 151 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 152 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 153 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 154 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 155 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 156 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 157 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 158 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 159 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 160 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 161 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 162 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 163 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 164 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 165 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 166 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 167 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 168 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 169 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 170 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 171 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 172 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 173 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 174 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 175 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 176 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 177 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 178 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 179 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 180 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 181 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 182 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 183 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 184 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 185 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 186 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 187 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 188 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 189 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 190 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 191 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 192 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 193 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 194 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 195 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 196 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 197 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 198 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 199 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 200 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 201 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 202 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 203 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 204 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 205 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 206 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 207 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 208 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 209 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 210 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 211 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 212 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 213 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 214 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 215 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 216 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 217 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 218 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 219 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 220 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 221 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 222 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 223 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 224 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 225 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 226 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 227 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 228 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 229 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 230 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 231 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 232 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 233 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 234 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 240 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 241 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 242 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 243 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 244 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 245 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 246 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 247 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 248 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 249 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 250 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 125 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 128 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 129 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 130 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 131 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 132 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 133 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 134 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 135 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 136 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 137 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 138 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 139 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 140 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 141 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 142 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 143 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 144 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 145 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 146 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 147 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 148 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 149 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 150 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 151 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 152 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 153 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 154 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 155 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 156 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 157 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 158 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 159 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 160 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 161 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 162 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 163 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 164 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 165 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 166 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 167 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 168 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 169 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 170 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 171 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 172 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 173 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 174 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 175 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 176 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 177 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 178 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 179 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 180 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 181 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 182 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 183 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 184 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 185 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 186 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 187 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 188 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 189 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 190 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 191 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 192 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 193 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 194 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 195 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 196 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 197 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 198 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 199 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 200 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 201 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 202 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 203 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 204 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 205 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 206 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 207 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 208 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 209 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 210 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 211 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 212 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 213 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 214 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 215 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 216 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 217 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 218 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 219 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 220 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 221 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 222 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 223 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 224 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 225 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 226 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 227 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 228 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 229 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 230 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 231 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 232 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 233 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 234 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 240 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 241 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 242 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 243 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 244 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 245 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 246 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 247 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 248 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 249 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 250 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +case 512 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); +case 513 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); +case 514 : return makeRegisterExpression(amdgpu_cdna2::acc2,0,opr_size); +case 515 : return makeRegisterExpression(amdgpu_cdna2::acc3,0,opr_size); +case 516 : return makeRegisterExpression(amdgpu_cdna2::acc4,0,opr_size); +case 517 : return makeRegisterExpression(amdgpu_cdna2::acc5,0,opr_size); +case 518 : return makeRegisterExpression(amdgpu_cdna2::acc6,0,opr_size); +case 519 : return makeRegisterExpression(amdgpu_cdna2::acc7,0,opr_size); +case 520 : return makeRegisterExpression(amdgpu_cdna2::acc8,0,opr_size); +case 521 : return makeRegisterExpression(amdgpu_cdna2::acc9,0,opr_size); +case 522 : return makeRegisterExpression(amdgpu_cdna2::acc10,0,opr_size); +case 523 : return makeRegisterExpression(amdgpu_cdna2::acc11,0,opr_size); +case 524 : return makeRegisterExpression(amdgpu_cdna2::acc12,0,opr_size); +case 525 : return makeRegisterExpression(amdgpu_cdna2::acc13,0,opr_size); +case 526 : return makeRegisterExpression(amdgpu_cdna2::acc14,0,opr_size); +case 527 : return makeRegisterExpression(amdgpu_cdna2::acc15,0,opr_size); +case 528 : return makeRegisterExpression(amdgpu_cdna2::acc16,0,opr_size); +case 529 : return makeRegisterExpression(amdgpu_cdna2::acc17,0,opr_size); +case 530 : return makeRegisterExpression(amdgpu_cdna2::acc18,0,opr_size); +case 531 : return makeRegisterExpression(amdgpu_cdna2::acc19,0,opr_size); +case 532 : return makeRegisterExpression(amdgpu_cdna2::acc20,0,opr_size); +case 533 : return makeRegisterExpression(amdgpu_cdna2::acc21,0,opr_size); +case 534 : return makeRegisterExpression(amdgpu_cdna2::acc22,0,opr_size); +case 535 : return makeRegisterExpression(amdgpu_cdna2::acc23,0,opr_size); +case 536 : return makeRegisterExpression(amdgpu_cdna2::acc24,0,opr_size); +case 537 : return makeRegisterExpression(amdgpu_cdna2::acc25,0,opr_size); +case 538 : return makeRegisterExpression(amdgpu_cdna2::acc26,0,opr_size); +case 539 : return makeRegisterExpression(amdgpu_cdna2::acc27,0,opr_size); +case 540 : return makeRegisterExpression(amdgpu_cdna2::acc28,0,opr_size); +case 541 : return makeRegisterExpression(amdgpu_cdna2::acc29,0,opr_size); +case 542 : return makeRegisterExpression(amdgpu_cdna2::acc30,0,opr_size); +case 543 : return makeRegisterExpression(amdgpu_cdna2::acc31,0,opr_size); +case 544 : return makeRegisterExpression(amdgpu_cdna2::acc32,0,opr_size); +case 545 : return makeRegisterExpression(amdgpu_cdna2::acc33,0,opr_size); +case 546 : return makeRegisterExpression(amdgpu_cdna2::acc34,0,opr_size); +case 547 : return makeRegisterExpression(amdgpu_cdna2::acc35,0,opr_size); +case 548 : return makeRegisterExpression(amdgpu_cdna2::acc36,0,opr_size); +case 549 : return makeRegisterExpression(amdgpu_cdna2::acc37,0,opr_size); +case 550 : return makeRegisterExpression(amdgpu_cdna2::acc38,0,opr_size); +case 551 : return makeRegisterExpression(amdgpu_cdna2::acc39,0,opr_size); +case 552 : return makeRegisterExpression(amdgpu_cdna2::acc40,0,opr_size); +case 553 : return makeRegisterExpression(amdgpu_cdna2::acc41,0,opr_size); +case 554 : return makeRegisterExpression(amdgpu_cdna2::acc42,0,opr_size); +case 555 : return makeRegisterExpression(amdgpu_cdna2::acc43,0,opr_size); +case 556 : return makeRegisterExpression(amdgpu_cdna2::acc44,0,opr_size); +case 557 : return makeRegisterExpression(amdgpu_cdna2::acc45,0,opr_size); +case 558 : return makeRegisterExpression(amdgpu_cdna2::acc46,0,opr_size); +case 559 : return makeRegisterExpression(amdgpu_cdna2::acc47,0,opr_size); +case 560 : return makeRegisterExpression(amdgpu_cdna2::acc48,0,opr_size); +case 561 : return makeRegisterExpression(amdgpu_cdna2::acc49,0,opr_size); +case 562 : return makeRegisterExpression(amdgpu_cdna2::acc50,0,opr_size); +case 563 : return makeRegisterExpression(amdgpu_cdna2::acc51,0,opr_size); +case 564 : return makeRegisterExpression(amdgpu_cdna2::acc52,0,opr_size); +case 565 : return makeRegisterExpression(amdgpu_cdna2::acc53,0,opr_size); +case 566 : return makeRegisterExpression(amdgpu_cdna2::acc54,0,opr_size); +case 567 : return makeRegisterExpression(amdgpu_cdna2::acc55,0,opr_size); +case 568 : return makeRegisterExpression(amdgpu_cdna2::acc56,0,opr_size); +case 569 : return makeRegisterExpression(amdgpu_cdna2::acc57,0,opr_size); +case 570 : return makeRegisterExpression(amdgpu_cdna2::acc58,0,opr_size); +case 571 : return makeRegisterExpression(amdgpu_cdna2::acc59,0,opr_size); +case 572 : return makeRegisterExpression(amdgpu_cdna2::acc60,0,opr_size); +case 573 : return makeRegisterExpression(amdgpu_cdna2::acc61,0,opr_size); +case 574 : return makeRegisterExpression(amdgpu_cdna2::acc62,0,opr_size); +case 575 : return makeRegisterExpression(amdgpu_cdna2::acc63,0,opr_size); +case 576 : return makeRegisterExpression(amdgpu_cdna2::acc64,0,opr_size); +case 577 : return makeRegisterExpression(amdgpu_cdna2::acc65,0,opr_size); +case 578 : return makeRegisterExpression(amdgpu_cdna2::acc66,0,opr_size); +case 579 : return makeRegisterExpression(amdgpu_cdna2::acc67,0,opr_size); +case 580 : return makeRegisterExpression(amdgpu_cdna2::acc68,0,opr_size); +case 581 : return makeRegisterExpression(amdgpu_cdna2::acc69,0,opr_size); +case 582 : return makeRegisterExpression(amdgpu_cdna2::acc70,0,opr_size); +case 583 : return makeRegisterExpression(amdgpu_cdna2::acc71,0,opr_size); +case 584 : return makeRegisterExpression(amdgpu_cdna2::acc72,0,opr_size); +case 585 : return makeRegisterExpression(amdgpu_cdna2::acc73,0,opr_size); +case 586 : return makeRegisterExpression(amdgpu_cdna2::acc74,0,opr_size); +case 587 : return makeRegisterExpression(amdgpu_cdna2::acc75,0,opr_size); +case 588 : return makeRegisterExpression(amdgpu_cdna2::acc76,0,opr_size); +case 589 : return makeRegisterExpression(amdgpu_cdna2::acc77,0,opr_size); +case 590 : return makeRegisterExpression(amdgpu_cdna2::acc78,0,opr_size); +case 591 : return makeRegisterExpression(amdgpu_cdna2::acc79,0,opr_size); +case 592 : return makeRegisterExpression(amdgpu_cdna2::acc80,0,opr_size); +case 593 : return makeRegisterExpression(amdgpu_cdna2::acc81,0,opr_size); +case 594 : return makeRegisterExpression(amdgpu_cdna2::acc82,0,opr_size); +case 595 : return makeRegisterExpression(amdgpu_cdna2::acc83,0,opr_size); +case 596 : return makeRegisterExpression(amdgpu_cdna2::acc84,0,opr_size); +case 597 : return makeRegisterExpression(amdgpu_cdna2::acc85,0,opr_size); +case 598 : return makeRegisterExpression(amdgpu_cdna2::acc86,0,opr_size); +case 599 : return makeRegisterExpression(amdgpu_cdna2::acc87,0,opr_size); +case 600 : return makeRegisterExpression(amdgpu_cdna2::acc88,0,opr_size); +case 601 : return makeRegisterExpression(amdgpu_cdna2::acc89,0,opr_size); +case 602 : return makeRegisterExpression(amdgpu_cdna2::acc90,0,opr_size); +case 603 : return makeRegisterExpression(amdgpu_cdna2::acc91,0,opr_size); +case 604 : return makeRegisterExpression(amdgpu_cdna2::acc92,0,opr_size); +case 605 : return makeRegisterExpression(amdgpu_cdna2::acc93,0,opr_size); +case 606 : return makeRegisterExpression(amdgpu_cdna2::acc94,0,opr_size); +case 607 : return makeRegisterExpression(amdgpu_cdna2::acc95,0,opr_size); +case 608 : return makeRegisterExpression(amdgpu_cdna2::acc96,0,opr_size); +case 609 : return makeRegisterExpression(amdgpu_cdna2::acc97,0,opr_size); +case 610 : return makeRegisterExpression(amdgpu_cdna2::acc98,0,opr_size); +case 611 : return makeRegisterExpression(amdgpu_cdna2::acc99,0,opr_size); +case 612 : return makeRegisterExpression(amdgpu_cdna2::acc100,0,opr_size); +case 613 : return makeRegisterExpression(amdgpu_cdna2::acc101,0,opr_size); +case 614 : return makeRegisterExpression(amdgpu_cdna2::acc102,0,opr_size); +case 615 : return makeRegisterExpression(amdgpu_cdna2::acc103,0,opr_size); +case 616 : return makeRegisterExpression(amdgpu_cdna2::acc104,0,opr_size); +case 617 : return makeRegisterExpression(amdgpu_cdna2::acc105,0,opr_size); +case 618 : return makeRegisterExpression(amdgpu_cdna2::acc106,0,opr_size); +case 619 : return makeRegisterExpression(amdgpu_cdna2::acc107,0,opr_size); +case 620 : return makeRegisterExpression(amdgpu_cdna2::acc108,0,opr_size); +case 621 : return makeRegisterExpression(amdgpu_cdna2::acc109,0,opr_size); +case 622 : return makeRegisterExpression(amdgpu_cdna2::acc110,0,opr_size); +case 623 : return makeRegisterExpression(amdgpu_cdna2::acc111,0,opr_size); +case 624 : return makeRegisterExpression(amdgpu_cdna2::acc112,0,opr_size); +case 625 : return makeRegisterExpression(amdgpu_cdna2::acc113,0,opr_size); +case 626 : return makeRegisterExpression(amdgpu_cdna2::acc114,0,opr_size); +case 627 : return makeRegisterExpression(amdgpu_cdna2::acc115,0,opr_size); +case 628 : return makeRegisterExpression(amdgpu_cdna2::acc116,0,opr_size); +case 629 : return makeRegisterExpression(amdgpu_cdna2::acc117,0,opr_size); +case 630 : return makeRegisterExpression(amdgpu_cdna2::acc118,0,opr_size); +case 631 : return makeRegisterExpression(amdgpu_cdna2::acc119,0,opr_size); +case 632 : return makeRegisterExpression(amdgpu_cdna2::acc120,0,opr_size); +case 633 : return makeRegisterExpression(amdgpu_cdna2::acc121,0,opr_size); +case 634 : return makeRegisterExpression(amdgpu_cdna2::acc122,0,opr_size); +case 635 : return makeRegisterExpression(amdgpu_cdna2::acc123,0,opr_size); +case 636 : return makeRegisterExpression(amdgpu_cdna2::acc124,0,opr_size); +case 637 : return makeRegisterExpression(amdgpu_cdna2::acc125,0,opr_size); +case 638 : return makeRegisterExpression(amdgpu_cdna2::acc126,0,opr_size); +case 639 : return makeRegisterExpression(amdgpu_cdna2::acc127,0,opr_size); +case 640 : return makeRegisterExpression(amdgpu_cdna2::acc128,0,opr_size); +case 641 : return makeRegisterExpression(amdgpu_cdna2::acc129,0,opr_size); +case 642 : return makeRegisterExpression(amdgpu_cdna2::acc130,0,opr_size); +case 643 : return makeRegisterExpression(amdgpu_cdna2::acc131,0,opr_size); +case 644 : return makeRegisterExpression(amdgpu_cdna2::acc132,0,opr_size); +case 645 : return makeRegisterExpression(amdgpu_cdna2::acc133,0,opr_size); +case 646 : return makeRegisterExpression(amdgpu_cdna2::acc134,0,opr_size); +case 647 : return makeRegisterExpression(amdgpu_cdna2::acc135,0,opr_size); +case 648 : return makeRegisterExpression(amdgpu_cdna2::acc136,0,opr_size); +case 649 : return makeRegisterExpression(amdgpu_cdna2::acc137,0,opr_size); +case 650 : return makeRegisterExpression(amdgpu_cdna2::acc138,0,opr_size); +case 651 : return makeRegisterExpression(amdgpu_cdna2::acc139,0,opr_size); +case 652 : return makeRegisterExpression(amdgpu_cdna2::acc140,0,opr_size); +case 653 : return makeRegisterExpression(amdgpu_cdna2::acc141,0,opr_size); +case 654 : return makeRegisterExpression(amdgpu_cdna2::acc142,0,opr_size); +case 655 : return makeRegisterExpression(amdgpu_cdna2::acc143,0,opr_size); +case 656 : return makeRegisterExpression(amdgpu_cdna2::acc144,0,opr_size); +case 657 : return makeRegisterExpression(amdgpu_cdna2::acc145,0,opr_size); +case 658 : return makeRegisterExpression(amdgpu_cdna2::acc146,0,opr_size); +case 659 : return makeRegisterExpression(amdgpu_cdna2::acc147,0,opr_size); +case 660 : return makeRegisterExpression(amdgpu_cdna2::acc148,0,opr_size); +case 661 : return makeRegisterExpression(amdgpu_cdna2::acc149,0,opr_size); +case 662 : return makeRegisterExpression(amdgpu_cdna2::acc150,0,opr_size); +case 663 : return makeRegisterExpression(amdgpu_cdna2::acc151,0,opr_size); +case 664 : return makeRegisterExpression(amdgpu_cdna2::acc152,0,opr_size); +case 665 : return makeRegisterExpression(amdgpu_cdna2::acc153,0,opr_size); +case 666 : return makeRegisterExpression(amdgpu_cdna2::acc154,0,opr_size); +case 667 : return makeRegisterExpression(amdgpu_cdna2::acc155,0,opr_size); +case 668 : return makeRegisterExpression(amdgpu_cdna2::acc156,0,opr_size); +case 669 : return makeRegisterExpression(amdgpu_cdna2::acc157,0,opr_size); +case 670 : return makeRegisterExpression(amdgpu_cdna2::acc158,0,opr_size); +case 671 : return makeRegisterExpression(amdgpu_cdna2::acc159,0,opr_size); +case 672 : return makeRegisterExpression(amdgpu_cdna2::acc160,0,opr_size); +case 673 : return makeRegisterExpression(amdgpu_cdna2::acc161,0,opr_size); +case 674 : return makeRegisterExpression(amdgpu_cdna2::acc162,0,opr_size); +case 675 : return makeRegisterExpression(amdgpu_cdna2::acc163,0,opr_size); +case 676 : return makeRegisterExpression(amdgpu_cdna2::acc164,0,opr_size); +case 677 : return makeRegisterExpression(amdgpu_cdna2::acc165,0,opr_size); +case 678 : return makeRegisterExpression(amdgpu_cdna2::acc166,0,opr_size); +case 679 : return makeRegisterExpression(amdgpu_cdna2::acc167,0,opr_size); +case 680 : return makeRegisterExpression(amdgpu_cdna2::acc168,0,opr_size); +case 681 : return makeRegisterExpression(amdgpu_cdna2::acc169,0,opr_size); +case 682 : return makeRegisterExpression(amdgpu_cdna2::acc170,0,opr_size); +case 683 : return makeRegisterExpression(amdgpu_cdna2::acc171,0,opr_size); +case 684 : return makeRegisterExpression(amdgpu_cdna2::acc172,0,opr_size); +case 685 : return makeRegisterExpression(amdgpu_cdna2::acc173,0,opr_size); +case 686 : return makeRegisterExpression(amdgpu_cdna2::acc174,0,opr_size); +case 687 : return makeRegisterExpression(amdgpu_cdna2::acc175,0,opr_size); +case 688 : return makeRegisterExpression(amdgpu_cdna2::acc176,0,opr_size); +case 689 : return makeRegisterExpression(amdgpu_cdna2::acc177,0,opr_size); +case 690 : return makeRegisterExpression(amdgpu_cdna2::acc178,0,opr_size); +case 691 : return makeRegisterExpression(amdgpu_cdna2::acc179,0,opr_size); +case 692 : return makeRegisterExpression(amdgpu_cdna2::acc180,0,opr_size); +case 693 : return makeRegisterExpression(amdgpu_cdna2::acc181,0,opr_size); +case 694 : return makeRegisterExpression(amdgpu_cdna2::acc182,0,opr_size); +case 695 : return makeRegisterExpression(amdgpu_cdna2::acc183,0,opr_size); +case 696 : return makeRegisterExpression(amdgpu_cdna2::acc184,0,opr_size); +case 697 : return makeRegisterExpression(amdgpu_cdna2::acc185,0,opr_size); +case 698 : return makeRegisterExpression(amdgpu_cdna2::acc186,0,opr_size); +case 699 : return makeRegisterExpression(amdgpu_cdna2::acc187,0,opr_size); +case 700 : return makeRegisterExpression(amdgpu_cdna2::acc188,0,opr_size); +case 701 : return makeRegisterExpression(amdgpu_cdna2::acc189,0,opr_size); +case 702 : return makeRegisterExpression(amdgpu_cdna2::acc190,0,opr_size); +case 703 : return makeRegisterExpression(amdgpu_cdna2::acc191,0,opr_size); +case 704 : return makeRegisterExpression(amdgpu_cdna2::acc192,0,opr_size); +case 705 : return makeRegisterExpression(amdgpu_cdna2::acc193,0,opr_size); +case 706 : return makeRegisterExpression(amdgpu_cdna2::acc194,0,opr_size); +case 707 : return makeRegisterExpression(amdgpu_cdna2::acc195,0,opr_size); +case 708 : return makeRegisterExpression(amdgpu_cdna2::acc196,0,opr_size); +case 709 : return makeRegisterExpression(amdgpu_cdna2::acc197,0,opr_size); +case 710 : return makeRegisterExpression(amdgpu_cdna2::acc198,0,opr_size); +case 711 : return makeRegisterExpression(amdgpu_cdna2::acc199,0,opr_size); +case 712 : return makeRegisterExpression(amdgpu_cdna2::acc200,0,opr_size); +case 713 : return makeRegisterExpression(amdgpu_cdna2::acc201,0,opr_size); +case 714 : return makeRegisterExpression(amdgpu_cdna2::acc202,0,opr_size); +case 715 : return makeRegisterExpression(amdgpu_cdna2::acc203,0,opr_size); +case 716 : return makeRegisterExpression(amdgpu_cdna2::acc204,0,opr_size); +case 717 : return makeRegisterExpression(amdgpu_cdna2::acc205,0,opr_size); +case 718 : return makeRegisterExpression(amdgpu_cdna2::acc206,0,opr_size); +case 719 : return makeRegisterExpression(amdgpu_cdna2::acc207,0,opr_size); +case 720 : return makeRegisterExpression(amdgpu_cdna2::acc208,0,opr_size); +case 721 : return makeRegisterExpression(amdgpu_cdna2::acc209,0,opr_size); +case 722 : return makeRegisterExpression(amdgpu_cdna2::acc210,0,opr_size); +case 723 : return makeRegisterExpression(amdgpu_cdna2::acc211,0,opr_size); +case 724 : return makeRegisterExpression(amdgpu_cdna2::acc212,0,opr_size); +case 725 : return makeRegisterExpression(amdgpu_cdna2::acc213,0,opr_size); +case 726 : return makeRegisterExpression(amdgpu_cdna2::acc214,0,opr_size); +case 727 : return makeRegisterExpression(amdgpu_cdna2::acc215,0,opr_size); +case 728 : return makeRegisterExpression(amdgpu_cdna2::acc216,0,opr_size); +case 729 : return makeRegisterExpression(amdgpu_cdna2::acc217,0,opr_size); +case 730 : return makeRegisterExpression(amdgpu_cdna2::acc218,0,opr_size); +case 731 : return makeRegisterExpression(amdgpu_cdna2::acc219,0,opr_size); +case 732 : return makeRegisterExpression(amdgpu_cdna2::acc220,0,opr_size); +case 733 : return makeRegisterExpression(amdgpu_cdna2::acc221,0,opr_size); +case 734 : return makeRegisterExpression(amdgpu_cdna2::acc222,0,opr_size); +case 735 : return makeRegisterExpression(amdgpu_cdna2::acc223,0,opr_size); +case 736 : return makeRegisterExpression(amdgpu_cdna2::acc224,0,opr_size); +case 737 : return makeRegisterExpression(amdgpu_cdna2::acc225,0,opr_size); +case 738 : return makeRegisterExpression(amdgpu_cdna2::acc226,0,opr_size); +case 739 : return makeRegisterExpression(amdgpu_cdna2::acc227,0,opr_size); +case 740 : return makeRegisterExpression(amdgpu_cdna2::acc228,0,opr_size); +case 741 : return makeRegisterExpression(amdgpu_cdna2::acc229,0,opr_size); +case 742 : return makeRegisterExpression(amdgpu_cdna2::acc230,0,opr_size); +case 743 : return makeRegisterExpression(amdgpu_cdna2::acc231,0,opr_size); +case 744 : return makeRegisterExpression(amdgpu_cdna2::acc232,0,opr_size); +case 745 : return makeRegisterExpression(amdgpu_cdna2::acc233,0,opr_size); +case 746 : return makeRegisterExpression(amdgpu_cdna2::acc234,0,opr_size); +case 747 : return makeRegisterExpression(amdgpu_cdna2::acc235,0,opr_size); +case 748 : return makeRegisterExpression(amdgpu_cdna2::acc236,0,opr_size); +case 749 : return makeRegisterExpression(amdgpu_cdna2::acc237,0,opr_size); +case 750 : return makeRegisterExpression(amdgpu_cdna2::acc238,0,opr_size); +case 751 : return makeRegisterExpression(amdgpu_cdna2::acc239,0,opr_size); +case 752 : return makeRegisterExpression(amdgpu_cdna2::acc240,0,opr_size); +case 753 : return makeRegisterExpression(amdgpu_cdna2::acc241,0,opr_size); +case 754 : return makeRegisterExpression(amdgpu_cdna2::acc242,0,opr_size); +case 755 : return makeRegisterExpression(amdgpu_cdna2::acc243,0,opr_size); +case 756 : return makeRegisterExpression(amdgpu_cdna2::acc244,0,opr_size); +case 757 : return makeRegisterExpression(amdgpu_cdna2::acc245,0,opr_size); +case 758 : return makeRegisterExpression(amdgpu_cdna2::acc246,0,opr_size); +case 759 : return makeRegisterExpression(amdgpu_cdna2::acc247,0,opr_size); +case 760 : return makeRegisterExpression(amdgpu_cdna2::acc248,0,opr_size); +case 761 : return makeRegisterExpression(amdgpu_cdna2::acc249,0,opr_size); +case 762 : return makeRegisterExpression(amdgpu_cdna2::acc250,0,opr_size); +case 763 : return makeRegisterExpression(amdgpu_cdna2::acc251,0,opr_size); +case 764 : return makeRegisterExpression(amdgpu_cdna2::acc252,0,opr_size); +case 765 : return makeRegisterExpression(amdgpu_cdna2::acc253,0,opr_size); +case 766 : return makeRegisterExpression(amdgpu_cdna2::acc254,0,opr_size); +case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_LDS(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_cdna2::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_cdna2::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_cdna2::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_cdna2::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_cdna2::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_cdna2::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_cdna2::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_cdna2::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_cdna2::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_cdna2::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_cdna2::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_cdna2::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_cdna2::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_cdna2::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_cdna2::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_cdna2::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_cdna2::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_cdna2::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_cdna2::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_cdna2::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_cdna2::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_cdna2::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_cdna2::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_cdna2::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_cdna2::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_cdna2::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_cdna2::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_cdna2::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_cdna2::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_cdna2::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_cdna2::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_cdna2::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_cdna2::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_cdna2::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_cdna2::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_cdna2::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_cdna2::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_cdna2::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_cdna2::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_cdna2::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_cdna2::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_cdna2::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_cdna2::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_cdna2::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_cdna2::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_cdna2::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_cdna2::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_cdna2::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_cdna2::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_cdna2::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_cdna2::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_cdna2::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_cdna2::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_cdna2::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_cdna2::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_cdna2::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_cdna2::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_cdna2::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_cdna2::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_cdna2::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_cdna2::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_cdna2::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_cdna2::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_cdna2::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_cdna2::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_cdna2::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_cdna2::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_cdna2::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_cdna2::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_cdna2::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_cdna2::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_cdna2::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_cdna2::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_cdna2::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_cdna2::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_cdna2::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_cdna2::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_cdna2::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_cdna2::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_cdna2::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_cdna2::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_cdna2::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_cdna2::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_cdna2::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_cdna2::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_cdna2::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_cdna2::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_cdna2::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_cdna2::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_cdna2::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_cdna2::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_cdna2::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_cdna2::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_cdna2::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_cdna2::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_cdna2::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_cdna2::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_cdna2::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_cdna2::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_cdna2::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_cdna2::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_cdna2::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_cdna2::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_cdna2::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_cdna2::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_cdna2::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_cdna2::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_cdna2::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_cdna2::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_cdna2::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_cdna2::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_cdna2::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_cdna2::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_cdna2::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_cdna2::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_cdna2::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_cdna2::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_cdna2::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_cdna2::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_cdna2::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_cdna2::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_cdna2::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_cdna2::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_cdna2::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_cdna2::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_cdna2::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_cdna2::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_cdna2::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_cdna2::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_cdna2::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_cdna2::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_cdna2::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_cdna2::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_cdna2::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_cdna2::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_cdna2::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_cdna2::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_cdna2::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_cdna2::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_cdna2::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_cdna2::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_cdna2::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_cdna2::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_cdna2::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_cdna2::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_cdna2::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_cdna2::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_cdna2::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_cdna2::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_cdna2::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_cdna2::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_cdna2::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_cdna2::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_cdna2::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_cdna2::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_cdna2::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_cdna2::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_cdna2::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_cdna2::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_cdna2::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_cdna2::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_cdna2::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_cdna2::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_cdna2::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_cdna2::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_cdna2::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_cdna2::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_cdna2::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_cdna2::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_cdna2::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_cdna2::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_cdna2::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_cdna2::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_cdna2::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_cdna2::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_cdna2::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_cdna2::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_cdna2::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_cdna2::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_cdna2::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_cdna2::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_cdna2::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_cdna2::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_cdna2::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_cdna2::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_cdna2::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_cdna2::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_cdna2::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_cdna2::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_cdna2::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_cdna2::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_cdna2::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_cdna2::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_cdna2::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_cdna2::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_cdna2::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_cdna2::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_cdna2::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_cdna2::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_cdna2::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_cdna2::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_cdna2::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_cdna2::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_cdna2::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_cdna2::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_cdna2::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_cdna2::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_cdna2::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_cdna2::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_cdna2::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_cdna2::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_cdna2::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_cdna2::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_cdna2::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_cdna2::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_cdna2::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_cdna2::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_cdna2::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_cdna2::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_cdna2::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_cdna2::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_cdna2::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_cdna2::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_cdna2::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_cdna2::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_cdna2::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_cdna2::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_cdna2::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_cdna2::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_cdna2::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_cdna2::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_cdna2::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_cdna2::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_cdna2::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_cdna2::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_cdna2::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_cdna2::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_cdna2::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_cdna2::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_cdna2::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_cdna2::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_cdna2::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_cdna2::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_cdna2::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_cdna2::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_cdna2::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_cdna2::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_cdna2::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_cdna2::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_cdna2::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_cdna2::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_cdna2::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_cdna2::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_XNACK_MASK_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_cdna2::invalid); +} +} diff --git a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h new file mode 100644 index 0000000000..8533c5a99a --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h @@ -0,0 +1,41 @@ +Expression::Ptr decodeOPR_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_ATTR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_PARAM(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_PC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_M0(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_TGT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_TRAP(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input ,uint32_t opr_size ); diff --git a/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C b/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C new file mode 100644 index 0000000000..f93b63d1c4 --- /dev/null +++ b/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C @@ -0,0 +1,9860 @@ +void InstructionDecoder_amdgpu_cdna2::finalizeENC_DSOperands(){ +layout_ENC_DS & layout = insn_layout.ENC_DS; +switch(layout.OP){ +case 0:// DS_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 1:// DS_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 2:// DS_RSUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 3:// DS_INC_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 4:// DS_DEC_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 5:// DS_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 6:// DS_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 7:// DS_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 8:// DS_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 9:// DS_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 10:// DS_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 11:// DS_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 12:// DS_MSKOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 13:// DS_WRITE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 14:// DS_WRITE2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 15:// DS_WRITE2ST64_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 16:// DS_CMPST_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 17:// DS_CMPST_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 18:// DS_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 19:// DS_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 20:// DS_NOP +break; +case 21:// DS_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 29:// DS_WRITE_ADDTID_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// DS_WRITE_B8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 31:// DS_WRITE_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 32:// DS_ADD_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 33:// DS_SUB_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 34:// DS_RSUB_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 35:// DS_INC_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 36:// DS_DEC_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 37:// DS_MIN_RTN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 38:// DS_MAX_RTN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 39:// DS_MIN_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 40:// DS_MAX_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 41:// DS_AND_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 42:// DS_OR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 43:// DS_XOR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 44:// DS_MSKOR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 45:// DS_WRXCHG_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 46:// DS_WRXCHG2_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 47:// DS_WRXCHG2ST64_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 48:// DS_CMPST_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 49:// DS_CMPST_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 50:// DS_MIN_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 51:// DS_MAX_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 52:// DS_WRAP_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1,32),true,false); +break; +case 53:// DS_ADD_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 54:// DS_READ_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 55:// DS_READ2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 56:// DS_READ2ST64_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 57:// DS_READ_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 58:// DS_READ_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 59:// DS_READ_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 60:// DS_READ_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 61:// DS_SWIZZLE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 62:// DS_PERMUTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 63:// DS_BPERMUTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 64:// DS_ADD_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 65:// DS_SUB_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 66:// DS_RSUB_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 67:// DS_INC_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 68:// DS_DEC_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 69:// DS_MIN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 70:// DS_MAX_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 71:// DS_MIN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 72:// DS_MAX_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 73:// DS_AND_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 74:// DS_OR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 75:// DS_XOR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 76:// DS_MSKOR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 77:// DS_WRITE_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 78:// DS_WRITE2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 79:// DS_WRITE2ST64_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 80:// DS_CMPST_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 81:// DS_CMPST_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 82:// DS_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 83:// DS_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 84:// DS_WRITE_B8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 85:// DS_WRITE_B16_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +break; +case 86:// DS_READ_U8_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 87:// DS_READ_U8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 88:// DS_READ_I8_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 89:// DS_READ_I8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 90:// DS_READ_U16_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 91:// DS_READ_U16_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 92:// DS_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 96:// DS_ADD_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 97:// DS_SUB_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 98:// DS_RSUB_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 99:// DS_INC_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 100:// DS_DEC_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 101:// DS_MIN_RTN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 102:// DS_MAX_RTN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 103:// DS_MIN_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 104:// DS_MAX_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 105:// DS_AND_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 106:// DS_OR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 107:// DS_XOR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 108:// DS_MSKOR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 109:// DS_WRXCHG_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 110:// DS_WRXCHG2_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 111:// DS_WRXCHG2ST64_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 112:// DS_CMPST_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 113:// DS_CMPST_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA1+1,32),true,false); +break; +case 114:// DS_MIN_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 115:// DS_MAX_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 118:// DS_READ_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 119:// DS_READ2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 120:// DS_READ2ST64_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 124:// DS_ADD_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 126:// DS_CONDXCHG32_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +break; +case 152:// DS_GWS_SEMA_RELEASE_ALL +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 153:// DS_GWS_INIT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 154:// DS_GWS_SEMA_V +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 155:// DS_GWS_SEMA_BR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 156:// DS_GWS_SEMA_P +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 157:// DS_GWS_BARRIER +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 182:// DS_READ_ADDTID_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 189:// DS_CONSUME +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 190:// DS_APPEND +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 222:// DS_WRITE_B96 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+2,32),true,false); +break; +case 223:// DS_WRITE_B128 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA0+3,32),true,false); +break; +case 254:// DS_READ_B96 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 255:// DS_READ_B128 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_FLATOperands(){ +layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; +switch(layout.OP){ +case 16:// FLAT_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// FLAT_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// FLAT_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// FLAT_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// FLAT_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// FLAT_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// FLAT_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// FLAT_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// FLAT_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// FLAT_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// FLAT_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// FLAT_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// FLAT_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// FLAT_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// FLAT_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// FLAT_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// FLAT_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// FLAT_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// FLAT_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// FLAT_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// FLAT_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// FLAT_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 64:// FLAT_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 65:// FLAT_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 66:// FLAT_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 67:// FLAT_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 68:// FLAT_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 69:// FLAT_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 70:// FLAT_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 71:// FLAT_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 72:// FLAT_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 73:// FLAT_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 74:// FLAT_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 75:// FLAT_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 76:// FLAT_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 79:// FLAT_ATOMIC_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 80:// FLAT_ATOMIC_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 81:// FLAT_ATOMIC_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 96:// FLAT_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 97:// FLAT_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 98:// FLAT_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 99:// FLAT_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 100:// FLAT_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 101:// FLAT_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 102:// FLAT_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 103:// FLAT_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 104:// FLAT_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 105:// FLAT_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 106:// FLAT_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 107:// FLAT_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 108:// FLAT_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_FLAT_GLBLOperands(){ +layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; +switch(layout.OP){ +case 16:// GLOBAL_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// GLOBAL_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// GLOBAL_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// GLOBAL_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// GLOBAL_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// GLOBAL_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// GLOBAL_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// GLOBAL_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// GLOBAL_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// GLOBAL_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// GLOBAL_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// GLOBAL_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// GLOBAL_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// GLOBAL_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// GLOBAL_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// GLOBAL_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// GLOBAL_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// GLOBAL_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// GLOBAL_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// GLOBAL_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// GLOBAL_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// GLOBAL_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 64:// GLOBAL_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 65:// GLOBAL_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 66:// GLOBAL_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 67:// GLOBAL_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 68:// GLOBAL_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 69:// GLOBAL_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 70:// GLOBAL_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 71:// GLOBAL_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 72:// GLOBAL_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 73:// GLOBAL_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 74:// GLOBAL_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 75:// GLOBAL_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 76:// GLOBAL_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 77:// GLOBAL_ATOMIC_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 78:// GLOBAL_ATOMIC_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 79:// GLOBAL_ATOMIC_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 80:// GLOBAL_ATOMIC_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 81:// GLOBAL_ATOMIC_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 96:// GLOBAL_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 97:// GLOBAL_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 98:// GLOBAL_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 99:// GLOBAL_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 100:// GLOBAL_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 101:// GLOBAL_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 102:// GLOBAL_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 103:// GLOBAL_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 104:// GLOBAL_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 105:// GLOBAL_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 106:// GLOBAL_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 107:// GLOBAL_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 108:// GLOBAL_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_FLAT_SCRATCHOperands(){ +layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; +switch(layout.OP){ +case 16:// SCRATCH_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// SCRATCH_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// SCRATCH_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// SCRATCH_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// SCRATCH_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// SCRATCH_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// SCRATCH_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// SCRATCH_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// SCRATCH_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// SCRATCH_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// SCRATCH_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// SCRATCH_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// SCRATCH_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// SCRATCH_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// SCRATCH_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// SCRATCH_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// SCRATCH_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// SCRATCH_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// SCRATCH_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// SCRATCH_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// SCRATCH_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// SCRATCH_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_MIMGOperands(){ +layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; +switch(layout.OP){ +case 0:// IMAGE_LOAD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 1:// IMAGE_LOAD_MIP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 2:// IMAGE_LOAD_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 3:// IMAGE_LOAD_PCK_SGN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 4:// IMAGE_LOAD_MIP_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 5:// IMAGE_LOAD_MIP_PCK_SGN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 8:// IMAGE_STORE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 9:// IMAGE_STORE_MIP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 10:// IMAGE_STORE_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 11:// IMAGE_STORE_MIP_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 14:// IMAGE_GET_RESINFO +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 16:// IMAGE_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 17:// IMAGE_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 18:// IMAGE_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 19:// IMAGE_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 20:// IMAGE_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 21:// IMAGE_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 22:// IMAGE_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 23:// IMAGE_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 24:// IMAGE_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 25:// IMAGE_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 26:// IMAGE_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 27:// IMAGE_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 28:// IMAGE_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 32:// IMAGE_SAMPLE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_MTBUFOperands(){ +layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; +switch(layout.OP){ +case 0:// TBUFFER_LOAD_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 1:// TBUFFER_LOAD_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 2:// TBUFFER_LOAD_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 3:// TBUFFER_LOAD_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 4:// TBUFFER_STORE_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 5:// TBUFFER_STORE_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 6:// TBUFFER_STORE_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 7:// TBUFFER_STORE_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 8:// TBUFFER_LOAD_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 9:// TBUFFER_LOAD_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 10:// TBUFFER_LOAD_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 11:// TBUFFER_LOAD_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 12:// TBUFFER_STORE_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 13:// TBUFFER_STORE_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 14:// TBUFFER_STORE_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 15:// TBUFFER_STORE_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_MUBUFOperands(){ +layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; +switch(layout.OP){ +case 0:// BUFFER_LOAD_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 1:// BUFFER_LOAD_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 2:// BUFFER_LOAD_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 3:// BUFFER_LOAD_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 4:// BUFFER_STORE_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 5:// BUFFER_STORE_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 6:// BUFFER_STORE_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 7:// BUFFER_STORE_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 8:// BUFFER_LOAD_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 9:// BUFFER_LOAD_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 10:// BUFFER_LOAD_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 11:// BUFFER_LOAD_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 12:// BUFFER_STORE_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 13:// BUFFER_STORE_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 14:// BUFFER_STORE_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 15:// BUFFER_STORE_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 16:// BUFFER_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 17:// BUFFER_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 18:// BUFFER_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 19:// BUFFER_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 20:// BUFFER_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 21:// BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 22:// BUFFER_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 23:// BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 24:// BUFFER_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 25:// BUFFER_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 26:// BUFFER_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 27:// BUFFER_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 28:// BUFFER_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 29:// BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 30:// BUFFER_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 31:// BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 32:// BUFFER_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 33:// BUFFER_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 34:// BUFFER_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 35:// BUFFER_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 36:// BUFFER_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 37:// BUFFER_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 38:// BUFFER_LOAD_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 39:// BUFFER_STORE_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 40:// BUFFER_WBL2 +break; +case 41:// BUFFER_INVL2 +break; +case 61:// BUFFER_STORE_LDS_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 62:// BUFFER_WBINVL1 +break; +case 63:// BUFFER_WBINVL1_VOL +break; +case 64:// BUFFER_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 65:// BUFFER_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 66:// BUFFER_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 67:// BUFFER_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 68:// BUFFER_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 69:// BUFFER_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 70:// BUFFER_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 71:// BUFFER_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 72:// BUFFER_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 73:// BUFFER_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 74:// BUFFER_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 75:// BUFFER_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 76:// BUFFER_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 77:// BUFFER_ATOMIC_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 78:// BUFFER_ATOMIC_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 79:// BUFFER_ATOMIC_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 80:// BUFFER_ATOMIC_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 81:// BUFFER_ATOMIC_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 96:// BUFFER_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 97:// BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 98:// BUFFER_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 99:// BUFFER_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 100:// BUFFER_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 101:// BUFFER_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 102:// BUFFER_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 103:// BUFFER_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 104:// BUFFER_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 105:// BUFFER_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 106:// BUFFER_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 107:// BUFFER_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 108:// BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SMEMOperands(){ +layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; +switch(layout.OP){ +case 0:// S_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 1:// S_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 2:// S_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 3:// S_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 4:// S_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 5:// S_SCRATCH_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 6:// S_SCRATCH_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 7:// S_SCRATCH_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 8:// S_BUFFER_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 9:// S_BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 10:// S_BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 11:// S_BUFFER_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 12:// S_BUFFER_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 16:// S_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 17:// S_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 18:// S_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 21:// S_SCRATCH_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 22:// S_SCRATCH_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 23:// S_SCRATCH_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 24:// S_BUFFER_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 25:// S_BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 26:// S_BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 32:// S_DCACHE_INV +break; +case 33:// S_DCACHE_WB +break; +case 34:// S_DCACHE_INV_VOL +break; +case 35:// S_DCACHE_WB_VOL +break; +case 36:// S_MEMTIME +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +break; +case 37:// S_MEMREALTIME +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +break; +case 38:// S_ATC_PROBE +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 39:// S_ATC_PROBE_BUFFER +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 40:// S_DCACHE_DISCARD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 41:// S_DCACHE_DISCARD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 64:// S_BUFFER_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 65:// S_BUFFER_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 66:// S_BUFFER_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 67:// S_BUFFER_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 68:// S_BUFFER_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 69:// S_BUFFER_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 70:// S_BUFFER_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 71:// S_BUFFER_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 72:// S_BUFFER_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 73:// S_BUFFER_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 74:// S_BUFFER_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 75:// S_BUFFER_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 76:// S_BUFFER_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 96:// S_BUFFER_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 97:// S_BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 98:// S_BUFFER_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 99:// S_BUFFER_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 100:// S_BUFFER_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 101:// S_BUFFER_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 102:// S_BUFFER_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 103:// S_BUFFER_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 104:// S_BUFFER_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 105:// S_BUFFER_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 106:// S_BUFFER_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 107:// S_BUFFER_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 108:// S_BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 128:// S_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 129:// S_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 130:// S_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 131:// S_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 132:// S_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 133:// S_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 134:// S_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 135:// S_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 136:// S_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 137:// S_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 138:// S_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 139:// S_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 140:// S_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 160:// S_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 161:// S_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 162:// S_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 163:// S_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 164:// S_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 165:// S_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 166:// S_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 167:// S_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 168:// S_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 169:// S_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 170:// S_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 171:// S_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 172:// S_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SOP1Operands(){ +layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; +switch(layout.OP){ +case 0:// S_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 1:// S_MOV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 2:// S_CMOV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 3:// S_CMOV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 4:// S_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_NOT_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_WQM_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_WQM_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_BREV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 9:// S_BREV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 10:// S_BCNT0_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_BCNT0_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_BCNT1_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_BCNT1_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_FF0_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 15:// S_FF0_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 16:// S_FF1_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 17:// S_FF1_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 18:// S_FLBIT_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 19:// S_FLBIT_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 20:// S_FLBIT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 21:// S_FLBIT_I32_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 22:// S_SEXT_I32_I8 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +break; +case 23:// S_SEXT_I32_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +break; +case 24:// S_BITSET0_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 25:// S_BITSET0_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 26:// S_BITSET1_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 27:// S_BITSET1_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 28:// S_GETPC_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +case 29:// S_SETPC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 30:// S_SWAPPC_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +case 31:// S_RFE_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 32:// S_AND_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 33:// S_OR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 34:// S_XOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 35:// S_ANDN2_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 36:// S_ORN2_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 37:// S_NAND_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 38:// S_NOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 39:// S_XNOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 40:// S_QUADMASK_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 41:// S_QUADMASK_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 42:// S_MOVRELS_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 43:// S_MOVRELS_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 44:// S_MOVRELD_B32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 45:// S_MOVRELD_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 46:// S_CBRANCH_JOIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 48:// S_ABS_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 50:// S_SET_GPR_IDX_IDX +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 51:// S_ANDN1_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 52:// S_ORN1_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 53:// S_ANDN1_WREXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 54:// S_ANDN2_WREXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 55:// S_BITREPLICATE_B64_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SOP2Operands(){ +layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; +switch(layout.OP){ +case 0:// S_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 1:// S_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 2:// S_ADD_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_SUB_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_ADDC_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 5:// S_SUBB_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 6:// S_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CSELECT_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 11:// S_CSELECT_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 12:// S_AND_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_AND_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_OR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_OR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 16:// S_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 17:// S_XOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 18:// S_ANDN2_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 19:// S_ANDN2_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 20:// S_ORN2_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 21:// S_ORN2_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 22:// S_NAND_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 23:// S_NAND_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 24:// S_NOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 25:// S_NOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 26:// S_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 27:// S_XNOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 28:// S_LSHL_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 29:// S_LSHL_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 30:// S_LSHR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 31:// S_LSHR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 32:// S_ASHR_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 33:// S_ASHR_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 34:// S_BFM_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 35:// S_BFM_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 36:// S_MUL_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 37:// S_BFE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 38:// S_BFE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 39:// S_BFE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 40:// S_BFE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 41:// S_CBRANCH_G_FORK +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 42:// S_ABSDIFF_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 43:// S_RFE_RESTORE_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 44:// S_MUL_HI_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 45:// S_MUL_HI_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 46:// S_LSHL1_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 47:// S_LSHL2_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 48:// S_LSHL3_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 49:// S_LSHL4_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 50:// S_PACK_LL_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,16),true,false); +break; +case 51:// S_PACK_LH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 52:// S_PACK_HH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SOPCOperands(){ +layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; +switch(layout.OP){ +case 0:// S_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 1:// S_CMP_LG_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 2:// S_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_CMP_LG_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_BITCMP0_B32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_BITCMP1_B32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_BITCMP0_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_BITCMP1_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 16:// S_SETVSKIP +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 17:// S_SET_GPR_IDX_ON +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// S_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 19:// S_CMP_LG_U64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SOPKOperands(){ +layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; +switch(layout.OP){ +case 0:// S_MOVK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 1:// S_CMOVK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 2:// S_CMPK_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_CMPK_LG_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_CMPK_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_CMPK_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_CMPK_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_CMPK_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_CMPK_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_CMPK_LG_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CMPK_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_CMPK_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_CMPK_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_CMPK_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_ADDK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_MULK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 16:// S_CBRANCH_I_FORK +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 17:// S_GETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 18:// S_SETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +break; +case 20:// S_SETREG_IMM32_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM32(decodeOPR_LITERAL()),true,false); +break; +case 21:// S_CALL_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_SOPPOperands(){ +layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; +switch(layout.OP){ +case 0:// S_NOP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 1:// S_ENDPGM +break; +case 2:// S_BRANCH +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 3:// S_WAKEUP +break; +case 4:// S_CBRANCH_SCC0 +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 5:// S_CBRANCH_SCC1 +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 6:// S_CBRANCH_VCCZ +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 7:// S_CBRANCH_VCCNZ +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 8:// S_CBRANCH_EXECZ +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 9:// S_CBRANCH_EXECNZ +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 10:// S_BARRIER +break; +case 11:// S_SETKILL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 12:// S_WAITCNT +insn_in_progress->appendOperand(decodeOPR_WAITCNT(layout.SIMM16),true,false); +break; +case 13:// S_SETHALT +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 14:// S_SLEEP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 15:// S_SETPRIO +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 16:// S_SENDMSG +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// S_SENDMSGHALT +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// S_TRAP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 19:// S_ICACHE_INV +break; +case 20:// S_INCPERFLEVEL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 21:// S_DECPERFLEVEL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 22:// S_TTRACEDATA +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// S_CBRANCH_CDBGSYS +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 24:// S_CBRANCH_CDBGUSER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 25:// S_CBRANCH_CDBGSYS_OR_USER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 26:// S_CBRANCH_CDBGSYS_AND_USER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 27:// S_ENDPGM_SAVED +break; +case 28:// S_SET_GPR_IDX_OFF +break; +case 29:// S_SET_GPR_IDX_MODE +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// S_ENDPGM_ORDERED_PS_DONE +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP1Operands(){ +layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; +switch(layout.OP){ +case 0:// V_NOP +break; +case 1:// V_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 2:// V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +break; +case 3:// V_CVT_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 4:// V_CVT_F64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 5:// V_CVT_F32_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 6:// V_CVT_F32_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 7:// V_CVT_U32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 8:// V_CVT_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 10:// V_CVT_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 11:// V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 12:// V_CVT_RPI_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 13:// V_CVT_FLR_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 14:// V_CVT_OFF_F32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 15:// V_CVT_F32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 16:// V_CVT_F64_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 17:// V_CVT_F32_UBYTE0 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 18:// V_CVT_F32_UBYTE1 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 19:// V_CVT_F32_UBYTE2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 20:// V_CVT_F32_UBYTE3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 21:// V_CVT_U32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 22:// V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 23:// V_TRUNC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 24:// V_CEIL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 25:// V_RNDNE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 26:// V_FLOOR_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 27:// V_FRACT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 28:// V_TRUNC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 29:// V_CEIL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 30:// V_RNDNE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 31:// V_FLOOR_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 32:// V_EXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 33:// V_LOG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 34:// V_RCP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 35:// V_RCP_IFLAG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 36:// V_RSQ_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 37:// V_RCP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 38:// V_RSQ_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 39:// V_SQRT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 40:// V_SQRT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 41:// V_SIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 42:// V_COS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 43:// V_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 44:// V_BFREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 45:// V_FFBH_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 46:// V_FFBL_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 47:// V_FFBH_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 48:// V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 49:// V_FREXP_MANT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 50:// V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 51:// V_FREXP_EXP_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 52:// V_FREXP_MANT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 53:// V_CLREXCP +break; +case 55:// V_SCREEN_PARTITION_4SE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 57:// V_CVT_F16_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 58:// V_CVT_F16_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 59:// V_CVT_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 60:// V_CVT_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 61:// V_RCP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 62:// V_SQRT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 63:// V_RSQ_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 64:// V_LOG_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 65:// V_EXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 66:// V_FREXP_MANT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 67:// V_FREXP_EXP_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 68:// V_FLOOR_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 69:// V_CEIL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 70:// V_TRUNC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 71:// V_RNDNE_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 72:// V_FRACT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 73:// V_SIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 74:// V_COS_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 75:// V_EXP_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 76:// V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 77:// V_CVT_NORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 78:// V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 79:// V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 81:// V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +break; +case 82:// V_ACCVGPR_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP3Operands(){ +layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; +switch(layout.OP){ +case 320:// V_NOP +break; +case 321:// V_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 322:// V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +break; +case 323:// V_CVT_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 324:// V_CVT_F64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 325:// V_CVT_F32_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 326:// V_CVT_F32_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 327:// V_CVT_U32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 328:// V_CVT_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 330:// V_CVT_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 331:// V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 332:// V_CVT_RPI_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 333:// V_CVT_FLR_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 334:// V_CVT_OFF_F32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 335:// V_CVT_F32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 336:// V_CVT_F64_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 337:// V_CVT_F32_UBYTE0 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 338:// V_CVT_F32_UBYTE1 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 339:// V_CVT_F32_UBYTE2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 340:// V_CVT_F32_UBYTE3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 341:// V_CVT_U32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 342:// V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 343:// V_TRUNC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 344:// V_CEIL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 345:// V_RNDNE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 346:// V_FLOOR_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 347:// V_FRACT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 348:// V_TRUNC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 349:// V_CEIL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 350:// V_RNDNE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 351:// V_FLOOR_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 352:// V_EXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 353:// V_LOG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 354:// V_RCP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 355:// V_RCP_IFLAG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 356:// V_RSQ_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 357:// V_RCP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 358:// V_RSQ_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 359:// V_SQRT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 360:// V_SQRT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 361:// V_SIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 362:// V_COS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 363:// V_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 364:// V_BFREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 365:// V_FFBH_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 366:// V_FFBL_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 367:// V_FFBH_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 368:// V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 369:// V_FREXP_MANT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 370:// V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 371:// V_FREXP_EXP_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 372:// V_FREXP_MANT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 373:// V_CLREXCP +break; +case 375:// V_SCREEN_PARTITION_4SE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 377:// V_CVT_F16_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 378:// V_CVT_F16_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 379:// V_CVT_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 380:// V_CVT_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 381:// V_RCP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 382:// V_SQRT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 383:// V_RSQ_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 384:// V_LOG_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 385:// V_EXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 386:// V_FREXP_MANT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 387:// V_FREXP_EXP_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 388:// V_FLOOR_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 389:// V_CEIL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 390:// V_TRUNC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 391:// V_RNDNE_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 392:// V_FRACT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 393:// V_SIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 394:// V_COS_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 395:// V_EXP_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 396:// V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 397:// V_CVT_NORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 398:// V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 399:// V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 401:// V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +break; +case 402:// V_ACCVGPR_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +break; +case 256:// V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 257:// V_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 258:// V_SUB_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 259:// V_SUBREV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 260:// V_FMAC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 261:// V_MUL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 262:// V_MUL_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 263:// V_MUL_HI_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 264:// V_MUL_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 265:// V_MUL_HI_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 266:// V_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 267:// V_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 268:// V_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 269:// V_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 270:// V_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 271:// V_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 272:// V_LSHRREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 273:// V_ASHRREV_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 274:// V_LSHLREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 275:// V_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 276:// V_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 277:// V_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 278:// V_MAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 287:// V_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 288:// V_SUB_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 289:// V_SUBREV_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 290:// V_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 291:// V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 294:// V_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 295:// V_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 296:// V_SUBREV_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 297:// V_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 298:// V_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 299:// V_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 300:// V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 301:// V_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 302:// V_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 303:// V_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 304:// V_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 305:// V_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 306:// V_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 307:// V_LDEXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 308:// V_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 309:// V_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 310:// V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 311:// V_DOT2C_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 312:// V_DOT2C_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 313:// V_DOT4C_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 314:// V_DOT8C_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 315:// V_FMAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 316:// V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 317:// V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 448:// V_MAD_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 449:// V_MAD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 450:// V_MAD_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 451:// V_MAD_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 452:// V_CUBEID_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 453:// V_CUBESC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 454:// V_CUBETC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 455:// V_CUBEMA_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 456:// V_BFE_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 457:// V_BFE_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 458:// V_BFI_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 459:// V_FMA_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 460:// V_FMA_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 461:// V_LERP_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 462:// V_ALIGNBIT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 463:// V_ALIGNBYTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 464:// V_MIN3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 465:// V_MIN3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 466:// V_MIN3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 467:// V_MAX3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 468:// V_MAX3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 469:// V_MAX3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 470:// V_MED3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 471:// V_MED3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 472:// V_MED3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 473:// V_SAD_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 474:// V_SAD_HI_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 475:// V_SAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 476:// V_SAD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 477:// V_CVT_PK_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 478:// V_DIV_FIXUP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 479:// V_DIV_FIXUP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 482:// V_DIV_FMAS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 483:// V_DIV_FMAS_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 484:// V_MSAD_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 485:// V_QSAD_PK_U16_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 486:// V_MQSAD_PK_U16_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 487:// V_MQSAD_U32_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,32),true,false); +break; +case 490:// V_MAD_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 491:// V_MAD_LEGACY_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 492:// V_MAD_LEGACY_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 493:// V_PERM_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 494:// V_FMA_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 495:// V_DIV_FIXUP_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 496:// V_CVT_PKACCUM_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 497:// V_MAD_U32_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 498:// V_MAD_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 499:// V_XAD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 500:// V_MIN3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 501:// V_MIN3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 502:// V_MIN3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 503:// V_MAX3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 504:// V_MAX3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 505:// V_MAX3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 506:// V_MED3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 507:// V_MED3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 508:// V_MED3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 509:// V_LSHL_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 510:// V_ADD_LSHL_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 511:// V_ADD3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 512:// V_LSHL_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 513:// V_AND_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 514:// V_OR3_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 515:// V_MAD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 516:// V_MAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 517:// V_MAD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 518:// V_FMA_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 519:// V_DIV_FIXUP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 640:// V_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 641:// V_MUL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 642:// V_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 643:// V_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 644:// V_LDEXP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 645:// V_MUL_LO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 646:// V_MUL_HI_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 647:// V_MUL_HI_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 648:// V_LDEXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 649:// V_READLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +break; +case 650:// V_WRITELANE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +break; +case 651:// V_BCNT_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 652:// V_MBCNT_LO_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 653:// V_MBCNT_HI_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 655:// V_LSHLREV_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 656:// V_LSHRREV_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 657:// V_ASHRREV_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 658:// V_TRIG_PREOP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 659:// V_BFM_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 660:// V_CVT_PKNORM_I16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 661:// V_CVT_PKNORM_U16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 662:// V_CVT_PKRTZ_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 663:// V_CVT_PK_U16_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 664:// V_CVT_PK_I16_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 665:// V_CVT_PKNORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 666:// V_CVT_PKNORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 668:// V_ADD_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 669:// V_SUB_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 670:// V_ADD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 671:// V_SUB_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 672:// V_PACK_B32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 673:// V_MUL_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 16:// V_CMP_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 17:// V_CMPX_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 18:// V_CMP_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 19:// V_CMPX_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 20:// V_CMP_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 21:// V_CMPX_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 32:// V_CMP_F_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 33:// V_CMP_LT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 34:// V_CMP_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 35:// V_CMP_LE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 36:// V_CMP_GT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 37:// V_CMP_LG_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 38:// V_CMP_GE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 39:// V_CMP_O_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 40:// V_CMP_U_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 41:// V_CMP_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 42:// V_CMP_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 43:// V_CMP_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 44:// V_CMP_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 45:// V_CMP_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 46:// V_CMP_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 47:// V_CMP_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 48:// V_CMPX_F_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 49:// V_CMPX_LT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 50:// V_CMPX_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 51:// V_CMPX_LE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 52:// V_CMPX_GT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 53:// V_CMPX_LG_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 54:// V_CMPX_GE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 55:// V_CMPX_O_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 56:// V_CMPX_U_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 57:// V_CMPX_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 58:// V_CMPX_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 59:// V_CMPX_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 60:// V_CMPX_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 61:// V_CMPX_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 62:// V_CMPX_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 63:// V_CMPX_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 64:// V_CMP_F_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 65:// V_CMP_LT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 66:// V_CMP_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 67:// V_CMP_LE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 68:// V_CMP_GT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 69:// V_CMP_LG_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 70:// V_CMP_GE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 71:// V_CMP_O_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 72:// V_CMP_U_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 73:// V_CMP_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 74:// V_CMP_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 75:// V_CMP_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 76:// V_CMP_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 77:// V_CMP_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 78:// V_CMP_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 79:// V_CMP_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 80:// V_CMPX_F_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 81:// V_CMPX_LT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 82:// V_CMPX_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 83:// V_CMPX_LE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 84:// V_CMPX_GT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 85:// V_CMPX_LG_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 86:// V_CMPX_GE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 87:// V_CMPX_O_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 88:// V_CMPX_U_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 89:// V_CMPX_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 90:// V_CMPX_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 91:// V_CMPX_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 92:// V_CMPX_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 93:// V_CMPX_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 94:// V_CMPX_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 95:// V_CMPX_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 96:// V_CMP_F_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 97:// V_CMP_LT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 98:// V_CMP_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 99:// V_CMP_LE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 100:// V_CMP_GT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 101:// V_CMP_LG_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 102:// V_CMP_GE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 103:// V_CMP_O_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 104:// V_CMP_U_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 105:// V_CMP_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 106:// V_CMP_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 107:// V_CMP_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 108:// V_CMP_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 109:// V_CMP_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 110:// V_CMP_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 111:// V_CMP_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 112:// V_CMPX_F_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 113:// V_CMPX_LT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 114:// V_CMPX_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 115:// V_CMPX_LE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 116:// V_CMPX_GT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 117:// V_CMPX_LG_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 118:// V_CMPX_GE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 119:// V_CMPX_O_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 120:// V_CMPX_U_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 121:// V_CMPX_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 122:// V_CMPX_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 123:// V_CMPX_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 124:// V_CMPX_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 125:// V_CMPX_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 126:// V_CMPX_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 127:// V_CMPX_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 160:// V_CMP_F_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 161:// V_CMP_LT_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 162:// V_CMP_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 163:// V_CMP_LE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 164:// V_CMP_GT_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 165:// V_CMP_NE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 166:// V_CMP_GE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 167:// V_CMP_T_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 168:// V_CMP_F_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 169:// V_CMP_LT_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 170:// V_CMP_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 171:// V_CMP_LE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 172:// V_CMP_GT_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 173:// V_CMP_NE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 174:// V_CMP_GE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 175:// V_CMP_T_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 176:// V_CMPX_F_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 177:// V_CMPX_LT_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 178:// V_CMPX_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 179:// V_CMPX_LE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 180:// V_CMPX_GT_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 181:// V_CMPX_NE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 182:// V_CMPX_GE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 183:// V_CMPX_T_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 184:// V_CMPX_F_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 185:// V_CMPX_LT_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 186:// V_CMPX_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 187:// V_CMPX_LE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 188:// V_CMPX_GT_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 189:// V_CMPX_NE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 190:// V_CMPX_GE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 191:// V_CMPX_T_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 192:// V_CMP_F_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 193:// V_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 194:// V_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 195:// V_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 196:// V_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 197:// V_CMP_NE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 198:// V_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 199:// V_CMP_T_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 200:// V_CMP_F_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 201:// V_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 202:// V_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 203:// V_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 204:// V_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 205:// V_CMP_NE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 206:// V_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 207:// V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 208:// V_CMPX_F_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 209:// V_CMPX_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 210:// V_CMPX_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 211:// V_CMPX_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 212:// V_CMPX_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 213:// V_CMPX_NE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 214:// V_CMPX_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 215:// V_CMPX_T_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 216:// V_CMPX_F_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 217:// V_CMPX_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 218:// V_CMPX_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 219:// V_CMPX_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 220:// V_CMPX_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 221:// V_CMPX_NE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 222:// V_CMPX_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 223:// V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 224:// V_CMP_F_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 225:// V_CMP_LT_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 226:// V_CMP_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 227:// V_CMP_LE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 228:// V_CMP_GT_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 229:// V_CMP_NE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 230:// V_CMP_GE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 231:// V_CMP_T_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 232:// V_CMP_F_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 233:// V_CMP_LT_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 234:// V_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 235:// V_CMP_LE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 236:// V_CMP_GT_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 237:// V_CMP_NE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 238:// V_CMP_GE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 239:// V_CMP_T_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 240:// V_CMPX_F_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 241:// V_CMPX_LT_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 242:// V_CMPX_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 243:// V_CMPX_LE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 244:// V_CMPX_GT_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 245:// V_CMPX_NE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 246:// V_CMPX_GE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 247:// V_CMPX_T_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 248:// V_CMPX_F_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 249:// V_CMPX_LT_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 250:// V_CMPX_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 251:// V_CMPX_LE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 252:// V_CMPX_GT_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 253:// V_CMPX_NE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 254:// V_CMPX_GE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 255:// V_CMPX_T_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP2Operands(){ +layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; +switch(layout.OP){ +case 0:// V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 1:// V_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 2:// V_SUB_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 3:// V_SUBREV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 4:// V_FMAC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 5:// V_MUL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 6:// V_MUL_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 7:// V_MUL_HI_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 8:// V_MUL_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 9:// V_MUL_HI_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 10:// V_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 11:// V_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 12:// V_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 13:// V_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 14:// V_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 15:// V_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 16:// V_LSHRREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 17:// V_ASHRREV_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 18:// V_LSHLREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 19:// V_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 20:// V_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 21:// V_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 22:// V_MAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 25:// V_ADD_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 26:// V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 27:// V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 28:// V_ADDC_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 29:// V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 30:// V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 31:// V_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 32:// V_SUB_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 33:// V_SUBREV_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 34:// V_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 35:// V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 38:// V_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 39:// V_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 40:// V_SUBREV_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 41:// V_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 42:// V_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 43:// V_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 44:// V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 45:// V_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 46:// V_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 47:// V_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 48:// V_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 49:// V_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 50:// V_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 51:// V_LDEXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 52:// V_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 53:// V_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 54:// V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 55:// V_DOT2C_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 56:// V_DOT2C_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 57:// V_DOT4C_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 58:// V_DOT8C_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 59:// V_FMAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 60:// V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 61:// V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP2_LITERALOperands(){ +layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; +switch(layout.OP){ +case 23:// V_MADMK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 24:// V_MADAK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +break; +case 36:// V_MADMK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 37:// V_MADAK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP3BOperands(){ +layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; +switch(layout.OP){ +case 281:// V_ADD_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 282:// V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 283:// V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 284:// V_ADDC_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 285:// V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 286:// V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 480:// V_DIV_SCALE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 481:// V_DIV_SCALE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 488:// V_MAD_U64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 489:// V_MAD_I64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP3POperands(){ +layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; +switch(layout.OP){ +case 0:// V_PK_MAD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 1:// V_PK_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 2:// V_PK_ADD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 3:// V_PK_SUB_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 4:// V_PK_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 5:// V_PK_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 6:// V_PK_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 7:// V_PK_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 8:// V_PK_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 9:// V_PK_MAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 10:// V_PK_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 11:// V_PK_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 12:// V_PK_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 13:// V_PK_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 14:// V_PK_FMA_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 15:// V_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 16:// V_PK_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 17:// V_PK_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 18:// V_PK_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 32:// V_MAD_MIX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 33:// V_MAD_MIXLO_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 34:// V_MAD_MIXHI_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 35:// V_DOT2_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 38:// V_DOT2_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 39:// V_DOT2_U32_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 40:// V_DOT4_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 41:// V_DOT4_U32_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 42:// V_DOT8_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 43:// V_DOT8_U32_U4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 48:// V_PK_FMA_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 49:// V_PK_MUL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 50:// V_PK_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 51:// V_PK_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 88:// V_ACCVGPR_READ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +break; +case 89:// V_ACCVGPR_WRITE +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOP3P_MFMAOperands(){ +layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; +switch(layout.OP){ +case 64:// V_MFMA_F32_32X32X1F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 65:// V_MFMA_F32_16X16X1F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 66:// V_MFMA_F32_4X4X1F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 68:// V_MFMA_F32_32X32X2F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 69:// V_MFMA_F32_16X16X4F32 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 72:// V_MFMA_F32_32X32X4F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 73:// V_MFMA_F32_16X16X4F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 74:// V_MFMA_F32_4X4X4F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 76:// V_MFMA_F32_32X32X8F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 77:// V_MFMA_F32_16X16X16F16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 80:// V_MFMA_I32_32X32X4I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 81:// V_MFMA_I32_16X16X4I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 82:// V_MFMA_I32_4X4X4I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 84:// V_MFMA_I32_32X32X8I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 85:// V_MFMA_I32_16X16X16I8 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 99:// V_MFMA_F32_32X32X4BF16_1K +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 100:// V_MFMA_F32_16X16X4BF16_1K +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 101:// V_MFMA_F32_4X4X4BF16_1K +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 102:// V_MFMA_F32_32X32X8BF16_1K +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 103:// V_MFMA_F32_16X16X16BF16_1K +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 104:// V_MFMA_F32_32X32X2BF16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 105:// V_MFMA_F32_16X16X2BF16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 107:// V_MFMA_F32_4X4X2BF16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 108:// V_MFMA_F32_32X32X4BF16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 109:// V_MFMA_F32_16X16X8BF16 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 110:// V_MFMA_F64_16X16X4F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 111:// V_MFMA_F64_4X4X4F64 +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_cdna2::finalizeENC_VOPCOperands(){ +layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; +switch(layout.OP){ +case 16:// V_CMP_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 17:// V_CMPX_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 18:// V_CMP_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 19:// V_CMPX_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 20:// V_CMP_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 21:// V_CMPX_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 32:// V_CMP_F_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 33:// V_CMP_LT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 34:// V_CMP_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 35:// V_CMP_LE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 36:// V_CMP_GT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 37:// V_CMP_LG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 38:// V_CMP_GE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 39:// V_CMP_O_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 40:// V_CMP_U_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 41:// V_CMP_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 42:// V_CMP_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 43:// V_CMP_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 44:// V_CMP_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 45:// V_CMP_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 46:// V_CMP_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 47:// V_CMP_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 48:// V_CMPX_F_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 49:// V_CMPX_LT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 50:// V_CMPX_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 51:// V_CMPX_LE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 52:// V_CMPX_GT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 53:// V_CMPX_LG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 54:// V_CMPX_GE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 55:// V_CMPX_O_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 56:// V_CMPX_U_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 57:// V_CMPX_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 58:// V_CMPX_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 59:// V_CMPX_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 60:// V_CMPX_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 61:// V_CMPX_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 62:// V_CMPX_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 63:// V_CMPX_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 64:// V_CMP_F_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 65:// V_CMP_LT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 66:// V_CMP_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 67:// V_CMP_LE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 68:// V_CMP_GT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 69:// V_CMP_LG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 70:// V_CMP_GE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 71:// V_CMP_O_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 72:// V_CMP_U_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 73:// V_CMP_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 74:// V_CMP_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 75:// V_CMP_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 76:// V_CMP_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 77:// V_CMP_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 78:// V_CMP_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 79:// V_CMP_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 80:// V_CMPX_F_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 81:// V_CMPX_LT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 82:// V_CMPX_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 83:// V_CMPX_LE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 84:// V_CMPX_GT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 85:// V_CMPX_LG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 86:// V_CMPX_GE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 87:// V_CMPX_O_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 88:// V_CMPX_U_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 89:// V_CMPX_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 90:// V_CMPX_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 91:// V_CMPX_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 92:// V_CMPX_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 93:// V_CMPX_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 94:// V_CMPX_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 95:// V_CMPX_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 96:// V_CMP_F_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 97:// V_CMP_LT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 98:// V_CMP_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 99:// V_CMP_LE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 100:// V_CMP_GT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 101:// V_CMP_LG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 102:// V_CMP_GE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 103:// V_CMP_O_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 104:// V_CMP_U_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 105:// V_CMP_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 106:// V_CMP_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 107:// V_CMP_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 108:// V_CMP_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 109:// V_CMP_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 110:// V_CMP_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 111:// V_CMP_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 112:// V_CMPX_F_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 113:// V_CMPX_LT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 114:// V_CMPX_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 115:// V_CMPX_LE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 116:// V_CMPX_GT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 117:// V_CMPX_LG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 118:// V_CMPX_GE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 119:// V_CMPX_O_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 120:// V_CMPX_U_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 121:// V_CMPX_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 122:// V_CMPX_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 123:// V_CMPX_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 124:// V_CMPX_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 125:// V_CMPX_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 126:// V_CMPX_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 127:// V_CMPX_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 160:// V_CMP_F_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 161:// V_CMP_LT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 162:// V_CMP_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 163:// V_CMP_LE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 164:// V_CMP_GT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 165:// V_CMP_NE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 166:// V_CMP_GE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 167:// V_CMP_T_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 168:// V_CMP_F_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 169:// V_CMP_LT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 170:// V_CMP_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 171:// V_CMP_LE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 172:// V_CMP_GT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 173:// V_CMP_NE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 174:// V_CMP_GE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 175:// V_CMP_T_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 176:// V_CMPX_F_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 177:// V_CMPX_LT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 178:// V_CMPX_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 179:// V_CMPX_LE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 180:// V_CMPX_GT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 181:// V_CMPX_NE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 182:// V_CMPX_GE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 183:// V_CMPX_T_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 184:// V_CMPX_F_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 185:// V_CMPX_LT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 186:// V_CMPX_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 187:// V_CMPX_LE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 188:// V_CMPX_GT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 189:// V_CMPX_NE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 190:// V_CMPX_GE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 191:// V_CMPX_T_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 192:// V_CMP_F_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 193:// V_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 194:// V_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 195:// V_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 196:// V_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 197:// V_CMP_NE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 198:// V_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 199:// V_CMP_T_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 200:// V_CMP_F_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 201:// V_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 202:// V_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 203:// V_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 204:// V_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 205:// V_CMP_NE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 206:// V_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 207:// V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 208:// V_CMPX_F_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 209:// V_CMPX_LT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 210:// V_CMPX_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 211:// V_CMPX_LE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 212:// V_CMPX_GT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 213:// V_CMPX_NE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 214:// V_CMPX_GE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 215:// V_CMPX_T_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 216:// V_CMPX_F_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 217:// V_CMPX_LT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 218:// V_CMPX_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 219:// V_CMPX_LE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 220:// V_CMPX_GT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 221:// V_CMPX_NE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 222:// V_CMPX_GE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 223:// V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 224:// V_CMP_F_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 225:// V_CMP_LT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 226:// V_CMP_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 227:// V_CMP_LE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 228:// V_CMP_GT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 229:// V_CMP_NE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 230:// V_CMP_GE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 231:// V_CMP_T_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 232:// V_CMP_F_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 233:// V_CMP_LT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 234:// V_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 235:// V_CMP_LE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 236:// V_CMP_GT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 237:// V_CMP_NE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 238:// V_CMP_GE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 239:// V_CMP_T_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 240:// V_CMPX_F_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 241:// V_CMPX_LT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 242:// V_CMPX_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 243:// V_CMPX_LE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 244:// V_CMPX_GT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 245:// V_CMPX_NE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 246:// V_CMPX_GE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 247:// V_CMPX_T_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 248:// V_CMPX_F_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 249:// V_CMPX_LT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 250:// V_CMPX_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 251:// V_CMPX_LE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 252:// V_CMPX_GT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 253:// V_CMPX_NE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 254:// V_CMPX_GE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 255:// V_CMPX_T_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +} +} diff --git a/instructionAPI/src/InstructionDecoder-amdgpu-vega.C b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C similarity index 98% rename from instructionAPI/src/InstructionDecoder-amdgpu-vega.C rename to instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C index 79ec72be3d..1666eb7387 100644 --- a/instructionAPI/src/InstructionDecoder-amdgpu-vega.C +++ b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C @@ -35,7 +35,8 @@ namespace Dyninst { namespace InstructionAPI { typedef void (InstructionDecoder_amdgpu_vega::*operandFactory)(); - typedef amdgpu_insn_entry amdgpu_insn_table[]; + typedef amdgpu_vega_insn_entry amdgpu_vega_insn_table[]; + typedef amdgpu_mask_entry amdgpu_decoder_table[]; const std::array InstructionDecoder_amdgpu_vega::condNames = { { @@ -54,7 +55,7 @@ namespace Dyninst { }; } -#include "amdgpu_insn_entry.h" +#include "amdgpu_vega_insn_entry.h" struct amdgpu_mask_entry { unsigned int mask; std::size_t branchCnt; @@ -65,7 +66,7 @@ namespace Dyninst { static const std::pair branchTable[]; }; -#include "amdgpu_opcode_tables.C" +#include "amdgpu_vega_opcode_tables.C" InstructionDecoder_amdgpu_vega::InstructionDecoder_amdgpu_vega(Architecture a) : InstructionDecoderImpl(a), @@ -554,7 +555,7 @@ namespace Dyninst { void InstructionDecoder_amdgpu_vega::finalizeVOP3POperands() { } - bool InstructionDecoder_amdgpu_vega::decodeOperands(const amdgpu_insn_entry & insn_entry) { + bool InstructionDecoder_amdgpu_vega::decodeOperands(const amdgpu_vega_insn_entry & insn_entry) { if(insn_entry.operandCnt!=0){ for (std::size_t i =0 ; i < insn_entry.operandCnt; i++){ std::mem_fun(insn_entry.operands[i])(this); @@ -575,7 +576,7 @@ namespace Dyninst { Expression::Ptr InstructionDecoder_amdgpu_vega::decodeVDST(unsigned int index){ - index += 255; + index += 256; return decodeSSRC(index); } @@ -671,7 +672,7 @@ namespace Dyninst { //std::cerr << "\nusing imm " << imm << std::endl; return Immediate::makeImmediate(Result(u32, unsign_extend32(32,immLiteral ))); }else if( 256 <= index && index <= 511){ - MachRegister mr = makeAmdgpuRegID(amdgpu_vega::vgpr0,index >>8); + MachRegister mr = makeAmdgpuRegID(amdgpu_vega::vgpr0,index &0xff); return makeRegisterExpression(mr); } @@ -680,7 +681,7 @@ namespace Dyninst { assert(0 && "unknown register value "); } -#include "amdgpu_decoder_impl_vega.C" +#include "amdgpu_vega_decoder_impl.C" void InstructionDecoder_amdgpu_vega::reset(){ immLen = 0; @@ -732,7 +733,7 @@ namespace Dyninst { if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){ std::mem_fun(decode_lookup_table[instr_family])(this); } - //debug_instr(); + debug_instr(); cout.clear(); b.start += insn_in_progress->size(); return *insn_in_progress; diff --git a/instructionAPI/src/InstructionDecoder-amdgpu-vega.h b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.h similarity index 98% rename from instructionAPI/src/InstructionDecoder-amdgpu-vega.h rename to instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.h index ce89b4701a..e263f5c939 100644 --- a/instructionAPI/src/InstructionDecoder-amdgpu-vega.h +++ b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.h @@ -43,11 +43,11 @@ namespace Dyninst { }while(0) #endif - struct amdgpu_insn_entry; + struct amdgpu_vega_insn_entry; struct amdgpu_mask_entry; class InstructionDecoder_amdgpu_vega : public InstructionDecoderImpl { - friend struct amdgpu_insn_entry; + friend struct amdgpu_vega_insn_entry; friend struct amdgpu_mask_entry; enum DecodeFamily {sopp}; @@ -66,7 +66,7 @@ namespace Dyninst { virtual bool decodeOperands(const Instruction *insn_to_complete); - bool decodeOperands(const amdgpu_insn_entry & insn_entry); + bool decodeOperands(const amdgpu_vega_insn_entry & insn_entry); virtual void doDelayedDecode(const Instruction *insn_to_complete); @@ -334,7 +334,7 @@ namespace Dyninst { void debug_instr(); -#include "amdgpu_decoder_impl_vega.h" +#include "amdgpu_vega_decoder_impl.h" }; } } diff --git a/instructionAPI/src/amdgpu_decoder_impl_vega.C b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C similarity index 84% rename from instructionAPI/src/amdgpu_decoder_impl_vega.C rename to instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C index 6d376c115c..9506a7661d 100644 --- a/instructionAPI/src/amdgpu_decoder_impl_vega.C +++ b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C @@ -5,7 +5,7 @@ void InstructionDecoder_amdgpu_vega::decodeSOP2(){ layout.ssrc1 = longfield<8,15>(insn_long); layout.sdst = longfield<16,22>(insn_long); layout.op = longfield<23,29>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop2_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop2_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSOP2Operands(); @@ -16,7 +16,7 @@ void InstructionDecoder_amdgpu_vega::decodeSOP1(){ layout.ssrc0 = longfield<0,7>(insn_long); layout.op = longfield<8,15>(insn_long); layout.sdst = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop1_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop1_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSOP1Operands(); @@ -27,7 +27,7 @@ void InstructionDecoder_amdgpu_vega::decodeSOPK(){ layout.simm16 = longfield<0,15>(insn_long); layout.sdst = longfield<16,22>(insn_long); layout.op = longfield<23,27>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopk_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopk_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSOPKOperands(); @@ -38,7 +38,7 @@ void InstructionDecoder_amdgpu_vega::decodeSOPC(){ layout.ssrc0 = longfield<0,7>(insn_long); layout.ssrc1 = longfield<8,15>(insn_long); layout.op = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopc_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopc_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSOPCOperands(); @@ -48,7 +48,7 @@ void InstructionDecoder_amdgpu_vega::decodeSOPP(){ layout_sopp & layout = insn_layout.sopp; layout.simm16 = longfield<0,15>(insn_long); layout.op = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopp_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopp_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSOPPOperands(); @@ -65,7 +65,7 @@ void InstructionDecoder_amdgpu_vega::decodeSMEM(){ layout.op = longfield<18,25>(insn_long); layout.offset = longfield<32,52>(insn_long); layout.soffset = longfield<57,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::smem_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::smem_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeSMEMOperands(); @@ -106,7 +106,7 @@ void InstructionDecoder_amdgpu_vega::decodeVOP2(){ vop_literal.bank_mask = longfield<56,59>(insn_long); vop_literal.row_mask = longfield<60,63>(insn_long); } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop2_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop2_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVOP2Operands(); @@ -146,7 +146,7 @@ void InstructionDecoder_amdgpu_vega::decodeVOP1(){ vop_literal.bank_mask = longfield<56,59>(insn_long); vop_literal.row_mask = longfield<60,63>(insn_long); } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop1_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop1_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVOP1Operands(); @@ -184,7 +184,7 @@ void InstructionDecoder_amdgpu_vega::decodeVOPC(){ vop_literal.bank_mask = longfield<56,59>(insn_long); vop_literal.row_mask = longfield<60,63>(insn_long); } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vopc_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vopc_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVOPCOperands(); @@ -197,7 +197,7 @@ void InstructionDecoder_amdgpu_vega::decodeVINTRP(){ layout.attr = longfield<10,15>(insn_long); layout.op = longfield<16,17>(insn_long); layout.vdst = longfield<18,25>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vintrp_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vintrp_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVINTRPOperands(); @@ -213,7 +213,7 @@ void InstructionDecoder_amdgpu_vega::decodeDS(){ layout.data0 = longfield<40,47>(insn_long); layout.data1 = longfield<48,55>(insn_long); layout.vdst = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::ds_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::ds_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeDSOperands(); @@ -234,7 +234,7 @@ void InstructionDecoder_amdgpu_vega::decodeMTBUF(){ layout.slc = longfield<54,54>(insn_long); layout.tfe = longfield<55,55>(insn_long); layout.soffset = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mtbuf_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mtbuf_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeMTBUFOperands(); @@ -254,7 +254,7 @@ void InstructionDecoder_amdgpu_vega::decodeMUBUF(){ layout.srsrc = longfield<48,52>(insn_long); layout.tfe = longfield<55,55>(insn_long); layout.soffset = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mubuf_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mubuf_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeMUBUFOperands(); @@ -263,7 +263,7 @@ void InstructionDecoder_amdgpu_vega::decodeVOP3AB(){ unsigned insn_size_ = 8; layout_vop3ab & layout = insn_layout.vop3ab; layout.op = longfield<16,25>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3ab_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3ab_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVOP3ABOperands(); @@ -282,7 +282,7 @@ void InstructionDecoder_amdgpu_vega::decodeVOP3P(){ layout.src2 = longfield<50,58>(insn_long); layout.opsel_hi = longfield<59,60>(insn_long); layout.neg = longfield<61,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3p_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3p_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeVOP3POperands(); @@ -301,7 +301,7 @@ void InstructionDecoder_amdgpu_vega::decodeFLAT(){ layout.saddr = longfield<48,54>(insn_long); layout.nv = longfield<55,55>(insn_long); layout.vdst = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::flat_insn_table[layout.op]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::flat_insn_table[layout.op]; decodeOperands(insn_entry); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); finalizeFLATOperands(); @@ -373,7 +373,7 @@ void InstructionDecoder_amdgpu_vega::mainDecode(InstructionDecoder::buffer &b){ void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer &b){ if(IS_SOP2(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop2_insn_table[longfield<23,29>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop2_insn_table[longfield<23,29>(insn_long)]; setUseImm<0,7,255>(b,4); setUseImm<8,15,255>(b,4); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); @@ -381,38 +381,38 @@ void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer } else if(IS_SOP1(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop1_insn_table[longfield<8,15>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop1_insn_table[longfield<8,15>(insn_long)]; setUseImm<0,7,255>(b,4); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = SOP1; } else if(IS_SOPK(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopk_insn_table[longfield<23,27>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopk_insn_table[longfield<23,27>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = SOPK; } else if(IS_SOPC(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopc_insn_table[longfield<16,22>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopc_insn_table[longfield<16,22>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = SOPC; } else if(IS_SOPP(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopp_insn_table[longfield<16,22>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopp_insn_table[longfield<16,22>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = SOPP; } else if(IS_SMEM(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::smem_insn_table[longfield<18,25>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::smem_insn_table[longfield<18,25>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = SMEM; } else if(IS_VOP2(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop2_insn_table[longfield<25,30>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop2_insn_table[longfield<25,30>(insn_long)]; setUseImm<0,8,249>(b,4); setUseImm<0,8,250>(b,4); setUseImm<0,8,255>(b,4); @@ -421,7 +421,7 @@ void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer } else if(IS_VOP1(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop1_insn_table[longfield<9,16>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop1_insn_table[longfield<9,16>(insn_long)]; setUseImm<0,8,249>(b,4); setUseImm<0,8,250>(b,4); setUseImm<0,8,255>(b,4); @@ -430,50 +430,50 @@ void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer } else if(IS_VOPC(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vopc_insn_table[longfield<17,24>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vopc_insn_table[longfield<17,24>(insn_long)]; setUseImm<0,8,255>(b,4); this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = VOPC; } else if(IS_VINTRP(insn_long)){ unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vintrp_insn_table[longfield<16,17>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vintrp_insn_table[longfield<16,17>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = VINTRP; } else if(IS_DS(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::ds_insn_table[longfield<17,24>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::ds_insn_table[longfield<17,24>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = DS; } else if(IS_MTBUF(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mtbuf_insn_table[longfield<15,18>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mtbuf_insn_table[longfield<15,18>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = MTBUF; } else if(IS_MUBUF(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mubuf_insn_table[longfield<18,24>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mubuf_insn_table[longfield<18,24>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = MUBUF; } else if(IS_VOP3AB(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3ab_insn_table[longfield<16,25>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3ab_insn_table[longfield<16,25>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = VOP3AB; } else if(IS_VOP3P(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3p_insn_table[longfield<11,13>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3p_insn_table[longfield<11,13>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = VOP3P; } else if(IS_FLAT(insn_long)){ unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::flat_insn_table[longfield<18,24>(insn_long)]; + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::flat_insn_table[longfield<18,24>(insn_long)]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); instr_family = FLAT; } diff --git a/instructionAPI/src/amdgpu_decoder_impl_vega.h b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.h similarity index 100% rename from instructionAPI/src/amdgpu_decoder_impl_vega.h rename to instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.h diff --git a/instructionAPI/src/AMDGPU/vega/amdgpu_vega_insn_entry.h b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_insn_entry.h new file mode 100644 index 0000000000..0e56a586da --- /dev/null +++ b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_insn_entry.h @@ -0,0 +1,24 @@ +struct amdgpu_vega_insn_entry { + entryID op; + const char *mnemonic; + std::size_t operandCnt; + const operandFactory *operands; + static const amdgpu_vega_insn_table main_insn_table; + static const operandFactory operandTable[]; + static const amdgpu_vega_insn_table sop2_insn_table; + static const amdgpu_vega_insn_table sop1_insn_table; + static const amdgpu_vega_insn_table sopk_insn_table; + static const amdgpu_vega_insn_table sopc_insn_table; + static const amdgpu_vega_insn_table sopp_insn_table; + static const amdgpu_vega_insn_table smem_insn_table; + static const amdgpu_vega_insn_table vop2_insn_table; + static const amdgpu_vega_insn_table vop1_insn_table; + static const amdgpu_vega_insn_table vopc_insn_table; + static const amdgpu_vega_insn_table vintrp_insn_table; + static const amdgpu_vega_insn_table ds_insn_table; + static const amdgpu_vega_insn_table mtbuf_insn_table; + static const amdgpu_vega_insn_table mubuf_insn_table; + static const amdgpu_vega_insn_table vop3ab_insn_table; + static const amdgpu_vega_insn_table vop3p_insn_table; + static const amdgpu_vega_insn_table flat_insn_table; +}; diff --git a/instructionAPI/src/amdgpu_opcode_tables.C b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_opcode_tables.C similarity index 96% rename from instructionAPI/src/amdgpu_opcode_tables.C rename to instructionAPI/src/AMDGPU/vega/amdgpu_vega_opcode_tables.C index ae76753077..d4bf51f453 100644 --- a/instructionAPI/src/amdgpu_opcode_tables.C +++ b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_opcode_tables.C @@ -1,5 +1,5 @@ #define fn(...) (&InstructionDecoder_amdgpu_vega::__VA_ARGS__) -const operandFactory amdgpu_insn_entry::operandTable[] = { +const operandFactory amdgpu_vega_insn_entry::operandTable[] = { fn(NOTHING), fn(setSMEM),fn(setLoad<1>),//s_load_dword fn(setSMEM),fn(setLoad<2>),//s_load_dwordx2 @@ -41,7 +41,7 @@ const operandFactory amdgpu_insn_entry::operandTable[] = { fn(setBranch),fn(setModifyPC),//s_setpc_b64 fn(setBranch),fn(setModifyPC),//s_swappc_b64 }; -const amdgpu_insn_table amdgpu_insn_entry::sop2_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::sop2_insn_table = { {amdgpu_op_s_add_u32,"s_add_u32",0,&operandTable[0]} ,//0 {amdgpu_op_s_sub_u32,"s_sub_u32",0,&operandTable[0]} ,//1 {amdgpu_op_s_add_i32,"s_add_i32",0,&operandTable[0]} ,//2 @@ -95,9 +95,9 @@ const amdgpu_insn_table amdgpu_insn_entry::sop2_insn_table = { {amdgpu_op_s_pack_ll_b32_b16,"s_pack_ll_b32_b16",0,&operandTable[0]} ,//50 {amdgpu_op_s_pack_lh_b32_b16,"s_pack_lh_b32_b16",0,&operandTable[0]} ,//51 {amdgpu_op_s_pack_hh_b32_B16,"s_pack_hh_b32_B16",0,&operandTable[0]} ,//52 -}; // end s_pack_hh_b32_B16_insn_table +}; // end sop2_insn_table -const amdgpu_insn_table amdgpu_insn_entry::sop1_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::sop1_insn_table = { {amdgpu_op_s_mov_b32,"s_mov_b32",0,&operandTable[0]} ,//0 {amdgpu_op_s_mov_b64,"s_mov_b64",0,&operandTable[0]} ,//1 {amdgpu_op_s_cmov_b32,"s_cmov_b32",0,&operandTable[0]} ,//2 @@ -154,9 +154,9 @@ const amdgpu_insn_table amdgpu_insn_entry::sop1_insn_table = { {amdgpu_op_s_andn1_wrexec_b64,"s_andn1_wrexec_b64",0,&operandTable[0]} ,//53 {amdgpu_op_s_andn2_wrexec_b64,"s_andn2_wrexec_b64",0,&operandTable[0]} ,//54 {amdgpu_op_s_bitreplicate_b64_b32,"s_bitreplicate_b64_b32",0,&operandTable[0]} ,//55 -}; // end s_bitreplicate_b64_b32_insn_table +}; // end sop1_insn_table -const amdgpu_insn_table amdgpu_insn_entry::sopk_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::sopk_insn_table = { {amdgpu_op_s_movk_i32,"s_movk_i32",0,&operandTable[0]} ,//0 {amdgpu_op_s_cmovk_i32,"s_cmovk_i32",0,&operandTable[0]} ,//1 {amdgpu_op_s_cmpk_eq_i32,"s_cmpk_eq_i32",0,&operandTable[0]} ,//2 @@ -179,20 +179,20 @@ const amdgpu_insn_table amdgpu_insn_entry::sopk_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 {amdgpu_op_s_setreg_imm32_b32,"s_setreg_imm32_b32",0,&operandTable[0]} ,//20 {amdgpu_op_s_call_b64,"s_call_b64",2,&operandTable[72]} ,//21 -}; // end s_call_b64_insn_table +}; // end sopk_insn_table -const amdgpu_insn_table amdgpu_insn_entry::sopc_insn_table = { - {amdgpu_op_s_cmp_ge_eq_i32,"s_cmp_ge_eq_i32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_cmp_ge_eq_u32,"s_cmp_ge_eq_u32",0,&operandTable[0]} ,//1 - {amdgpu_op_s_cmp_lg_i32,"s_cmp_lg_i32",0,&operandTable[0]} ,//2 - {amdgpu_op_s_cmp_lg_u32,"s_cmp_lg_u32",0,&operandTable[0]} ,//3 - {amdgpu_op_s_cmp_gt_i32,"s_cmp_gt_i32",0,&operandTable[0]} ,//4 - {amdgpu_op_s_cmp_gt_u32,"s_cmp_gt_u32",0,&operandTable[0]} ,//5 - {amdgpu_op_s_cmp_ge_i32,"s_cmp_ge_i32",0,&operandTable[0]} ,//6 - {amdgpu_op_s_cmp_ge_u32,"s_cmp_ge_u32",0,&operandTable[0]} ,//7 - {amdgpu_op_s_cmp_lt_i32,"s_cmp_lt_i32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_cmp_lt_u32,"s_cmp_lt_u32",0,&operandTable[0]} ,//9 - {amdgpu_op_s_cmp_le_i32,"s_cmp_le_i32",0,&operandTable[0]} ,//10 +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::sopc_insn_table = { + {amdgpu_op_s_cmp_eq_i32,"s_cmp_eq_i32",0,&operandTable[0]} ,//0 + {amdgpu_op_s_cmp_lg_i32,"s_cmp_lg_i32",0,&operandTable[0]} ,//1 + {amdgpu_op_s_cmp_gt_i32,"s_cmp_gt_i32",0,&operandTable[0]} ,//2 + {amdgpu_op_s_cmp_ge_i32,"s_cmp_ge_i32",0,&operandTable[0]} ,//3 + {amdgpu_op_s_cmp_lt_i32,"s_cmp_lt_i32",0,&operandTable[0]} ,//4 + {amdgpu_op_s_cmp_le_i32,"s_cmp_le_i32",0,&operandTable[0]} ,//5 + {amdgpu_op_s_cmp_eq_u32,"s_cmp_eq_u32",0,&operandTable[0]} ,//6 + {amdgpu_op_s_cmp_lg_u32,"s_cmp_lg_u32",0,&operandTable[0]} ,//7 + {amdgpu_op_s_cmp_gt_u32,"s_cmp_gt_u32",0,&operandTable[0]} ,//8 + {amdgpu_op_s_cmp_ge_u32,"s_cmp_ge_u32",0,&operandTable[0]} ,//9 + {amdgpu_op_s_cmp_lt_u32,"s_cmp_lt_u32",0,&operandTable[0]} ,//10 {amdgpu_op_s_cmp_le_u32,"s_cmp_le_u32",0,&operandTable[0]} ,//11 {amdgpu_op_s_bitcmp0_b32,"s_bitcmp0_b32",0,&operandTable[0]} ,//12 {amdgpu_op_s_bitcmp1_b32,"s_bitcmp1_b32",0,&operandTable[0]} ,//13 @@ -202,9 +202,9 @@ const amdgpu_insn_table amdgpu_insn_entry::sopc_insn_table = { {amdgpu_op_s_set_gpr_idx_on,"s_set_gpr_idx_on",0,&operandTable[0]} ,//17 {amdgpu_op_s_cmp_eq_u64,"s_cmp_eq_u64",0,&operandTable[0]} ,//18 {amdgpu_op_s_cmp_lg_u64,"s_cmp_lg_u64",0,&operandTable[0]} ,//19 -}; // end s_cmp_lg_u64_insn_table +}; // end sopc_insn_table -const amdgpu_insn_table amdgpu_insn_entry::sopp_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::sopp_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 {amdgpu_op_s_endpgm,"s_endpgm",0,&operandTable[0]} ,//1 {amdgpu_op_s_branch,"s_branch",1,&operandTable[53]} ,//2 @@ -236,9 +236,9 @@ const amdgpu_insn_table amdgpu_insn_entry::sopp_insn_table = { {amdgpu_op_s_set_gpr_idx_off,"s_set_gpr_idx_off",0,&operandTable[0]} ,//28 {amdgpu_op_s_set_gpr_idx_mode,"s_set_gpr_idx_mode",0,&operandTable[0]} ,//29 {amdgpu_op_s_endpgm_ordered_ps_done,"s_endpgm_ordered_ps_done",0,&operandTable[0]} ,//30 -}; // end s_endpgm_ordered_ps_done_insn_table +}; // end sopp_insn_table -const amdgpu_insn_table amdgpu_insn_entry::smem_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::smem_insn_table = { {amdgpu_op_s_load_dword,"s_load_dword",2,&operandTable[1]} ,//0 {amdgpu_op_s_load_dwordx2,"s_load_dwordx2",2,&operandTable[3]} ,//1 {amdgpu_op_s_load_dwordx4,"s_load_dwordx4",2,&operandTable[5]} ,//2 @@ -412,9 +412,9 @@ const amdgpu_insn_table amdgpu_insn_entry::smem_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//170 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//171 {amdgpu_op_s_atomic_dec_x2,"s_atomic_dec_x2",0,&operandTable[0]} ,//172 -}; // end s_atomic_dec_x2_insn_table +}; // end smem_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vop2_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vop2_insn_table = { {amdgpu_op_v_cndmask_b32,"v_cndmask_b32",0,&operandTable[0]} ,//0 {amdgpu_op_v_add_f32,"v_add_f32",0,&operandTable[0]} ,//1 {amdgpu_op_v_sub_f32,"v_sub_f32",0,&operandTable[0]} ,//2 @@ -477,9 +477,9 @@ const amdgpu_insn_table amdgpu_insn_entry::vop2_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 {amdgpu_op_v_xno2_b32,"v_xno2_b32",0,&operandTable[0]} ,//61 -}; // end v_xno2_b32_insn_table +}; // end vop2_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vop1_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vop1_insn_table = { {amdgpu_op_v_nop,"v_nop",0,&operandTable[0]} ,//0 {amdgpu_op_v_mov_b32,"v_mov_b32",0,&operandTable[0]} ,//1 {amdgpu_op_v_readfirstlane_b32,"v_readfirstlane_b32",0,&operandTable[0]} ,//2 @@ -515,7 +515,7 @@ const amdgpu_insn_table amdgpu_insn_entry::vop1_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 + {amdgpu_op_v_rcp_iflag_f32,"v_rcp_iflag_f32",0,&operandTable[0]} ,//35 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 @@ -562,9 +562,9 @@ const amdgpu_insn_table amdgpu_insn_entry::vop1_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 {amdgpu_op_v_swap_b32,"v_swap_b32",0,&operandTable[0]} ,//81 -}; // end v_swap_b32_insn_table +}; // end vop1_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vopc_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vopc_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 @@ -821,15 +821,15 @@ const amdgpu_insn_table amdgpu_insn_entry::vopc_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//253 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//254 {amdgpu_op_v_cmpx_t_u64,"v_cmpx_t_u64",0,&operandTable[0]} ,//255 -}; // end v_cmpx_t_u64_insn_table +}; // end vopc_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vintrp_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vintrp_insn_table = { {amdgpu_op_v_interp_p1_f32,"v_interp_p1_f32",0,&operandTable[0]} ,//0 {amdgpu_op_v_interp_p2_f32,"v_interp_p2_f32",0,&operandTable[0]} ,//1 {amdgpu_op_v_interp_mov_f32,"v_interp_mov_f32",0,&operandTable[0]} ,//2 -}; // end v_interp_mov_f32_insn_table +}; // end vintrp_insn_table -const amdgpu_insn_table amdgpu_insn_entry::ds_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::ds_insn_table = { {amdgpu_op_ds_add_u32,"ds_add_u32",0,&operandTable[0]} ,//0 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 @@ -843,7 +843,7 @@ const amdgpu_insn_table amdgpu_insn_entry::ds_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 + {amdgpu_op_ds_write_b32,"ds_write_b32",0,&operandTable[0]} ,//13 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//16 @@ -884,8 +884,8 @@ const amdgpu_insn_table amdgpu_insn_entry::ds_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 + {amdgpu_op_ds_read_b32,"ds_read_b32",0,&operandTable[0]} ,//54 + {amdgpu_op_ds_read2_b32,"ds_read2_b32",0,&operandTable[0]} ,//55 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 @@ -1086,9 +1086,9 @@ const amdgpu_insn_table amdgpu_insn_entry::ds_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//253 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//254 {amdgpu_op_ds_read_b128,"ds_read_b128",0,&operandTable[0]} ,//255 -}; // end ds_read_b128_insn_table +}; // end ds_insn_table -const amdgpu_insn_table amdgpu_insn_entry::mtbuf_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::mtbuf_insn_table = { {amdgpu_op_tbuffer_load_format_x,"tbuffer_load_format_x",2,&operandTable[37]} ,//0 {amdgpu_op_tbuffer_load_format_xy,"tbuffer_load_format_xy",2,&operandTable[39]} ,//1 {amdgpu_op_tbuffer_load_format_xyz,"tbuffer_load_format_xyz",2,&operandTable[41]} ,//2 @@ -1105,9 +1105,9 @@ const amdgpu_insn_table amdgpu_insn_entry::mtbuf_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 {amdgpu_op_tbuffer_store_format_d16_xyzw,"tbuffer_store_format_d16_xyzw",0,&operandTable[0]} ,//15 -}; // end tbuffer_store_format_d16_xyzw_insn_table +}; // end mtbuf_insn_table -const amdgpu_insn_table amdgpu_insn_entry::mubuf_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::mubuf_insn_table = { {amdgpu_op_buffer_load_format_x,"buffer_load_format_x",2,&operandTable[21]} ,//0 {amdgpu_op_buffer_load_format_xy,"buffer_load_format_xy",2,&operandTable[23]} ,//1 {amdgpu_op_buffer_load_format_xyz,"buffer_load_format_xyz",2,&operandTable[25]} ,//2 @@ -1116,7 +1116,7 @@ const amdgpu_insn_table amdgpu_insn_entry::mubuf_insn_table = { {amdgpu_op_buffer_store_format_xy,"buffer_store_format_xy",2,&operandTable[31]} ,//5 {amdgpu_op_buffer_store_format_xyz,"buffer_store_format_xyz",2,&operandTable[33]} ,//6 {amdgpu_op_buffer_store_format_xyzw,"buffer_store_format_xyzw",2,&operandTable[35]} ,//7 - {amdgpu_op_buffer_load_dwordx4,"buffer_load_dwordx4",0,&operandTable[0]} ,//8 + {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 @@ -1128,10 +1128,10 @@ const amdgpu_insn_table amdgpu_insn_entry::mubuf_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 + {amdgpu_op_buffer_load_dword,"buffer_load_dword",0,&operandTable[0]} ,//20 + {amdgpu_op_buffer_load_dwordx2,"buffer_load_dwordx2",0,&operandTable[0]} ,//21 + {amdgpu_op_buffer_load_dwordx3,"buffer_load_dwordx3",0,&operandTable[0]} ,//22 + {amdgpu_op_buffer_load_dwordx4,"buffer_load_dwordx4",0,&operandTable[0]} ,//23 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 @@ -1217,9 +1217,9 @@ const amdgpu_insn_table amdgpu_insn_entry::mubuf_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 {amdgpu_op_buffer_atomic_dec_x2,"buffer_atomic_dec_x2",0,&operandTable[0]} ,//108 -}; // end buffer_atomic_dec_x2_insn_table +}; // end mubuf_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vop3ab_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 @@ -1575,7 +1575,7 @@ const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//352 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//353 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//354 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//355 + {amdgpu_op_v_rcp_iflag_f32_e64,"v_rcp_iflag_f32_e64",0,&operandTable[0]} ,//355 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//356 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//357 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//358 @@ -1700,16 +1700,16 @@ const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//477 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//478 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//479 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//480 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//481 + {amdgpu_op_v_div_scale_f32,"v_div_scale_f32",0,&operandTable[0]} ,//480 + {amdgpu_op_v_div_scale_f64,"v_div_scale_f64",0,&operandTable[0]} ,//481 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//482 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//483 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//484 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//485 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//486 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//487 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//488 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//489 + {amdgpu_op_v_mad_u64_u32,"v_mad_u64_u32",0,&operandTable[0]} ,//488 + {amdgpu_op_v_mad_i64_i32,"v_mad_i64_i32",0,&operandTable[0]} ,//489 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//490 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//491 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//492 @@ -1865,9 +1865,9 @@ const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//642 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//643 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//644 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//645 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//646 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//647 + {amdgpu_op_v_mul_lo_u32,"v_mul_lo_u32",0,&operandTable[0]} ,//645 + {amdgpu_op_v_mul_hi_u32,"v_mul_hi_u32",0,&operandTable[0]} ,//646 + {amdgpu_op_v_mul_hi_i32,"v_mul_hi_i32",0,&operandTable[0]} ,//647 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//648 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//649 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//650 @@ -1893,9 +1893,9 @@ const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//670 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//671 {amdgpu_op_v_pack_b32_f16,"v_pack_b32_f16",0,&operandTable[0]} ,//672 -}; // end v_pack_b32_f16_insn_table +}; // end vop3ab_insn_table -const amdgpu_insn_table amdgpu_insn_entry::vop3p_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::vop3p_insn_table = { {amdgpu_op_v_pk_mad_i16,"v_pk_mad_i16",0,&operandTable[0]} ,//0 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 @@ -1940,9 +1940,9 @@ const amdgpu_insn_table amdgpu_insn_entry::vop3p_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 {amdgpu_op_v_dot8_u32_u4,"v_dot8_u32_u4",0,&operandTable[0]} ,//43 -}; // end v_dot8_u32_u4_insn_table +}; // end vop3p_insn_table -const amdgpu_insn_table amdgpu_insn_entry::flat_insn_table = { +const amdgpu_vega_insn_table amdgpu_vega_insn_entry::flat_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 @@ -1959,11 +1959,11 @@ const amdgpu_insn_table amdgpu_insn_entry::flat_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_load_ubyte,"load_ubyte",0,&operandTable[0]} ,//16 + {amdgpu_op_flat_load_ubyte,"flat_load_ubyte",0,&operandTable[0]} ,//16 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_load_dword,"load_dword",0,&operandTable[0]} ,//20 + {amdgpu_op_flat_load_dword,"flat_load_dword",0,&operandTable[0]} ,//20 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 @@ -1971,7 +1971,7 @@ const amdgpu_insn_table amdgpu_insn_entry::flat_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_store_dword,"store_dword",0,&operandTable[0]} ,//28 + {amdgpu_op_flat_store_dword,"flat_store_dword",0,&operandTable[0]} ,//28 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 @@ -2052,5 +2052,5 @@ const amdgpu_insn_table amdgpu_insn_entry::flat_insn_table = { {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 {amdgpu_op_atomic_dec_x2,"atomic_dec_x2",0,&operandTable[0]} ,//108 -}; // end atomic_dec_x2_insn_table +}; // end flat_insn_table diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index 1063d77fc9..a22ff3f109 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -57,622 +57,587 @@ using namespace NS_x86; #include "../../common/src/singleton_object_pool.h" #include "ArchSpecificFormatters.h" +#define DECODE_OPERANDS() \ + do { \ + if (arch_decoded_from != Arch_cuda && arch_decoded_from != Arch_amdgpu_cdna2 && m_Operands.empty()) { \ + decodeOperands(); \ + }\ + }while(0) + namespace Dyninst { - namespace InstructionAPI - { - - static const int IAPI_major_version = DYNINST_MAJOR_VERSION; - static const int IAPI_minor_version = DYNINST_MINOR_VERSION; - static const int IAPI_maintenance_version = DYNINST_PATCH_VERSION; - - void Instruction::version(int& major, int& minor, int& maintenance) - { - major = IAPI_major_version; - minor = IAPI_minor_version; - maintenance = IAPI_maintenance_version; - } - - int Instruction::numInsnsAllocated = 0; - INSTRUCTION_EXPORT Instruction::Instruction(Operation what, - size_t size, const unsigned char* raw, - Dyninst::Architecture arch) - : m_InsnOp(what), m_Valid(true), arch_decoded_from(arch), - formatter(ArchSpecificFormatter::getFormatter(arch)) + namespace InstructionAPI { - copyRaw(size, raw); -#if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) + static const int IAPI_major_version = DYNINST_MAJOR_VERSION; + static const int IAPI_minor_version = DYNINST_MINOR_VERSION; + static const int IAPI_maintenance_version = DYNINST_PATCH_VERSION; + + void Instruction::version(int& major, int& minor, int& maintenance) { - fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + major = IAPI_major_version; + minor = IAPI_minor_version; + maintenance = IAPI_maintenance_version; } -#endif - } - void Instruction::copyRaw(size_t size, const unsigned char* raw) - { - - if(raw) - { - m_size = size; - m_RawInsn.small_insn = 0; - if(size <= sizeof(m_RawInsn.small_insn)) - { - memcpy(&m_RawInsn.small_insn, raw, size); - } - else - { - m_RawInsn.large_insn = new unsigned char[size]; - memcpy(m_RawInsn.large_insn, raw, size); - } - } - else - { - m_size = 0; - m_RawInsn.small_insn = 0; - } - } + int Instruction::numInsnsAllocated = 0; + INSTRUCTION_EXPORT Instruction::Instruction(Operation what, + size_t size, const unsigned char* raw, + Dyninst::Architecture arch) + : m_InsnOp(what), m_Valid(true), arch_decoded_from(arch), + formatter(ArchSpecificFormatter::getFormatter(arch)) + { + copyRaw(size, raw); - void Instruction::decodeOperands() const - { - //m_Operands.reserve(5); - InstructionDecoder dec(ptr(), size(), arch_decoded_from); - dec.doDelayedDecode(this); - } - - INSTRUCTION_EXPORT Instruction::Instruction() : - m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(ArchSpecificFormatter::getFormatter(Arch_x86_64)) - { #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + } +#endif + } + + void Instruction::copyRaw(size_t size, const unsigned char* raw) + { + + if(raw) + { + m_size = size; + m_RawInsn.small_insn = 0; + if(size <= sizeof(m_RawInsn.small_insn)) + { + memcpy(&m_RawInsn.small_insn, raw, size); + } + else + { + m_RawInsn.large_insn = new unsigned char[size]; + memcpy(m_RawInsn.large_insn, raw, size); + } + } + else + { + m_size = 0; + m_RawInsn.small_insn = 0; + } + } + + void Instruction::decodeOperands() const { - fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + //m_Operands.reserve(5); + InstructionDecoder dec(ptr(), size(), arch_decoded_from); + dec.doDelayedDecode(this); } + + INSTRUCTION_EXPORT Instruction::Instruction() : + m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(ArchSpecificFormatter::getFormatter(Arch_x86_64)) + { +#if defined(DEBUG_INSN_ALLOCATIONS) + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } - - INSTRUCTION_EXPORT Instruction::~Instruction() - { + } + + INSTRUCTION_EXPORT Instruction::~Instruction() + { - if(m_size > sizeof(m_RawInsn.small_insn)) - { - delete[] m_RawInsn.large_insn; - } + if(m_size > sizeof(m_RawInsn.small_insn)) + { + delete[] m_RawInsn.large_insn; + } #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated--; - if((numInsnsAllocated % 1000) == 0) - { - fprintf(stderr, "Instruction DTOR, %d insns allocated\n", numInsnsAllocated); - } + numInsnsAllocated--; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction DTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } + } - INSTRUCTION_EXPORT Instruction::Instruction(const Instruction& o) : - m_Operands(o.m_Operands), - m_InsnOp(o.m_InsnOp), - m_Valid(o.m_Valid), - arch_decoded_from(o.arch_decoded_from), - formatter(o.formatter) + INSTRUCTION_EXPORT Instruction::Instruction(const Instruction& o) : + m_Operands(o.m_Operands), + m_InsnOp(o.m_InsnOp), + m_Valid(o.m_Valid), + arch_decoded_from(o.arch_decoded_from), + formatter(o.formatter) - { - m_size = o.m_size; - if(o.m_size > sizeof(m_RawInsn.small_insn)) - { - m_RawInsn.large_insn = new unsigned char[o.m_size]; - memcpy(m_RawInsn.large_insn, o.m_RawInsn.large_insn, m_size); - } - else - { - m_RawInsn.small_insn = o.m_RawInsn.small_insn; - } - - m_Successors = o.m_Successors; + { + m_size = o.m_size; + if(o.m_size > sizeof(m_RawInsn.small_insn)) + { + m_RawInsn.large_insn = new unsigned char[o.m_size]; + memcpy(m_RawInsn.large_insn, o.m_RawInsn.large_insn, m_size); + } + else + { + m_RawInsn.small_insn = o.m_RawInsn.small_insn; + } + + m_Successors = o.m_Successors; #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) - { - fprintf(stderr, "Instruction COPY CTOR, %d insns allocated\n", numInsnsAllocated); - } + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction COPY CTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } + } - INSTRUCTION_EXPORT const Instruction& Instruction::operator=(const Instruction& rhs) - { - m_Operands = rhs.m_Operands; - //m_Operands.reserve(rhs.m_Operands.size()); - //std::copy(rhs.m_Operands.begin(), rhs.m_Operands.end(), std::back_inserter(m_Operands)); - if(m_size > sizeof(m_RawInsn.small_insn)) - { - delete[] m_RawInsn.large_insn; - } - - m_size = rhs.m_size; - if(rhs.m_size > sizeof(m_RawInsn.small_insn)) - { - m_RawInsn.large_insn = new unsigned char[rhs.m_size]; - memcpy(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size); - } - else - { - m_RawInsn.small_insn = rhs.m_RawInsn.small_insn; - } - - - m_InsnOp = rhs.m_InsnOp; - m_Valid = rhs.m_Valid; - formatter = rhs.formatter; - arch_decoded_from = rhs.arch_decoded_from; - m_Successors = rhs.m_Successors; - return *this; - } - - INSTRUCTION_EXPORT bool Instruction::isValid() const - { - return m_Valid; - } - - INSTRUCTION_EXPORT Operation& Instruction::getOperation() - { - return m_InsnOp; - } - INSTRUCTION_EXPORT const Operation& Instruction::getOperation() const - { - return m_InsnOp; - } + INSTRUCTION_EXPORT const Instruction& Instruction::operator=(const Instruction& rhs) + { + m_Operands = rhs.m_Operands; + //m_Operands.reserve(rhs.m_Operands.size()); + //std::copy(rhs.m_Operands.begin(), rhs.m_Operands.end(), std::back_inserter(m_Operands)); + if(m_size > sizeof(m_RawInsn.small_insn)) + { + delete[] m_RawInsn.large_insn; + } + + m_size = rhs.m_size; + if(rhs.m_size > sizeof(m_RawInsn.small_insn)) + { + m_RawInsn.large_insn = new unsigned char[rhs.m_size]; + memcpy(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size); + } + else + { + m_RawInsn.small_insn = rhs.m_RawInsn.small_insn; + } + + + m_InsnOp = rhs.m_InsnOp; + m_Valid = rhs.m_Valid; + formatter = rhs.formatter; + arch_decoded_from = rhs.arch_decoded_from; + m_Successors = rhs.m_Successors; + return *this; + } + + INSTRUCTION_EXPORT bool Instruction::isValid() const + { + return m_Valid; + } - INSTRUCTION_EXPORT void Instruction::getOperands(std::vector& operands) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - std::copy(m_Operands.begin(), m_Operands.end(), std::back_inserter(operands)); - } - - INSTRUCTION_EXPORT Operand Instruction::getOperand(int index) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + INSTRUCTION_EXPORT Operation& Instruction::getOperation() + { + return m_InsnOp; + } + INSTRUCTION_EXPORT const Operation& Instruction::getOperation() const + { + return m_InsnOp; + } - if(index < 0 || index >= (int)(m_Operands.size())) + INSTRUCTION_EXPORT void Instruction::getOperands(std::vector& operands) const { - // Out of range = empty operand - return Operand(Expression::Ptr(), false, false); + + DECODE_OPERANDS(); + std::copy(m_Operands.begin(), m_Operands.end(), std::back_inserter(operands)); } - std::list::const_iterator found = m_Operands.begin(); - std::advance(found, index); - return *found; - } - - INSTRUCTION_EXPORT const void* Instruction::ptr() const - { - if(m_size > sizeof(m_RawInsn.small_insn)) - { - return m_RawInsn.large_insn; - } - else - { - return reinterpret_cast(&m_RawInsn.small_insn); - } - } - INSTRUCTION_EXPORT unsigned char Instruction::rawByte(unsigned int index) const - { - if(index >= m_size) return 0; - if(m_size > sizeof(m_RawInsn.small_insn)) - { - return m_RawInsn.large_insn[index]; - } - else - { - return reinterpret_cast(&m_RawInsn.small_insn)[index]; - } - } - - INSTRUCTION_EXPORT size_t Instruction::size() const - { - return m_size; - - } - - INSTRUCTION_EXPORT void Instruction::getReadSet(std::set& regsRead) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->getReadSet(regsRead); - } - std::copy(m_InsnOp.implicitReads().begin(), m_InsnOp.implicitReads().end(), - std::inserter(regsRead, regsRead.begin())); - - } - - INSTRUCTION_EXPORT void Instruction::getWriteSet(std::set& regsWritten) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->getWriteSet(regsWritten); - } - std::copy(m_InsnOp.implicitWrites().begin(), m_InsnOp.implicitWrites().end(), - std::inserter(regsWritten, regsWritten.begin())); - - } - - INSTRUCTION_EXPORT bool Instruction::isRead(Expression::Ptr candidate) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->isRead(candidate)) - { - return true; - } - } - return m_InsnOp.isRead(candidate); - } - INSTRUCTION_EXPORT bool Instruction::isWritten(Expression::Ptr candidate) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->isWritten(candidate)) - { - return true; - } - } - return m_InsnOp.isWritten(candidate); - } - - INSTRUCTION_EXPORT bool Instruction::readsMemory() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - if(getCategory() == c_PrefetchInsn) - { - return false; - } - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->readsMemory()) - { - return true; - } - } - return !m_InsnOp.getImplicitMemReads().empty(); - } - - INSTRUCTION_EXPORT bool Instruction::writesMemory() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->writesMemory()) - { - return true; - } - } - return !m_InsnOp.getImplicitMemWrites().empty(); - } - - INSTRUCTION_EXPORT void Instruction::getMemoryReadOperands(std::set& memAccessors) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->addEffectiveReadAddresses(memAccessors); - } - std::copy(m_InsnOp.getImplicitMemReads().begin(), m_InsnOp.getImplicitMemReads().end(), std::inserter(memAccessors, -memAccessors.begin())); - } - - INSTRUCTION_EXPORT void Instruction::getMemoryWriteOperands(std::set& memAccessors) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->addEffectiveWriteAddresses(memAccessors); - } - std::copy(m_InsnOp.getImplicitMemWrites().begin(), m_InsnOp.getImplicitMemWrites().end(), std::inserter(memAccessors, -memAccessors.begin())); - } + INSTRUCTION_EXPORT Operand Instruction::getOperand(int index) const + { + DECODE_OPERANDS(); + if(index < 0 || index >= (int)(m_Operands.size())) + { + // Out of range = empty operand + return Operand(Expression::Ptr(), false, false); + } + std::list::const_iterator found = m_Operands.begin(); + std::advance(found, index); + return *found; + } - INSTRUCTION_EXPORT Operand Instruction::getPredicateOperand() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + INSTRUCTION_EXPORT const void* Instruction::ptr() const + { + if(m_size > sizeof(m_RawInsn.small_insn)) + { + return m_RawInsn.large_insn; + } + else + { + return reinterpret_cast(&m_RawInsn.small_insn); + } + } + INSTRUCTION_EXPORT unsigned char Instruction::rawByte(unsigned int index) const + { + if(index >= m_size) return 0; + if(m_size > sizeof(m_RawInsn.small_insn)) + { + return m_RawInsn.large_insn[index]; + } + else + { + return reinterpret_cast(&m_RawInsn.small_insn)[index]; + } + } + + INSTRUCTION_EXPORT size_t Instruction::size() const + { + return m_size; - for(auto const &op : m_Operands) { - if (op.isTruePredicate() || op.isFalsePredicate()) { - return op; } - } - return Operand(Expression::Ptr(), false, false); - } - INSTRUCTION_EXPORT bool Instruction::hasPredicateOperand() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + INSTRUCTION_EXPORT void Instruction::getReadSet(std::set& regsRead) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->getReadSet(regsRead); + } + std::copy(m_InsnOp.implicitReads().begin(), m_InsnOp.implicitReads().end(), + std::inserter(regsRead, regsRead.begin())); - for(auto const &op : m_Operands) { - if (op.isTruePredicate() || op.isFalsePredicate()) { - return true; } - } - return false; - } + INSTRUCTION_EXPORT void Instruction::getWriteSet(std::set& regsWritten) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->getWriteSet(regsWritten); + } + std::copy(m_InsnOp.implicitWrites().begin(), m_InsnOp.implicitWrites().end(), + std::inserter(regsWritten, regsWritten.begin())); - INSTRUCTION_EXPORT Expression::Ptr Instruction::getControlFlowTarget() const - { - // We assume control flow transfer instructions have the PC as - // an implicit write, and that we have decoded the control flow - // target's full location as the first and only operand. - // If this is not the case, we'll squawk for the time being... - if(getCategory() == c_NoCategory || - getCategory() == c_CompareInsn || - getCategory() == c_PrefetchInsn) + } + + INSTRUCTION_EXPORT bool Instruction::isRead(Expression::Ptr candidate) const { - return Expression::Ptr(); + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + // Check if the candidate is read as an explicit operand + if(curOperand->isRead(candidate)) + { + return true; + } + } + // Check if the candidate is read as an implicit operand + return m_InsnOp.isRead(candidate); } - if(getCategory() == c_ReturnInsn) + + INSTRUCTION_EXPORT bool Instruction::isWritten(Expression::Ptr candidate) const { - return makeReturnExpression(); + DECODE_OPERANDS(); + + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->isWritten(candidate)) + { + return true; + } + } + return m_InsnOp.isWritten(candidate); } - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); + + INSTRUCTION_EXPORT bool Instruction::readsMemory() const + { + DECODE_OPERANDS(); + if(getCategory() == c_PrefetchInsn) + { + return false; + } + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->readsMemory()) + { + return true; + } + } + return !m_InsnOp.getImplicitMemReads().empty(); } - if(m_Successors.empty()) + INSTRUCTION_EXPORT bool Instruction::writesMemory() const { - return Expression::Ptr(); + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->writesMemory()) + { + return true; + } + } + return !m_InsnOp.getImplicitMemWrites().empty(); } - return m_Successors.front().target; - } - INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const { - return formatter; - } + INSTRUCTION_EXPORT void Instruction::getMemoryReadOperands(std::set& memAccessors) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->addEffectiveReadAddresses(memAccessors); + } + std::copy(m_InsnOp.getImplicitMemReads().begin(), m_InsnOp.getImplicitMemReads().end(), std::inserter(memAccessors, + memAccessors.begin())); + } - INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); + INSTRUCTION_EXPORT void Instruction::getMemoryWriteOperands(std::set& memAccessors) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->addEffectiveWriteAddresses(memAccessors); + } + std::copy(m_InsnOp.getImplicitMemWrites().begin(), m_InsnOp.getImplicitMemWrites().end(), std::inserter(memAccessors, + memAccessors.begin())); } - //remove this once ArchSpecificFormatter is extended for all architectures + INSTRUCTION_EXPORT Operand Instruction::getPredicateOperand() const + { + DECODE_OPERANDS(); + for(auto const &op : m_Operands) { + if (op.isTruePredicate() || op.isFalsePredicate()) { + return op; + } + } - std::string opstr = m_InsnOp.format(); - opstr += " "; - std::list::const_iterator currOperand; - std::vector formattedOperands; - int op = 0; - for(currOperand = m_Operands.begin(); - currOperand != m_Operands.end(); - op++, ++currOperand) + return Operand(Expression::Ptr(), false, false); + } + INSTRUCTION_EXPORT bool Instruction::hasPredicateOperand() const { - /* If this operand is implicit, don't put it in the list of operands. */ - if(currOperand->isImplicit()) - continue; + DECODE_OPERANDS(); + for(auto const &op : m_Operands) { + if (op.isTruePredicate() || op.isFalsePredicate()) { + return true; + } + } + + return false; + } - formattedOperands.push_back(currOperand->format(getArch(), addr)); + INSTRUCTION_EXPORT Expression::Ptr Instruction::getControlFlowTarget() const + { + // We assume control flow transfer instructions have the PC as + // an implicit write, and that we have decoded the control flow + // target's full location as the first and only operand. + // If this is not the case, we'll squawk for the time being... + if(getCategory() == c_NoCategory || + getCategory() == c_CompareInsn || + getCategory() == c_PrefetchInsn) + { + return Expression::Ptr(); + } + if(getCategory() == c_ReturnInsn) + { + return makeReturnExpression(); + } + DECODE_OPERANDS(); + if(m_Successors.empty()) + { + return Expression::Ptr(); + } + return m_Successors.front().target; } + INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const { + return formatter; + } + + INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const + { + DECODE_OPERANDS(); + //remove this once ArchSpecificFormatter is extended for all architectures + + std::string opstr = m_InsnOp.format(); + opstr += " "; + std::list::const_iterator currOperand; + std::vector formattedOperands; + int op = 0; + for(currOperand = m_Operands.begin(); + currOperand != m_Operands.end(); + op++, ++currOperand) + { + /* If this operand is implicit, don't put it in the list of operands. */ + if(currOperand->isImplicit()) + continue; + + formattedOperands.push_back(currOperand->format(getArch(), addr)); + } + #if defined(DEBUG_READ_WRITE) - std::set tmp; - getReadSet(tmp); - cout << "Read set:" << endl; - for(std::set::iterator i = tmp.begin(); - i != tmp.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - tmp.clear(); - getWriteSet(tmp); - cout << "Write set:" << endl; - for(std::set::iterator i = tmp.begin(); - i != tmp.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - std::set mem; - getMemoryReadOperands(mem); - cout << "Read mem:" << endl; - for(std::set::iterator i = mem.begin(); - i != mem.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - mem.clear(); - getMemoryWriteOperands(mem); - cout << "Write mem:" << endl; - for(std::set::iterator i = mem.begin(); - i != mem.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; + std::set tmp; + getReadSet(tmp); + cout << "Read set:" << endl; + for(std::set::iterator i = tmp.begin(); + i != tmp.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + tmp.clear(); + getWriteSet(tmp); + cout << "Write set:" << endl; + for(std::set::iterator i = tmp.begin(); + i != tmp.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + std::set mem; + getMemoryReadOperands(mem); + cout << "Read mem:" << endl; + for(std::set::iterator i = mem.begin(); + i != mem.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + mem.clear(); + getMemoryWriteOperands(mem); + cout << "Write mem:" << endl; + for(std::set::iterator i = mem.begin(); + i != mem.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; #endif // defined(DEBUG_READ_WRITE) - return opstr + formatter.getInstructionString(formattedOperands); - } + return opstr + formatter.getInstructionString(formattedOperands); + } - INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const - { - switch(m_InsnOp.getID()) - { - case e_ret_far: - case e_ret_near: - case e_iret: - case e_jmp: - case e_hlt: - case e_sysret: - case e_sysexit: - case e_call: - case e_syscall: - case amdgpu_op_s_swappc_b64: - return false; - case e_jnb: - case e_jb: - case e_jb_jnaej_j: - case e_jbe: - case e_jcxz_jec: - case e_jl: - case e_jle: - case e_jnb_jae_j: - case e_jnbe: - case e_jnl: - case e_jnle: - case e_jno: - case e_jnp: - case e_jns: - case e_jnz: - case e_jo: - case e_jp: - case e_js: - case e_jz: - return true; - default: - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - for(cftConstIter targ = m_Successors.begin(); - targ != m_Successors.end(); - ++targ) - { - if(targ->isFallthrough) return true; - } - return m_Successors.empty(); - } - } - // can't happen but make the compiler happy - return false; - } - INSTRUCTION_EXPORT bool Instruction::isLegalInsn() const - { - return (m_InsnOp.getID() != e_No_Entry); - } + INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const + { + switch(m_InsnOp.getID()) + { + case e_ret_far: + case e_ret_near: + case e_iret: + case e_jmp: + case e_hlt: + case e_sysret: + case e_sysexit: + case e_call: + case e_syscall: + case amdgpu_op_s_swappc_b64: + return false; + case e_jnb: + case e_jb: + case e_jb_jnaej_j: + case e_jbe: + case e_jcxz_jec: + case e_jl: + case e_jle: + case e_jnb_jae_j: + case e_jnbe: + case e_jnl: + case e_jnle: + case e_jno: + case e_jnp: + case e_jns: + case e_jnz: + case e_jo: + case e_jp: + case e_js: + case e_jz: + return true; + default: + { + DECODE_OPERANDS(); + for(cftConstIter targ = m_Successors.begin(); + targ != m_Successors.end(); + ++targ) + { + if(targ->isFallthrough) return true; + } + return m_Successors.empty(); + } + } + // can't happen but make the compiler happy + return false; + } + INSTRUCTION_EXPORT bool Instruction::isLegalInsn() const + { + return (m_InsnOp.getID() != e_No_Entry); + } - INSTRUCTION_EXPORT Architecture Instruction::getArch() const { - return arch_decoded_from; - } + INSTRUCTION_EXPORT Architecture Instruction::getArch() const { + return arch_decoded_from; + } - Expression::Ptr Instruction::makeReturnExpression() const - { - Expression::Ptr stackPtr = Expression::Ptr(new RegisterAST(MachRegister::getStackPointer(arch_decoded_from), - 0, MachRegister::getStackPointer(arch_decoded_from).size())); - Expression::Ptr retLoc = Expression::Ptr(new Dereference(stackPtr, u32)); - return retLoc; - } - INSTRUCTION_EXPORT InsnCategory Instruction::getCategory() const - { - if(m_InsnOp.isVectorInsn) return c_VectorInsn; - InsnCategory c = entryToCategory(m_InsnOp.getID()); - if(c == c_BranchInsn && (arch_decoded_from == Arch_ppc32 || arch_decoded_from == Arch_ppc64)) - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - for(cftConstIter cft = cft_begin(); - cft != cft_end(); - ++cft) - { - if(cft->isCall) - { - return c_CallInsn; - } - } - if(m_InsnOp.getID() == power_op_bclr) - { - return c_ReturnInsn; - } - } - return c; - } - void Instruction::addSuccessor(Expression::Ptr e, - bool isCall, - bool isIndirect, - bool isConditional, - bool isFallthrough) const - { - CFT c(e, isCall, isIndirect, isConditional, isFallthrough); - m_Successors.push_back(c); - if (!isFallthrough) appendOperand(e, true, false); - } - void Instruction::appendOperand(Expression::Ptr e, bool isRead, bool isWritten) const - { - m_Operands.push_back(Operand(e, isRead, isWritten)); - } + Expression::Ptr Instruction::makeReturnExpression() const + { + Expression::Ptr stackPtr = Expression::Ptr(new RegisterAST(MachRegister::getStackPointer(arch_decoded_from), + 0, MachRegister::getStackPointer(arch_decoded_from).size())); + Expression::Ptr retLoc = Expression::Ptr(new Dereference(stackPtr, u32)); + return retLoc; + } + INSTRUCTION_EXPORT InsnCategory Instruction::getCategory() const + { + if(m_InsnOp.isVectorInsn) return c_VectorInsn; + InsnCategory c = entryToCategory(m_InsnOp.getID()); + if(c == c_BranchInsn && (arch_decoded_from == Arch_ppc32 || arch_decoded_from == Arch_ppc64)) + { + DECODE_OPERANDS(); + for(cftConstIter cft = cft_begin(); + cft != cft_end(); + ++cft) + { + if(cft->isCall) + { + return c_CallInsn; + } + } + if(m_InsnOp.getID() == power_op_bclr) + { + return c_ReturnInsn; + } + } + return c; + } + void Instruction::addSuccessor(Expression::Ptr e, + bool isCall, + bool isIndirect, + bool isConditional, + bool isFallthrough) const + { + CFT c(e, isCall, isIndirect, isConditional, isFallthrough); + m_Successors.push_back(c); + if (!isFallthrough) appendOperand(e, true, false); + } + void Instruction::appendOperand(Expression::Ptr e, bool isRead, bool isWritten) const + { + m_Operands.push_back(Operand(e, isRead, isWritten)); + } - void Instruction::appendOperand(Expression::Ptr e, - bool isRead, bool isWritten, bool isImplicit) const - { - m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit)); - } - - void Instruction::appendOperand(Expression::Ptr e, - bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const - { - m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit, trueP, falseP)); - } + void Instruction::appendOperand(Expression::Ptr e, + bool isRead, bool isWritten, bool isImplicit) const + { + m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit)); + } + void Instruction::appendOperand(Expression::Ptr e, + bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const + { + m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit, trueP, falseP)); + } - } + + } } diff --git a/instructionAPI/src/InstructionCategories.C b/instructionAPI/src/InstructionCategories.C index d0de937d91..703e018c16 100644 --- a/instructionAPI/src/InstructionCategories.C +++ b/instructionAPI/src/InstructionCategories.C @@ -44,6 +44,7 @@ namespace Dyninst case aarch64_op_ret: return c_ReturnInsn; case amdgpu_op_s_endpgm: // special treatment for endpgm + case amdgpu_cdna2_op_S_ENDPGM: // special treatment for endpgm return c_GPUKernelExitInsn; case e_call: case aarch64_op_bl: diff --git a/instructionAPI/src/InstructionDecoderImpl.C b/instructionAPI/src/InstructionDecoderImpl.C index 1784a2f446..424f96f706 100644 --- a/instructionAPI/src/InstructionDecoderImpl.C +++ b/instructionAPI/src/InstructionDecoderImpl.C @@ -33,7 +33,8 @@ #include "InstructionDecoder-x86.h" #include "InstructionDecoder-power.h" #include "InstructionDecoder-aarch64.h" -#include "InstructionDecoder-amdgpu-vega.h" +#include "AMDGPU/vega/InstructionDecoder-amdgpu-vega.h" +#include "AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h" #include "BinaryFunction.h" #include "Dereference.h" @@ -77,6 +78,8 @@ namespace Dyninst return Ptr(new InstructionDecoder_aarch64(a)); case Arch_amdgpu_vega: return Ptr(new InstructionDecoder_amdgpu_vega(a)); + case Arch_amdgpu_cdna2: + return Ptr(new InstructionDecoder_amdgpu_cdna2(a)); default: assert(0); return Ptr(); diff --git a/instructionAPI/src/Operand.C b/instructionAPI/src/Operand.C index 3bd216ed5d..ddab6629a7 100644 --- a/instructionAPI/src/Operand.C +++ b/instructionAPI/src/Operand.C @@ -41,109 +41,110 @@ using namespace std; namespace Dyninst { - namespace InstructionAPI - { - INSTRUCTION_EXPORT void Operand::getReadSet(std::set& regsRead) const + namespace InstructionAPI { - std::set useSet; - op_value->getUses(useSet); - std::set::const_iterator curUse; - for(curUse = useSet.begin(); curUse != useSet.end(); ++curUse) - { - RegisterAST::Ptr tmp = boost::dynamic_pointer_cast(*curUse); - if(tmp) - { - if(m_isRead || !(*tmp == *op_value)) - regsRead.insert(tmp); - } - } - } - INSTRUCTION_EXPORT void Operand::getWriteSet(std::set& regsWritten) const - { - RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); - if(m_isWritten && op_as_reg) - { - regsWritten.insert(op_as_reg); - } - } + INSTRUCTION_EXPORT void Operand::getReadSet(std::set& regsRead) const + { + std::set useSet; + // This thing returns something only for RegisterAST Expression + op_value->getUses(useSet); + std::set::const_iterator curUse; + for(curUse = useSet.begin(); curUse != useSet.end(); ++curUse) + { + RegisterAST::Ptr tmp = boost::dynamic_pointer_cast(*curUse); + if(tmp) + { + if(m_isRead || !(*tmp == *op_value)) + regsRead.insert(tmp); + } + } + } + INSTRUCTION_EXPORT void Operand::getWriteSet(std::set& regsWritten) const + { + RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); + if(m_isWritten && op_as_reg) + { + regsWritten.insert(op_as_reg); + } + } - INSTRUCTION_EXPORT RegisterAST::Ptr Operand::getPredicate() const - { - RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); - if (m_isTruePredicate || m_isFalsePredicate) { - return op_as_reg; - } - return nullptr; - } + INSTRUCTION_EXPORT RegisterAST::Ptr Operand::getPredicate() const + { + RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); + if (m_isTruePredicate || m_isFalsePredicate) { + return op_as_reg; + } + return nullptr; + } - INSTRUCTION_EXPORT bool Operand::isRead(Expression::Ptr candidate) const - { - // The whole expression of a read, any subexpression of a write - return op_value->isUsed(candidate) && (m_isRead || !(*candidate == *op_value)); - } - INSTRUCTION_EXPORT bool Operand::isWritten(Expression::Ptr candidate) const - { - // Whole expression of a write - return m_isWritten && (*op_value == *candidate); - } - INSTRUCTION_EXPORT bool Operand::readsMemory() const - { - return (boost::dynamic_pointer_cast(op_value) && m_isRead); - } - INSTRUCTION_EXPORT bool Operand::writesMemory() const - { - return (boost::dynamic_pointer_cast(op_value) && m_isWritten); - } - INSTRUCTION_EXPORT void Operand::addEffectiveReadAddresses(std::set& memAccessors) const - { - if(m_isRead && boost::dynamic_pointer_cast(op_value)) - { - std::vector tmp; - op_value->getChildren(tmp); - for(std::vector::const_iterator curKid = tmp.begin(); - curKid != tmp.end(); - ++curKid) - { - memAccessors.insert(*curKid); - } - } - } - INSTRUCTION_EXPORT void Operand::addEffectiveWriteAddresses(std::set& memAccessors) const - { - if(m_isWritten && boost::dynamic_pointer_cast(op_value)) - { - std::vector tmp; - op_value->getChildren(tmp); - for(std::vector::const_iterator curKid = tmp.begin(); - curKid != tmp.end(); - ++curKid) - { - memAccessors.insert(*curKid); - } - } - } + INSTRUCTION_EXPORT bool Operand::isRead(Expression::Ptr candidate) const + { + // The whole expression of a read, any subexpression of a write + return op_value->isUsed(candidate) && (m_isRead || !(*candidate == *op_value)); + } + INSTRUCTION_EXPORT bool Operand::isWritten(Expression::Ptr candidate) const + { + // Whole expression of a write + return m_isWritten && (*op_value == *candidate); + } + INSTRUCTION_EXPORT bool Operand::readsMemory() const + { + return (boost::dynamic_pointer_cast(op_value) && m_isRead); + } + INSTRUCTION_EXPORT bool Operand::writesMemory() const + { + return (boost::dynamic_pointer_cast(op_value) && m_isWritten); + } + INSTRUCTION_EXPORT void Operand::addEffectiveReadAddresses(std::set& memAccessors) const + { + if(m_isRead && boost::dynamic_pointer_cast(op_value)) + { + std::vector tmp; + op_value->getChildren(tmp); + for(std::vector::const_iterator curKid = tmp.begin(); + curKid != tmp.end(); + ++curKid) + { + memAccessors.insert(*curKid); + } + } + } + INSTRUCTION_EXPORT void Operand::addEffectiveWriteAddresses(std::set& memAccessors) const + { + if(m_isWritten && boost::dynamic_pointer_cast(op_value)) + { + std::vector tmp; + op_value->getChildren(tmp); + for(std::vector::const_iterator curKid = tmp.begin(); + curKid != tmp.end(); + ++curKid) + { + memAccessors.insert(*curKid); + } + } + } - INSTRUCTION_EXPORT std::string Operand::format(Architecture arch, Address addr) const - { - if(!op_value) return "ERROR: format() called on empty operand!"; - if (addr) { - Expression::Ptr thePC = Expression::Ptr(new RegisterAST(MachRegister::getPC(arch))); - op_value->bind(thePC.get(), Result(u32, addr)); - Result res = op_value->eval(); - if (res.defined) { - char hex[20]; - snprintf(hex, 20, "%lux", res.convert()); - return string(hex); - } - } - return op_value->format(arch); - } + INSTRUCTION_EXPORT std::string Operand::format(Architecture arch, Address addr) const + { + if(!op_value) return "ERROR: format() called on empty operand!"; + if (addr) { + Expression::Ptr thePC = Expression::Ptr(new RegisterAST(MachRegister::getPC(arch))); + op_value->bind(thePC.get(), Result(u32, addr)); + Result res = op_value->eval(); + if (res.defined) { + char hex[20]; + snprintf(hex, 20, "%lux", res.convert()); + return string(hex); + } + } + return op_value->format(arch); + } - INSTRUCTION_EXPORT Expression::Ptr Operand::getValue() const - { - return op_value; + INSTRUCTION_EXPORT Expression::Ptr Operand::getValue() const + { + return op_value; + } } - } } diff --git a/instructionAPI/src/Operation.C b/instructionAPI/src/Operation.C index 084312d878..fec8f1713d 100644 --- a/instructionAPI/src/Operation.C +++ b/instructionAPI/src/Operation.C @@ -49,503 +49,503 @@ using namespace NS_x86; namespace Dyninst { - namespace InstructionAPI - { - RegisterAST::Ptr makeRegFromID(MachRegister regID, unsigned int low, unsigned int high) + namespace InstructionAPI { - return make_shared(singleton_object_pool::construct(regID, low, high)); - } - RegisterAST::Ptr makeRegFromID(MachRegister regID) - { - return make_shared(singleton_object_pool::construct(regID, 0, regID.size() * 8)); - } + RegisterAST::Ptr makeRegFromID(MachRegister regID, unsigned int low, unsigned int high) + { + return make_shared(singleton_object_pool::construct(regID, low, high)); + } + RegisterAST::Ptr makeRegFromID(MachRegister regID) + { + return make_shared(singleton_object_pool::construct(regID, 0, regID.size() * 8)); + } - Operation_impl::Operation_impl(entryID id, std::string m, Architecture arch) - : operationID(id), archDecodedFrom(arch), prefixID(prefix_none) - { - switch(archDecodedFrom) + Operation_impl::Operation_impl(entryID id, std::string m, Architecture arch) + : operationID(id), archDecodedFrom(arch), prefixID(prefix_none) { - case Arch_x86: - case Arch_ppc32: - addrWidth = u32; - break; - default: - addrWidth = u64; - break; + switch(archDecodedFrom) + { + case Arch_x86: + case Arch_ppc32: + addrWidth = u32; + break; + default: + addrWidth = u64; + break; + } + segPrefix = 0; + isVectorInsn = false; + mnemonic = m; } - segPrefix = 0; - isVectorInsn = false; - mnemonic = m; - } - static bool getVectorizationInfo(ia32_entry* e) - { - for(int i = 0; i < 3; i++) + static bool getVectorizationInfo(ia32_entry* e) { - switch(e->operands[i].admet) + for(int i = 0; i < 3; i++) { - case am_V: - case am_W: - case am_P: - case am_Q: - case am_HK: - case am_H: - case am_X: - case am_XH: - case am_XU: - case am_XV: - case am_XW: - case am_Y: - case am_YH: - case am_YU: - case am_YV: - case am_YW: - case am_VK: - case am_WK: + switch(e->operands[i].admet) + { + case am_V: + case am_W: + case am_P: + case am_Q: + case am_HK: + case am_H: + case am_X: + case am_XH: + case am_XU: + case am_XV: + case am_XW: + case am_Y: + case am_YH: + case am_YU: + case am_YV: + case am_YW: + case am_VK: + case am_WK: - return true; + return true; + default: + break; + } + } + return false; + } + + Operation_impl::Operation_impl(ia32_entry* e, ia32_prefixes* p, ia32_locations* l, Architecture arch) : + archDecodedFrom(arch), prefixID(prefix_none) + { + segPrefix = 0; + isVectorInsn = getVectorizationInfo(e); + operationID = e->getID(l); + // Defaults for no size prefix + switch(archDecodedFrom) + { + case Arch_x86: + case Arch_ppc32: + addrWidth = u32; + break; default: + addrWidth = u64; break; } + if(p && p->getCount()) + { + if (p->getPrefix(0) == PREFIX_REP) prefixID = prefix_rep; + if (p->getPrefix(0) == PREFIX_REPNZ) prefixID = prefix_repnz; + segPrefix = p->getPrefix(1); + if(p->getAddrSzPrefix()) + { + addrWidth = u16; + } + } } - return false; - } - - Operation_impl::Operation_impl(ia32_entry* e, ia32_prefixes* p, ia32_locations* l, Architecture arch) : - archDecodedFrom(arch), prefixID(prefix_none) - { - segPrefix = 0; - isVectorInsn = getVectorizationInfo(e); - operationID = e->getID(l); - // Defaults for no size prefix - switch(archDecodedFrom) - { - case Arch_x86: - case Arch_ppc32: - addrWidth = u32; - break; - default: - addrWidth = u64; - break; - } - if(p && p->getCount()) - { - if (p->getPrefix(0) == PREFIX_REP) prefixID = prefix_rep; - if (p->getPrefix(0) == PREFIX_REPNZ) prefixID = prefix_repnz; - segPrefix = p->getPrefix(1); - if(p->getAddrSzPrefix()) + + Operation_impl::Operation_impl(const Operation_impl& o) { - addrWidth = u16; + operationID = o.operationID; + archDecodedFrom = o.archDecodedFrom; + prefixID = o.prefixID; + addrWidth = o.addrWidth; + segPrefix = o.segPrefix; + isVectorInsn = o.isVectorInsn; + mnemonic = o.mnemonic; + } + const Operation_impl& Operation_impl::operator=(const Operation_impl& o) + { + operationID = o.operationID; + archDecodedFrom = o.archDecodedFrom; + prefixID = o.prefixID; + addrWidth = o.addrWidth; + segPrefix = o.segPrefix; + isVectorInsn = o.isVectorInsn; + mnemonic = o.mnemonic; + return *this; + } + Operation_impl::Operation_impl() + { + operationID = e_No_Entry; + archDecodedFrom = Arch_none; + prefixID = prefix_none; + addrWidth = u64; + segPrefix = 0; + isVectorInsn = false; } - } - } - - Operation_impl::Operation_impl(const Operation_impl& o) - { - operationID = o.operationID; - archDecodedFrom = o.archDecodedFrom; - prefixID = o.prefixID; - addrWidth = o.addrWidth; - segPrefix = o.segPrefix; - isVectorInsn = o.isVectorInsn; - mnemonic = o.mnemonic; - } - const Operation_impl& Operation_impl::operator=(const Operation_impl& o) - { - operationID = o.operationID; - archDecodedFrom = o.archDecodedFrom; - prefixID = o.prefixID; - addrWidth = o.addrWidth; - segPrefix = o.segPrefix; - isVectorInsn = o.isVectorInsn; - mnemonic = o.mnemonic; - return *this; - } - Operation_impl::Operation_impl() - { - operationID = e_No_Entry; - archDecodedFrom = Arch_none; - prefixID = prefix_none; - addrWidth = u64; - segPrefix = 0; - isVectorInsn = false; - } - - const Operation_impl::registerSet& Operation_impl::implicitReads() - { - SetUpNonOperandData(); - - return otherRead; - } - const Operation_impl::registerSet& Operation_impl::implicitWrites() - { - SetUpNonOperandData(); - return otherWritten; - } - bool Operation_impl::isRead(Expression::Ptr candidate) - { - - SetUpNonOperandData(); - - for(registerSet::const_iterator r = otherRead.begin(); - r != otherRead.end(); - ++r) - { - if(*candidate == *(*r)) - { - return true; - } - } - for(VCSet::const_iterator e = otherEffAddrsRead.begin(); - e != otherEffAddrsRead.end(); - ++e) - { - if(*candidate == *(*e)) - { - return true; - } - } - return false; - } - const Operation_impl::VCSet& Operation_impl::getImplicitMemReads() - { - SetUpNonOperandData(); - return otherEffAddrsRead; - } - const Operation_impl::VCSet& Operation_impl::getImplicitMemWrites() - { - SetUpNonOperandData(); - return otherEffAddrsWritten; - } + const Operation_impl::registerSet& Operation_impl::implicitReads() + { + SetUpNonOperandData(); - bool Operation_impl::isWritten(Expression::Ptr candidate) - { - - SetUpNonOperandData(); - - for(registerSet::const_iterator r = otherWritten.begin(); - r != otherWritten.end(); - ++r) - { - if(*candidate == *(*r)) - { - return true; - } - } - for(VCSet::const_iterator e = otherEffAddrsWritten.begin(); - e != otherEffAddrsWritten.end(); - ++e) - { - if(*candidate == *(*e)) - { - return true; - } - } - return false; - } - - std::string Operation_impl::format() const - { - if(mnemonic != "") + return otherRead; + } + const Operation_impl::registerSet& Operation_impl::implicitWrites() { - return mnemonic; + SetUpNonOperandData(); + + return otherWritten; } - dyn_hash_map::const_iterator foundPrefix = prefixEntryNames_IAPI.find(prefixID); - dyn_hash_map::const_iterator found = entryNames_IAPI.find(operationID); - std::string result; - if(foundPrefix != prefixEntryNames_IAPI.end()) - { - result += (foundPrefix->second + " "); - } - if(found != entryNames_IAPI.end()) - { - result += found->second; - } - else - { - result += "[INVALID]"; - } - return result; - } + bool Operation_impl::isRead(Expression::Ptr candidate) + { - entryID Operation_impl::getID() const - { - return operationID; - } + SetUpNonOperandData(); - prefixEntryID Operation_impl::getPrefixID() const - { - return prefixID; - } + for(registerSet::const_iterator r = otherRead.begin(); + r != otherRead.end(); + ++r) + { + if(*candidate == *(*r)) + { + return true; + } + } + for(VCSet::const_iterator e = otherEffAddrsRead.begin(); + e != otherEffAddrsRead.end(); + ++e) + { + if(*candidate == *(*e)) + { + return true; + } + } + return false; + } + const Operation_impl::VCSet& Operation_impl::getImplicitMemReads() + { + SetUpNonOperandData(); + return otherEffAddrsRead; + } + const Operation_impl::VCSet& Operation_impl::getImplicitMemWrites() + { + SetUpNonOperandData(); + return otherEffAddrsWritten; + } - struct OperationMaps - { - typedef dyn_c_hash_map reg_info_t; - typedef dyn_c_hash_map mem_info_t; - public: - OperationMaps(Architecture arch) - { - thePC.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); - pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); - pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - stackPointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - stackPointerAsExpr.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - framePointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); - spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); - si.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); - di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); - si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); - si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); - - nonOperandRegisterReads.insert(make_pair(e_call, pcAndSP)); - nonOperandRegisterReads.insert(make_pair(e_ret_near, stackPointer)); - nonOperandRegisterReads.insert(make_pair(e_ret_far, stackPointer)); - nonOperandRegisterReads.insert(make_pair(e_leave, framePointer)); - nonOperandRegisterReads.insert(make_pair(e_enter, spAndBP)); - - nonOperandRegisterWrites.insert(make_pair(e_call, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_ret_near, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_ret_far, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_leave, spAndBP)); - nonOperandRegisterWrites.insert(make_pair(e_enter, spAndBP)); - - nonOperandRegisterWrites.insert(make_pair(e_loop, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_loope, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_loopn, thePC)); - - nonOperandRegisterWrites.insert(make_pair(e_jb, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jb_jnaej_j, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jbe, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jcxz_jec, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jl, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jle, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jmp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnb, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnb_jae_j, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnbe, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnl, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnle, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jno, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jns, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnz, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jo, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_js, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jz, thePC)); - - nonOperandMemoryReads.insert(make_pair(e_pop, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_popa, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_popad, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_push, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_pusha, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_pushad, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_call, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_ret_near, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_ret_far, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_leave, stackPointerAsExpr)); - - nonOperandRegisterWrites.insert(make_pair(e_cmpsb, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_cmpsd, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_cmpsw, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsb, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsd, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsw, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_insb, di)); - nonOperandRegisterWrites.insert(make_pair(e_insd, di)); - nonOperandRegisterWrites.insert(make_pair(e_insw, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosb, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosd, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosw, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasb, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasd, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasw, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsb, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsd, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsw, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsb, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsd, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsw, di)); - - - } - Operation_impl::registerSet thePC; - Operation_impl::registerSet pcAndSP; - Operation_impl::registerSet stackPointer; - Operation_impl::VCSet stackPointerAsExpr; - Operation_impl::registerSet framePointer; - Operation_impl::registerSet spAndBP; - Operation_impl::registerSet si; - Operation_impl::registerSet di; - Operation_impl::registerSet si_and_di; - - reg_info_t nonOperandRegisterReads; - reg_info_t nonOperandRegisterWrites; - - mem_info_t nonOperandMemoryReads; - mem_info_t nonOperandMemoryWrites; - }; - OperationMaps op_data_32(Arch_x86); - OperationMaps op_data_64(Arch_x86_64); - const OperationMaps& op_data(Architecture arch) - { - switch(arch) + bool Operation_impl::isWritten(Expression::Ptr candidate) { - case Arch_x86: - return op_data_32; - case Arch_x86_64: - return op_data_64; - default: - return op_data_32; + + SetUpNonOperandData(); + + for(registerSet::const_iterator r = otherWritten.begin(); + r != otherWritten.end(); + ++r) + { + if(*candidate == *(*r)) + { + return true; + } + } + for(VCSet::const_iterator e = otherEffAddrsWritten.begin(); + e != otherEffAddrsWritten.end(); + ++e) + { + if(*candidate == *(*e)) + { + return true; + } + } + return false; } - } - void Operation_impl::SetUpNonOperandData() - { - if (archDecodedFrom != Arch_x86 && archDecodedFrom != Arch_x86_64) return; - std::call_once(data_initialized, [&]() { - if (prefixID == prefix_rep || prefixID == prefix_repnz) { - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); - if(prefixID == prefix_repnz) + + std::string Operation_impl::format() const + { + if(mnemonic != "") + { + return mnemonic; + } + dyn_hash_map::const_iterator foundPrefix = prefixEntryNames_IAPI.find(prefixID); + dyn_hash_map::const_iterator found = entryNames_IAPI.find(operationID); + std::string result; + if(foundPrefix != prefixEntryNames_IAPI.end()) + { + result += (foundPrefix->second + " "); + } + if(found != entryNames_IAPI.end()) + { + result += found->second; + } + else { - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + result += "[INVALID]"; } + return result; } - switch(segPrefix) + + entryID Operation_impl::getID() const { - case PREFIX_SEGCS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cs : x86_64::cs)); - break; - case PREFIX_SEGDS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ds : x86_64::ds)); - break; - case PREFIX_SEGES: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::es : x86_64::es)); - break; - case PREFIX_SEGFS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::fs : x86_64::fs)); - break; - case PREFIX_SEGGS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::gs : x86_64::gs)); - break; - case PREFIX_SEGSS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ss : x86_64::ss)); - break; + return operationID; } - OperationMaps::reg_info_t::const_accessor a, b; - if (op_data(archDecodedFrom).nonOperandRegisterReads.find(a, operationID)) { - otherRead.insert(a->second.begin(), a->second.end()); - } - if (op_data(archDecodedFrom).nonOperandRegisterWrites.find(b, operationID)) { - otherWritten.insert(b->second.begin(), b->second.end()); - } - OperationMaps::mem_info_t::const_accessor c, d; - if (op_data(archDecodedFrom).nonOperandMemoryReads.find(c, operationID)) { - otherEffAddrsRead.insert(c->second.begin(), c->second.end()); + prefixEntryID Operation_impl::getPrefixID() const + { + return prefixID; + } + + struct OperationMaps + { + typedef dyn_c_hash_map reg_info_t; + typedef dyn_c_hash_map mem_info_t; + public: + OperationMaps(Architecture arch) + { + thePC.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); + pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); + pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + stackPointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + stackPointerAsExpr.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + framePointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); + spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); + si.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); + di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); + si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); + si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); + + nonOperandRegisterReads.insert(make_pair(e_call, pcAndSP)); + nonOperandRegisterReads.insert(make_pair(e_ret_near, stackPointer)); + nonOperandRegisterReads.insert(make_pair(e_ret_far, stackPointer)); + nonOperandRegisterReads.insert(make_pair(e_leave, framePointer)); + nonOperandRegisterReads.insert(make_pair(e_enter, spAndBP)); + + nonOperandRegisterWrites.insert(make_pair(e_call, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_ret_near, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_ret_far, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_leave, spAndBP)); + nonOperandRegisterWrites.insert(make_pair(e_enter, spAndBP)); + + nonOperandRegisterWrites.insert(make_pair(e_loop, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_loope, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_loopn, thePC)); + + nonOperandRegisterWrites.insert(make_pair(e_jb, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jb_jnaej_j, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jbe, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jcxz_jec, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jl, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jle, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jmp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnb, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnb_jae_j, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnbe, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnl, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnle, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jno, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jns, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnz, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jo, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_js, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jz, thePC)); + + nonOperandMemoryReads.insert(make_pair(e_pop, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_popa, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_popad, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_push, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_pusha, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_pushad, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_call, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_ret_near, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_ret_far, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_leave, stackPointerAsExpr)); + + nonOperandRegisterWrites.insert(make_pair(e_cmpsb, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_cmpsd, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_cmpsw, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsb, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsd, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsw, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_insb, di)); + nonOperandRegisterWrites.insert(make_pair(e_insd, di)); + nonOperandRegisterWrites.insert(make_pair(e_insw, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosb, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosd, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosw, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasb, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasd, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasw, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsb, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsd, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsw, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsb, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsd, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsw, di)); + + } - if (operationID == e_push) { - BinaryFunction::funcT::Ptr adder(new BinaryFunction::addResult()); - // special case for push: we write at the new value of the SP. - Result dummy(addrWidth, 0); - Expression::Ptr push_addr(new BinaryFunction( - *(op_data(archDecodedFrom).stackPointerAsExpr.begin()), - Immediate::makeImmediate(Result(s8, -(dummy.size()))), - addrWidth, - adder)); - - otherEffAddrsWritten.insert(push_addr); - - } else { - if (op_data(archDecodedFrom).nonOperandMemoryWrites.find(d, operationID)) { - otherEffAddrsWritten.insert(d->second.begin(), d->second.end()); - } + Operation_impl::registerSet thePC; + Operation_impl::registerSet pcAndSP; + Operation_impl::registerSet stackPointer; + Operation_impl::VCSet stackPointerAsExpr; + Operation_impl::registerSet framePointer; + Operation_impl::registerSet spAndBP; + Operation_impl::registerSet si; + Operation_impl::registerSet di; + Operation_impl::registerSet si_and_di; + + reg_info_t nonOperandRegisterReads; + reg_info_t nonOperandRegisterWrites; + + mem_info_t nonOperandMemoryReads; + mem_info_t nonOperandMemoryWrites; + }; + OperationMaps op_data_32(Arch_x86); + OperationMaps op_data_64(Arch_x86_64); + const OperationMaps& op_data(Architecture arch) + { + switch(arch) + { + case Arch_x86: + return op_data_32; + case Arch_x86_64: + return op_data_64; + default: + return op_data_32; } + } + void Operation_impl::SetUpNonOperandData() + { + if (archDecodedFrom != Arch_x86 && archDecodedFrom != Arch_x86_64) return; + std::call_once(data_initialized, [&]() { + if (prefixID == prefix_rep || prefixID == prefix_repnz) { + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); + if(prefixID == prefix_repnz) + { + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + } + } + switch(segPrefix) + { + case PREFIX_SEGCS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cs : x86_64::cs)); + break; + case PREFIX_SEGDS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ds : x86_64::ds)); + break; + case PREFIX_SEGES: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::es : x86_64::es)); + break; + case PREFIX_SEGFS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::fs : x86_64::fs)); + break; + case PREFIX_SEGGS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::gs : x86_64::gs)); + break; + case PREFIX_SEGSS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ss : x86_64::ss)); + break; + } - dyn_hash_map::const_iterator found = ia32_instruction::getFlagTable().find(operationID); - if (found != ia32_instruction::getFlagTable().end()) { - for (unsigned i = 0; i < found->second.readFlags.size(); i++) { - switch (found->second.readFlags[i]) { - case x86::icf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); - break; - case x86::ipf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); - break; - case x86::iaf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); - break; - case x86::izf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); - break; - case x86::isf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); - break; - case x86::itf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); - break; - case x86::idf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - break; - case x86::iof: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); - break; - case x86::int_: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); - break; - case x86::iif_: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); - break; - default: - assert(0); + OperationMaps::reg_info_t::const_accessor a, b; + if (op_data(archDecodedFrom).nonOperandRegisterReads.find(a, operationID)) { + otherRead.insert(a->second.begin(), a->second.end()); } - } + if (op_data(archDecodedFrom).nonOperandRegisterWrites.find(b, operationID)) { + otherWritten.insert(b->second.begin(), b->second.end()); + } + OperationMaps::mem_info_t::const_accessor c, d; + if (op_data(archDecodedFrom).nonOperandMemoryReads.find(c, operationID)) { + otherEffAddrsRead.insert(c->second.begin(), c->second.end()); + } + if (operationID == e_push) { + BinaryFunction::funcT::Ptr adder(new BinaryFunction::addResult()); + // special case for push: we write at the new value of the SP. + Result dummy(addrWidth, 0); + Expression::Ptr push_addr(new BinaryFunction( + *(op_data(archDecodedFrom).stackPointerAsExpr.begin()), + Immediate::makeImmediate(Result(s8, -(dummy.size()))), + addrWidth, + adder)); + + otherEffAddrsWritten.insert(push_addr); - for (unsigned j = 0; j < found->second.writtenFlags.size(); j++) { - switch (found->second.writtenFlags[j]) { - case x86::icf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); - break; - case x86::ipf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); - break; - case x86::iaf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); - break; - case x86::izf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); - break; - case x86::isf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); - break; - case x86::itf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); - break; - case x86::idf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - break; - case x86::iof: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); - break; - case x86::int_: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); - break; - case x86::iif_: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); - break; - default: - fprintf(stderr, "ERROR: unhandled entry %s\n", - found->second.writtenFlags[j].name().c_str()); - assert(0); + } else { + if (op_data(archDecodedFrom).nonOperandMemoryWrites.find(d, operationID)) { + otherEffAddrsWritten.insert(d->second.begin(), d->second.end()); + } } - } - } - }); - return; + + dyn_hash_map::const_iterator found = ia32_instruction::getFlagTable().find(operationID); + if (found != ia32_instruction::getFlagTable().end()) { + for (unsigned i = 0; i < found->second.readFlags.size(); i++) { + switch (found->second.readFlags[i]) { + case x86::icf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); + break; + case x86::ipf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); + break; + case x86::iaf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); + break; + case x86::izf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + break; + case x86::isf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); + break; + case x86::itf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); + break; + case x86::idf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + break; + case x86::iof: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); + break; + case x86::int_: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); + break; + case x86::iif_: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); + break; + default: + assert(0); + } + } + + for (unsigned j = 0; j < found->second.writtenFlags.size(); j++) { + switch (found->second.writtenFlags[j]) { + case x86::icf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); + break; + case x86::ipf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); + break; + case x86::iaf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); + break; + case x86::izf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + break; + case x86::isf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); + break; + case x86::itf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); + break; + case x86::idf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + break; + case x86::iof: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); + break; + case x86::int_: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); + break; + case x86::iif_: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); + break; + default: + fprintf(stderr, "ERROR: unhandled entry %s\n", + found->second.writtenFlags[j].name().c_str()); + assert(0); + } + } + } + }); + return; + } } - } } diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index 306328ae93..f5b612fef0 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -91,7 +91,7 @@ namespace Dyninst std::string RegisterAST::format(Architecture arch, formatStyle f) const { - if(arch == Arch_amdgpu_vega){ + if(arch == Arch_amdgpu_vega || arch == Arch_amdgpu_cdna2){ return RegisterAST::format(f); } return ArchSpecificFormatter::getFormatter(arch).formatRegister(m_Reg.name()); @@ -100,15 +100,35 @@ namespace Dyninst std::string RegisterAST::format(formatStyle) const { std::string name = m_Reg.name(); - std::string::size_type substr = name.rfind(':'); - if(substr != std::string::npos) + std::string::size_type substr = name.rfind("::"); + Architecture arch = m_Reg.getArchitecture(); + if(/*arch != Arch_amdgpu_vega && arch != Arch_amdgpu_cdna2 && */substr != std::string::npos) { - name = name.substr(substr + 1, name.length()); - } - if ( m_Reg.size()*8 != m_High - m_Low){ - name += "["+to_string(m_Low)+":"+to_string(m_High)+"]"; + name = name.substr(substr + 2, name.length()); } + // Size of base register * 8 != m_High - mLow ( in bits) when we it is a register vector + if ( m_High -m_Low > 32 && m_Reg.size()*8 != m_High - m_Low){ + uint32_t id = m_Reg & 0xff ; + uint32_t regClass = m_Reg.regClass(); + uint32_t size = (m_High - m_Low ) / 32; + if( regClass == amdgpu_cdna2::SGPR || regClass == amdgpu_vega::SGPR){ + return "S["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_cdna2::VGPR || regClass == amdgpu_vega::VGPR){ + return "V["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_cdna2::ACC_VGPR){ + return "ACC["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + if(m_Reg == amdgpu_cdna2::vcc_lo || m_Reg == amdgpu_vega::vcc_lo) + return "VCC"; + if(m_Reg == amdgpu_cdna2::exec_lo || m_Reg == amdgpu_vega::exec_lo) + return "EXEC"; + name += "["+to_string(m_Low)+":"+to_string(m_High)+"]"; + } /* we have moved to AT&T syntax (lowercase registers) */ for(char &c : name) c = std::toupper(c); diff --git a/instructionAPI/src/amdgpu_branchinsn_table.h b/instructionAPI/src/amdgpu_branchinsn_table.h index b6b9bcfd7a..c6ecc58feb 100644 --- a/instructionAPI/src/amdgpu_branchinsn_table.h +++ b/instructionAPI/src/amdgpu_branchinsn_table.h @@ -14,3 +14,19 @@ case amdgpu_op_s_cbranch_g_fork: case amdgpu_op_s_cbranch_i_fork: case amdgpu_op_s_call_b64: + case amdgpu_cdna2_op_S_BRANCH: + case amdgpu_cdna2_op_S_CBRANCH_SCC0: + case amdgpu_cdna2_op_S_CBRANCH_SCC1: + case amdgpu_cdna2_op_S_CBRANCH_VCCZ: + case amdgpu_cdna2_op_S_CBRANCH_VCCNZ: + case amdgpu_cdna2_op_S_CBRANCH_EXECZ: + case amdgpu_cdna2_op_S_CBRANCH_EXECNZ: + case amdgpu_cdna2_op_S_CBRANCH_CDBGSYS: + case amdgpu_cdna2_op_S_CBRANCH_CDBGUSER: + case amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER: + case amdgpu_cdna2_op_S_SETPC_B64: + case amdgpu_cdna2_op_S_SWAPPC_B64: + case amdgpu_cdna2_op_S_RFE_B64: + case amdgpu_cdna2_op_S_CBRANCH_G_FORK: + case amdgpu_cdna2_op_S_CBRANCH_I_FORK: + case amdgpu_cdna2_op_S_CALL_B64: diff --git a/instructionAPI/src/amdgpu_insn_entry.h b/instructionAPI/src/amdgpu_insn_entry.h deleted file mode 100644 index 2f13df5b88..0000000000 --- a/instructionAPI/src/amdgpu_insn_entry.h +++ /dev/null @@ -1,24 +0,0 @@ -struct amdgpu_insn_entry { - entryID op; - const char *mnemonic; - std::size_t operandCnt; - const operandFactory *operands; - static const amdgpu_insn_table main_insn_table; - static const operandFactory operandTable[]; - static const amdgpu_insn_table sop2_insn_table; - static const amdgpu_insn_table sop1_insn_table; - static const amdgpu_insn_table sopk_insn_table; - static const amdgpu_insn_table sopc_insn_table; - static const amdgpu_insn_table sopp_insn_table; - static const amdgpu_insn_table smem_insn_table; - static const amdgpu_insn_table vop2_insn_table; - static const amdgpu_insn_table vop1_insn_table; - static const amdgpu_insn_table vopc_insn_table; - static const amdgpu_insn_table vintrp_insn_table; - static const amdgpu_insn_table ds_insn_table; - static const amdgpu_insn_table mtbuf_insn_table; - static const amdgpu_insn_table mubuf_insn_table; - static const amdgpu_insn_table vop3ab_insn_table; - static const amdgpu_insn_table vop3p_insn_table; - static const amdgpu_insn_table flat_insn_table; -}; diff --git a/parseAPI/src/IA_IAPI.C b/parseAPI/src/IA_IAPI.C index 5ffc9a6ed6..948be3001f 100644 --- a/parseAPI/src/IA_IAPI.C +++ b/parseAPI/src/IA_IAPI.C @@ -123,6 +123,10 @@ IA_IAPI* IA_IAPI::makePlatformIA_IAPI(Architecture arch, case Arch_amdgpu_vega: return new IA_amdgpu(dec_, where_, o, r, isrc, curBlk_); + case Arch_amdgpu_cdna2: + + return new IA_amdgpu(dec_, where_, o, r, isrc, curBlk_); + default: assert(!"unimplemented architecture"); } @@ -136,21 +140,23 @@ void IA_IAPI::initASTs() std::call_once(IA_IAPI::ptrInit, [&]{ if(framePtr.empty()) { - framePtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86))); - framePtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86_64))); - framePtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc32))); - framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64))); - framePtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_aarch64))); - framePtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_vega))); + framePtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86))); + framePtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86_64))); + framePtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc32))); + framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64))); + framePtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_aarch64))); + framePtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_vega))); + framePtr[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_cdna2))); } if(stackPtr.empty()) { - stackPtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86))); - stackPtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86_64))); - stackPtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc32))); - stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64))); - stackPtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_aarch64))); - stackPtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_vega))); + stackPtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86))); + stackPtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86_64))); + stackPtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc32))); + stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64))); + stackPtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_aarch64))); + stackPtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_vega))); + stackPtr[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_cdna2))); } if(thePC.empty()) { @@ -160,6 +166,7 @@ void IA_IAPI::initASTs() thePC[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc64))); thePC[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_aarch64))); thePC[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_vega))); + thePC[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_cdna2))); } ANNOTATE_HAPPENS_BEFORE(&IA_IAPI::ptrInit); }); diff --git a/parseAPI/src/IA_amdgpu.C b/parseAPI/src/IA_amdgpu.C index c3305017cc..463fe7f9c7 100644 --- a/parseAPI/src/IA_amdgpu.C +++ b/parseAPI/src/IA_amdgpu.C @@ -73,7 +73,8 @@ bool IA_amdgpu::isFrameSetupInsn(Instruction ) const bool IA_amdgpu::isNop() const { Instruction ci = curInsn(); - if(ci.getOperation().getID() == amdgpu_op_s_nop) + auto id = ci.getOperation().getID(); + if(id == amdgpu_op_s_nop || id == amdgpu_cdna2_op_S_NOP ) return true; return false; } diff --git a/parseAPI/src/SymbolicExpression.C b/parseAPI/src/SymbolicExpression.C index e44a0582de..b9f556f28a 100644 --- a/parseAPI/src/SymbolicExpression.C +++ b/parseAPI/src/SymbolicExpression.C @@ -423,9 +423,9 @@ Address SymbolicExpression::PCValue(Address cur, size_t insnSize, Architecture a case Arch_x86: case Arch_x86_64: case Arch_amdgpu_vega: + case Arch_amdgpu_cdna2: return cur + insnSize; case Arch_aarch64: - case Arch_amdgpu_rdna: case Arch_ppc32: case Arch_ppc64: return cur; diff --git a/proccontrol/src/process.C b/proccontrol/src/process.C index 4d50a2559b..1fb3da15ee 100644 --- a/proccontrol/src/process.C +++ b/proccontrol/src/process.C @@ -1938,7 +1938,8 @@ int int_process::getAddressWidth() case Arch_intelGen9: return 8; case Arch_amdgpu_vega: // according to the vega architecture, there are 32/64 address mode - case Arch_amdgpu_rdna: + case Arch_amdgpu_cdna2: + return 8; case Arch_none: assert(0); } From ee629d08b3a76d36d4fbded2395e7c8780cb65da Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 24 Feb 2022 15:53:26 -0600 Subject: [PATCH 077/505] Build fixes for amdgpu/cdna2 (#1203) * Clean up duplicate cdna2 sys_reg headers (#1200) * add install rule to install amdgpu headers under common/h (#1201) Co-authored-by: bbiiggppiigg --- common/CMakeLists.txt | 7 + .../cdna2}/amdgpu_cdna2_op_table.h | 0 common/h/amdgpu_cdna2_sys_regs.h | 1563 ----------------- common/h/entryIDs.h | 2 +- 4 files changed, 8 insertions(+), 1564 deletions(-) rename common/h/{ => AMDGPU/cdna2}/amdgpu_cdna2_op_table.h (100%) delete mode 100644 common/h/amdgpu_cdna2_sys_regs.h diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 5bde2b9e5c..91e0ea258a 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -136,3 +136,10 @@ target_link_libraries(common PUBLIC ${TBB_LIBRARIES}) if(USE_OpenMP) set_target_properties(common PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) endif() + +# Install AMDGPU headers under subdirectory of common/h/AMDGPU +set(AMDGPU_HEADER + ${DYNINST_ROOT}/common/h/AMDGPU +) +install(DIRECTORY ${AMDGPU_HEADER} DESTINATION ${INSTALL_INCLUDE_DIR}) + diff --git a/common/h/amdgpu_cdna2_op_table.h b/common/h/AMDGPU/cdna2/amdgpu_cdna2_op_table.h similarity index 100% rename from common/h/amdgpu_cdna2_op_table.h rename to common/h/AMDGPU/cdna2/amdgpu_cdna2_op_table.h diff --git a/common/h/amdgpu_cdna2_sys_regs.h b/common/h/amdgpu_cdna2_sys_regs.h deleted file mode 100644 index eb74b6cf98..0000000000 --- a/common/h/amdgpu_cdna2_sys_regs.h +++ /dev/null @@ -1,1563 +0,0 @@ -#ifndef DYNINST_AMDGPU_CDNA2_SYS_REGS_H -#define DYNINST_AMDGPU_CDNA2_SYS_REGS_H -DEF_REGISTER(address_mode_32, Arch_amdgpu_cdna2 | HWR | BITS_32 | 0,"amdgpu_cdna2"); -DEF_REGISTER(exec, Arch_amdgpu_cdna2 | HWR | BITS_64 | 1,"amdgpu_cdna2"); -DEF_REGISTER(exec_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 1,"amdgpu_cdna2"); -DEF_REGISTER(exec_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 1,"amdgpu_cdna2"); -DEF_REGISTER(expcnt, Arch_amdgpu_cdna2 | HWR | BITS_3 | 2,"amdgpu_cdna2"); -DEF_REGISTER(export_icount, Arch_amdgpu_cdna2 | HWR | BITS_8 | 3,"amdgpu_cdna2"); -DEF_REGISTER(flat_scratch, Arch_amdgpu_cdna2 | HWR | BITS_64 | 4,"amdgpu_cdna2"); -DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 4,"amdgpu_cdna2"); -DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 4,"amdgpu_cdna2"); -DEF_REGISTER(gpr_alloc, Arch_amdgpu_cdna2 | HWR | BITS_32 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_base, Arch_amdgpu_cdna2 | 0x0 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpt_size, Arch_amdgpu_cdna2 | 0x80000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_base, Arch_amdgpu_cdna2 | 0x100000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_size, Arch_amdgpu_cdna2 | 0x180000 | BITS_4 | 0x8000 | 5,"amdgpu_cdna2"); -DEF_REGISTER(ib_sts, Arch_amdgpu_cdna2 | HWR | BITS_32 | 6,"amdgpu_cdna2"); -DEF_REGISTER(exp_cnt, Arch_amdgpu_cdna2 | 0x40000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna2"); -DEF_REGISTER(lgkm_cnt, Arch_amdgpu_cdna2 | 0x80000 | BITS_4 | 0x8000 | 6,"amdgpu_cdna2"); -DEF_REGISTER(valu_cnt, Arch_amdgpu_cdna2 | 0xc0000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vm_cnt, Arch_amdgpu_cdna2 | 0xf0000 | BITS_6 | 0x8000 | 6,"amdgpu_cdna2"); -DEF_REGISTER(lds_alloc, Arch_amdgpu_cdna2 | HWR | BITS_32 | 7,"amdgpu_cdna2"); -DEF_REGISTER(lds_base, Arch_amdgpu_cdna2 | 0x0 | BITS_8 | 0x8000 | 7,"amdgpu_cdna2"); -DEF_REGISTER(lds_size, Arch_amdgpu_cdna2 | 0xc0000 | BITS_9 | 0x8000 | 7,"amdgpu_cdna2"); -DEF_REGISTER(lds_gds_constant_message_count, Arch_amdgpu_cdna2 | HWR | BITS_8 | 8,"amdgpu_cdna2"); -DEF_REGISTER(lgkmcnt, Arch_amdgpu_cdna2 | HWR | BITS_4 | 9,"amdgpu_cdna2"); -DEF_REGISTER(m0, Arch_amdgpu_cdna2 | HWR | BITS_32 | 10,"amdgpu_cdna2"); -DEF_REGISTER(gds_size, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(lds_direct_address, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(lds_interpolation_parameter_offset, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(lds_memory_vfetch_offset, Arch_amdgpu_cdna2 | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(lds_direct_data_type, Arch_amdgpu_cdna2 | 0x100000 | BITS_3 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(lds_interpolation_new_prim_mask, Arch_amdgpu_cdna2 | 0x100000 | BITS_15 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(gds_base, Arch_amdgpu_cdna2 | 0x100000 | BITS_16 | 0x8000 | 10,"amdgpu_cdna2"); -DEF_REGISTER(mode, Arch_amdgpu_cdna2 | HWR | BITS_32 | 11,"amdgpu_cdna2"); -DEF_REGISTER(fp_round, Arch_amdgpu_cdna2 | 0x0 | BITS_4 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(fp_denorm, Arch_amdgpu_cdna2 | 0x40000 | BITS_4 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(dx10_clamp, Arch_amdgpu_cdna2 | 0x80000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(ieee, Arch_amdgpu_cdna2 | 0x90000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(lod_clamped, Arch_amdgpu_cdna2 | 0xa0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(debug, Arch_amdgpu_cdna2 | 0xb0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(excp_en, Arch_amdgpu_cdna2 | 0xc0000 | BITS_7 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(fp16_ovfl, Arch_amdgpu_cdna2 | 0x170000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(pops_packer0, Arch_amdgpu_cdna2 | 0x180000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(pops_packer1, Arch_amdgpu_cdna2 | 0x190000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(disable_perf, Arch_amdgpu_cdna2 | 0x1a0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(gpr_idx_en, Arch_amdgpu_cdna2 | 0x1b0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vskip, Arch_amdgpu_cdna2 | 0x1c0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(csp, Arch_amdgpu_cdna2 | 0x1d0000 | BITS_3 | 0x8000 | 11,"amdgpu_cdna2"); -DEF_REGISTER(pc, Arch_amdgpu_cdna2 | PC | BITS_48 | 0,"amdgpu_cdna2"); -DEF_REGISTER(pops_exiting_wave_id, Arch_amdgpu_cdna2 | HWR | BITS_64 | 12,"amdgpu_cdna2"); -DEF_REGISTER(private_base, Arch_amdgpu_cdna2 | HWR | BITS_64 | 13,"amdgpu_cdna2"); -DEF_REGISTER(private_limit, Arch_amdgpu_cdna2 | HWR | BITS_64 | 14,"amdgpu_cdna2"); -DEF_REGISTER(shared_base, Arch_amdgpu_cdna2 | HWR | BITS_64 | 15,"amdgpu_cdna2"); -DEF_REGISTER(shared_limit, Arch_amdgpu_cdna2 | HWR | BITS_64 | 16,"amdgpu_cdna2"); -DEF_REGISTER(status, Arch_amdgpu_cdna2 | HWR | BITS_32 | 17,"amdgpu_cdna2"); -DEF_REGISTER(scc, Arch_amdgpu_cdna2 | 0x0 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(spi_prio, Arch_amdgpu_cdna2 | 0x10000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(wave_prio, Arch_amdgpu_cdna2 | 0x30000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(priv, Arch_amdgpu_cdna2 | 0x50000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(trap_en, Arch_amdgpu_cdna2 | 0x60000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(ttrace_en, Arch_amdgpu_cdna2 | 0x70000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(export_rdy, Arch_amdgpu_cdna2 | 0x80000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(execz, Arch_amdgpu_cdna2 | 0x90000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vccz, Arch_amdgpu_cdna2 | 0xa0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(in_tg, Arch_amdgpu_cdna2 | 0xb0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(in_barrier, Arch_amdgpu_cdna2 | 0xc0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(halt, Arch_amdgpu_cdna2 | 0xd0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(trap, Arch_amdgpu_cdna2 | 0xe0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(ttrace_cu_en, Arch_amdgpu_cdna2 | 0xf0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(valid, Arch_amdgpu_cdna2 | 0x100000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(ecc_err, Arch_amdgpu_cdna2 | 0x110000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(skin_export, Arch_amdgpu_cdna2 | 0x120000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(perf_en, Arch_amdgpu_cdna2 | 0x130000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(cond_dbg_user, Arch_amdgpu_cdna2 | 0x140000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(cond_dbg_sys, Arch_amdgpu_cdna2 | 0x150000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(allow_replay, Arch_amdgpu_cdna2 | 0x160000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(must_export, Arch_amdgpu_cdna2 | 0x1b0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna2"); -DEF_REGISTER(tba, Arch_amdgpu_cdna2 | HWR | BITS_64 | 18,"amdgpu_cdna2"); -DEF_REGISTER(tid, Arch_amdgpu_cdna2 | HWR | BITS_32 | 19,"amdgpu_cdna2"); -DEF_REGISTER(tma, Arch_amdgpu_cdna2 | HWR | BITS_64 | 20,"amdgpu_cdna2"); -DEF_REGISTER(trap_base_address, Arch_amdgpu_cdna2 | HWR | BITS_64 | 21,"amdgpu_cdna2"); -DEF_REGISTER(trap_memory_address, Arch_amdgpu_cdna2 | HWR | BITS_64 | 22,"amdgpu_cdna2"); -DEF_REGISTER(ttmp0, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 0,"amdgpu_cdna2"); -DEF_REGISTER(ttmp1, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 1,"amdgpu_cdna2"); -DEF_REGISTER(ttmp10, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 2,"amdgpu_cdna2"); -DEF_REGISTER(ttmp11, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 3,"amdgpu_cdna2"); -DEF_REGISTER(ttmp12, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 4,"amdgpu_cdna2"); -DEF_REGISTER(ttmp13, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 5,"amdgpu_cdna2"); -DEF_REGISTER(ttmp14, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 6,"amdgpu_cdna2"); -DEF_REGISTER(ttmp15, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 7,"amdgpu_cdna2"); -DEF_REGISTER(ttmp2, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 8,"amdgpu_cdna2"); -DEF_REGISTER(ttmp3, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 9,"amdgpu_cdna2"); -DEF_REGISTER(ttmp4, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 10,"amdgpu_cdna2"); -DEF_REGISTER(ttmp5, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 11,"amdgpu_cdna2"); -DEF_REGISTER(ttmp6, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 12,"amdgpu_cdna2"); -DEF_REGISTER(ttmp7, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 13,"amdgpu_cdna2"); -DEF_REGISTER(ttmp8, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 14,"amdgpu_cdna2"); -DEF_REGISTER(ttmp9, Arch_amdgpu_cdna2 | TTMP_SGPR | BITS_32 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vcc, Arch_amdgpu_cdna2 | HWR | BITS_64 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vcc_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vcc_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vectory_memory_icount, Arch_amdgpu_cdna2 | HWR | BITS_8 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vmcnt, Arch_amdgpu_cdna2 | HWR | BITS_6 | 25,"amdgpu_cdna2"); -DEF_REGISTER(xnack_mask, Arch_amdgpu_cdna2 | HWR | BITS_64 | 26,"amdgpu_cdna2"); -DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_cdna2 | 0x0 | BITS_32 | 0x8000 | 26,"amdgpu_cdna2"); -DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_cdna2 | 0x200000 | BITS_32 | 0x8000 | 26,"amdgpu_cdna2"); -DEF_REGISTER(sgpr0, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 0,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_0, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_0, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_0, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_0, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna2"); -DEF_REGISTER(sgpr1, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 1,"amdgpu_cdna2"); -DEF_REGISTER(sgpr2, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 2,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_2, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna2"); -DEF_REGISTER(sgpr3, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 3,"amdgpu_cdna2"); -DEF_REGISTER(sgpr4, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 4,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_4, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_4, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna2"); -DEF_REGISTER(sgpr5, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 5,"amdgpu_cdna2"); -DEF_REGISTER(sgpr6, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 6,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_6, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna2"); -DEF_REGISTER(sgpr7, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 7,"amdgpu_cdna2"); -DEF_REGISTER(sgpr8, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 8,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_8, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_8, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_8, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna2"); -DEF_REGISTER(sgpr9, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 9,"amdgpu_cdna2"); -DEF_REGISTER(sgpr10, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 10,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_10, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna2"); -DEF_REGISTER(sgpr11, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 11,"amdgpu_cdna2"); -DEF_REGISTER(sgpr12, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 12,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_12, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_12, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna2"); -DEF_REGISTER(sgpr13, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 13,"amdgpu_cdna2"); -DEF_REGISTER(sgpr14, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 14,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_14, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna2"); -DEF_REGISTER(sgpr15, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 15,"amdgpu_cdna2"); -DEF_REGISTER(sgpr16, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 16,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_16, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_16, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_16, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_16, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna2"); -DEF_REGISTER(sgpr17, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 17,"amdgpu_cdna2"); -DEF_REGISTER(sgpr18, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 18,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_18, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna2"); -DEF_REGISTER(sgpr19, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 19,"amdgpu_cdna2"); -DEF_REGISTER(sgpr20, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 20,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_20, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_20, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna2"); -DEF_REGISTER(sgpr21, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 21,"amdgpu_cdna2"); -DEF_REGISTER(sgpr22, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 22,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_22, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna2"); -DEF_REGISTER(sgpr23, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 23,"amdgpu_cdna2"); -DEF_REGISTER(sgpr24, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 24,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_24, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_24, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_24, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna2"); -DEF_REGISTER(sgpr25, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 25,"amdgpu_cdna2"); -DEF_REGISTER(sgpr26, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 26,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_26, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna2"); -DEF_REGISTER(sgpr27, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 27,"amdgpu_cdna2"); -DEF_REGISTER(sgpr28, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 28,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_28, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_28, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna2"); -DEF_REGISTER(sgpr29, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 29,"amdgpu_cdna2"); -DEF_REGISTER(sgpr30, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 30,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_30, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna2"); -DEF_REGISTER(sgpr31, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 31,"amdgpu_cdna2"); -DEF_REGISTER(sgpr32, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 32,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_32, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_32, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_32, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_32, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna2"); -DEF_REGISTER(sgpr33, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 33,"amdgpu_cdna2"); -DEF_REGISTER(sgpr34, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 34,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_34, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna2"); -DEF_REGISTER(sgpr35, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 35,"amdgpu_cdna2"); -DEF_REGISTER(sgpr36, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 36,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_36, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_36, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna2"); -DEF_REGISTER(sgpr37, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 37,"amdgpu_cdna2"); -DEF_REGISTER(sgpr38, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 38,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_38, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna2"); -DEF_REGISTER(sgpr39, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 39,"amdgpu_cdna2"); -DEF_REGISTER(sgpr40, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 40,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_40, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_40, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_40, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna2"); -DEF_REGISTER(sgpr41, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 41,"amdgpu_cdna2"); -DEF_REGISTER(sgpr42, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 42,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_42, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna2"); -DEF_REGISTER(sgpr43, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 43,"amdgpu_cdna2"); -DEF_REGISTER(sgpr44, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 44,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_44, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_44, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna2"); -DEF_REGISTER(sgpr45, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 45,"amdgpu_cdna2"); -DEF_REGISTER(sgpr46, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 46,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_46, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna2"); -DEF_REGISTER(sgpr47, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 47,"amdgpu_cdna2"); -DEF_REGISTER(sgpr48, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 48,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_48, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_48, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_48, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_48, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna2"); -DEF_REGISTER(sgpr49, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 49,"amdgpu_cdna2"); -DEF_REGISTER(sgpr50, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 50,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_50, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna2"); -DEF_REGISTER(sgpr51, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 51,"amdgpu_cdna2"); -DEF_REGISTER(sgpr52, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 52,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_52, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_52, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna2"); -DEF_REGISTER(sgpr53, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 53,"amdgpu_cdna2"); -DEF_REGISTER(sgpr54, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 54,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_54, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna2"); -DEF_REGISTER(sgpr55, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 55,"amdgpu_cdna2"); -DEF_REGISTER(sgpr56, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 56,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_56, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_56, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_56, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna2"); -DEF_REGISTER(sgpr57, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 57,"amdgpu_cdna2"); -DEF_REGISTER(sgpr58, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 58,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_58, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna2"); -DEF_REGISTER(sgpr59, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 59,"amdgpu_cdna2"); -DEF_REGISTER(sgpr60, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 60,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_60, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_60, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna2"); -DEF_REGISTER(sgpr61, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 61,"amdgpu_cdna2"); -DEF_REGISTER(sgpr62, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 62,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_62, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna2"); -DEF_REGISTER(sgpr63, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 63,"amdgpu_cdna2"); -DEF_REGISTER(sgpr64, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 64,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_64, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_64, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_64, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_64, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna2"); -DEF_REGISTER(sgpr65, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 65,"amdgpu_cdna2"); -DEF_REGISTER(sgpr66, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 66,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_66, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna2"); -DEF_REGISTER(sgpr67, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 67,"amdgpu_cdna2"); -DEF_REGISTER(sgpr68, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 68,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_68, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_68, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna2"); -DEF_REGISTER(sgpr69, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 69,"amdgpu_cdna2"); -DEF_REGISTER(sgpr70, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 70,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_70, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna2"); -DEF_REGISTER(sgpr71, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 71,"amdgpu_cdna2"); -DEF_REGISTER(sgpr72, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 72,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_72, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_72, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_72, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna2"); -DEF_REGISTER(sgpr73, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 73,"amdgpu_cdna2"); -DEF_REGISTER(sgpr74, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 74,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_74, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna2"); -DEF_REGISTER(sgpr75, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 75,"amdgpu_cdna2"); -DEF_REGISTER(sgpr76, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 76,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_76, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_76, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna2"); -DEF_REGISTER(sgpr77, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 77,"amdgpu_cdna2"); -DEF_REGISTER(sgpr78, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 78,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_78, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna2"); -DEF_REGISTER(sgpr79, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 79,"amdgpu_cdna2"); -DEF_REGISTER(sgpr80, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 80,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_80, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_80, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_80, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec16_80, Arch_amdgpu_cdna2 | SGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna2"); -DEF_REGISTER(sgpr81, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 81,"amdgpu_cdna2"); -DEF_REGISTER(sgpr82, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 82,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_82, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna2"); -DEF_REGISTER(sgpr83, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 83,"amdgpu_cdna2"); -DEF_REGISTER(sgpr84, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 84,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_84, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_84, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna2"); -DEF_REGISTER(sgpr85, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 85,"amdgpu_cdna2"); -DEF_REGISTER(sgpr86, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 86,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_86, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna2"); -DEF_REGISTER(sgpr87, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 87,"amdgpu_cdna2"); -DEF_REGISTER(sgpr88, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 88,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_88, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_88, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_88, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna2"); -DEF_REGISTER(sgpr89, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 89,"amdgpu_cdna2"); -DEF_REGISTER(sgpr90, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 90,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_90, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna2"); -DEF_REGISTER(sgpr91, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 91,"amdgpu_cdna2"); -DEF_REGISTER(sgpr92, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 92,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_92, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_92, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna2"); -DEF_REGISTER(sgpr93, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 93,"amdgpu_cdna2"); -DEF_REGISTER(sgpr94, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 94,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_94, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna2"); -DEF_REGISTER(sgpr95, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 95,"amdgpu_cdna2"); -DEF_REGISTER(sgpr96, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 96,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_96, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_96, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec8_96, Arch_amdgpu_cdna2 | SGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna2"); -DEF_REGISTER(sgpr97, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 97,"amdgpu_cdna2"); -DEF_REGISTER(sgpr98, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 98,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_98, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna2"); -DEF_REGISTER(sgpr99, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 99,"amdgpu_cdna2"); -DEF_REGISTER(sgpr100, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 100,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_100, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec4_100, Arch_amdgpu_cdna2 | SGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna2"); -DEF_REGISTER(sgpr101, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 101,"amdgpu_cdna2"); -DEF_REGISTER(sgpr102, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 102,"amdgpu_cdna2"); -DEF_REGISTER(sgpr_vec2_102, Arch_amdgpu_cdna2 | SGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna2"); -DEF_REGISTER(sgpr103, Arch_amdgpu_cdna2 | SGPR | BITS_32 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr0, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 0,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_0, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_0, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_0, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_0, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna2"); -DEF_REGISTER(vgpr1, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 1,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_1, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 1,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_1, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 1,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_1, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 1,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_1, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 1,"amdgpu_cdna2"); -DEF_REGISTER(vgpr2, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 2,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_2, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_2, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 2,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_2, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 2,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_2, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 2,"amdgpu_cdna2"); -DEF_REGISTER(vgpr3, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 3,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_3, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 3,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_3, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 3,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_3, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 3,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_3, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 3,"amdgpu_cdna2"); -DEF_REGISTER(vgpr4, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 4,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_4, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_4, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_4, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 4,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_4, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 4,"amdgpu_cdna2"); -DEF_REGISTER(vgpr5, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_5, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_5, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_5, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_5, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 5,"amdgpu_cdna2"); -DEF_REGISTER(vgpr6, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_6, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_6, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_6, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_6, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 6,"amdgpu_cdna2"); -DEF_REGISTER(vgpr7, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 7,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_7, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 7,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_7, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 7,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_7, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 7,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_7, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 7,"amdgpu_cdna2"); -DEF_REGISTER(vgpr8, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 8,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_8, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_8, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_8, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_8, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 8,"amdgpu_cdna2"); -DEF_REGISTER(vgpr9, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 9,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_9, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 9,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_9, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 9,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_9, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 9,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_9, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 9,"amdgpu_cdna2"); -DEF_REGISTER(vgpr10, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 10,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_10, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_10, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 10,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_10, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 10,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_10, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 10,"amdgpu_cdna2"); -DEF_REGISTER(vgpr11, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_11, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_11, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_11, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_11, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 11,"amdgpu_cdna2"); -DEF_REGISTER(vgpr12, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 12,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_12, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_12, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_12, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 12,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_12, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 12,"amdgpu_cdna2"); -DEF_REGISTER(vgpr13, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 13,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_13, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 13,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_13, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 13,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_13, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 13,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_13, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 13,"amdgpu_cdna2"); -DEF_REGISTER(vgpr14, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 14,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_14, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_14, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 14,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_14, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 14,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_14, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 14,"amdgpu_cdna2"); -DEF_REGISTER(vgpr15, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_15, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_15, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_15, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_15, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 15,"amdgpu_cdna2"); -DEF_REGISTER(vgpr16, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 16,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_16, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_16, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_16, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_16, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna2"); -DEF_REGISTER(vgpr17, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_17, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_17, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_17, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_17, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 17,"amdgpu_cdna2"); -DEF_REGISTER(vgpr18, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 18,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_18, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_18, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 18,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_18, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 18,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_18, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 18,"amdgpu_cdna2"); -DEF_REGISTER(vgpr19, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 19,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_19, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 19,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_19, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 19,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_19, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 19,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_19, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 19,"amdgpu_cdna2"); -DEF_REGISTER(vgpr20, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 20,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_20, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_20, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_20, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 20,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_20, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 20,"amdgpu_cdna2"); -DEF_REGISTER(vgpr21, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 21,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_21, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 21,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_21, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 21,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_21, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 21,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_21, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 21,"amdgpu_cdna2"); -DEF_REGISTER(vgpr22, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 22,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_22, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_22, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 22,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_22, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 22,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_22, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 22,"amdgpu_cdna2"); -DEF_REGISTER(vgpr23, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_23, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_23, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_23, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_23, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 23,"amdgpu_cdna2"); -DEF_REGISTER(vgpr24, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_24, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_24, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_24, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_24, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 24,"amdgpu_cdna2"); -DEF_REGISTER(vgpr25, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 25,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_25, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 25,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_25, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 25,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_25, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 25,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_25, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 25,"amdgpu_cdna2"); -DEF_REGISTER(vgpr26, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 26,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_26, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_26, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 26,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_26, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 26,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_26, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 26,"amdgpu_cdna2"); -DEF_REGISTER(vgpr27, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 27,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_27, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 27,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_27, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 27,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_27, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 27,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_27, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 27,"amdgpu_cdna2"); -DEF_REGISTER(vgpr28, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 28,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_28, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_28, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_28, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 28,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_28, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 28,"amdgpu_cdna2"); -DEF_REGISTER(vgpr29, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 29,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_29, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 29,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_29, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 29,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_29, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 29,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_29, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 29,"amdgpu_cdna2"); -DEF_REGISTER(vgpr30, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 30,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_30, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_30, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 30,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_30, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 30,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_30, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 30,"amdgpu_cdna2"); -DEF_REGISTER(vgpr31, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 31,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_31, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 31,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_31, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 31,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_31, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 31,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_31, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 31,"amdgpu_cdna2"); -DEF_REGISTER(vgpr32, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 32,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_32, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_32, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_32, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_32, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna2"); -DEF_REGISTER(vgpr33, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 33,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_33, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 33,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_33, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 33,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_33, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 33,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_33, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 33,"amdgpu_cdna2"); -DEF_REGISTER(vgpr34, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 34,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_34, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_34, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 34,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_34, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 34,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_34, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 34,"amdgpu_cdna2"); -DEF_REGISTER(vgpr35, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 35,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_35, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 35,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_35, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 35,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_35, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 35,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_35, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 35,"amdgpu_cdna2"); -DEF_REGISTER(vgpr36, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 36,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_36, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_36, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_36, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 36,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_36, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 36,"amdgpu_cdna2"); -DEF_REGISTER(vgpr37, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 37,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_37, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 37,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_37, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 37,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_37, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 37,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_37, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 37,"amdgpu_cdna2"); -DEF_REGISTER(vgpr38, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 38,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_38, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_38, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 38,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_38, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 38,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_38, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 38,"amdgpu_cdna2"); -DEF_REGISTER(vgpr39, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 39,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_39, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 39,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_39, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 39,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_39, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 39,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_39, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 39,"amdgpu_cdna2"); -DEF_REGISTER(vgpr40, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 40,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_40, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_40, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_40, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_40, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 40,"amdgpu_cdna2"); -DEF_REGISTER(vgpr41, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 41,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_41, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 41,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_41, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 41,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_41, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 41,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_41, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 41,"amdgpu_cdna2"); -DEF_REGISTER(vgpr42, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 42,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_42, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_42, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 42,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_42, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 42,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_42, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 42,"amdgpu_cdna2"); -DEF_REGISTER(vgpr43, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 43,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_43, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 43,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_43, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 43,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_43, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 43,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_43, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 43,"amdgpu_cdna2"); -DEF_REGISTER(vgpr44, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 44,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_44, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_44, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_44, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 44,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_44, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 44,"amdgpu_cdna2"); -DEF_REGISTER(vgpr45, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 45,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_45, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 45,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_45, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 45,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_45, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 45,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_45, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 45,"amdgpu_cdna2"); -DEF_REGISTER(vgpr46, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 46,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_46, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_46, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 46,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_46, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 46,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_46, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 46,"amdgpu_cdna2"); -DEF_REGISTER(vgpr47, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 47,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_47, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 47,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_47, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 47,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_47, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 47,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_47, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 47,"amdgpu_cdna2"); -DEF_REGISTER(vgpr48, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 48,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_48, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_48, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_48, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_48, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna2"); -DEF_REGISTER(vgpr49, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 49,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_49, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 49,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_49, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 49,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_49, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 49,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_49, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 49,"amdgpu_cdna2"); -DEF_REGISTER(vgpr50, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 50,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_50, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_50, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 50,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_50, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 50,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_50, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 50,"amdgpu_cdna2"); -DEF_REGISTER(vgpr51, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 51,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_51, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 51,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_51, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 51,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_51, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 51,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_51, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 51,"amdgpu_cdna2"); -DEF_REGISTER(vgpr52, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 52,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_52, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_52, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_52, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 52,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_52, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 52,"amdgpu_cdna2"); -DEF_REGISTER(vgpr53, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 53,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_53, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 53,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_53, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 53,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_53, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 53,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_53, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 53,"amdgpu_cdna2"); -DEF_REGISTER(vgpr54, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 54,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_54, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_54, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 54,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_54, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 54,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_54, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 54,"amdgpu_cdna2"); -DEF_REGISTER(vgpr55, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 55,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_55, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 55,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_55, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 55,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_55, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 55,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_55, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 55,"amdgpu_cdna2"); -DEF_REGISTER(vgpr56, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 56,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_56, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_56, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_56, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_56, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 56,"amdgpu_cdna2"); -DEF_REGISTER(vgpr57, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 57,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_57, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 57,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_57, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 57,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_57, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 57,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_57, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 57,"amdgpu_cdna2"); -DEF_REGISTER(vgpr58, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 58,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_58, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_58, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 58,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_58, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 58,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_58, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 58,"amdgpu_cdna2"); -DEF_REGISTER(vgpr59, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 59,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_59, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 59,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_59, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 59,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_59, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 59,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_59, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 59,"amdgpu_cdna2"); -DEF_REGISTER(vgpr60, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 60,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_60, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_60, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_60, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 60,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_60, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 60,"amdgpu_cdna2"); -DEF_REGISTER(vgpr61, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 61,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_61, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 61,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_61, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 61,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_61, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 61,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_61, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 61,"amdgpu_cdna2"); -DEF_REGISTER(vgpr62, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 62,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_62, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_62, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 62,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_62, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 62,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_62, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 62,"amdgpu_cdna2"); -DEF_REGISTER(vgpr63, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 63,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_63, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 63,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_63, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 63,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_63, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 63,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_63, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 63,"amdgpu_cdna2"); -DEF_REGISTER(vgpr64, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 64,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_64, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_64, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_64, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_64, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna2"); -DEF_REGISTER(vgpr65, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 65,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_65, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 65,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_65, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 65,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_65, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 65,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_65, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 65,"amdgpu_cdna2"); -DEF_REGISTER(vgpr66, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 66,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_66, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_66, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 66,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_66, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 66,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_66, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 66,"amdgpu_cdna2"); -DEF_REGISTER(vgpr67, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 67,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_67, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 67,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_67, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 67,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_67, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 67,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_67, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 67,"amdgpu_cdna2"); -DEF_REGISTER(vgpr68, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 68,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_68, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_68, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_68, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 68,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_68, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 68,"amdgpu_cdna2"); -DEF_REGISTER(vgpr69, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 69,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_69, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 69,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_69, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 69,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_69, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 69,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_69, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 69,"amdgpu_cdna2"); -DEF_REGISTER(vgpr70, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 70,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_70, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_70, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 70,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_70, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 70,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_70, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 70,"amdgpu_cdna2"); -DEF_REGISTER(vgpr71, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 71,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_71, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 71,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_71, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 71,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_71, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 71,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_71, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 71,"amdgpu_cdna2"); -DEF_REGISTER(vgpr72, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 72,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_72, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_72, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_72, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_72, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 72,"amdgpu_cdna2"); -DEF_REGISTER(vgpr73, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 73,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_73, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 73,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_73, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 73,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_73, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 73,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_73, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 73,"amdgpu_cdna2"); -DEF_REGISTER(vgpr74, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 74,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_74, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_74, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 74,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_74, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 74,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_74, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 74,"amdgpu_cdna2"); -DEF_REGISTER(vgpr75, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 75,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_75, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 75,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_75, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 75,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_75, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 75,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_75, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 75,"amdgpu_cdna2"); -DEF_REGISTER(vgpr76, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 76,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_76, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_76, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_76, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 76,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_76, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 76,"amdgpu_cdna2"); -DEF_REGISTER(vgpr77, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 77,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_77, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 77,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_77, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 77,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_77, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 77,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_77, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 77,"amdgpu_cdna2"); -DEF_REGISTER(vgpr78, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 78,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_78, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_78, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 78,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_78, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 78,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_78, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 78,"amdgpu_cdna2"); -DEF_REGISTER(vgpr79, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 79,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_79, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 79,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_79, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 79,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_79, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 79,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_79, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 79,"amdgpu_cdna2"); -DEF_REGISTER(vgpr80, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 80,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_80, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_80, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_80, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_80, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna2"); -DEF_REGISTER(vgpr81, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 81,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_81, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 81,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_81, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 81,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_81, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 81,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_81, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 81,"amdgpu_cdna2"); -DEF_REGISTER(vgpr82, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 82,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_82, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_82, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 82,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_82, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 82,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_82, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 82,"amdgpu_cdna2"); -DEF_REGISTER(vgpr83, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 83,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_83, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 83,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_83, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 83,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_83, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 83,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_83, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 83,"amdgpu_cdna2"); -DEF_REGISTER(vgpr84, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 84,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_84, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_84, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_84, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 84,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_84, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 84,"amdgpu_cdna2"); -DEF_REGISTER(vgpr85, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 85,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_85, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 85,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_85, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 85,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_85, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 85,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_85, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 85,"amdgpu_cdna2"); -DEF_REGISTER(vgpr86, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 86,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_86, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_86, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 86,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_86, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 86,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_86, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 86,"amdgpu_cdna2"); -DEF_REGISTER(vgpr87, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 87,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_87, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 87,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_87, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 87,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_87, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 87,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_87, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 87,"amdgpu_cdna2"); -DEF_REGISTER(vgpr88, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 88,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_88, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_88, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_88, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_88, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 88,"amdgpu_cdna2"); -DEF_REGISTER(vgpr89, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 89,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_89, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 89,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_89, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 89,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_89, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 89,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_89, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 89,"amdgpu_cdna2"); -DEF_REGISTER(vgpr90, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 90,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_90, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_90, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 90,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_90, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 90,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_90, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 90,"amdgpu_cdna2"); -DEF_REGISTER(vgpr91, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 91,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_91, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 91,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_91, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 91,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_91, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 91,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_91, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 91,"amdgpu_cdna2"); -DEF_REGISTER(vgpr92, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 92,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_92, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_92, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_92, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 92,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_92, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 92,"amdgpu_cdna2"); -DEF_REGISTER(vgpr93, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 93,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_93, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 93,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_93, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 93,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_93, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 93,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_93, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 93,"amdgpu_cdna2"); -DEF_REGISTER(vgpr94, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 94,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_94, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_94, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 94,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_94, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 94,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_94, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 94,"amdgpu_cdna2"); -DEF_REGISTER(vgpr95, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 95,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_95, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 95,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_95, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 95,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_95, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 95,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_95, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 95,"amdgpu_cdna2"); -DEF_REGISTER(vgpr96, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 96,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_96, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_96, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_96, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_96, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 96,"amdgpu_cdna2"); -DEF_REGISTER(vgpr97, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 97,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_97, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 97,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_97, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 97,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_97, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 97,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_97, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 97,"amdgpu_cdna2"); -DEF_REGISTER(vgpr98, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 98,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_98, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_98, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 98,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_98, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 98,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_98, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 98,"amdgpu_cdna2"); -DEF_REGISTER(vgpr99, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 99,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_99, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 99,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_99, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 99,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_99, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 99,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_99, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 99,"amdgpu_cdna2"); -DEF_REGISTER(vgpr100, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 100,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_100, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_100, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_100, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 100,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_100, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 100,"amdgpu_cdna2"); -DEF_REGISTER(vgpr101, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 101,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_101, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 101,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_101, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 101,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_101, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 101,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_101, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 101,"amdgpu_cdna2"); -DEF_REGISTER(vgpr102, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 102,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_102, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_102, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 102,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_102, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 102,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_102, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 102,"amdgpu_cdna2"); -DEF_REGISTER(vgpr103, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_103, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_103, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_103, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_103, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 103,"amdgpu_cdna2"); -DEF_REGISTER(vgpr104, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 104,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_104, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 104,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_104, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 104,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_104, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 104,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_104, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 104,"amdgpu_cdna2"); -DEF_REGISTER(vgpr105, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 105,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_105, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 105,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_105, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 105,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_105, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 105,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_105, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 105,"amdgpu_cdna2"); -DEF_REGISTER(vgpr106, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 106,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_106, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 106,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_106, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 106,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_106, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 106,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_106, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 106,"amdgpu_cdna2"); -DEF_REGISTER(vgpr107, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 107,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_107, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 107,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_107, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 107,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_107, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 107,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_107, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 107,"amdgpu_cdna2"); -DEF_REGISTER(vgpr108, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 108,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_108, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 108,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_108, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 108,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_108, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 108,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_108, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 108,"amdgpu_cdna2"); -DEF_REGISTER(vgpr109, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 109,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_109, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 109,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_109, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 109,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_109, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 109,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_109, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 109,"amdgpu_cdna2"); -DEF_REGISTER(vgpr110, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 110,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_110, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 110,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_110, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 110,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_110, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 110,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_110, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 110,"amdgpu_cdna2"); -DEF_REGISTER(vgpr111, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 111,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_111, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 111,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_111, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 111,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_111, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 111,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_111, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 111,"amdgpu_cdna2"); -DEF_REGISTER(vgpr112, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 112,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_112, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 112,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_112, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 112,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_112, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 112,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_112, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 112,"amdgpu_cdna2"); -DEF_REGISTER(vgpr113, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 113,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_113, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 113,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_113, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 113,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_113, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 113,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_113, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 113,"amdgpu_cdna2"); -DEF_REGISTER(vgpr114, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 114,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_114, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 114,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_114, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 114,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_114, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 114,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_114, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 114,"amdgpu_cdna2"); -DEF_REGISTER(vgpr115, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 115,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_115, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 115,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_115, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 115,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_115, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 115,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_115, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 115,"amdgpu_cdna2"); -DEF_REGISTER(vgpr116, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 116,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_116, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 116,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_116, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 116,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_116, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 116,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_116, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 116,"amdgpu_cdna2"); -DEF_REGISTER(vgpr117, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 117,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_117, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 117,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_117, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 117,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_117, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 117,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_117, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 117,"amdgpu_cdna2"); -DEF_REGISTER(vgpr118, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 118,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_118, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 118,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_118, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 118,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_118, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 118,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_118, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 118,"amdgpu_cdna2"); -DEF_REGISTER(vgpr119, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 119,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_119, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 119,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_119, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 119,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_119, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 119,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_119, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 119,"amdgpu_cdna2"); -DEF_REGISTER(vgpr120, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 120,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_120, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 120,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_120, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 120,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_120, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 120,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_120, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 120,"amdgpu_cdna2"); -DEF_REGISTER(vgpr121, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 121,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_121, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 121,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_121, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 121,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_121, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 121,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_121, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 121,"amdgpu_cdna2"); -DEF_REGISTER(vgpr122, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 122,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_122, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 122,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_122, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 122,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_122, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 122,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_122, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 122,"amdgpu_cdna2"); -DEF_REGISTER(vgpr123, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 123,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_123, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 123,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_123, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 123,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_123, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 123,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_123, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 123,"amdgpu_cdna2"); -DEF_REGISTER(vgpr124, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 124,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_124, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 124,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_124, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 124,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_124, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 124,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_124, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 124,"amdgpu_cdna2"); -DEF_REGISTER(vgpr125, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 125,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_125, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 125,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_125, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 125,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_125, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 125,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_125, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 125,"amdgpu_cdna2"); -DEF_REGISTER(vgpr126, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 126,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_126, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 126,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_126, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 126,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_126, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 126,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_126, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 126,"amdgpu_cdna2"); -DEF_REGISTER(vgpr127, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 127,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_127, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 127,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_127, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 127,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_127, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 127,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_127, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 127,"amdgpu_cdna2"); -DEF_REGISTER(vgpr128, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 128,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_128, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 128,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_128, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 128,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_128, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 128,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_128, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 128,"amdgpu_cdna2"); -DEF_REGISTER(vgpr129, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 129,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_129, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 129,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_129, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 129,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_129, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 129,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_129, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 129,"amdgpu_cdna2"); -DEF_REGISTER(vgpr130, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 130,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_130, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 130,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_130, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 130,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_130, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 130,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_130, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 130,"amdgpu_cdna2"); -DEF_REGISTER(vgpr131, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 131,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_131, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 131,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_131, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 131,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_131, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 131,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_131, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 131,"amdgpu_cdna2"); -DEF_REGISTER(vgpr132, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 132,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_132, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 132,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_132, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 132,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_132, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 132,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_132, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 132,"amdgpu_cdna2"); -DEF_REGISTER(vgpr133, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 133,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_133, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 133,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_133, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 133,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_133, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 133,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_133, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 133,"amdgpu_cdna2"); -DEF_REGISTER(vgpr134, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 134,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_134, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 134,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_134, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 134,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_134, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 134,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_134, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 134,"amdgpu_cdna2"); -DEF_REGISTER(vgpr135, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 135,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_135, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 135,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_135, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 135,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_135, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 135,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_135, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 135,"amdgpu_cdna2"); -DEF_REGISTER(vgpr136, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 136,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_136, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 136,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_136, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 136,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_136, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 136,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_136, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 136,"amdgpu_cdna2"); -DEF_REGISTER(vgpr137, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 137,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_137, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 137,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_137, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 137,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_137, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 137,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_137, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 137,"amdgpu_cdna2"); -DEF_REGISTER(vgpr138, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 138,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_138, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 138,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_138, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 138,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_138, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 138,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_138, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 138,"amdgpu_cdna2"); -DEF_REGISTER(vgpr139, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 139,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_139, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 139,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_139, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 139,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_139, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 139,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_139, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 139,"amdgpu_cdna2"); -DEF_REGISTER(vgpr140, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 140,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_140, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 140,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_140, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 140,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_140, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 140,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_140, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 140,"amdgpu_cdna2"); -DEF_REGISTER(vgpr141, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 141,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_141, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 141,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_141, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 141,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_141, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 141,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_141, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 141,"amdgpu_cdna2"); -DEF_REGISTER(vgpr142, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 142,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_142, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 142,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_142, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 142,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_142, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 142,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_142, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 142,"amdgpu_cdna2"); -DEF_REGISTER(vgpr143, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 143,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_143, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 143,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_143, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 143,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_143, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 143,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_143, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 143,"amdgpu_cdna2"); -DEF_REGISTER(vgpr144, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 144,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_144, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 144,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_144, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 144,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_144, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 144,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_144, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 144,"amdgpu_cdna2"); -DEF_REGISTER(vgpr145, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 145,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_145, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 145,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_145, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 145,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_145, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 145,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_145, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 145,"amdgpu_cdna2"); -DEF_REGISTER(vgpr146, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 146,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_146, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 146,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_146, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 146,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_146, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 146,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_146, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 146,"amdgpu_cdna2"); -DEF_REGISTER(vgpr147, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 147,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_147, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 147,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_147, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 147,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_147, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 147,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_147, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 147,"amdgpu_cdna2"); -DEF_REGISTER(vgpr148, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 148,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_148, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 148,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_148, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 148,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_148, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 148,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_148, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 148,"amdgpu_cdna2"); -DEF_REGISTER(vgpr149, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 149,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_149, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 149,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_149, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 149,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_149, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 149,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_149, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 149,"amdgpu_cdna2"); -DEF_REGISTER(vgpr150, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 150,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_150, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 150,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_150, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 150,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_150, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 150,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_150, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 150,"amdgpu_cdna2"); -DEF_REGISTER(vgpr151, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 151,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_151, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 151,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_151, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 151,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_151, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 151,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_151, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 151,"amdgpu_cdna2"); -DEF_REGISTER(vgpr152, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 152,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_152, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 152,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_152, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 152,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_152, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 152,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_152, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 152,"amdgpu_cdna2"); -DEF_REGISTER(vgpr153, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 153,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_153, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 153,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_153, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 153,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_153, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 153,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_153, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 153,"amdgpu_cdna2"); -DEF_REGISTER(vgpr154, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 154,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_154, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 154,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_154, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 154,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_154, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 154,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_154, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 154,"amdgpu_cdna2"); -DEF_REGISTER(vgpr155, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 155,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_155, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 155,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_155, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 155,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_155, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 155,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_155, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 155,"amdgpu_cdna2"); -DEF_REGISTER(vgpr156, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 156,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_156, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 156,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_156, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 156,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_156, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 156,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_156, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 156,"amdgpu_cdna2"); -DEF_REGISTER(vgpr157, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 157,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_157, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 157,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_157, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 157,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_157, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 157,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_157, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 157,"amdgpu_cdna2"); -DEF_REGISTER(vgpr158, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 158,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_158, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 158,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_158, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 158,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_158, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 158,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_158, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 158,"amdgpu_cdna2"); -DEF_REGISTER(vgpr159, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 159,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_159, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 159,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_159, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 159,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_159, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 159,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_159, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 159,"amdgpu_cdna2"); -DEF_REGISTER(vgpr160, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 160,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_160, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 160,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_160, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 160,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_160, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 160,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_160, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 160,"amdgpu_cdna2"); -DEF_REGISTER(vgpr161, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 161,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_161, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 161,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_161, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 161,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_161, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 161,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_161, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 161,"amdgpu_cdna2"); -DEF_REGISTER(vgpr162, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 162,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_162, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 162,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_162, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 162,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_162, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 162,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_162, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 162,"amdgpu_cdna2"); -DEF_REGISTER(vgpr163, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 163,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_163, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 163,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_163, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 163,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_163, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 163,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_163, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 163,"amdgpu_cdna2"); -DEF_REGISTER(vgpr164, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 164,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_164, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 164,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_164, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 164,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_164, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 164,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_164, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 164,"amdgpu_cdna2"); -DEF_REGISTER(vgpr165, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 165,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_165, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 165,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_165, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 165,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_165, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 165,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_165, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 165,"amdgpu_cdna2"); -DEF_REGISTER(vgpr166, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 166,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_166, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 166,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_166, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 166,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_166, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 166,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_166, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 166,"amdgpu_cdna2"); -DEF_REGISTER(vgpr167, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 167,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_167, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 167,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_167, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 167,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_167, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 167,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_167, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 167,"amdgpu_cdna2"); -DEF_REGISTER(vgpr168, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 168,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_168, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 168,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_168, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 168,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_168, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 168,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_168, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 168,"amdgpu_cdna2"); -DEF_REGISTER(vgpr169, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 169,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_169, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 169,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_169, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 169,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_169, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 169,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_169, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 169,"amdgpu_cdna2"); -DEF_REGISTER(vgpr170, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 170,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_170, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 170,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_170, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 170,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_170, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 170,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_170, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 170,"amdgpu_cdna2"); -DEF_REGISTER(vgpr171, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 171,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_171, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 171,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_171, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 171,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_171, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 171,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_171, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 171,"amdgpu_cdna2"); -DEF_REGISTER(vgpr172, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 172,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_172, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 172,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_172, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 172,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_172, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 172,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_172, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 172,"amdgpu_cdna2"); -DEF_REGISTER(vgpr173, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 173,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_173, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 173,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_173, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 173,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_173, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 173,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_173, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 173,"amdgpu_cdna2"); -DEF_REGISTER(vgpr174, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 174,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_174, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 174,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_174, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 174,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_174, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 174,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_174, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 174,"amdgpu_cdna2"); -DEF_REGISTER(vgpr175, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 175,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_175, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 175,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_175, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 175,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_175, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 175,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_175, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 175,"amdgpu_cdna2"); -DEF_REGISTER(vgpr176, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 176,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_176, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 176,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_176, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 176,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_176, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 176,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_176, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 176,"amdgpu_cdna2"); -DEF_REGISTER(vgpr177, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 177,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_177, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 177,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_177, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 177,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_177, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 177,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_177, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 177,"amdgpu_cdna2"); -DEF_REGISTER(vgpr178, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 178,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_178, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 178,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_178, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 178,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_178, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 178,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_178, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 178,"amdgpu_cdna2"); -DEF_REGISTER(vgpr179, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 179,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_179, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 179,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_179, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 179,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_179, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 179,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_179, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 179,"amdgpu_cdna2"); -DEF_REGISTER(vgpr180, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 180,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_180, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 180,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_180, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 180,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_180, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 180,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_180, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 180,"amdgpu_cdna2"); -DEF_REGISTER(vgpr181, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 181,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_181, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 181,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_181, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 181,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_181, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 181,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_181, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 181,"amdgpu_cdna2"); -DEF_REGISTER(vgpr182, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 182,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_182, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 182,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_182, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 182,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_182, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 182,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_182, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 182,"amdgpu_cdna2"); -DEF_REGISTER(vgpr183, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 183,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_183, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 183,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_183, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 183,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_183, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 183,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_183, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 183,"amdgpu_cdna2"); -DEF_REGISTER(vgpr184, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 184,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_184, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 184,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_184, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 184,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_184, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 184,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_184, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 184,"amdgpu_cdna2"); -DEF_REGISTER(vgpr185, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 185,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_185, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 185,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_185, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 185,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_185, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 185,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_185, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 185,"amdgpu_cdna2"); -DEF_REGISTER(vgpr186, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 186,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_186, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 186,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_186, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 186,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_186, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 186,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_186, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 186,"amdgpu_cdna2"); -DEF_REGISTER(vgpr187, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 187,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_187, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 187,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_187, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 187,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_187, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 187,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_187, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 187,"amdgpu_cdna2"); -DEF_REGISTER(vgpr188, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 188,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_188, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 188,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_188, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 188,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_188, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 188,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_188, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 188,"amdgpu_cdna2"); -DEF_REGISTER(vgpr189, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 189,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_189, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 189,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_189, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 189,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_189, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 189,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_189, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 189,"amdgpu_cdna2"); -DEF_REGISTER(vgpr190, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 190,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_190, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 190,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_190, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 190,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_190, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 190,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_190, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 190,"amdgpu_cdna2"); -DEF_REGISTER(vgpr191, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 191,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_191, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 191,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_191, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 191,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_191, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 191,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_191, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 191,"amdgpu_cdna2"); -DEF_REGISTER(vgpr192, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 192,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_192, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 192,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_192, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 192,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_192, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 192,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_192, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 192,"amdgpu_cdna2"); -DEF_REGISTER(vgpr193, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 193,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_193, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 193,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_193, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 193,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_193, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 193,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_193, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 193,"amdgpu_cdna2"); -DEF_REGISTER(vgpr194, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 194,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_194, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 194,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_194, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 194,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_194, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 194,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_194, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 194,"amdgpu_cdna2"); -DEF_REGISTER(vgpr195, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 195,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_195, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 195,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_195, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 195,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_195, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 195,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_195, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 195,"amdgpu_cdna2"); -DEF_REGISTER(vgpr196, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 196,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_196, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 196,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_196, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 196,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_196, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 196,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_196, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 196,"amdgpu_cdna2"); -DEF_REGISTER(vgpr197, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 197,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_197, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 197,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_197, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 197,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_197, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 197,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_197, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 197,"amdgpu_cdna2"); -DEF_REGISTER(vgpr198, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 198,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_198, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 198,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_198, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 198,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_198, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 198,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_198, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 198,"amdgpu_cdna2"); -DEF_REGISTER(vgpr199, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 199,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_199, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 199,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_199, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 199,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_199, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 199,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_199, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 199,"amdgpu_cdna2"); -DEF_REGISTER(vgpr200, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 200,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_200, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 200,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_200, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 200,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_200, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 200,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_200, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 200,"amdgpu_cdna2"); -DEF_REGISTER(vgpr201, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 201,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_201, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 201,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_201, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 201,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_201, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 201,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_201, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 201,"amdgpu_cdna2"); -DEF_REGISTER(vgpr202, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 202,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_202, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 202,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_202, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 202,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_202, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 202,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_202, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 202,"amdgpu_cdna2"); -DEF_REGISTER(vgpr203, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 203,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_203, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 203,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_203, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 203,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_203, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 203,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_203, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 203,"amdgpu_cdna2"); -DEF_REGISTER(vgpr204, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 204,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_204, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 204,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_204, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 204,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_204, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 204,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_204, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 204,"amdgpu_cdna2"); -DEF_REGISTER(vgpr205, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 205,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_205, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 205,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_205, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 205,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_205, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 205,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_205, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 205,"amdgpu_cdna2"); -DEF_REGISTER(vgpr206, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 206,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_206, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 206,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_206, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 206,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_206, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 206,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_206, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 206,"amdgpu_cdna2"); -DEF_REGISTER(vgpr207, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 207,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_207, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 207,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_207, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 207,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_207, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 207,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_207, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 207,"amdgpu_cdna2"); -DEF_REGISTER(vgpr208, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 208,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_208, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 208,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_208, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 208,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_208, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 208,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_208, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 208,"amdgpu_cdna2"); -DEF_REGISTER(vgpr209, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 209,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_209, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 209,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_209, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 209,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_209, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 209,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_209, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 209,"amdgpu_cdna2"); -DEF_REGISTER(vgpr210, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 210,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_210, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 210,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_210, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 210,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_210, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 210,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_210, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 210,"amdgpu_cdna2"); -DEF_REGISTER(vgpr211, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 211,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_211, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 211,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_211, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 211,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_211, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 211,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_211, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 211,"amdgpu_cdna2"); -DEF_REGISTER(vgpr212, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 212,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_212, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 212,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_212, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 212,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_212, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 212,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_212, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 212,"amdgpu_cdna2"); -DEF_REGISTER(vgpr213, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 213,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_213, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 213,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_213, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 213,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_213, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 213,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_213, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 213,"amdgpu_cdna2"); -DEF_REGISTER(vgpr214, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 214,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_214, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 214,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_214, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 214,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_214, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 214,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_214, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 214,"amdgpu_cdna2"); -DEF_REGISTER(vgpr215, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 215,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_215, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 215,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_215, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 215,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_215, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 215,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_215, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 215,"amdgpu_cdna2"); -DEF_REGISTER(vgpr216, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 216,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_216, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 216,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_216, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 216,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_216, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 216,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_216, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 216,"amdgpu_cdna2"); -DEF_REGISTER(vgpr217, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 217,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_217, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 217,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_217, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 217,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_217, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 217,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_217, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 217,"amdgpu_cdna2"); -DEF_REGISTER(vgpr218, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 218,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_218, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 218,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_218, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 218,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_218, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 218,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_218, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 218,"amdgpu_cdna2"); -DEF_REGISTER(vgpr219, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 219,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_219, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 219,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_219, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 219,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_219, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 219,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_219, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 219,"amdgpu_cdna2"); -DEF_REGISTER(vgpr220, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 220,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_220, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 220,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_220, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 220,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_220, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 220,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_220, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 220,"amdgpu_cdna2"); -DEF_REGISTER(vgpr221, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 221,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_221, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 221,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_221, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 221,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_221, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 221,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_221, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 221,"amdgpu_cdna2"); -DEF_REGISTER(vgpr222, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 222,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_222, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 222,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_222, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 222,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_222, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 222,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_222, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 222,"amdgpu_cdna2"); -DEF_REGISTER(vgpr223, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 223,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_223, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 223,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_223, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 223,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_223, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 223,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_223, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 223,"amdgpu_cdna2"); -DEF_REGISTER(vgpr224, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 224,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_224, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 224,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_224, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 224,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_224, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 224,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_224, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 224,"amdgpu_cdna2"); -DEF_REGISTER(vgpr225, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 225,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_225, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 225,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_225, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 225,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_225, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 225,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_225, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 225,"amdgpu_cdna2"); -DEF_REGISTER(vgpr226, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 226,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_226, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 226,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_226, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 226,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_226, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 226,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_226, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 226,"amdgpu_cdna2"); -DEF_REGISTER(vgpr227, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 227,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_227, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 227,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_227, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 227,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_227, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 227,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_227, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 227,"amdgpu_cdna2"); -DEF_REGISTER(vgpr228, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 228,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_228, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 228,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_228, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 228,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_228, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 228,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_228, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 228,"amdgpu_cdna2"); -DEF_REGISTER(vgpr229, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 229,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_229, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 229,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_229, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 229,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_229, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 229,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_229, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 229,"amdgpu_cdna2"); -DEF_REGISTER(vgpr230, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 230,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_230, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 230,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_230, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 230,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_230, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 230,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_230, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 230,"amdgpu_cdna2"); -DEF_REGISTER(vgpr231, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 231,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_231, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 231,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_231, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 231,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_231, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 231,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_231, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 231,"amdgpu_cdna2"); -DEF_REGISTER(vgpr232, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 232,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_232, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 232,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_232, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 232,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_232, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 232,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_232, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 232,"amdgpu_cdna2"); -DEF_REGISTER(vgpr233, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 233,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_233, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 233,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_233, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 233,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_233, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 233,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_233, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 233,"amdgpu_cdna2"); -DEF_REGISTER(vgpr234, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 234,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_234, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 234,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_234, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 234,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_234, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 234,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_234, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 234,"amdgpu_cdna2"); -DEF_REGISTER(vgpr235, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 235,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_235, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 235,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_235, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 235,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_235, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 235,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_235, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 235,"amdgpu_cdna2"); -DEF_REGISTER(vgpr236, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 236,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_236, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 236,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_236, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 236,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_236, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 236,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_236, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 236,"amdgpu_cdna2"); -DEF_REGISTER(vgpr237, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 237,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_237, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 237,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_237, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 237,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_237, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 237,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_237, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 237,"amdgpu_cdna2"); -DEF_REGISTER(vgpr238, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 238,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_238, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 238,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_238, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 238,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_238, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 238,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_238, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 238,"amdgpu_cdna2"); -DEF_REGISTER(vgpr239, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 239,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_239, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 239,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_239, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 239,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_239, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 239,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_239, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 239,"amdgpu_cdna2"); -DEF_REGISTER(vgpr240, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 240,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_240, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 240,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_240, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 240,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_240, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 240,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec16_240, Arch_amdgpu_cdna2 | VGPR_VEC16 | BITS_512 | 240,"amdgpu_cdna2"); -DEF_REGISTER(vgpr241, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 241,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_241, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 241,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_241, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 241,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_241, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 241,"amdgpu_cdna2"); -DEF_REGISTER(vgpr242, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 242,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_242, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 242,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_242, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 242,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_242, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 242,"amdgpu_cdna2"); -DEF_REGISTER(vgpr243, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 243,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_243, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 243,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_243, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 243,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_243, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 243,"amdgpu_cdna2"); -DEF_REGISTER(vgpr244, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 244,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_244, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 244,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_244, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 244,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_244, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 244,"amdgpu_cdna2"); -DEF_REGISTER(vgpr245, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 245,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_245, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 245,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_245, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 245,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_245, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 245,"amdgpu_cdna2"); -DEF_REGISTER(vgpr246, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 246,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_246, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 246,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_246, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 246,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_246, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 246,"amdgpu_cdna2"); -DEF_REGISTER(vgpr247, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 247,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_247, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 247,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_247, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 247,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_247, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 247,"amdgpu_cdna2"); -DEF_REGISTER(vgpr248, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 248,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_248, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 248,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_248, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 248,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec8_248, Arch_amdgpu_cdna2 | VGPR_VEC8 | BITS_256 | 248,"amdgpu_cdna2"); -DEF_REGISTER(vgpr249, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 249,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_249, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 249,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_249, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 249,"amdgpu_cdna2"); -DEF_REGISTER(vgpr250, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 250,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_250, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 250,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_250, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 250,"amdgpu_cdna2"); -DEF_REGISTER(vgpr251, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 251,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_251, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 251,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_251, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 251,"amdgpu_cdna2"); -DEF_REGISTER(vgpr252, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 252,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_252, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 252,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec4_252, Arch_amdgpu_cdna2 | VGPR_VEC4 | BITS_128 | 252,"amdgpu_cdna2"); -DEF_REGISTER(vgpr253, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 253,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_253, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 253,"amdgpu_cdna2"); -DEF_REGISTER(vgpr254, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 254,"amdgpu_cdna2"); -DEF_REGISTER(vgpr_vec2_254, Arch_amdgpu_cdna2 | VGPR_VEC2 | BITS_64 | 254,"amdgpu_cdna2"); -DEF_REGISTER(vgpr255, Arch_amdgpu_cdna2 | VGPR | BITS_32 | 255,"amdgpu_cdna2"); -#endif //DYNINST_AMDGPU_CDNA2_SYS_REGS_H diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index f812f84045..da6d489c55 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -3009,7 +3009,7 @@ power_op_dxex, amdgpu_op_sop1_nop, #include "amdgpu_op_table.h" #include "amdgpu_cdna_op_table.h" -#include "amdgpu_cdna2_op_table.h" +#include "AMDGPU/cdna2/amdgpu_cdna2_op_table.h" cuda_op_general, cuda_op_call, intel_gpu_op_general, From b5facb8f2a4f29d6fdedbcc11553c0844d33710c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 24 Feb 2022 16:50:38 -0600 Subject: [PATCH 078/505] Fix compiler warnings in amdgpu cdna2 code (#1198) * Fix 'unused-variable' warnings from gcc * Fix 'unused-parameter' warnings from gcc --- common/src/dyn_regs.C | 10 +--------- .../src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C | 2 +- instructionAPI/src/AMDGPU/cdna2/decodeOperands.C | 8 ++++---- instructionAPI/src/Register.C | 3 +-- 4 files changed, 7 insertions(+), 16 deletions(-) diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index 9ecddaa534..7cfd5aa0d4 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -218,15 +218,7 @@ std::string MachRegister::name() const { } return ret; }else if(getArchitecture() == Arch_amdgpu_cdna2){ - signed int category = reg & 0x00ff0000; - signed int base_val = reg & 0x000000ff; - switch(category){ - default: - ret = iter->second; - break; - } - return ret; - + return iter->second; }else{ return iter->second; } diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C index 46e999577e..ede1f86a04 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -91,7 +91,7 @@ namespace Dyninst { // decoding opcodes // **************** - MachRegister InstructionDecoder_amdgpu_cdna2::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int len) { + MachRegister InstructionDecoder_amdgpu_cdna2::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { MachRegister realBase = base; /*if (base == amdgpu_cdna2::s0){ switch(len){ diff --git a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C index d170f06d0c..a27ced6083 100644 --- a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C @@ -318,7 +318,7 @@ case 2 : return makeRegisterExpression(amdgpu_cdna2::p0,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input,uint32_t){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::pc_all); default: return makeRegisterExpression(amdgpu_cdna2::invalid); @@ -4785,7 +4785,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -4854,7 +4854,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -5587,7 +5587,7 @@ case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input,uint32_t){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::vcc); default: return makeRegisterExpression(amdgpu_cdna2::invalid); diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index f5b612fef0..beaea43b0a 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -101,8 +101,7 @@ namespace Dyninst { std::string name = m_Reg.name(); std::string::size_type substr = name.rfind("::"); - Architecture arch = m_Reg.getArchitecture(); - if(/*arch != Arch_amdgpu_vega && arch != Arch_amdgpu_cdna2 && */substr != std::string::npos) + if(substr != std::string::npos) { name = name.substr(substr + 2, name.length()); } From 1c8a880e0b49ff4db1f44d3920903805fd77548a Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 25 Feb 2022 13:47:22 -0600 Subject: [PATCH 079/505] Tidy up classes in AMDGPU (#1204) * Remove dead code in makeAmdgpuRegID * Fix possible no-return cdna2 functions * Simplify code in bitfieldInsnAliasMap and condInsnAliasMap * Correctly initialize all members of InstructionDecoder_amdgpu_cdna2 * Inline InstructionDecoder_amdgpu_cdna2 constructor * Explicitly default ~InstructionDecoder_amdgpu_cdna2 * Fix possible non-return in decodeSGPRorM0 --- .../cdna2/InstructionDecoder-amdgpu-cdna2.C | 61 +++-------------- .../cdna2/InstructionDecoder-amdgpu-cdna2.h | 66 +++++++++---------- .../AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h | 2 +- 3 files changed, 42 insertions(+), 87 deletions(-) diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C index ede1f86a04..27b70c7eae 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -43,15 +43,13 @@ namespace Dyninst { "lt", "gt", "le", "al", "nv", } }; - const char* InstructionDecoder_amdgpu_cdna2::bitfieldInsnAliasMap(entryID e) { - switch(e) { - default: assert(!"no alias for entryID"); - }; + const char* InstructionDecoder_amdgpu_cdna2::bitfieldInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; } - const char* InstructionDecoder_amdgpu_cdna2::condInsnAliasMap(entryID e) { - switch(e) { - default: assert(!"no alias for entryID"); - }; + const char* InstructionDecoder_amdgpu_cdna2::condInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; } #include "amdgpu_cdna2_insn_entry.h" @@ -67,17 +65,6 @@ namespace Dyninst { #include "amdgpu_cdna2_opcode_tables.C" - InstructionDecoder_amdgpu_cdna2::InstructionDecoder_amdgpu_cdna2(Architecture a) - : InstructionDecoderImpl(a), - insn_size(0), immLen(0) , num_elements(1) , isSMEM(false), isLoad(false), isStore(false),isBuffer(false), - isScratch(false) , isBranch(false), isConditional(false) ,isCall(false), isModifyPC(false) - { - } - - InstructionDecoder_amdgpu_cdna2::~InstructionDecoder_amdgpu_cdna2() { - } - - using namespace std; void InstructionDecoder_amdgpu_cdna2::NOTHING() { } @@ -92,40 +79,7 @@ namespace Dyninst { // **************** MachRegister InstructionDecoder_amdgpu_cdna2::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { - MachRegister realBase = base; - /*if (base == amdgpu_cdna2::s0){ - switch(len){ - case 2: - realBase = amdgpu_cdna2::sgpr_vec2_0; - break; - case 4: - realBase = amdgpu_cdna2::sgpr_vec4_0; - break; - case 8: - realBase = amdgpu_cdna2::sgpr_vec8_0; - break; - case 16: - realBase = amdgpu_cdna2::sgpr_vec16_0; - break; - } - }else if (base == amdgpu_cdna2::v0){ - switch(len){ - case 2: - realBase = amdgpu_cdna2::vgpr_vec2_0; - break; - case 4: - realBase = amdgpu_cdna2::vgpr_vec4_0; - break; - case 8: - realBase = amdgpu_cdna2::vgpr_vec8_0; - break; - case 16: - realBase = amdgpu_cdna2::vgpr_vec16_0; - break; - } - - }*/ - return MachRegister(realBase.val() + encoding); + return MachRegister(base.val() + encoding); } @@ -167,6 +121,7 @@ namespace Dyninst { return makeRegisterExpression(amdgpu_cdna2::m0); cerr << " unknown offset in sgpr or m0 " << offset << endl; assert(0 && "shouldn't reach here"); + return {}; } diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h index 7acd5e0a2b..d35482ffad 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h @@ -50,9 +50,9 @@ namespace Dyninst { enum DecodeFamily {sopp}; public: - InstructionDecoder_amdgpu_cdna2(Architecture a); + InstructionDecoder_amdgpu_cdna2(Architecture a) : InstructionDecoderImpl(a) {} - virtual ~InstructionDecoder_amdgpu_cdna2(); + virtual ~InstructionDecoder_amdgpu_cdna2() = default; virtual void decodeOpcode(InstructionDecoder::buffer &b); @@ -78,12 +78,12 @@ namespace Dyninst { private: virtual Result_Type makeSizeType(unsigned int opType); - bool is64Bit; + bool is64Bit{}; - unsigned int insn_size; // size of the instruction that we are currently working on - unsigned int insn; // the first 32 bit - unsigned int insn_high; // the second 32 bit - unsigned long long int insn_long; // the combined 64 bit: insn_high << 32 | insn + unsigned int insn_size{}; // size of the instruction that we are currently working on + unsigned int insn{}; // the first 32 bit + unsigned int insn_high{}; // the second 32 bit + unsigned long long int insn_long{}; // the combined 64 bit: insn_high << 32 | insn // the main process of decoding an instruciton, won't advance buffer void mainDecode(); @@ -154,23 +154,23 @@ namespace Dyninst { } - bool hasHw; - int hwField; + bool hasHw{}; + int hwField{}; void processHwFieldInsn(int, int); - bool hasShift; - int shiftField; + bool hasShift{}; + int shiftField{}; void makeBranchTarget(bool, bool, int, int); Expression::Ptr makeFallThroughExpr(); - int _szField, size; - int _typeField; - int cmode; - int op; - int simdAlphabetImm; + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; void processAlphabetImm(); @@ -200,33 +200,33 @@ namespace Dyninst { Expression::Ptr decodeSGPRorM0(unsigned int offset); - bool useImm; - uint32_t immLen; - uint32_t immLiteral; - uint32_t imm_at_32; - uint32_t imm_at_64; - uint32_t imm_at_96; + bool useImm{}; + uint32_t immLen{}; + uint32_t immLiteral{}; + uint32_t imm_at_32{}; + uint32_t imm_at_64{}; + uint32_t imm_at_96{}; - bool setSCC; + bool setSCC{}; #define IS_LD_ST() (isLoad || isStore ) - unsigned int num_elements ; // the number of elements that will be load or store by each instruction - bool isSMEM; // this is set when using smem instruction - bool isLoad; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time - bool isStore; // similar to isLoad, but for store instructions - bool isBuffer; // - bool isScratch; + unsigned int num_elements{1}; // the number of elements that will be load or store by each instruction + bool isSMEM{}; // this is set when using smem instruction + bool isLoad{}; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time + bool isStore{}; // similar to isLoad, but for store instructions + bool isBuffer{}; // + bool isScratch{}; - bool isBranch; // this is set for all branch instructions, - bool isConditional; // this is set for all conditional branch instruction, will set branchCond - bool isCall; // this is a call function + bool isBranch{}; // this is set for all branch instructions, + bool isConditional{}; // this is set for all conditional branch instruction, will set branchCond + bool isCall{}; // this is a call function // this is set for instructions that directly modify pc // namely s_setpc and s_swappc - bool isModifyPC; + bool isModifyPC{}; // reset the decoder internal state for decoding the next instruction void reset(); diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h index aad5a985a4..44327b6834 100644 --- a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h @@ -44,7 +44,7 @@ enum InstructionFamily{ ENC_VOP3B = 20, ENC_VOP3P_MFMA = 21, }; -InstructionFamily instr_family; +InstructionFamily instr_family{}; typedef void (InstructionDecoder_amdgpu_cdna2::*func_ptr)(void); func_ptr decode_lookup_table [22] = { (&InstructionDecoder_amdgpu_cdna2::decodeENC_SOP1), From 4655b907f0dee6ad1062543ade0489e157ccdc58 Mon Sep 17 00:00:00 2001 From: bbiiggppiigg Date: Fri, 25 Feb 2022 22:39:49 +0000 Subject: [PATCH 080/505] Code clean up for AMDGPU (#1205) * Update the code layout for vega headers * Remove unused cda headers * remove duplicate cdna2 headers in instructionAPI --- .../vega/amdgpu_vega_op_table.h} | 0 .../{ => AMDGPU/vega}/amdgpu_vega_sys_regs.h | 0 common/h/amdgpu_cdna_op_table.h | 1152 ------------ common/h/amdgpu_cdna_sys_regs.h | 1563 ----------------- common/h/dyn_regs.h | 2 +- common/h/entryIDs.h | 3 +- .../src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h | 1135 ------------ .../src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h | 617 ------- 8 files changed, 2 insertions(+), 4470 deletions(-) rename common/h/{amdgpu_op_table.h => AMDGPU/vega/amdgpu_vega_op_table.h} (100%) rename common/h/{ => AMDGPU/vega}/amdgpu_vega_sys_regs.h (100%) delete mode 100644 common/h/amdgpu_cdna_op_table.h delete mode 100644 common/h/amdgpu_cdna_sys_regs.h delete mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h delete mode 100644 instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h diff --git a/common/h/amdgpu_op_table.h b/common/h/AMDGPU/vega/amdgpu_vega_op_table.h similarity index 100% rename from common/h/amdgpu_op_table.h rename to common/h/AMDGPU/vega/amdgpu_vega_op_table.h diff --git a/common/h/amdgpu_vega_sys_regs.h b/common/h/AMDGPU/vega/amdgpu_vega_sys_regs.h similarity index 100% rename from common/h/amdgpu_vega_sys_regs.h rename to common/h/AMDGPU/vega/amdgpu_vega_sys_regs.h diff --git a/common/h/amdgpu_cdna_op_table.h b/common/h/amdgpu_cdna_op_table.h deleted file mode 100644 index e27bcc8ff2..0000000000 --- a/common/h/amdgpu_cdna_op_table.h +++ /dev/null @@ -1,1152 +0,0 @@ -amdgpu_cdna_op_BUFFER_ATOMIC_ADD, -amdgpu_cdna_op_BUFFER_ATOMIC_ADD_F32, -amdgpu_cdna_op_BUFFER_ATOMIC_ADD_F64, -amdgpu_cdna_op_BUFFER_ATOMIC_ADD_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_AND, -amdgpu_cdna_op_BUFFER_ATOMIC_AND_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_CMPSWAP, -amdgpu_cdna_op_BUFFER_ATOMIC_CMPSWAP_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_DEC, -amdgpu_cdna_op_BUFFER_ATOMIC_DEC_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_INC, -amdgpu_cdna_op_BUFFER_ATOMIC_INC_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_MAX_F64, -amdgpu_cdna_op_BUFFER_ATOMIC_MIN_F64, -amdgpu_cdna_op_BUFFER_ATOMIC_OR, -amdgpu_cdna_op_BUFFER_ATOMIC_OR_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_PK_ADD_F16, -amdgpu_cdna_op_BUFFER_ATOMIC_SMAX, -amdgpu_cdna_op_BUFFER_ATOMIC_SMAX_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_SMIN, -amdgpu_cdna_op_BUFFER_ATOMIC_SMIN_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_SUB, -amdgpu_cdna_op_BUFFER_ATOMIC_SUB_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_SWAP, -amdgpu_cdna_op_BUFFER_ATOMIC_SWAP_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_UMAX, -amdgpu_cdna_op_BUFFER_ATOMIC_UMAX_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_UMIN, -amdgpu_cdna_op_BUFFER_ATOMIC_UMIN_X2, -amdgpu_cdna_op_BUFFER_ATOMIC_XOR, -amdgpu_cdna_op_BUFFER_ATOMIC_XOR_X2, -amdgpu_cdna_op_BUFFER_INV, -amdgpu_cdna_op_BUFFER_LOAD_DWORD, -amdgpu_cdna_op_BUFFER_LOAD_DWORDX2, -amdgpu_cdna_op_BUFFER_LOAD_DWORDX3, -amdgpu_cdna_op_BUFFER_LOAD_DWORDX4, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_HI_X, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_X, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XY, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XYZ, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_D16_XYZW, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_X, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XY, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XYZ, -amdgpu_cdna_op_BUFFER_LOAD_FORMAT_XYZW, -amdgpu_cdna_op_BUFFER_LOAD_SBYTE, -amdgpu_cdna_op_BUFFER_LOAD_SBYTE_D16, -amdgpu_cdna_op_BUFFER_LOAD_SBYTE_D16_HI, -amdgpu_cdna_op_BUFFER_LOAD_SHORT_D16, -amdgpu_cdna_op_BUFFER_LOAD_SHORT_D16_HI, -amdgpu_cdna_op_BUFFER_LOAD_SSHORT, -amdgpu_cdna_op_BUFFER_LOAD_UBYTE, -amdgpu_cdna_op_BUFFER_LOAD_UBYTE_D16, -amdgpu_cdna_op_BUFFER_LOAD_UBYTE_D16_HI, -amdgpu_cdna_op_BUFFER_LOAD_USHORT, -amdgpu_cdna_op_BUFFER_STORE_BYTE, -amdgpu_cdna_op_BUFFER_STORE_BYTE_D16_HI, -amdgpu_cdna_op_BUFFER_STORE_DWORD, -amdgpu_cdna_op_BUFFER_STORE_DWORDX2, -amdgpu_cdna_op_BUFFER_STORE_DWORDX3, -amdgpu_cdna_op_BUFFER_STORE_DWORDX4, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_HI_X, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_X, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XY, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XYZ, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_D16_XYZW, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_X, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_XY, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_XYZ, -amdgpu_cdna_op_BUFFER_STORE_FORMAT_XYZW, -amdgpu_cdna_op_BUFFER_STORE_SHORT, -amdgpu_cdna_op_BUFFER_STORE_SHORT_D16_HI, -amdgpu_cdna_op_BUFFER_WBL2, -amdgpu_cdna_op_DS_ADD_F32, -amdgpu_cdna_op_DS_ADD_F64, -amdgpu_cdna_op_DS_ADD_RTN_F32, -amdgpu_cdna_op_DS_ADD_RTN_F64, -amdgpu_cdna_op_DS_ADD_RTN_U32, -amdgpu_cdna_op_DS_ADD_RTN_U64, -amdgpu_cdna_op_DS_ADD_U32, -amdgpu_cdna_op_DS_ADD_U64, -amdgpu_cdna_op_DS_AND_B32, -amdgpu_cdna_op_DS_AND_B64, -amdgpu_cdna_op_DS_AND_RTN_B32, -amdgpu_cdna_op_DS_AND_RTN_B64, -amdgpu_cdna_op_DS_APPEND, -amdgpu_cdna_op_DS_BPERMUTE_B32, -amdgpu_cdna_op_DS_CMPST_B32, -amdgpu_cdna_op_DS_CMPST_B64, -amdgpu_cdna_op_DS_CMPST_F32, -amdgpu_cdna_op_DS_CMPST_F64, -amdgpu_cdna_op_DS_CMPST_RTN_B32, -amdgpu_cdna_op_DS_CMPST_RTN_B64, -amdgpu_cdna_op_DS_CMPST_RTN_F32, -amdgpu_cdna_op_DS_CMPST_RTN_F64, -amdgpu_cdna_op_DS_CONDXCHG32_RTN_B64, -amdgpu_cdna_op_DS_CONSUME, -amdgpu_cdna_op_DS_DEC_RTN_U32, -amdgpu_cdna_op_DS_DEC_RTN_U64, -amdgpu_cdna_op_DS_DEC_U32, -amdgpu_cdna_op_DS_DEC_U64, -amdgpu_cdna_op_DS_GWS_BARRIER, -amdgpu_cdna_op_DS_GWS_INIT, -amdgpu_cdna_op_DS_GWS_SEMA_BR, -amdgpu_cdna_op_DS_GWS_SEMA_P, -amdgpu_cdna_op_DS_GWS_SEMA_RELEASE_ALL, -amdgpu_cdna_op_DS_GWS_SEMA_V, -amdgpu_cdna_op_DS_INC_RTN_U32, -amdgpu_cdna_op_DS_INC_RTN_U64, -amdgpu_cdna_op_DS_INC_U32, -amdgpu_cdna_op_DS_INC_U64, -amdgpu_cdna_op_DS_MAX_F32, -amdgpu_cdna_op_DS_MAX_F64, -amdgpu_cdna_op_DS_MAX_I32, -amdgpu_cdna_op_DS_MAX_I64, -amdgpu_cdna_op_DS_MAX_RTN_F32, -amdgpu_cdna_op_DS_MAX_RTN_F64, -amdgpu_cdna_op_DS_MAX_RTN_I32, -amdgpu_cdna_op_DS_MAX_RTN_I64, -amdgpu_cdna_op_DS_MAX_RTN_U32, -amdgpu_cdna_op_DS_MAX_RTN_U64, -amdgpu_cdna_op_DS_MAX_U32, -amdgpu_cdna_op_DS_MAX_U64, -amdgpu_cdna_op_DS_MIN_F32, -amdgpu_cdna_op_DS_MIN_F64, -amdgpu_cdna_op_DS_MIN_I32, -amdgpu_cdna_op_DS_MIN_I64, -amdgpu_cdna_op_DS_MIN_RTN_F32, -amdgpu_cdna_op_DS_MIN_RTN_F64, -amdgpu_cdna_op_DS_MIN_RTN_I32, -amdgpu_cdna_op_DS_MIN_RTN_I64, -amdgpu_cdna_op_DS_MIN_RTN_U32, -amdgpu_cdna_op_DS_MIN_RTN_U64, -amdgpu_cdna_op_DS_MIN_U32, -amdgpu_cdna_op_DS_MIN_U64, -amdgpu_cdna_op_DS_MSKOR_B32, -amdgpu_cdna_op_DS_MSKOR_B64, -amdgpu_cdna_op_DS_MSKOR_RTN_B32, -amdgpu_cdna_op_DS_MSKOR_RTN_B64, -amdgpu_cdna_op_DS_NOP, -amdgpu_cdna_op_DS_OR_B32, -amdgpu_cdna_op_DS_OR_B64, -amdgpu_cdna_op_DS_OR_RTN_B32, -amdgpu_cdna_op_DS_OR_RTN_B64, -amdgpu_cdna_op_DS_PERMUTE_B32, -amdgpu_cdna_op_DS_PK_ADD_BF16, -amdgpu_cdna_op_DS_PK_ADD_F16, -amdgpu_cdna_op_DS_PK_ADD_RTN_BF16, -amdgpu_cdna_op_DS_PK_ADD_RTN_F16, -amdgpu_cdna_op_DS_READ2ST64_B32, -amdgpu_cdna_op_DS_READ2ST64_B64, -amdgpu_cdna_op_DS_READ2_B32, -amdgpu_cdna_op_DS_READ2_B64, -amdgpu_cdna_op_DS_READ_ADDTID_B32, -amdgpu_cdna_op_DS_READ_B128, -amdgpu_cdna_op_DS_READ_B32, -amdgpu_cdna_op_DS_READ_B64, -amdgpu_cdna_op_DS_READ_B96, -amdgpu_cdna_op_DS_READ_I16, -amdgpu_cdna_op_DS_READ_I8, -amdgpu_cdna_op_DS_READ_I8_D16, -amdgpu_cdna_op_DS_READ_I8_D16_HI, -amdgpu_cdna_op_DS_READ_U16, -amdgpu_cdna_op_DS_READ_U16_D16, -amdgpu_cdna_op_DS_READ_U16_D16_HI, -amdgpu_cdna_op_DS_READ_U8, -amdgpu_cdna_op_DS_READ_U8_D16, -amdgpu_cdna_op_DS_READ_U8_D16_HI, -amdgpu_cdna_op_DS_RSUB_RTN_U32, -amdgpu_cdna_op_DS_RSUB_RTN_U64, -amdgpu_cdna_op_DS_RSUB_U32, -amdgpu_cdna_op_DS_RSUB_U64, -amdgpu_cdna_op_DS_SUB_RTN_U32, -amdgpu_cdna_op_DS_SUB_RTN_U64, -amdgpu_cdna_op_DS_SUB_U32, -amdgpu_cdna_op_DS_SUB_U64, -amdgpu_cdna_op_DS_SWIZZLE_B32, -amdgpu_cdna_op_DS_WRAP_RTN_B32, -amdgpu_cdna_op_DS_WRITE2ST64_B32, -amdgpu_cdna_op_DS_WRITE2ST64_B64, -amdgpu_cdna_op_DS_WRITE2_B32, -amdgpu_cdna_op_DS_WRITE2_B64, -amdgpu_cdna_op_DS_WRITE_ADDTID_B32, -amdgpu_cdna_op_DS_WRITE_B128, -amdgpu_cdna_op_DS_WRITE_B16, -amdgpu_cdna_op_DS_WRITE_B16_D16_HI, -amdgpu_cdna_op_DS_WRITE_B32, -amdgpu_cdna_op_DS_WRITE_B64, -amdgpu_cdna_op_DS_WRITE_B8, -amdgpu_cdna_op_DS_WRITE_B8_D16_HI, -amdgpu_cdna_op_DS_WRITE_B96, -amdgpu_cdna_op_DS_WRXCHG2ST64_RTN_B32, -amdgpu_cdna_op_DS_WRXCHG2ST64_RTN_B64, -amdgpu_cdna_op_DS_WRXCHG2_RTN_B32, -amdgpu_cdna_op_DS_WRXCHG2_RTN_B64, -amdgpu_cdna_op_DS_WRXCHG_RTN_B32, -amdgpu_cdna_op_DS_WRXCHG_RTN_B64, -amdgpu_cdna_op_DS_XOR_B32, -amdgpu_cdna_op_DS_XOR_B64, -amdgpu_cdna_op_DS_XOR_RTN_B32, -amdgpu_cdna_op_DS_XOR_RTN_B64, -amdgpu_cdna_op_FLAT_ATOMIC_ADD, -amdgpu_cdna_op_FLAT_ATOMIC_ADD_F32, -amdgpu_cdna_op_FLAT_ATOMIC_ADD_F64, -amdgpu_cdna_op_FLAT_ATOMIC_ADD_X2, -amdgpu_cdna_op_FLAT_ATOMIC_AND, -amdgpu_cdna_op_FLAT_ATOMIC_AND_X2, -amdgpu_cdna_op_FLAT_ATOMIC_CMPSWAP, -amdgpu_cdna_op_FLAT_ATOMIC_CMPSWAP_X2, -amdgpu_cdna_op_FLAT_ATOMIC_DEC, -amdgpu_cdna_op_FLAT_ATOMIC_DEC_X2, -amdgpu_cdna_op_FLAT_ATOMIC_INC, -amdgpu_cdna_op_FLAT_ATOMIC_INC_X2, -amdgpu_cdna_op_FLAT_ATOMIC_MAX_F64, -amdgpu_cdna_op_FLAT_ATOMIC_MIN_F64, -amdgpu_cdna_op_FLAT_ATOMIC_OR, -amdgpu_cdna_op_FLAT_ATOMIC_OR_X2, -amdgpu_cdna_op_FLAT_ATOMIC_PK_ADD_BF16, -amdgpu_cdna_op_FLAT_ATOMIC_PK_ADD_F16, -amdgpu_cdna_op_FLAT_ATOMIC_SMAX, -amdgpu_cdna_op_FLAT_ATOMIC_SMAX_X2, -amdgpu_cdna_op_FLAT_ATOMIC_SMIN, -amdgpu_cdna_op_FLAT_ATOMIC_SMIN_X2, -amdgpu_cdna_op_FLAT_ATOMIC_SUB, -amdgpu_cdna_op_FLAT_ATOMIC_SUB_X2, -amdgpu_cdna_op_FLAT_ATOMIC_SWAP, -amdgpu_cdna_op_FLAT_ATOMIC_SWAP_X2, -amdgpu_cdna_op_FLAT_ATOMIC_UMAX, -amdgpu_cdna_op_FLAT_ATOMIC_UMAX_X2, -amdgpu_cdna_op_FLAT_ATOMIC_UMIN, -amdgpu_cdna_op_FLAT_ATOMIC_UMIN_X2, -amdgpu_cdna_op_FLAT_ATOMIC_XOR, -amdgpu_cdna_op_FLAT_ATOMIC_XOR_X2, -amdgpu_cdna_op_FLAT_LOAD_DWORD, -amdgpu_cdna_op_FLAT_LOAD_DWORDX2, -amdgpu_cdna_op_FLAT_LOAD_DWORDX3, -amdgpu_cdna_op_FLAT_LOAD_DWORDX4, -amdgpu_cdna_op_FLAT_LOAD_SBYTE, -amdgpu_cdna_op_FLAT_LOAD_SBYTE_D16, -amdgpu_cdna_op_FLAT_LOAD_SBYTE_D16_HI, -amdgpu_cdna_op_FLAT_LOAD_SHORT_D16, -amdgpu_cdna_op_FLAT_LOAD_SHORT_D16_HI, -amdgpu_cdna_op_FLAT_LOAD_SSHORT, -amdgpu_cdna_op_FLAT_LOAD_UBYTE, -amdgpu_cdna_op_FLAT_LOAD_UBYTE_D16, -amdgpu_cdna_op_FLAT_LOAD_UBYTE_D16_HI, -amdgpu_cdna_op_FLAT_LOAD_USHORT, -amdgpu_cdna_op_FLAT_STORE_BYTE, -amdgpu_cdna_op_FLAT_STORE_BYTE_D16_HI, -amdgpu_cdna_op_FLAT_STORE_DWORD, -amdgpu_cdna_op_FLAT_STORE_DWORDX2, -amdgpu_cdna_op_FLAT_STORE_DWORDX3, -amdgpu_cdna_op_FLAT_STORE_DWORDX4, -amdgpu_cdna_op_FLAT_STORE_SHORT, -amdgpu_cdna_op_FLAT_STORE_SHORT_D16_HI, -amdgpu_cdna_op_GLOBAL_ATOMIC_ADD, -amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_F32, -amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_F64, -amdgpu_cdna_op_GLOBAL_ATOMIC_ADD_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_AND, -amdgpu_cdna_op_GLOBAL_ATOMIC_AND_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_CMPSWAP, -amdgpu_cdna_op_GLOBAL_ATOMIC_CMPSWAP_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_DEC, -amdgpu_cdna_op_GLOBAL_ATOMIC_DEC_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_INC, -amdgpu_cdna_op_GLOBAL_ATOMIC_INC_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_MAX_F64, -amdgpu_cdna_op_GLOBAL_ATOMIC_MIN_F64, -amdgpu_cdna_op_GLOBAL_ATOMIC_OR, -amdgpu_cdna_op_GLOBAL_ATOMIC_OR_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_PK_ADD_BF16, -amdgpu_cdna_op_GLOBAL_ATOMIC_PK_ADD_F16, -amdgpu_cdna_op_GLOBAL_ATOMIC_SMAX, -amdgpu_cdna_op_GLOBAL_ATOMIC_SMAX_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_SMIN, -amdgpu_cdna_op_GLOBAL_ATOMIC_SMIN_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_SUB, -amdgpu_cdna_op_GLOBAL_ATOMIC_SUB_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_SWAP, -amdgpu_cdna_op_GLOBAL_ATOMIC_SWAP_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_UMAX, -amdgpu_cdna_op_GLOBAL_ATOMIC_UMAX_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_UMIN, -amdgpu_cdna_op_GLOBAL_ATOMIC_UMIN_X2, -amdgpu_cdna_op_GLOBAL_ATOMIC_XOR, -amdgpu_cdna_op_GLOBAL_ATOMIC_XOR_X2, -amdgpu_cdna_op_GLOBAL_LOAD_DWORD, -amdgpu_cdna_op_GLOBAL_LOAD_DWORDX2, -amdgpu_cdna_op_GLOBAL_LOAD_DWORDX3, -amdgpu_cdna_op_GLOBAL_LOAD_DWORDX4, -amdgpu_cdna_op_GLOBAL_LOAD_LDS_DWORD, -amdgpu_cdna_op_GLOBAL_LOAD_LDS_SBYTE, -amdgpu_cdna_op_GLOBAL_LOAD_LDS_SSHORT, -amdgpu_cdna_op_GLOBAL_LOAD_LDS_UBYTE, -amdgpu_cdna_op_GLOBAL_LOAD_LDS_USHORT, -amdgpu_cdna_op_GLOBAL_LOAD_SBYTE, -amdgpu_cdna_op_GLOBAL_LOAD_SBYTE_D16, -amdgpu_cdna_op_GLOBAL_LOAD_SBYTE_D16_HI, -amdgpu_cdna_op_GLOBAL_LOAD_SHORT_D16, -amdgpu_cdna_op_GLOBAL_LOAD_SHORT_D16_HI, -amdgpu_cdna_op_GLOBAL_LOAD_SSHORT, -amdgpu_cdna_op_GLOBAL_LOAD_UBYTE, -amdgpu_cdna_op_GLOBAL_LOAD_UBYTE_D16, -amdgpu_cdna_op_GLOBAL_LOAD_UBYTE_D16_HI, -amdgpu_cdna_op_GLOBAL_LOAD_USHORT, -amdgpu_cdna_op_GLOBAL_STORE_BYTE, -amdgpu_cdna_op_GLOBAL_STORE_BYTE_D16_HI, -amdgpu_cdna_op_GLOBAL_STORE_DWORD, -amdgpu_cdna_op_GLOBAL_STORE_DWORDX2, -amdgpu_cdna_op_GLOBAL_STORE_DWORDX3, -amdgpu_cdna_op_GLOBAL_STORE_DWORDX4, -amdgpu_cdna_op_GLOBAL_STORE_SHORT, -amdgpu_cdna_op_GLOBAL_STORE_SHORT_D16_HI, -amdgpu_cdna_op_SCRATCH_LOAD_DWORD, -amdgpu_cdna_op_SCRATCH_LOAD_DWORDX2, -amdgpu_cdna_op_SCRATCH_LOAD_DWORDX3, -amdgpu_cdna_op_SCRATCH_LOAD_DWORDX4, -amdgpu_cdna_op_SCRATCH_LOAD_LDS_DWORD, -amdgpu_cdna_op_SCRATCH_LOAD_LDS_SBYTE, -amdgpu_cdna_op_SCRATCH_LOAD_LDS_SSHORT, -amdgpu_cdna_op_SCRATCH_LOAD_LDS_UBYTE, -amdgpu_cdna_op_SCRATCH_LOAD_LDS_USHORT, -amdgpu_cdna_op_SCRATCH_LOAD_SBYTE, -amdgpu_cdna_op_SCRATCH_LOAD_SBYTE_D16, -amdgpu_cdna_op_SCRATCH_LOAD_SBYTE_D16_HI, -amdgpu_cdna_op_SCRATCH_LOAD_SHORT_D16, -amdgpu_cdna_op_SCRATCH_LOAD_SHORT_D16_HI, -amdgpu_cdna_op_SCRATCH_LOAD_SSHORT, -amdgpu_cdna_op_SCRATCH_LOAD_UBYTE, -amdgpu_cdna_op_SCRATCH_LOAD_UBYTE_D16, -amdgpu_cdna_op_SCRATCH_LOAD_UBYTE_D16_HI, -amdgpu_cdna_op_SCRATCH_LOAD_USHORT, -amdgpu_cdna_op_SCRATCH_STORE_BYTE, -amdgpu_cdna_op_SCRATCH_STORE_BYTE_D16_HI, -amdgpu_cdna_op_SCRATCH_STORE_DWORD, -amdgpu_cdna_op_SCRATCH_STORE_DWORDX2, -amdgpu_cdna_op_SCRATCH_STORE_DWORDX3, -amdgpu_cdna_op_SCRATCH_STORE_DWORDX4, -amdgpu_cdna_op_SCRATCH_STORE_SHORT, -amdgpu_cdna_op_SCRATCH_STORE_SHORT_D16_HI, -amdgpu_cdna_op_S_ABSDIFF_I32, -amdgpu_cdna_op_S_ABS_I32, -amdgpu_cdna_op_S_ADDC_U32, -amdgpu_cdna_op_S_ADDK_I32, -amdgpu_cdna_op_S_ADD_I32, -amdgpu_cdna_op_S_ADD_U32, -amdgpu_cdna_op_S_ANDN1_SAVEEXEC_B64, -amdgpu_cdna_op_S_ANDN1_WREXEC_B64, -amdgpu_cdna_op_S_ANDN2_B32, -amdgpu_cdna_op_S_ANDN2_B64, -amdgpu_cdna_op_S_ANDN2_SAVEEXEC_B64, -amdgpu_cdna_op_S_ANDN2_WREXEC_B64, -amdgpu_cdna_op_S_AND_B32, -amdgpu_cdna_op_S_AND_B64, -amdgpu_cdna_op_S_AND_SAVEEXEC_B64, -amdgpu_cdna_op_S_ASHR_I32, -amdgpu_cdna_op_S_ASHR_I64, -amdgpu_cdna_op_S_ATC_PROBE, -amdgpu_cdna_op_S_ATC_PROBE_BUFFER, -amdgpu_cdna_op_S_ATOMIC_ADD, -amdgpu_cdna_op_S_ATOMIC_ADD_X2, -amdgpu_cdna_op_S_ATOMIC_AND, -amdgpu_cdna_op_S_ATOMIC_AND_X2, -amdgpu_cdna_op_S_ATOMIC_CMPSWAP, -amdgpu_cdna_op_S_ATOMIC_CMPSWAP_X2, -amdgpu_cdna_op_S_ATOMIC_DEC, -amdgpu_cdna_op_S_ATOMIC_DEC_X2, -amdgpu_cdna_op_S_ATOMIC_INC, -amdgpu_cdna_op_S_ATOMIC_INC_X2, -amdgpu_cdna_op_S_ATOMIC_OR, -amdgpu_cdna_op_S_ATOMIC_OR_X2, -amdgpu_cdna_op_S_ATOMIC_SMAX, -amdgpu_cdna_op_S_ATOMIC_SMAX_X2, -amdgpu_cdna_op_S_ATOMIC_SMIN, -amdgpu_cdna_op_S_ATOMIC_SMIN_X2, -amdgpu_cdna_op_S_ATOMIC_SUB, -amdgpu_cdna_op_S_ATOMIC_SUB_X2, -amdgpu_cdna_op_S_ATOMIC_SWAP, -amdgpu_cdna_op_S_ATOMIC_SWAP_X2, -amdgpu_cdna_op_S_ATOMIC_UMAX, -amdgpu_cdna_op_S_ATOMIC_UMAX_X2, -amdgpu_cdna_op_S_ATOMIC_UMIN, -amdgpu_cdna_op_S_ATOMIC_UMIN_X2, -amdgpu_cdna_op_S_ATOMIC_XOR, -amdgpu_cdna_op_S_ATOMIC_XOR_X2, -amdgpu_cdna_op_S_BARRIER, -amdgpu_cdna_op_S_BCNT0_I32_B32, -amdgpu_cdna_op_S_BCNT0_I32_B64, -amdgpu_cdna_op_S_BCNT1_I32_B32, -amdgpu_cdna_op_S_BCNT1_I32_B64, -amdgpu_cdna_op_S_BFE_I32, -amdgpu_cdna_op_S_BFE_I64, -amdgpu_cdna_op_S_BFE_U32, -amdgpu_cdna_op_S_BFE_U64, -amdgpu_cdna_op_S_BFM_B32, -amdgpu_cdna_op_S_BFM_B64, -amdgpu_cdna_op_S_BITCMP0_B32, -amdgpu_cdna_op_S_BITCMP0_B64, -amdgpu_cdna_op_S_BITCMP1_B32, -amdgpu_cdna_op_S_BITCMP1_B64, -amdgpu_cdna_op_S_BITREPLICATE_B64_B32, -amdgpu_cdna_op_S_BITSET0_B32, -amdgpu_cdna_op_S_BITSET0_B64, -amdgpu_cdna_op_S_BITSET1_B32, -amdgpu_cdna_op_S_BITSET1_B64, -amdgpu_cdna_op_S_BRANCH, -amdgpu_cdna_op_S_BREV_B32, -amdgpu_cdna_op_S_BREV_B64, -amdgpu_cdna_op_S_BUFFER_ATOMIC_ADD, -amdgpu_cdna_op_S_BUFFER_ATOMIC_ADD_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_AND, -amdgpu_cdna_op_S_BUFFER_ATOMIC_AND_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_CMPSWAP, -amdgpu_cdna_op_S_BUFFER_ATOMIC_CMPSWAP_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_DEC, -amdgpu_cdna_op_S_BUFFER_ATOMIC_DEC_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_INC, -amdgpu_cdna_op_S_BUFFER_ATOMIC_INC_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_OR, -amdgpu_cdna_op_S_BUFFER_ATOMIC_OR_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SMAX, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SMAX_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SMIN, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SMIN_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SUB, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SUB_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SWAP, -amdgpu_cdna_op_S_BUFFER_ATOMIC_SWAP_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_UMAX, -amdgpu_cdna_op_S_BUFFER_ATOMIC_UMAX_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_UMIN, -amdgpu_cdna_op_S_BUFFER_ATOMIC_UMIN_X2, -amdgpu_cdna_op_S_BUFFER_ATOMIC_XOR, -amdgpu_cdna_op_S_BUFFER_ATOMIC_XOR_X2, -amdgpu_cdna_op_S_BUFFER_LOAD_DWORD, -amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX16, -amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX2, -amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX4, -amdgpu_cdna_op_S_BUFFER_LOAD_DWORDX8, -amdgpu_cdna_op_S_BUFFER_STORE_DWORD, -amdgpu_cdna_op_S_BUFFER_STORE_DWORDX2, -amdgpu_cdna_op_S_BUFFER_STORE_DWORDX4, -amdgpu_cdna_op_S_CALL_B64, -amdgpu_cdna_op_S_CBRANCH_CDBGSYS, -amdgpu_cdna_op_S_CBRANCH_CDBGSYS_AND_USER, -amdgpu_cdna_op_S_CBRANCH_CDBGSYS_OR_USER, -amdgpu_cdna_op_S_CBRANCH_CDBGUSER, -amdgpu_cdna_op_S_CBRANCH_EXECNZ, -amdgpu_cdna_op_S_CBRANCH_EXECZ, -amdgpu_cdna_op_S_CBRANCH_G_FORK, -amdgpu_cdna_op_S_CBRANCH_I_FORK, -amdgpu_cdna_op_S_CBRANCH_JOIN, -amdgpu_cdna_op_S_CBRANCH_SCC0, -amdgpu_cdna_op_S_CBRANCH_SCC1, -amdgpu_cdna_op_S_CBRANCH_VCCNZ, -amdgpu_cdna_op_S_CBRANCH_VCCZ, -amdgpu_cdna_op_S_CMOVK_I32, -amdgpu_cdna_op_S_CMOV_B32, -amdgpu_cdna_op_S_CMOV_B64, -amdgpu_cdna_op_S_CMPK_EQ_I32, -amdgpu_cdna_op_S_CMPK_EQ_U32, -amdgpu_cdna_op_S_CMPK_GE_I32, -amdgpu_cdna_op_S_CMPK_GE_U32, -amdgpu_cdna_op_S_CMPK_GT_I32, -amdgpu_cdna_op_S_CMPK_GT_U32, -amdgpu_cdna_op_S_CMPK_LE_I32, -amdgpu_cdna_op_S_CMPK_LE_U32, -amdgpu_cdna_op_S_CMPK_LG_I32, -amdgpu_cdna_op_S_CMPK_LG_U32, -amdgpu_cdna_op_S_CMPK_LT_I32, -amdgpu_cdna_op_S_CMPK_LT_U32, -amdgpu_cdna_op_S_CMP_EQ_I32, -amdgpu_cdna_op_S_CMP_EQ_U32, -amdgpu_cdna_op_S_CMP_EQ_U64, -amdgpu_cdna_op_S_CMP_GE_I32, -amdgpu_cdna_op_S_CMP_GE_U32, -amdgpu_cdna_op_S_CMP_GT_I32, -amdgpu_cdna_op_S_CMP_GT_U32, -amdgpu_cdna_op_S_CMP_LE_I32, -amdgpu_cdna_op_S_CMP_LE_U32, -amdgpu_cdna_op_S_CMP_LG_I32, -amdgpu_cdna_op_S_CMP_LG_U32, -amdgpu_cdna_op_S_CMP_LG_U64, -amdgpu_cdna_op_S_CMP_LT_I32, -amdgpu_cdna_op_S_CMP_LT_U32, -amdgpu_cdna_op_S_CSELECT_B32, -amdgpu_cdna_op_S_CSELECT_B64, -amdgpu_cdna_op_S_DCACHE_DISCARD, -amdgpu_cdna_op_S_DCACHE_DISCARD_X2, -amdgpu_cdna_op_S_DCACHE_INV, -amdgpu_cdna_op_S_DCACHE_INV_VOL, -amdgpu_cdna_op_S_DCACHE_WB, -amdgpu_cdna_op_S_DCACHE_WB_VOL, -amdgpu_cdna_op_S_DECPERFLEVEL, -amdgpu_cdna_op_S_ENDPGM, -amdgpu_cdna_op_S_ENDPGM_ORDERED_PS_DONE, -amdgpu_cdna_op_S_ENDPGM_SAVED, -amdgpu_cdna_op_S_FF0_I32_B32, -amdgpu_cdna_op_S_FF0_I32_B64, -amdgpu_cdna_op_S_FF1_I32_B32, -amdgpu_cdna_op_S_FF1_I32_B64, -amdgpu_cdna_op_S_FLBIT_I32, -amdgpu_cdna_op_S_FLBIT_I32_B32, -amdgpu_cdna_op_S_FLBIT_I32_B64, -amdgpu_cdna_op_S_FLBIT_I32_I64, -amdgpu_cdna_op_S_GETPC_B64, -amdgpu_cdna_op_S_GETREG_B32, -amdgpu_cdna_op_S_ICACHE_INV, -amdgpu_cdna_op_S_INCPERFLEVEL, -amdgpu_cdna_op_S_LOAD_DWORD, -amdgpu_cdna_op_S_LOAD_DWORDX16, -amdgpu_cdna_op_S_LOAD_DWORDX2, -amdgpu_cdna_op_S_LOAD_DWORDX4, -amdgpu_cdna_op_S_LOAD_DWORDX8, -amdgpu_cdna_op_S_LSHL1_ADD_U32, -amdgpu_cdna_op_S_LSHL2_ADD_U32, -amdgpu_cdna_op_S_LSHL3_ADD_U32, -amdgpu_cdna_op_S_LSHL4_ADD_U32, -amdgpu_cdna_op_S_LSHL_B32, -amdgpu_cdna_op_S_LSHL_B64, -amdgpu_cdna_op_S_LSHR_B32, -amdgpu_cdna_op_S_LSHR_B64, -amdgpu_cdna_op_S_MAX_I32, -amdgpu_cdna_op_S_MAX_U32, -amdgpu_cdna_op_S_MEMREALTIME, -amdgpu_cdna_op_S_MEMTIME, -amdgpu_cdna_op_S_MIN_I32, -amdgpu_cdna_op_S_MIN_U32, -amdgpu_cdna_op_S_MOVK_I32, -amdgpu_cdna_op_S_MOVRELD_B32, -amdgpu_cdna_op_S_MOVRELD_B64, -amdgpu_cdna_op_S_MOVRELS_B32, -amdgpu_cdna_op_S_MOVRELS_B64, -amdgpu_cdna_op_S_MOV_B32, -amdgpu_cdna_op_S_MOV_B64, -amdgpu_cdna_op_S_MULK_I32, -amdgpu_cdna_op_S_MUL_HI_I32, -amdgpu_cdna_op_S_MUL_HI_U32, -amdgpu_cdna_op_S_MUL_I32, -amdgpu_cdna_op_S_NAND_B32, -amdgpu_cdna_op_S_NAND_B64, -amdgpu_cdna_op_S_NAND_SAVEEXEC_B64, -amdgpu_cdna_op_S_NOP, -amdgpu_cdna_op_S_NOR_B32, -amdgpu_cdna_op_S_NOR_B64, -amdgpu_cdna_op_S_NOR_SAVEEXEC_B64, -amdgpu_cdna_op_S_NOT_B32, -amdgpu_cdna_op_S_NOT_B64, -amdgpu_cdna_op_S_ORN1_SAVEEXEC_B64, -amdgpu_cdna_op_S_ORN2_B32, -amdgpu_cdna_op_S_ORN2_B64, -amdgpu_cdna_op_S_ORN2_SAVEEXEC_B64, -amdgpu_cdna_op_S_OR_B32, -amdgpu_cdna_op_S_OR_B64, -amdgpu_cdna_op_S_OR_SAVEEXEC_B64, -amdgpu_cdna_op_S_PACK_HH_B32_B16, -amdgpu_cdna_op_S_PACK_LH_B32_B16, -amdgpu_cdna_op_S_PACK_LL_B32_B16, -amdgpu_cdna_op_S_QUADMASK_B32, -amdgpu_cdna_op_S_QUADMASK_B64, -amdgpu_cdna_op_S_RFE_B64, -amdgpu_cdna_op_S_RFE_RESTORE_B64, -amdgpu_cdna_op_S_SCRATCH_LOAD_DWORD, -amdgpu_cdna_op_S_SCRATCH_LOAD_DWORDX2, -amdgpu_cdna_op_S_SCRATCH_LOAD_DWORDX4, -amdgpu_cdna_op_S_SCRATCH_STORE_DWORD, -amdgpu_cdna_op_S_SCRATCH_STORE_DWORDX2, -amdgpu_cdna_op_S_SCRATCH_STORE_DWORDX4, -amdgpu_cdna_op_S_SENDMSG, -amdgpu_cdna_op_S_SENDMSGHALT, -amdgpu_cdna_op_S_SETHALT, -amdgpu_cdna_op_S_SETKILL, -amdgpu_cdna_op_S_SETPC_B64, -amdgpu_cdna_op_S_SETPRIO, -amdgpu_cdna_op_S_SETREG_B32, -amdgpu_cdna_op_S_SETREG_IMM32_B32, -amdgpu_cdna_op_S_SETVSKIP, -amdgpu_cdna_op_S_SET_GPR_IDX_IDX, -amdgpu_cdna_op_S_SET_GPR_IDX_MODE, -amdgpu_cdna_op_S_SET_GPR_IDX_OFF, -amdgpu_cdna_op_S_SET_GPR_IDX_ON, -amdgpu_cdna_op_S_SET_VALU_COEXEC_MODE, -amdgpu_cdna_op_S_SEXT_I32_I16, -amdgpu_cdna_op_S_SEXT_I32_I8, -amdgpu_cdna_op_S_SLEEP, -amdgpu_cdna_op_S_STORE_DWORD, -amdgpu_cdna_op_S_STORE_DWORDX2, -amdgpu_cdna_op_S_STORE_DWORDX4, -amdgpu_cdna_op_S_SUBB_U32, -amdgpu_cdna_op_S_SUB_I32, -amdgpu_cdna_op_S_SUB_U32, -amdgpu_cdna_op_S_SWAPPC_B64, -amdgpu_cdna_op_S_TRAP, -amdgpu_cdna_op_S_TTRACEDATA, -amdgpu_cdna_op_S_WAITCNT, -amdgpu_cdna_op_S_WAKEUP, -amdgpu_cdna_op_S_WQM_B32, -amdgpu_cdna_op_S_WQM_B64, -amdgpu_cdna_op_S_XNOR_B32, -amdgpu_cdna_op_S_XNOR_B64, -amdgpu_cdna_op_S_XNOR_SAVEEXEC_B64, -amdgpu_cdna_op_S_XOR_B32, -amdgpu_cdna_op_S_XOR_B64, -amdgpu_cdna_op_S_XOR_SAVEEXEC_B64, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_X, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XY, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XYZ, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_D16_XYZW, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_X, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XY, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XYZ, -amdgpu_cdna_op_TBUFFER_LOAD_FORMAT_XYZW, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_X, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XY, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XYZ, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_D16_XYZW, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_X, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XY, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XYZ, -amdgpu_cdna_op_TBUFFER_STORE_FORMAT_XYZW, -amdgpu_cdna_op_V_ACCVGPR_MOV_B32, -amdgpu_cdna_op_V_ACCVGPR_READ, -amdgpu_cdna_op_V_ACCVGPR_WRITE, -amdgpu_cdna_op_V_ADD3_U32, -amdgpu_cdna_op_V_ADDC_CO_U32, -amdgpu_cdna_op_V_ADD_CO_U32, -amdgpu_cdna_op_V_ADD_F16, -amdgpu_cdna_op_V_ADD_F32, -amdgpu_cdna_op_V_ADD_F64, -amdgpu_cdna_op_V_ADD_I16, -amdgpu_cdna_op_V_ADD_I32, -amdgpu_cdna_op_V_ADD_LSHL_U32, -amdgpu_cdna_op_V_ADD_U16, -amdgpu_cdna_op_V_ADD_U32, -amdgpu_cdna_op_V_ALIGNBIT_B32, -amdgpu_cdna_op_V_ALIGNBYTE_B32, -amdgpu_cdna_op_V_AND_B32, -amdgpu_cdna_op_V_AND_OR_B32, -amdgpu_cdna_op_V_ASHRREV_I16, -amdgpu_cdna_op_V_ASHRREV_I32, -amdgpu_cdna_op_V_ASHRREV_I64, -amdgpu_cdna_op_V_BCNT_U32_B32, -amdgpu_cdna_op_V_BFE_I32, -amdgpu_cdna_op_V_BFE_U32, -amdgpu_cdna_op_V_BFI_B32, -amdgpu_cdna_op_V_BFM_B32, -amdgpu_cdna_op_V_BFREV_B32, -amdgpu_cdna_op_V_CEIL_F16, -amdgpu_cdna_op_V_CEIL_F32, -amdgpu_cdna_op_V_CEIL_F64, -amdgpu_cdna_op_V_CLREXCP, -amdgpu_cdna_op_V_CMPX_CLASS_F16, -amdgpu_cdna_op_V_CMPX_CLASS_F32, -amdgpu_cdna_op_V_CMPX_CLASS_F64, -amdgpu_cdna_op_V_CMPX_EQ_F16, -amdgpu_cdna_op_V_CMPX_EQ_F32, -amdgpu_cdna_op_V_CMPX_EQ_F64, -amdgpu_cdna_op_V_CMPX_EQ_I16, -amdgpu_cdna_op_V_CMPX_EQ_I32, -amdgpu_cdna_op_V_CMPX_EQ_I64, -amdgpu_cdna_op_V_CMPX_EQ_U16, -amdgpu_cdna_op_V_CMPX_EQ_U32, -amdgpu_cdna_op_V_CMPX_EQ_U64, -amdgpu_cdna_op_V_CMPX_F_F16, -amdgpu_cdna_op_V_CMPX_F_F32, -amdgpu_cdna_op_V_CMPX_F_F64, -amdgpu_cdna_op_V_CMPX_F_I16, -amdgpu_cdna_op_V_CMPX_F_I32, -amdgpu_cdna_op_V_CMPX_F_I64, -amdgpu_cdna_op_V_CMPX_F_U16, -amdgpu_cdna_op_V_CMPX_F_U32, -amdgpu_cdna_op_V_CMPX_F_U64, -amdgpu_cdna_op_V_CMPX_GE_F16, -amdgpu_cdna_op_V_CMPX_GE_F32, -amdgpu_cdna_op_V_CMPX_GE_F64, -amdgpu_cdna_op_V_CMPX_GE_I16, -amdgpu_cdna_op_V_CMPX_GE_I32, -amdgpu_cdna_op_V_CMPX_GE_I64, -amdgpu_cdna_op_V_CMPX_GE_U16, -amdgpu_cdna_op_V_CMPX_GE_U32, -amdgpu_cdna_op_V_CMPX_GE_U64, -amdgpu_cdna_op_V_CMPX_GT_F16, -amdgpu_cdna_op_V_CMPX_GT_F32, -amdgpu_cdna_op_V_CMPX_GT_F64, -amdgpu_cdna_op_V_CMPX_GT_I16, -amdgpu_cdna_op_V_CMPX_GT_I32, -amdgpu_cdna_op_V_CMPX_GT_I64, -amdgpu_cdna_op_V_CMPX_GT_U16, -amdgpu_cdna_op_V_CMPX_GT_U32, -amdgpu_cdna_op_V_CMPX_GT_U64, -amdgpu_cdna_op_V_CMPX_LE_F16, -amdgpu_cdna_op_V_CMPX_LE_F32, -amdgpu_cdna_op_V_CMPX_LE_F64, -amdgpu_cdna_op_V_CMPX_LE_I16, -amdgpu_cdna_op_V_CMPX_LE_I32, -amdgpu_cdna_op_V_CMPX_LE_I64, -amdgpu_cdna_op_V_CMPX_LE_U16, -amdgpu_cdna_op_V_CMPX_LE_U32, -amdgpu_cdna_op_V_CMPX_LE_U64, -amdgpu_cdna_op_V_CMPX_LG_F16, -amdgpu_cdna_op_V_CMPX_LG_F32, -amdgpu_cdna_op_V_CMPX_LG_F64, -amdgpu_cdna_op_V_CMPX_LT_F16, -amdgpu_cdna_op_V_CMPX_LT_F32, -amdgpu_cdna_op_V_CMPX_LT_F64, -amdgpu_cdna_op_V_CMPX_LT_I16, -amdgpu_cdna_op_V_CMPX_LT_I32, -amdgpu_cdna_op_V_CMPX_LT_I64, -amdgpu_cdna_op_V_CMPX_LT_U16, -amdgpu_cdna_op_V_CMPX_LT_U32, -amdgpu_cdna_op_V_CMPX_LT_U64, -amdgpu_cdna_op_V_CMPX_NEQ_F16, -amdgpu_cdna_op_V_CMPX_NEQ_F32, -amdgpu_cdna_op_V_CMPX_NEQ_F64, -amdgpu_cdna_op_V_CMPX_NE_I16, -amdgpu_cdna_op_V_CMPX_NE_I32, -amdgpu_cdna_op_V_CMPX_NE_I64, -amdgpu_cdna_op_V_CMPX_NE_U16, -amdgpu_cdna_op_V_CMPX_NE_U32, -amdgpu_cdna_op_V_CMPX_NE_U64, -amdgpu_cdna_op_V_CMPX_NGE_F16, -amdgpu_cdna_op_V_CMPX_NGE_F32, -amdgpu_cdna_op_V_CMPX_NGE_F64, -amdgpu_cdna_op_V_CMPX_NGT_F16, -amdgpu_cdna_op_V_CMPX_NGT_F32, -amdgpu_cdna_op_V_CMPX_NGT_F64, -amdgpu_cdna_op_V_CMPX_NLE_F16, -amdgpu_cdna_op_V_CMPX_NLE_F32, -amdgpu_cdna_op_V_CMPX_NLE_F64, -amdgpu_cdna_op_V_CMPX_NLG_F16, -amdgpu_cdna_op_V_CMPX_NLG_F32, -amdgpu_cdna_op_V_CMPX_NLG_F64, -amdgpu_cdna_op_V_CMPX_NLT_F16, -amdgpu_cdna_op_V_CMPX_NLT_F32, -amdgpu_cdna_op_V_CMPX_NLT_F64, -amdgpu_cdna_op_V_CMPX_O_F16, -amdgpu_cdna_op_V_CMPX_O_F32, -amdgpu_cdna_op_V_CMPX_O_F64, -amdgpu_cdna_op_V_CMPX_TRU_F16, -amdgpu_cdna_op_V_CMPX_TRU_F32, -amdgpu_cdna_op_V_CMPX_TRU_F64, -amdgpu_cdna_op_V_CMPX_T_I16, -amdgpu_cdna_op_V_CMPX_T_I32, -amdgpu_cdna_op_V_CMPX_T_I64, -amdgpu_cdna_op_V_CMPX_T_U16, -amdgpu_cdna_op_V_CMPX_T_U32, -amdgpu_cdna_op_V_CMPX_T_U64, -amdgpu_cdna_op_V_CMPX_U_F16, -amdgpu_cdna_op_V_CMPX_U_F32, -amdgpu_cdna_op_V_CMPX_U_F64, -amdgpu_cdna_op_V_CMP_CLASS_F16, -amdgpu_cdna_op_V_CMP_CLASS_F32, -amdgpu_cdna_op_V_CMP_CLASS_F64, -amdgpu_cdna_op_V_CMP_EQ_F16, -amdgpu_cdna_op_V_CMP_EQ_F32, -amdgpu_cdna_op_V_CMP_EQ_F64, -amdgpu_cdna_op_V_CMP_EQ_I16, -amdgpu_cdna_op_V_CMP_EQ_I32, -amdgpu_cdna_op_V_CMP_EQ_I64, -amdgpu_cdna_op_V_CMP_EQ_U16, -amdgpu_cdna_op_V_CMP_EQ_U32, -amdgpu_cdna_op_V_CMP_EQ_U64, -amdgpu_cdna_op_V_CMP_F_F16, -amdgpu_cdna_op_V_CMP_F_F32, -amdgpu_cdna_op_V_CMP_F_F64, -amdgpu_cdna_op_V_CMP_F_I16, -amdgpu_cdna_op_V_CMP_F_I32, -amdgpu_cdna_op_V_CMP_F_I64, -amdgpu_cdna_op_V_CMP_F_U16, -amdgpu_cdna_op_V_CMP_F_U32, -amdgpu_cdna_op_V_CMP_F_U64, -amdgpu_cdna_op_V_CMP_GE_F16, -amdgpu_cdna_op_V_CMP_GE_F32, -amdgpu_cdna_op_V_CMP_GE_F64, -amdgpu_cdna_op_V_CMP_GE_I16, -amdgpu_cdna_op_V_CMP_GE_I32, -amdgpu_cdna_op_V_CMP_GE_I64, -amdgpu_cdna_op_V_CMP_GE_U16, -amdgpu_cdna_op_V_CMP_GE_U32, -amdgpu_cdna_op_V_CMP_GE_U64, -amdgpu_cdna_op_V_CMP_GT_F16, -amdgpu_cdna_op_V_CMP_GT_F32, -amdgpu_cdna_op_V_CMP_GT_F64, -amdgpu_cdna_op_V_CMP_GT_I16, -amdgpu_cdna_op_V_CMP_GT_I32, -amdgpu_cdna_op_V_CMP_GT_I64, -amdgpu_cdna_op_V_CMP_GT_U16, -amdgpu_cdna_op_V_CMP_GT_U32, -amdgpu_cdna_op_V_CMP_GT_U64, -amdgpu_cdna_op_V_CMP_LE_F16, -amdgpu_cdna_op_V_CMP_LE_F32, -amdgpu_cdna_op_V_CMP_LE_F64, -amdgpu_cdna_op_V_CMP_LE_I16, -amdgpu_cdna_op_V_CMP_LE_I32, -amdgpu_cdna_op_V_CMP_LE_I64, -amdgpu_cdna_op_V_CMP_LE_U16, -amdgpu_cdna_op_V_CMP_LE_U32, -amdgpu_cdna_op_V_CMP_LE_U64, -amdgpu_cdna_op_V_CMP_LG_F16, -amdgpu_cdna_op_V_CMP_LG_F32, -amdgpu_cdna_op_V_CMP_LG_F64, -amdgpu_cdna_op_V_CMP_LT_F16, -amdgpu_cdna_op_V_CMP_LT_F32, -amdgpu_cdna_op_V_CMP_LT_F64, -amdgpu_cdna_op_V_CMP_LT_I16, -amdgpu_cdna_op_V_CMP_LT_I32, -amdgpu_cdna_op_V_CMP_LT_I64, -amdgpu_cdna_op_V_CMP_LT_U16, -amdgpu_cdna_op_V_CMP_LT_U32, -amdgpu_cdna_op_V_CMP_LT_U64, -amdgpu_cdna_op_V_CMP_NEQ_F16, -amdgpu_cdna_op_V_CMP_NEQ_F32, -amdgpu_cdna_op_V_CMP_NEQ_F64, -amdgpu_cdna_op_V_CMP_NE_I16, -amdgpu_cdna_op_V_CMP_NE_I32, -amdgpu_cdna_op_V_CMP_NE_I64, -amdgpu_cdna_op_V_CMP_NE_U16, -amdgpu_cdna_op_V_CMP_NE_U32, -amdgpu_cdna_op_V_CMP_NE_U64, -amdgpu_cdna_op_V_CMP_NGE_F16, -amdgpu_cdna_op_V_CMP_NGE_F32, -amdgpu_cdna_op_V_CMP_NGE_F64, -amdgpu_cdna_op_V_CMP_NGT_F16, -amdgpu_cdna_op_V_CMP_NGT_F32, -amdgpu_cdna_op_V_CMP_NGT_F64, -amdgpu_cdna_op_V_CMP_NLE_F16, -amdgpu_cdna_op_V_CMP_NLE_F32, -amdgpu_cdna_op_V_CMP_NLE_F64, -amdgpu_cdna_op_V_CMP_NLG_F16, -amdgpu_cdna_op_V_CMP_NLG_F32, -amdgpu_cdna_op_V_CMP_NLG_F64, -amdgpu_cdna_op_V_CMP_NLT_F16, -amdgpu_cdna_op_V_CMP_NLT_F32, -amdgpu_cdna_op_V_CMP_NLT_F64, -amdgpu_cdna_op_V_CMP_O_F16, -amdgpu_cdna_op_V_CMP_O_F32, -amdgpu_cdna_op_V_CMP_O_F64, -amdgpu_cdna_op_V_CMP_TRU_F16, -amdgpu_cdna_op_V_CMP_TRU_F32, -amdgpu_cdna_op_V_CMP_TRU_F64, -amdgpu_cdna_op_V_CMP_T_I16, -amdgpu_cdna_op_V_CMP_T_I32, -amdgpu_cdna_op_V_CMP_T_I64, -amdgpu_cdna_op_V_CMP_T_U16, -amdgpu_cdna_op_V_CMP_T_U32, -amdgpu_cdna_op_V_CMP_T_U64, -amdgpu_cdna_op_V_CMP_U_F16, -amdgpu_cdna_op_V_CMP_U_F32, -amdgpu_cdna_op_V_CMP_U_F64, -amdgpu_cdna_op_V_CNDMASK_B32, -amdgpu_cdna_op_V_COS_F16, -amdgpu_cdna_op_V_COS_F32, -amdgpu_cdna_op_V_CUBEID_F32, -amdgpu_cdna_op_V_CUBEMA_F32, -amdgpu_cdna_op_V_CUBESC_F32, -amdgpu_cdna_op_V_CUBETC_F32, -amdgpu_cdna_op_V_CVT_F16_F32, -amdgpu_cdna_op_V_CVT_F16_I16, -amdgpu_cdna_op_V_CVT_F16_U16, -amdgpu_cdna_op_V_CVT_F32_BF8, -amdgpu_cdna_op_V_CVT_F32_F16, -amdgpu_cdna_op_V_CVT_F32_F64, -amdgpu_cdna_op_V_CVT_F32_FP8, -amdgpu_cdna_op_V_CVT_F32_I32, -amdgpu_cdna_op_V_CVT_F32_U32, -amdgpu_cdna_op_V_CVT_F32_UBYTE0, -amdgpu_cdna_op_V_CVT_F32_UBYTE1, -amdgpu_cdna_op_V_CVT_F32_UBYTE2, -amdgpu_cdna_op_V_CVT_F32_UBYTE3, -amdgpu_cdna_op_V_CVT_F64_F32, -amdgpu_cdna_op_V_CVT_F64_I32, -amdgpu_cdna_op_V_CVT_F64_U32, -amdgpu_cdna_op_V_CVT_FLR_I32_F32, -amdgpu_cdna_op_V_CVT_I16_F16, -amdgpu_cdna_op_V_CVT_I32_F32, -amdgpu_cdna_op_V_CVT_I32_F64, -amdgpu_cdna_op_V_CVT_NORM_I16_F16, -amdgpu_cdna_op_V_CVT_NORM_U16_F16, -amdgpu_cdna_op_V_CVT_OFF_F32_I4, -amdgpu_cdna_op_V_CVT_PKACCUM_U8_F32, -amdgpu_cdna_op_V_CVT_PKNORM_I16_F16, -amdgpu_cdna_op_V_CVT_PKNORM_I16_F32, -amdgpu_cdna_op_V_CVT_PKNORM_U16_F16, -amdgpu_cdna_op_V_CVT_PKNORM_U16_F32, -amdgpu_cdna_op_V_CVT_PKRTZ_F16_F32, -amdgpu_cdna_op_V_CVT_PK_BF8_F32, -amdgpu_cdna_op_V_CVT_PK_F32_BF8, -amdgpu_cdna_op_V_CVT_PK_F32_FP8, -amdgpu_cdna_op_V_CVT_PK_FP8_F32, -amdgpu_cdna_op_V_CVT_PK_I16_I32, -amdgpu_cdna_op_V_CVT_PK_U16_U32, -amdgpu_cdna_op_V_CVT_PK_U8_F32, -amdgpu_cdna_op_V_CVT_RPI_I32_F32, -amdgpu_cdna_op_V_CVT_SR_BF8_F32, -amdgpu_cdna_op_V_CVT_SR_FP8_F32, -amdgpu_cdna_op_V_CVT_U16_F16, -amdgpu_cdna_op_V_CVT_U32_F32, -amdgpu_cdna_op_V_CVT_U32_F64, -amdgpu_cdna_op_V_DIV_FIXUP_F16, -amdgpu_cdna_op_V_DIV_FIXUP_F32, -amdgpu_cdna_op_V_DIV_FIXUP_F64, -amdgpu_cdna_op_V_DIV_FIXUP_LEGACY_F16, -amdgpu_cdna_op_V_DIV_FMAS_F32, -amdgpu_cdna_op_V_DIV_FMAS_F64, -amdgpu_cdna_op_V_DIV_SCALE_F32, -amdgpu_cdna_op_V_DIV_SCALE_F64, -amdgpu_cdna_op_V_DOT2C_F32_F16, -amdgpu_cdna_op_V_DOT2C_I32_I16, -amdgpu_cdna_op_V_DOT2_F32_F16, -amdgpu_cdna_op_V_DOT2_I32_I16, -amdgpu_cdna_op_V_DOT2_U32_U16, -amdgpu_cdna_op_V_DOT4C_I32_I8, -amdgpu_cdna_op_V_DOT4_I32_I8, -amdgpu_cdna_op_V_DOT4_U32_U8, -amdgpu_cdna_op_V_DOT8C_I32_I4, -amdgpu_cdna_op_V_DOT8_I32_I4, -amdgpu_cdna_op_V_DOT8_U32_U4, -amdgpu_cdna_op_V_EXP_F16, -amdgpu_cdna_op_V_EXP_F32, -amdgpu_cdna_op_V_EXP_LEGACY_F32, -amdgpu_cdna_op_V_FFBH_I32, -amdgpu_cdna_op_V_FFBH_U32, -amdgpu_cdna_op_V_FFBL_B32, -amdgpu_cdna_op_V_FLOOR_F16, -amdgpu_cdna_op_V_FLOOR_F32, -amdgpu_cdna_op_V_FLOOR_F64, -amdgpu_cdna_op_V_FMAAK_F32, -amdgpu_cdna_op_V_FMAC_F32, -amdgpu_cdna_op_V_FMAC_F64, -amdgpu_cdna_op_V_FMAMK_F32, -amdgpu_cdna_op_V_FMA_F16, -amdgpu_cdna_op_V_FMA_F32, -amdgpu_cdna_op_V_FMA_F64, -amdgpu_cdna_op_V_FMA_LEGACY_F16, -amdgpu_cdna_op_V_FRACT_F16, -amdgpu_cdna_op_V_FRACT_F32, -amdgpu_cdna_op_V_FRACT_F64, -amdgpu_cdna_op_V_FREXP_EXP_I16_F16, -amdgpu_cdna_op_V_FREXP_EXP_I32_F32, -amdgpu_cdna_op_V_FREXP_EXP_I32_F64, -amdgpu_cdna_op_V_FREXP_MANT_F16, -amdgpu_cdna_op_V_FREXP_MANT_F32, -amdgpu_cdna_op_V_FREXP_MANT_F64, -amdgpu_cdna_op_V_LDEXP_F16, -amdgpu_cdna_op_V_LDEXP_F32, -amdgpu_cdna_op_V_LDEXP_F64, -amdgpu_cdna_op_V_LERP_U8, -amdgpu_cdna_op_V_LOG_F16, -amdgpu_cdna_op_V_LOG_F32, -amdgpu_cdna_op_V_LOG_LEGACY_F32, -amdgpu_cdna_op_V_LSHLREV_B16, -amdgpu_cdna_op_V_LSHLREV_B32, -amdgpu_cdna_op_V_LSHLREV_B64, -amdgpu_cdna_op_V_LSHL_ADD_U32, -amdgpu_cdna_op_V_LSHL_ADD_U64, -amdgpu_cdna_op_V_LSHL_OR_B32, -amdgpu_cdna_op_V_LSHRREV_B16, -amdgpu_cdna_op_V_LSHRREV_B32, -amdgpu_cdna_op_V_LSHRREV_B64, -amdgpu_cdna_op_V_MAC_F16, -amdgpu_cdna_op_V_MADAK_F16, -amdgpu_cdna_op_V_MADMK_F16, -amdgpu_cdna_op_V_MAD_F16, -amdgpu_cdna_op_V_MAD_I16, -amdgpu_cdna_op_V_MAD_I32_I16, -amdgpu_cdna_op_V_MAD_I32_I24, -amdgpu_cdna_op_V_MAD_I64_I32, -amdgpu_cdna_op_V_MAD_LEGACY_F16, -amdgpu_cdna_op_V_MAD_LEGACY_I16, -amdgpu_cdna_op_V_MAD_LEGACY_U16, -amdgpu_cdna_op_V_MAD_MIXHI_F16, -amdgpu_cdna_op_V_MAD_MIXLO_F16, -amdgpu_cdna_op_V_MAD_MIX_F32, -amdgpu_cdna_op_V_MAD_U16, -amdgpu_cdna_op_V_MAD_U32_U16, -amdgpu_cdna_op_V_MAD_U32_U24, -amdgpu_cdna_op_V_MAD_U64_U32, -amdgpu_cdna_op_V_MAX3_F16, -amdgpu_cdna_op_V_MAX3_F32, -amdgpu_cdna_op_V_MAX3_I16, -amdgpu_cdna_op_V_MAX3_I32, -amdgpu_cdna_op_V_MAX3_U16, -amdgpu_cdna_op_V_MAX3_U32, -amdgpu_cdna_op_V_MAX_F16, -amdgpu_cdna_op_V_MAX_F32, -amdgpu_cdna_op_V_MAX_F64, -amdgpu_cdna_op_V_MAX_I16, -amdgpu_cdna_op_V_MAX_I32, -amdgpu_cdna_op_V_MAX_U16, -amdgpu_cdna_op_V_MAX_U32, -amdgpu_cdna_op_V_MBCNT_HI_U32_B32, -amdgpu_cdna_op_V_MBCNT_LO_U32_B32, -amdgpu_cdna_op_V_MED3_F16, -amdgpu_cdna_op_V_MED3_F32, -amdgpu_cdna_op_V_MED3_I16, -amdgpu_cdna_op_V_MED3_I32, -amdgpu_cdna_op_V_MED3_U16, -amdgpu_cdna_op_V_MED3_U32, -amdgpu_cdna_op_V_MFMA_F32_16X16X16_BF16, -amdgpu_cdna_op_V_MFMA_F32_16X16X16_F16, -amdgpu_cdna_op_V_MFMA_F32_16X16X1_4B_F32, -amdgpu_cdna_op_V_MFMA_F32_16X16X32_BF8_BF8, -amdgpu_cdna_op_V_MFMA_F32_16X16X32_BF8_FP8, -amdgpu_cdna_op_V_MFMA_F32_16X16X32_FP8_BF8, -amdgpu_cdna_op_V_MFMA_F32_16X16X32_FP8_FP8, -amdgpu_cdna_op_V_MFMA_F32_16X16X4_4B_BF16, -amdgpu_cdna_op_V_MFMA_F32_16X16X4_4B_F16, -amdgpu_cdna_op_V_MFMA_F32_16X16X4_F32, -amdgpu_cdna_op_V_MFMA_F32_16X16X8_XF32, -amdgpu_cdna_op_V_MFMA_F32_32X32X16_BF8_BF8, -amdgpu_cdna_op_V_MFMA_F32_32X32X16_BF8_FP8, -amdgpu_cdna_op_V_MFMA_F32_32X32X16_FP8_BF8, -amdgpu_cdna_op_V_MFMA_F32_32X32X16_FP8_FP8, -amdgpu_cdna_op_V_MFMA_F32_32X32X1_2B_F32, -amdgpu_cdna_op_V_MFMA_F32_32X32X2_F32, -amdgpu_cdna_op_V_MFMA_F32_32X32X4_2B_BF16, -amdgpu_cdna_op_V_MFMA_F32_32X32X4_2B_F16, -amdgpu_cdna_op_V_MFMA_F32_32X32X4_XF32, -amdgpu_cdna_op_V_MFMA_F32_32X32X8_BF16, -amdgpu_cdna_op_V_MFMA_F32_32X32X8_F16, -amdgpu_cdna_op_V_MFMA_F32_4X4X1_16B_F32, -amdgpu_cdna_op_V_MFMA_F32_4X4X4_16B_BF16, -amdgpu_cdna_op_V_MFMA_F32_4X4X4_16B_F16, -amdgpu_cdna_op_V_MFMA_F64_16X16X4_F64, -amdgpu_cdna_op_V_MFMA_F64_4X4X4_4B_F64, -amdgpu_cdna_op_V_MFMA_I32_16X16X32_I8, -amdgpu_cdna_op_V_MFMA_I32_16X16X4_4B_I8, -amdgpu_cdna_op_V_MFMA_I32_32X32X16_I8, -amdgpu_cdna_op_V_MFMA_I32_32X32X4_2B_I8, -amdgpu_cdna_op_V_MFMA_I32_4X4X4_16B_I8, -amdgpu_cdna_op_V_MIN3_F16, -amdgpu_cdna_op_V_MIN3_F32, -amdgpu_cdna_op_V_MIN3_I16, -amdgpu_cdna_op_V_MIN3_I32, -amdgpu_cdna_op_V_MIN3_U16, -amdgpu_cdna_op_V_MIN3_U32, -amdgpu_cdna_op_V_MIN_F16, -amdgpu_cdna_op_V_MIN_F32, -amdgpu_cdna_op_V_MIN_F64, -amdgpu_cdna_op_V_MIN_I16, -amdgpu_cdna_op_V_MIN_I32, -amdgpu_cdna_op_V_MIN_U16, -amdgpu_cdna_op_V_MIN_U32, -amdgpu_cdna_op_V_MOV_B32, -amdgpu_cdna_op_V_MOV_B64, -amdgpu_cdna_op_V_MQSAD_PK_U16_U8, -amdgpu_cdna_op_V_MQSAD_U32_U8, -amdgpu_cdna_op_V_MSAD_U8, -amdgpu_cdna_op_V_MUL_F16, -amdgpu_cdna_op_V_MUL_F32, -amdgpu_cdna_op_V_MUL_F64, -amdgpu_cdna_op_V_MUL_HI_I32, -amdgpu_cdna_op_V_MUL_HI_I32_I24, -amdgpu_cdna_op_V_MUL_HI_U32, -amdgpu_cdna_op_V_MUL_HI_U32_U24, -amdgpu_cdna_op_V_MUL_I32_I24, -amdgpu_cdna_op_V_MUL_LEGACY_F32, -amdgpu_cdna_op_V_MUL_LO_U16, -amdgpu_cdna_op_V_MUL_LO_U32, -amdgpu_cdna_op_V_MUL_U32_U24, -amdgpu_cdna_op_V_NOP, -amdgpu_cdna_op_V_NOT_B32, -amdgpu_cdna_op_V_OR3_B32, -amdgpu_cdna_op_V_OR_B32, -amdgpu_cdna_op_V_PACK_B32_F16, -amdgpu_cdna_op_V_PERM_B32, -amdgpu_cdna_op_V_PK_ADD_F16, -amdgpu_cdna_op_V_PK_ADD_F32, -amdgpu_cdna_op_V_PK_ADD_I16, -amdgpu_cdna_op_V_PK_ADD_U16, -amdgpu_cdna_op_V_PK_ASHRREV_I16, -amdgpu_cdna_op_V_PK_FMAC_F16, -amdgpu_cdna_op_V_PK_FMA_F16, -amdgpu_cdna_op_V_PK_FMA_F32, -amdgpu_cdna_op_V_PK_LSHLREV_B16, -amdgpu_cdna_op_V_PK_LSHRREV_B16, -amdgpu_cdna_op_V_PK_MAD_I16, -amdgpu_cdna_op_V_PK_MAD_U16, -amdgpu_cdna_op_V_PK_MAX_F16, -amdgpu_cdna_op_V_PK_MAX_I16, -amdgpu_cdna_op_V_PK_MAX_U16, -amdgpu_cdna_op_V_PK_MIN_F16, -amdgpu_cdna_op_V_PK_MIN_I16, -amdgpu_cdna_op_V_PK_MIN_U16, -amdgpu_cdna_op_V_PK_MOV_B32, -amdgpu_cdna_op_V_PK_MUL_F16, -amdgpu_cdna_op_V_PK_MUL_F32, -amdgpu_cdna_op_V_PK_MUL_LO_U16, -amdgpu_cdna_op_V_PK_SUB_I16, -amdgpu_cdna_op_V_PK_SUB_U16, -amdgpu_cdna_op_V_QSAD_PK_U16_U8, -amdgpu_cdna_op_V_RCP_F16, -amdgpu_cdna_op_V_RCP_F32, -amdgpu_cdna_op_V_RCP_F64, -amdgpu_cdna_op_V_RCP_IFLAG_F32, -amdgpu_cdna_op_V_READFIRSTLANE_B32, -amdgpu_cdna_op_V_READLANE_B32, -amdgpu_cdna_op_V_RNDNE_F16, -amdgpu_cdna_op_V_RNDNE_F32, -amdgpu_cdna_op_V_RNDNE_F64, -amdgpu_cdna_op_V_RSQ_F16, -amdgpu_cdna_op_V_RSQ_F32, -amdgpu_cdna_op_V_RSQ_F64, -amdgpu_cdna_op_V_SAD_HI_U8, -amdgpu_cdna_op_V_SAD_U16, -amdgpu_cdna_op_V_SAD_U32, -amdgpu_cdna_op_V_SAD_U8, -amdgpu_cdna_op_V_SAT_PK_U8_I16, -amdgpu_cdna_op_V_SCREEN_PARTITION_4SE_B32, -amdgpu_cdna_op_V_SIN_F16, -amdgpu_cdna_op_V_SIN_F32, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X32_BF16, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X32_F16, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_BF8_BF8, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_BF8_FP8, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_FP8_BF8, -amdgpu_cdna_op_V_SMFMAC_F32_16X16X64_FP8_FP8, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X16_BF16, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X16_F16, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_BF8_BF8, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_BF8_FP8, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_FP8_BF8, -amdgpu_cdna_op_V_SMFMAC_F32_32X32X32_FP8_FP8, -amdgpu_cdna_op_V_SMFMAC_I32_16X16X64_I8, -amdgpu_cdna_op_V_SMFMAC_I32_32X32X32_I8, -amdgpu_cdna_op_V_SQRT_F16, -amdgpu_cdna_op_V_SQRT_F32, -amdgpu_cdna_op_V_SQRT_F64, -amdgpu_cdna_op_V_SUBBREV_CO_U32, -amdgpu_cdna_op_V_SUBB_CO_U32, -amdgpu_cdna_op_V_SUBREV_CO_U32, -amdgpu_cdna_op_V_SUBREV_F16, -amdgpu_cdna_op_V_SUBREV_F32, -amdgpu_cdna_op_V_SUBREV_U16, -amdgpu_cdna_op_V_SUBREV_U32, -amdgpu_cdna_op_V_SUB_CO_U32, -amdgpu_cdna_op_V_SUB_F16, -amdgpu_cdna_op_V_SUB_F32, -amdgpu_cdna_op_V_SUB_I16, -amdgpu_cdna_op_V_SUB_I32, -amdgpu_cdna_op_V_SUB_U16, -amdgpu_cdna_op_V_SUB_U32, -amdgpu_cdna_op_V_SWAP_B32, -amdgpu_cdna_op_V_TRIG_PREOP_F64, -amdgpu_cdna_op_V_TRUNC_F16, -amdgpu_cdna_op_V_TRUNC_F32, -amdgpu_cdna_op_V_TRUNC_F64, -amdgpu_cdna_op_V_WRITELANE_B32, -amdgpu_cdna_op_V_XAD_U32, -amdgpu_cdna_op_V_XNOR_B32, -amdgpu_cdna_op_V_XOR_B32, diff --git a/common/h/amdgpu_cdna_sys_regs.h b/common/h/amdgpu_cdna_sys_regs.h deleted file mode 100644 index c90bf12e57..0000000000 --- a/common/h/amdgpu_cdna_sys_regs.h +++ /dev/null @@ -1,1563 +0,0 @@ -#ifndef DYNINST_AMDGPU_CDNA_SYS_REGS_H -#define DYNINST_AMDGPU_CDNA_SYS_REGS_H -DEF_REGISTER(address_mode_32, Arch_amdgpu_cdna | HWR | BITS_32 | 0,"amdgpu_cdna"); -DEF_REGISTER(exec, Arch_amdgpu_cdna | HWR | BITS_64 | 1,"amdgpu_cdna"); -DEF_REGISTER(exec_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 1,"amdgpu_cdna"); -DEF_REGISTER(exec_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 1,"amdgpu_cdna"); -DEF_REGISTER(expcnt, Arch_amdgpu_cdna | HWR | BITS_3 | 2,"amdgpu_cdna"); -DEF_REGISTER(export_icount, Arch_amdgpu_cdna | HWR | BITS_8 | 3,"amdgpu_cdna"); -DEF_REGISTER(flat_scratch, Arch_amdgpu_cdna | HWR | BITS_64 | 4,"amdgpu_cdna"); -DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 4,"amdgpu_cdna"); -DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 4,"amdgpu_cdna"); -DEF_REGISTER(gpr_alloc, Arch_amdgpu_cdna | HWR | BITS_32 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr_base, Arch_amdgpu_cdna | 0x0 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpt_size, Arch_amdgpu_cdna | 0x80000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); -DEF_REGISTER(sgpr_base, Arch_amdgpu_cdna | 0x100000 | BITS_6 | 0x8000 | 5,"amdgpu_cdna"); -DEF_REGISTER(sgpr_size, Arch_amdgpu_cdna | 0x180000 | BITS_4 | 0x8000 | 5,"amdgpu_cdna"); -DEF_REGISTER(ib_sts, Arch_amdgpu_cdna | HWR | BITS_32 | 6,"amdgpu_cdna"); -DEF_REGISTER(exp_cnt, Arch_amdgpu_cdna | 0x40000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna"); -DEF_REGISTER(lgkm_cnt, Arch_amdgpu_cdna | 0x80000 | BITS_4 | 0x8000 | 6,"amdgpu_cdna"); -DEF_REGISTER(valu_cnt, Arch_amdgpu_cdna | 0xc0000 | BITS_3 | 0x8000 | 6,"amdgpu_cdna"); -DEF_REGISTER(vm_cnt, Arch_amdgpu_cdna | 0xf0000 | BITS_6 | 0x8000 | 6,"amdgpu_cdna"); -DEF_REGISTER(lds_alloc, Arch_amdgpu_cdna | HWR | BITS_32 | 7,"amdgpu_cdna"); -DEF_REGISTER(lds_base, Arch_amdgpu_cdna | 0x0 | BITS_8 | 0x8000 | 7,"amdgpu_cdna"); -DEF_REGISTER(lds_size, Arch_amdgpu_cdna | 0xc0000 | BITS_9 | 0x8000 | 7,"amdgpu_cdna"); -DEF_REGISTER(lds_gds_constant_message_count, Arch_amdgpu_cdna | HWR | BITS_8 | 8,"amdgpu_cdna"); -DEF_REGISTER(lgkmcnt, Arch_amdgpu_cdna | HWR | BITS_4 | 9,"amdgpu_cdna"); -DEF_REGISTER(m0, Arch_amdgpu_cdna | HWR | BITS_32 | 10,"amdgpu_cdna"); -DEF_REGISTER(gds_size, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(lds_direct_address, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(lds_interpolation_parameter_offset, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(lds_memory_vfetch_offset, Arch_amdgpu_cdna | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(lds_direct_data_type, Arch_amdgpu_cdna | 0x100000 | BITS_3 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(lds_interpolation_new_prim_mask, Arch_amdgpu_cdna | 0x100000 | BITS_15 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(gds_base, Arch_amdgpu_cdna | 0x100000 | BITS_16 | 0x8000 | 10,"amdgpu_cdna"); -DEF_REGISTER(mode, Arch_amdgpu_cdna | HWR | BITS_32 | 11,"amdgpu_cdna"); -DEF_REGISTER(fp_round, Arch_amdgpu_cdna | 0x0 | BITS_4 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(fp_denorm, Arch_amdgpu_cdna | 0x40000 | BITS_4 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(dx10_clamp, Arch_amdgpu_cdna | 0x80000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(ieee, Arch_amdgpu_cdna | 0x90000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(lod_clamped, Arch_amdgpu_cdna | 0xa0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(debug, Arch_amdgpu_cdna | 0xb0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(excp_en, Arch_amdgpu_cdna | 0xc0000 | BITS_7 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(fp16_ovfl, Arch_amdgpu_cdna | 0x170000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(pops_packer0, Arch_amdgpu_cdna | 0x180000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(pops_packer1, Arch_amdgpu_cdna | 0x190000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(disable_perf, Arch_amdgpu_cdna | 0x1a0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(gpr_idx_en, Arch_amdgpu_cdna | 0x1b0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(vskip, Arch_amdgpu_cdna | 0x1c0000 | BITS_1 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(csp, Arch_amdgpu_cdna | 0x1d0000 | BITS_3 | 0x8000 | 11,"amdgpu_cdna"); -DEF_REGISTER(pc, Arch_amdgpu_cdna | PC | BITS_48 | 0,"amdgpu_cdna"); -DEF_REGISTER(pops_exiting_wave_id, Arch_amdgpu_cdna | HWR | BITS_64 | 12,"amdgpu_cdna"); -DEF_REGISTER(private_base, Arch_amdgpu_cdna | HWR | BITS_64 | 13,"amdgpu_cdna"); -DEF_REGISTER(private_limit, Arch_amdgpu_cdna | HWR | BITS_64 | 14,"amdgpu_cdna"); -DEF_REGISTER(shared_base, Arch_amdgpu_cdna | HWR | BITS_64 | 15,"amdgpu_cdna"); -DEF_REGISTER(shared_limit, Arch_amdgpu_cdna | HWR | BITS_64 | 16,"amdgpu_cdna"); -DEF_REGISTER(status, Arch_amdgpu_cdna | HWR | BITS_32 | 17,"amdgpu_cdna"); -DEF_REGISTER(scc, Arch_amdgpu_cdna | 0x0 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(spi_prio, Arch_amdgpu_cdna | 0x10000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(wave_prio, Arch_amdgpu_cdna | 0x30000 | BITS_2 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(priv, Arch_amdgpu_cdna | 0x50000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(trap_en, Arch_amdgpu_cdna | 0x60000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(ttrace_en, Arch_amdgpu_cdna | 0x70000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(export_rdy, Arch_amdgpu_cdna | 0x80000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(execz, Arch_amdgpu_cdna | 0x90000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(vccz, Arch_amdgpu_cdna | 0xa0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(in_tg, Arch_amdgpu_cdna | 0xb0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(in_barrier, Arch_amdgpu_cdna | 0xc0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(halt, Arch_amdgpu_cdna | 0xd0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(trap, Arch_amdgpu_cdna | 0xe0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(ttrace_cu_en, Arch_amdgpu_cdna | 0xf0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(valid, Arch_amdgpu_cdna | 0x100000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(ecc_err, Arch_amdgpu_cdna | 0x110000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(skin_export, Arch_amdgpu_cdna | 0x120000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(perf_en, Arch_amdgpu_cdna | 0x130000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(cond_dbg_user, Arch_amdgpu_cdna | 0x140000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(cond_dbg_sys, Arch_amdgpu_cdna | 0x150000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(allow_replay, Arch_amdgpu_cdna | 0x160000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(must_export, Arch_amdgpu_cdna | 0x1b0000 | BITS_1 | 0x8000 | 17,"amdgpu_cdna"); -DEF_REGISTER(tba, Arch_amdgpu_cdna | HWR | BITS_64 | 18,"amdgpu_cdna"); -DEF_REGISTER(tid, Arch_amdgpu_cdna | HWR | BITS_32 | 19,"amdgpu_cdna"); -DEF_REGISTER(tma, Arch_amdgpu_cdna | HWR | BITS_64 | 20,"amdgpu_cdna"); -DEF_REGISTER(trap_base_address, Arch_amdgpu_cdna | HWR | BITS_64 | 21,"amdgpu_cdna"); -DEF_REGISTER(trap_memory_address, Arch_amdgpu_cdna | HWR | BITS_64 | 22,"amdgpu_cdna"); -DEF_REGISTER(ttmp0, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 0,"amdgpu_cdna"); -DEF_REGISTER(ttmp1, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 1,"amdgpu_cdna"); -DEF_REGISTER(ttmp10, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 2,"amdgpu_cdna"); -DEF_REGISTER(ttmp11, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 3,"amdgpu_cdna"); -DEF_REGISTER(ttmp12, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 4,"amdgpu_cdna"); -DEF_REGISTER(ttmp13, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 5,"amdgpu_cdna"); -DEF_REGISTER(ttmp14, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 6,"amdgpu_cdna"); -DEF_REGISTER(ttmp15, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 7,"amdgpu_cdna"); -DEF_REGISTER(ttmp2, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 8,"amdgpu_cdna"); -DEF_REGISTER(ttmp3, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 9,"amdgpu_cdna"); -DEF_REGISTER(ttmp4, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 10,"amdgpu_cdna"); -DEF_REGISTER(ttmp5, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 11,"amdgpu_cdna"); -DEF_REGISTER(ttmp6, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 12,"amdgpu_cdna"); -DEF_REGISTER(ttmp7, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 13,"amdgpu_cdna"); -DEF_REGISTER(ttmp8, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 14,"amdgpu_cdna"); -DEF_REGISTER(ttmp9, Arch_amdgpu_cdna | TTMP_SGPR | BITS_32 | 15,"amdgpu_cdna"); -DEF_REGISTER(vcc, Arch_amdgpu_cdna | HWR | BITS_64 | 23,"amdgpu_cdna"); -DEF_REGISTER(vcc_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 23,"amdgpu_cdna"); -DEF_REGISTER(vcc_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 23,"amdgpu_cdna"); -DEF_REGISTER(vectory_memory_icount, Arch_amdgpu_cdna | HWR | BITS_8 | 24,"amdgpu_cdna"); -DEF_REGISTER(vmcnt, Arch_amdgpu_cdna | HWR | BITS_6 | 25,"amdgpu_cdna"); -DEF_REGISTER(xnack_mask, Arch_amdgpu_cdna | HWR | BITS_64 | 26,"amdgpu_cdna"); -DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_cdna | 0x0 | BITS_32 | 0x8000 | 26,"amdgpu_cdna"); -DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_cdna | 0x200000 | BITS_32 | 0x8000 | 26,"amdgpu_cdna"); -DEF_REGISTER(sgpr0, Arch_amdgpu_cdna | SGPR | BITS_32 | 0,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_0, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_0, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_0, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_0, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna"); -DEF_REGISTER(sgpr1, Arch_amdgpu_cdna | SGPR | BITS_32 | 1,"amdgpu_cdna"); -DEF_REGISTER(sgpr2, Arch_amdgpu_cdna | SGPR | BITS_32 | 2,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_2, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna"); -DEF_REGISTER(sgpr3, Arch_amdgpu_cdna | SGPR | BITS_32 | 3,"amdgpu_cdna"); -DEF_REGISTER(sgpr4, Arch_amdgpu_cdna | SGPR | BITS_32 | 4,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_4, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_4, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna"); -DEF_REGISTER(sgpr5, Arch_amdgpu_cdna | SGPR | BITS_32 | 5,"amdgpu_cdna"); -DEF_REGISTER(sgpr6, Arch_amdgpu_cdna | SGPR | BITS_32 | 6,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_6, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna"); -DEF_REGISTER(sgpr7, Arch_amdgpu_cdna | SGPR | BITS_32 | 7,"amdgpu_cdna"); -DEF_REGISTER(sgpr8, Arch_amdgpu_cdna | SGPR | BITS_32 | 8,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_8, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_8, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_8, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna"); -DEF_REGISTER(sgpr9, Arch_amdgpu_cdna | SGPR | BITS_32 | 9,"amdgpu_cdna"); -DEF_REGISTER(sgpr10, Arch_amdgpu_cdna | SGPR | BITS_32 | 10,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_10, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna"); -DEF_REGISTER(sgpr11, Arch_amdgpu_cdna | SGPR | BITS_32 | 11,"amdgpu_cdna"); -DEF_REGISTER(sgpr12, Arch_amdgpu_cdna | SGPR | BITS_32 | 12,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_12, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_12, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna"); -DEF_REGISTER(sgpr13, Arch_amdgpu_cdna | SGPR | BITS_32 | 13,"amdgpu_cdna"); -DEF_REGISTER(sgpr14, Arch_amdgpu_cdna | SGPR | BITS_32 | 14,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_14, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna"); -DEF_REGISTER(sgpr15, Arch_amdgpu_cdna | SGPR | BITS_32 | 15,"amdgpu_cdna"); -DEF_REGISTER(sgpr16, Arch_amdgpu_cdna | SGPR | BITS_32 | 16,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_16, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_16, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_16, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_16, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna"); -DEF_REGISTER(sgpr17, Arch_amdgpu_cdna | SGPR | BITS_32 | 17,"amdgpu_cdna"); -DEF_REGISTER(sgpr18, Arch_amdgpu_cdna | SGPR | BITS_32 | 18,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_18, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna"); -DEF_REGISTER(sgpr19, Arch_amdgpu_cdna | SGPR | BITS_32 | 19,"amdgpu_cdna"); -DEF_REGISTER(sgpr20, Arch_amdgpu_cdna | SGPR | BITS_32 | 20,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_20, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_20, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna"); -DEF_REGISTER(sgpr21, Arch_amdgpu_cdna | SGPR | BITS_32 | 21,"amdgpu_cdna"); -DEF_REGISTER(sgpr22, Arch_amdgpu_cdna | SGPR | BITS_32 | 22,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_22, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna"); -DEF_REGISTER(sgpr23, Arch_amdgpu_cdna | SGPR | BITS_32 | 23,"amdgpu_cdna"); -DEF_REGISTER(sgpr24, Arch_amdgpu_cdna | SGPR | BITS_32 | 24,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_24, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_24, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_24, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna"); -DEF_REGISTER(sgpr25, Arch_amdgpu_cdna | SGPR | BITS_32 | 25,"amdgpu_cdna"); -DEF_REGISTER(sgpr26, Arch_amdgpu_cdna | SGPR | BITS_32 | 26,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_26, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna"); -DEF_REGISTER(sgpr27, Arch_amdgpu_cdna | SGPR | BITS_32 | 27,"amdgpu_cdna"); -DEF_REGISTER(sgpr28, Arch_amdgpu_cdna | SGPR | BITS_32 | 28,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_28, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_28, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna"); -DEF_REGISTER(sgpr29, Arch_amdgpu_cdna | SGPR | BITS_32 | 29,"amdgpu_cdna"); -DEF_REGISTER(sgpr30, Arch_amdgpu_cdna | SGPR | BITS_32 | 30,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_30, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna"); -DEF_REGISTER(sgpr31, Arch_amdgpu_cdna | SGPR | BITS_32 | 31,"amdgpu_cdna"); -DEF_REGISTER(sgpr32, Arch_amdgpu_cdna | SGPR | BITS_32 | 32,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_32, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_32, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_32, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_32, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna"); -DEF_REGISTER(sgpr33, Arch_amdgpu_cdna | SGPR | BITS_32 | 33,"amdgpu_cdna"); -DEF_REGISTER(sgpr34, Arch_amdgpu_cdna | SGPR | BITS_32 | 34,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_34, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna"); -DEF_REGISTER(sgpr35, Arch_amdgpu_cdna | SGPR | BITS_32 | 35,"amdgpu_cdna"); -DEF_REGISTER(sgpr36, Arch_amdgpu_cdna | SGPR | BITS_32 | 36,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_36, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_36, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna"); -DEF_REGISTER(sgpr37, Arch_amdgpu_cdna | SGPR | BITS_32 | 37,"amdgpu_cdna"); -DEF_REGISTER(sgpr38, Arch_amdgpu_cdna | SGPR | BITS_32 | 38,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_38, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna"); -DEF_REGISTER(sgpr39, Arch_amdgpu_cdna | SGPR | BITS_32 | 39,"amdgpu_cdna"); -DEF_REGISTER(sgpr40, Arch_amdgpu_cdna | SGPR | BITS_32 | 40,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_40, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_40, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_40, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna"); -DEF_REGISTER(sgpr41, Arch_amdgpu_cdna | SGPR | BITS_32 | 41,"amdgpu_cdna"); -DEF_REGISTER(sgpr42, Arch_amdgpu_cdna | SGPR | BITS_32 | 42,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_42, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna"); -DEF_REGISTER(sgpr43, Arch_amdgpu_cdna | SGPR | BITS_32 | 43,"amdgpu_cdna"); -DEF_REGISTER(sgpr44, Arch_amdgpu_cdna | SGPR | BITS_32 | 44,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_44, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_44, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna"); -DEF_REGISTER(sgpr45, Arch_amdgpu_cdna | SGPR | BITS_32 | 45,"amdgpu_cdna"); -DEF_REGISTER(sgpr46, Arch_amdgpu_cdna | SGPR | BITS_32 | 46,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_46, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna"); -DEF_REGISTER(sgpr47, Arch_amdgpu_cdna | SGPR | BITS_32 | 47,"amdgpu_cdna"); -DEF_REGISTER(sgpr48, Arch_amdgpu_cdna | SGPR | BITS_32 | 48,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_48, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_48, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_48, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_48, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna"); -DEF_REGISTER(sgpr49, Arch_amdgpu_cdna | SGPR | BITS_32 | 49,"amdgpu_cdna"); -DEF_REGISTER(sgpr50, Arch_amdgpu_cdna | SGPR | BITS_32 | 50,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_50, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna"); -DEF_REGISTER(sgpr51, Arch_amdgpu_cdna | SGPR | BITS_32 | 51,"amdgpu_cdna"); -DEF_REGISTER(sgpr52, Arch_amdgpu_cdna | SGPR | BITS_32 | 52,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_52, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_52, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna"); -DEF_REGISTER(sgpr53, Arch_amdgpu_cdna | SGPR | BITS_32 | 53,"amdgpu_cdna"); -DEF_REGISTER(sgpr54, Arch_amdgpu_cdna | SGPR | BITS_32 | 54,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_54, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna"); -DEF_REGISTER(sgpr55, Arch_amdgpu_cdna | SGPR | BITS_32 | 55,"amdgpu_cdna"); -DEF_REGISTER(sgpr56, Arch_amdgpu_cdna | SGPR | BITS_32 | 56,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_56, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_56, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_56, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna"); -DEF_REGISTER(sgpr57, Arch_amdgpu_cdna | SGPR | BITS_32 | 57,"amdgpu_cdna"); -DEF_REGISTER(sgpr58, Arch_amdgpu_cdna | SGPR | BITS_32 | 58,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_58, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna"); -DEF_REGISTER(sgpr59, Arch_amdgpu_cdna | SGPR | BITS_32 | 59,"amdgpu_cdna"); -DEF_REGISTER(sgpr60, Arch_amdgpu_cdna | SGPR | BITS_32 | 60,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_60, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_60, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna"); -DEF_REGISTER(sgpr61, Arch_amdgpu_cdna | SGPR | BITS_32 | 61,"amdgpu_cdna"); -DEF_REGISTER(sgpr62, Arch_amdgpu_cdna | SGPR | BITS_32 | 62,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_62, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna"); -DEF_REGISTER(sgpr63, Arch_amdgpu_cdna | SGPR | BITS_32 | 63,"amdgpu_cdna"); -DEF_REGISTER(sgpr64, Arch_amdgpu_cdna | SGPR | BITS_32 | 64,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_64, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_64, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_64, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_64, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna"); -DEF_REGISTER(sgpr65, Arch_amdgpu_cdna | SGPR | BITS_32 | 65,"amdgpu_cdna"); -DEF_REGISTER(sgpr66, Arch_amdgpu_cdna | SGPR | BITS_32 | 66,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_66, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna"); -DEF_REGISTER(sgpr67, Arch_amdgpu_cdna | SGPR | BITS_32 | 67,"amdgpu_cdna"); -DEF_REGISTER(sgpr68, Arch_amdgpu_cdna | SGPR | BITS_32 | 68,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_68, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_68, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna"); -DEF_REGISTER(sgpr69, Arch_amdgpu_cdna | SGPR | BITS_32 | 69,"amdgpu_cdna"); -DEF_REGISTER(sgpr70, Arch_amdgpu_cdna | SGPR | BITS_32 | 70,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_70, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna"); -DEF_REGISTER(sgpr71, Arch_amdgpu_cdna | SGPR | BITS_32 | 71,"amdgpu_cdna"); -DEF_REGISTER(sgpr72, Arch_amdgpu_cdna | SGPR | BITS_32 | 72,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_72, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_72, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_72, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna"); -DEF_REGISTER(sgpr73, Arch_amdgpu_cdna | SGPR | BITS_32 | 73,"amdgpu_cdna"); -DEF_REGISTER(sgpr74, Arch_amdgpu_cdna | SGPR | BITS_32 | 74,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_74, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna"); -DEF_REGISTER(sgpr75, Arch_amdgpu_cdna | SGPR | BITS_32 | 75,"amdgpu_cdna"); -DEF_REGISTER(sgpr76, Arch_amdgpu_cdna | SGPR | BITS_32 | 76,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_76, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_76, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna"); -DEF_REGISTER(sgpr77, Arch_amdgpu_cdna | SGPR | BITS_32 | 77,"amdgpu_cdna"); -DEF_REGISTER(sgpr78, Arch_amdgpu_cdna | SGPR | BITS_32 | 78,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_78, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna"); -DEF_REGISTER(sgpr79, Arch_amdgpu_cdna | SGPR | BITS_32 | 79,"amdgpu_cdna"); -DEF_REGISTER(sgpr80, Arch_amdgpu_cdna | SGPR | BITS_32 | 80,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_80, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_80, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_80, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec16_80, Arch_amdgpu_cdna | SGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna"); -DEF_REGISTER(sgpr81, Arch_amdgpu_cdna | SGPR | BITS_32 | 81,"amdgpu_cdna"); -DEF_REGISTER(sgpr82, Arch_amdgpu_cdna | SGPR | BITS_32 | 82,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_82, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna"); -DEF_REGISTER(sgpr83, Arch_amdgpu_cdna | SGPR | BITS_32 | 83,"amdgpu_cdna"); -DEF_REGISTER(sgpr84, Arch_amdgpu_cdna | SGPR | BITS_32 | 84,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_84, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_84, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna"); -DEF_REGISTER(sgpr85, Arch_amdgpu_cdna | SGPR | BITS_32 | 85,"amdgpu_cdna"); -DEF_REGISTER(sgpr86, Arch_amdgpu_cdna | SGPR | BITS_32 | 86,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_86, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna"); -DEF_REGISTER(sgpr87, Arch_amdgpu_cdna | SGPR | BITS_32 | 87,"amdgpu_cdna"); -DEF_REGISTER(sgpr88, Arch_amdgpu_cdna | SGPR | BITS_32 | 88,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_88, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_88, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_88, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna"); -DEF_REGISTER(sgpr89, Arch_amdgpu_cdna | SGPR | BITS_32 | 89,"amdgpu_cdna"); -DEF_REGISTER(sgpr90, Arch_amdgpu_cdna | SGPR | BITS_32 | 90,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_90, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna"); -DEF_REGISTER(sgpr91, Arch_amdgpu_cdna | SGPR | BITS_32 | 91,"amdgpu_cdna"); -DEF_REGISTER(sgpr92, Arch_amdgpu_cdna | SGPR | BITS_32 | 92,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_92, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_92, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna"); -DEF_REGISTER(sgpr93, Arch_amdgpu_cdna | SGPR | BITS_32 | 93,"amdgpu_cdna"); -DEF_REGISTER(sgpr94, Arch_amdgpu_cdna | SGPR | BITS_32 | 94,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_94, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna"); -DEF_REGISTER(sgpr95, Arch_amdgpu_cdna | SGPR | BITS_32 | 95,"amdgpu_cdna"); -DEF_REGISTER(sgpr96, Arch_amdgpu_cdna | SGPR | BITS_32 | 96,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_96, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_96, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec8_96, Arch_amdgpu_cdna | SGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna"); -DEF_REGISTER(sgpr97, Arch_amdgpu_cdna | SGPR | BITS_32 | 97,"amdgpu_cdna"); -DEF_REGISTER(sgpr98, Arch_amdgpu_cdna | SGPR | BITS_32 | 98,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_98, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna"); -DEF_REGISTER(sgpr99, Arch_amdgpu_cdna | SGPR | BITS_32 | 99,"amdgpu_cdna"); -DEF_REGISTER(sgpr100, Arch_amdgpu_cdna | SGPR | BITS_32 | 100,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_100, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec4_100, Arch_amdgpu_cdna | SGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna"); -DEF_REGISTER(sgpr101, Arch_amdgpu_cdna | SGPR | BITS_32 | 101,"amdgpu_cdna"); -DEF_REGISTER(sgpr102, Arch_amdgpu_cdna | SGPR | BITS_32 | 102,"amdgpu_cdna"); -DEF_REGISTER(sgpr_vec2_102, Arch_amdgpu_cdna | SGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna"); -DEF_REGISTER(sgpr103, Arch_amdgpu_cdna | SGPR | BITS_32 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr0, Arch_amdgpu_cdna | VGPR | BITS_32 | 0,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_0, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 0,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_0, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 0,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_0, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 0,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_0, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 0,"amdgpu_cdna"); -DEF_REGISTER(vgpr1, Arch_amdgpu_cdna | VGPR | BITS_32 | 1,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_1, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 1,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_1, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 1,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_1, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 1,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_1, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 1,"amdgpu_cdna"); -DEF_REGISTER(vgpr2, Arch_amdgpu_cdna | VGPR | BITS_32 | 2,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_2, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 2,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_2, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 2,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_2, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 2,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_2, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 2,"amdgpu_cdna"); -DEF_REGISTER(vgpr3, Arch_amdgpu_cdna | VGPR | BITS_32 | 3,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_3, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 3,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_3, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 3,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_3, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 3,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_3, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 3,"amdgpu_cdna"); -DEF_REGISTER(vgpr4, Arch_amdgpu_cdna | VGPR | BITS_32 | 4,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_4, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 4,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_4, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 4,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_4, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 4,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_4, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 4,"amdgpu_cdna"); -DEF_REGISTER(vgpr5, Arch_amdgpu_cdna | VGPR | BITS_32 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_5, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_5, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_5, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_5, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 5,"amdgpu_cdna"); -DEF_REGISTER(vgpr6, Arch_amdgpu_cdna | VGPR | BITS_32 | 6,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_6, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 6,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_6, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 6,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_6, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 6,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_6, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 6,"amdgpu_cdna"); -DEF_REGISTER(vgpr7, Arch_amdgpu_cdna | VGPR | BITS_32 | 7,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_7, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 7,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_7, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 7,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_7, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 7,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_7, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 7,"amdgpu_cdna"); -DEF_REGISTER(vgpr8, Arch_amdgpu_cdna | VGPR | BITS_32 | 8,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_8, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 8,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_8, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 8,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_8, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 8,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_8, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 8,"amdgpu_cdna"); -DEF_REGISTER(vgpr9, Arch_amdgpu_cdna | VGPR | BITS_32 | 9,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_9, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 9,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_9, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 9,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_9, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 9,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_9, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 9,"amdgpu_cdna"); -DEF_REGISTER(vgpr10, Arch_amdgpu_cdna | VGPR | BITS_32 | 10,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_10, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 10,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_10, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 10,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_10, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 10,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_10, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 10,"amdgpu_cdna"); -DEF_REGISTER(vgpr11, Arch_amdgpu_cdna | VGPR | BITS_32 | 11,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_11, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 11,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_11, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 11,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_11, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 11,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_11, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 11,"amdgpu_cdna"); -DEF_REGISTER(vgpr12, Arch_amdgpu_cdna | VGPR | BITS_32 | 12,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_12, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 12,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_12, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 12,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_12, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 12,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_12, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 12,"amdgpu_cdna"); -DEF_REGISTER(vgpr13, Arch_amdgpu_cdna | VGPR | BITS_32 | 13,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_13, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 13,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_13, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 13,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_13, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 13,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_13, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 13,"amdgpu_cdna"); -DEF_REGISTER(vgpr14, Arch_amdgpu_cdna | VGPR | BITS_32 | 14,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_14, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 14,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_14, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 14,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_14, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 14,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_14, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 14,"amdgpu_cdna"); -DEF_REGISTER(vgpr15, Arch_amdgpu_cdna | VGPR | BITS_32 | 15,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_15, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 15,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_15, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 15,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_15, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 15,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_15, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 15,"amdgpu_cdna"); -DEF_REGISTER(vgpr16, Arch_amdgpu_cdna | VGPR | BITS_32 | 16,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_16, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 16,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_16, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 16,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_16, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 16,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_16, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 16,"amdgpu_cdna"); -DEF_REGISTER(vgpr17, Arch_amdgpu_cdna | VGPR | BITS_32 | 17,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_17, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 17,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_17, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 17,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_17, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 17,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_17, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 17,"amdgpu_cdna"); -DEF_REGISTER(vgpr18, Arch_amdgpu_cdna | VGPR | BITS_32 | 18,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_18, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 18,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_18, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 18,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_18, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 18,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_18, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 18,"amdgpu_cdna"); -DEF_REGISTER(vgpr19, Arch_amdgpu_cdna | VGPR | BITS_32 | 19,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_19, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 19,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_19, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 19,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_19, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 19,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_19, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 19,"amdgpu_cdna"); -DEF_REGISTER(vgpr20, Arch_amdgpu_cdna | VGPR | BITS_32 | 20,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_20, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 20,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_20, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 20,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_20, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 20,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_20, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 20,"amdgpu_cdna"); -DEF_REGISTER(vgpr21, Arch_amdgpu_cdna | VGPR | BITS_32 | 21,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_21, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 21,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_21, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 21,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_21, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 21,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_21, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 21,"amdgpu_cdna"); -DEF_REGISTER(vgpr22, Arch_amdgpu_cdna | VGPR | BITS_32 | 22,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_22, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 22,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_22, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 22,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_22, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 22,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_22, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 22,"amdgpu_cdna"); -DEF_REGISTER(vgpr23, Arch_amdgpu_cdna | VGPR | BITS_32 | 23,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_23, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 23,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_23, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 23,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_23, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 23,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_23, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 23,"amdgpu_cdna"); -DEF_REGISTER(vgpr24, Arch_amdgpu_cdna | VGPR | BITS_32 | 24,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_24, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 24,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_24, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 24,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_24, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 24,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_24, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 24,"amdgpu_cdna"); -DEF_REGISTER(vgpr25, Arch_amdgpu_cdna | VGPR | BITS_32 | 25,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_25, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 25,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_25, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 25,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_25, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 25,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_25, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 25,"amdgpu_cdna"); -DEF_REGISTER(vgpr26, Arch_amdgpu_cdna | VGPR | BITS_32 | 26,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_26, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 26,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_26, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 26,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_26, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 26,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_26, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 26,"amdgpu_cdna"); -DEF_REGISTER(vgpr27, Arch_amdgpu_cdna | VGPR | BITS_32 | 27,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_27, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 27,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_27, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 27,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_27, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 27,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_27, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 27,"amdgpu_cdna"); -DEF_REGISTER(vgpr28, Arch_amdgpu_cdna | VGPR | BITS_32 | 28,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_28, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 28,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_28, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 28,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_28, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 28,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_28, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 28,"amdgpu_cdna"); -DEF_REGISTER(vgpr29, Arch_amdgpu_cdna | VGPR | BITS_32 | 29,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_29, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 29,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_29, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 29,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_29, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 29,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_29, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 29,"amdgpu_cdna"); -DEF_REGISTER(vgpr30, Arch_amdgpu_cdna | VGPR | BITS_32 | 30,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_30, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 30,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_30, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 30,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_30, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 30,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_30, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 30,"amdgpu_cdna"); -DEF_REGISTER(vgpr31, Arch_amdgpu_cdna | VGPR | BITS_32 | 31,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_31, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 31,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_31, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 31,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_31, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 31,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_31, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 31,"amdgpu_cdna"); -DEF_REGISTER(vgpr32, Arch_amdgpu_cdna | VGPR | BITS_32 | 32,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_32, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 32,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_32, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 32,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_32, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 32,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_32, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 32,"amdgpu_cdna"); -DEF_REGISTER(vgpr33, Arch_amdgpu_cdna | VGPR | BITS_32 | 33,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_33, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 33,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_33, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 33,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_33, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 33,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_33, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 33,"amdgpu_cdna"); -DEF_REGISTER(vgpr34, Arch_amdgpu_cdna | VGPR | BITS_32 | 34,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_34, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 34,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_34, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 34,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_34, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 34,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_34, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 34,"amdgpu_cdna"); -DEF_REGISTER(vgpr35, Arch_amdgpu_cdna | VGPR | BITS_32 | 35,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_35, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 35,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_35, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 35,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_35, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 35,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_35, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 35,"amdgpu_cdna"); -DEF_REGISTER(vgpr36, Arch_amdgpu_cdna | VGPR | BITS_32 | 36,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_36, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 36,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_36, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 36,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_36, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 36,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_36, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 36,"amdgpu_cdna"); -DEF_REGISTER(vgpr37, Arch_amdgpu_cdna | VGPR | BITS_32 | 37,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_37, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 37,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_37, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 37,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_37, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 37,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_37, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 37,"amdgpu_cdna"); -DEF_REGISTER(vgpr38, Arch_amdgpu_cdna | VGPR | BITS_32 | 38,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_38, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 38,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_38, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 38,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_38, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 38,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_38, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 38,"amdgpu_cdna"); -DEF_REGISTER(vgpr39, Arch_amdgpu_cdna | VGPR | BITS_32 | 39,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_39, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 39,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_39, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 39,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_39, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 39,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_39, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 39,"amdgpu_cdna"); -DEF_REGISTER(vgpr40, Arch_amdgpu_cdna | VGPR | BITS_32 | 40,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_40, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 40,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_40, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 40,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_40, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 40,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_40, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 40,"amdgpu_cdna"); -DEF_REGISTER(vgpr41, Arch_amdgpu_cdna | VGPR | BITS_32 | 41,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_41, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 41,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_41, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 41,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_41, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 41,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_41, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 41,"amdgpu_cdna"); -DEF_REGISTER(vgpr42, Arch_amdgpu_cdna | VGPR | BITS_32 | 42,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_42, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 42,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_42, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 42,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_42, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 42,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_42, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 42,"amdgpu_cdna"); -DEF_REGISTER(vgpr43, Arch_amdgpu_cdna | VGPR | BITS_32 | 43,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_43, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 43,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_43, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 43,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_43, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 43,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_43, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 43,"amdgpu_cdna"); -DEF_REGISTER(vgpr44, Arch_amdgpu_cdna | VGPR | BITS_32 | 44,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_44, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 44,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_44, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 44,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_44, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 44,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_44, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 44,"amdgpu_cdna"); -DEF_REGISTER(vgpr45, Arch_amdgpu_cdna | VGPR | BITS_32 | 45,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_45, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 45,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_45, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 45,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_45, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 45,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_45, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 45,"amdgpu_cdna"); -DEF_REGISTER(vgpr46, Arch_amdgpu_cdna | VGPR | BITS_32 | 46,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_46, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 46,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_46, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 46,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_46, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 46,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_46, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 46,"amdgpu_cdna"); -DEF_REGISTER(vgpr47, Arch_amdgpu_cdna | VGPR | BITS_32 | 47,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_47, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 47,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_47, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 47,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_47, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 47,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_47, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 47,"amdgpu_cdna"); -DEF_REGISTER(vgpr48, Arch_amdgpu_cdna | VGPR | BITS_32 | 48,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_48, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 48,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_48, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 48,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_48, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 48,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_48, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 48,"amdgpu_cdna"); -DEF_REGISTER(vgpr49, Arch_amdgpu_cdna | VGPR | BITS_32 | 49,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_49, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 49,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_49, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 49,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_49, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 49,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_49, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 49,"amdgpu_cdna"); -DEF_REGISTER(vgpr50, Arch_amdgpu_cdna | VGPR | BITS_32 | 50,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_50, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 50,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_50, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 50,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_50, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 50,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_50, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 50,"amdgpu_cdna"); -DEF_REGISTER(vgpr51, Arch_amdgpu_cdna | VGPR | BITS_32 | 51,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_51, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 51,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_51, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 51,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_51, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 51,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_51, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 51,"amdgpu_cdna"); -DEF_REGISTER(vgpr52, Arch_amdgpu_cdna | VGPR | BITS_32 | 52,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_52, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 52,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_52, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 52,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_52, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 52,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_52, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 52,"amdgpu_cdna"); -DEF_REGISTER(vgpr53, Arch_amdgpu_cdna | VGPR | BITS_32 | 53,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_53, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 53,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_53, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 53,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_53, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 53,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_53, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 53,"amdgpu_cdna"); -DEF_REGISTER(vgpr54, Arch_amdgpu_cdna | VGPR | BITS_32 | 54,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_54, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 54,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_54, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 54,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_54, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 54,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_54, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 54,"amdgpu_cdna"); -DEF_REGISTER(vgpr55, Arch_amdgpu_cdna | VGPR | BITS_32 | 55,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_55, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 55,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_55, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 55,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_55, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 55,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_55, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 55,"amdgpu_cdna"); -DEF_REGISTER(vgpr56, Arch_amdgpu_cdna | VGPR | BITS_32 | 56,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_56, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 56,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_56, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 56,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_56, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 56,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_56, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 56,"amdgpu_cdna"); -DEF_REGISTER(vgpr57, Arch_amdgpu_cdna | VGPR | BITS_32 | 57,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_57, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 57,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_57, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 57,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_57, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 57,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_57, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 57,"amdgpu_cdna"); -DEF_REGISTER(vgpr58, Arch_amdgpu_cdna | VGPR | BITS_32 | 58,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_58, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 58,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_58, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 58,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_58, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 58,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_58, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 58,"amdgpu_cdna"); -DEF_REGISTER(vgpr59, Arch_amdgpu_cdna | VGPR | BITS_32 | 59,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_59, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 59,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_59, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 59,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_59, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 59,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_59, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 59,"amdgpu_cdna"); -DEF_REGISTER(vgpr60, Arch_amdgpu_cdna | VGPR | BITS_32 | 60,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_60, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 60,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_60, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 60,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_60, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 60,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_60, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 60,"amdgpu_cdna"); -DEF_REGISTER(vgpr61, Arch_amdgpu_cdna | VGPR | BITS_32 | 61,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_61, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 61,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_61, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 61,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_61, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 61,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_61, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 61,"amdgpu_cdna"); -DEF_REGISTER(vgpr62, Arch_amdgpu_cdna | VGPR | BITS_32 | 62,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_62, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 62,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_62, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 62,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_62, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 62,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_62, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 62,"amdgpu_cdna"); -DEF_REGISTER(vgpr63, Arch_amdgpu_cdna | VGPR | BITS_32 | 63,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_63, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 63,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_63, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 63,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_63, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 63,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_63, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 63,"amdgpu_cdna"); -DEF_REGISTER(vgpr64, Arch_amdgpu_cdna | VGPR | BITS_32 | 64,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_64, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 64,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_64, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 64,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_64, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 64,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_64, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 64,"amdgpu_cdna"); -DEF_REGISTER(vgpr65, Arch_amdgpu_cdna | VGPR | BITS_32 | 65,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_65, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 65,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_65, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 65,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_65, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 65,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_65, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 65,"amdgpu_cdna"); -DEF_REGISTER(vgpr66, Arch_amdgpu_cdna | VGPR | BITS_32 | 66,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_66, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 66,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_66, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 66,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_66, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 66,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_66, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 66,"amdgpu_cdna"); -DEF_REGISTER(vgpr67, Arch_amdgpu_cdna | VGPR | BITS_32 | 67,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_67, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 67,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_67, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 67,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_67, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 67,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_67, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 67,"amdgpu_cdna"); -DEF_REGISTER(vgpr68, Arch_amdgpu_cdna | VGPR | BITS_32 | 68,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_68, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 68,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_68, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 68,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_68, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 68,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_68, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 68,"amdgpu_cdna"); -DEF_REGISTER(vgpr69, Arch_amdgpu_cdna | VGPR | BITS_32 | 69,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_69, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 69,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_69, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 69,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_69, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 69,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_69, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 69,"amdgpu_cdna"); -DEF_REGISTER(vgpr70, Arch_amdgpu_cdna | VGPR | BITS_32 | 70,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_70, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 70,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_70, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 70,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_70, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 70,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_70, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 70,"amdgpu_cdna"); -DEF_REGISTER(vgpr71, Arch_amdgpu_cdna | VGPR | BITS_32 | 71,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_71, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 71,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_71, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 71,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_71, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 71,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_71, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 71,"amdgpu_cdna"); -DEF_REGISTER(vgpr72, Arch_amdgpu_cdna | VGPR | BITS_32 | 72,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_72, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 72,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_72, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 72,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_72, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 72,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_72, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 72,"amdgpu_cdna"); -DEF_REGISTER(vgpr73, Arch_amdgpu_cdna | VGPR | BITS_32 | 73,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_73, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 73,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_73, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 73,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_73, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 73,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_73, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 73,"amdgpu_cdna"); -DEF_REGISTER(vgpr74, Arch_amdgpu_cdna | VGPR | BITS_32 | 74,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_74, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 74,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_74, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 74,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_74, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 74,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_74, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 74,"amdgpu_cdna"); -DEF_REGISTER(vgpr75, Arch_amdgpu_cdna | VGPR | BITS_32 | 75,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_75, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 75,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_75, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 75,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_75, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 75,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_75, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 75,"amdgpu_cdna"); -DEF_REGISTER(vgpr76, Arch_amdgpu_cdna | VGPR | BITS_32 | 76,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_76, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 76,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_76, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 76,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_76, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 76,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_76, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 76,"amdgpu_cdna"); -DEF_REGISTER(vgpr77, Arch_amdgpu_cdna | VGPR | BITS_32 | 77,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_77, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 77,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_77, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 77,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_77, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 77,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_77, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 77,"amdgpu_cdna"); -DEF_REGISTER(vgpr78, Arch_amdgpu_cdna | VGPR | BITS_32 | 78,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_78, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 78,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_78, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 78,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_78, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 78,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_78, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 78,"amdgpu_cdna"); -DEF_REGISTER(vgpr79, Arch_amdgpu_cdna | VGPR | BITS_32 | 79,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_79, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 79,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_79, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 79,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_79, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 79,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_79, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 79,"amdgpu_cdna"); -DEF_REGISTER(vgpr80, Arch_amdgpu_cdna | VGPR | BITS_32 | 80,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_80, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 80,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_80, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 80,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_80, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 80,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_80, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 80,"amdgpu_cdna"); -DEF_REGISTER(vgpr81, Arch_amdgpu_cdna | VGPR | BITS_32 | 81,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_81, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 81,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_81, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 81,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_81, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 81,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_81, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 81,"amdgpu_cdna"); -DEF_REGISTER(vgpr82, Arch_amdgpu_cdna | VGPR | BITS_32 | 82,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_82, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 82,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_82, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 82,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_82, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 82,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_82, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 82,"amdgpu_cdna"); -DEF_REGISTER(vgpr83, Arch_amdgpu_cdna | VGPR | BITS_32 | 83,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_83, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 83,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_83, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 83,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_83, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 83,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_83, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 83,"amdgpu_cdna"); -DEF_REGISTER(vgpr84, Arch_amdgpu_cdna | VGPR | BITS_32 | 84,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_84, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 84,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_84, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 84,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_84, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 84,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_84, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 84,"amdgpu_cdna"); -DEF_REGISTER(vgpr85, Arch_amdgpu_cdna | VGPR | BITS_32 | 85,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_85, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 85,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_85, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 85,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_85, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 85,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_85, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 85,"amdgpu_cdna"); -DEF_REGISTER(vgpr86, Arch_amdgpu_cdna | VGPR | BITS_32 | 86,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_86, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 86,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_86, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 86,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_86, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 86,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_86, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 86,"amdgpu_cdna"); -DEF_REGISTER(vgpr87, Arch_amdgpu_cdna | VGPR | BITS_32 | 87,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_87, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 87,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_87, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 87,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_87, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 87,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_87, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 87,"amdgpu_cdna"); -DEF_REGISTER(vgpr88, Arch_amdgpu_cdna | VGPR | BITS_32 | 88,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_88, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 88,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_88, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 88,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_88, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 88,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_88, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 88,"amdgpu_cdna"); -DEF_REGISTER(vgpr89, Arch_amdgpu_cdna | VGPR | BITS_32 | 89,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_89, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 89,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_89, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 89,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_89, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 89,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_89, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 89,"amdgpu_cdna"); -DEF_REGISTER(vgpr90, Arch_amdgpu_cdna | VGPR | BITS_32 | 90,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_90, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 90,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_90, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 90,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_90, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 90,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_90, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 90,"amdgpu_cdna"); -DEF_REGISTER(vgpr91, Arch_amdgpu_cdna | VGPR | BITS_32 | 91,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_91, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 91,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_91, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 91,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_91, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 91,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_91, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 91,"amdgpu_cdna"); -DEF_REGISTER(vgpr92, Arch_amdgpu_cdna | VGPR | BITS_32 | 92,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_92, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 92,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_92, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 92,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_92, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 92,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_92, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 92,"amdgpu_cdna"); -DEF_REGISTER(vgpr93, Arch_amdgpu_cdna | VGPR | BITS_32 | 93,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_93, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 93,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_93, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 93,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_93, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 93,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_93, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 93,"amdgpu_cdna"); -DEF_REGISTER(vgpr94, Arch_amdgpu_cdna | VGPR | BITS_32 | 94,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_94, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 94,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_94, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 94,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_94, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 94,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_94, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 94,"amdgpu_cdna"); -DEF_REGISTER(vgpr95, Arch_amdgpu_cdna | VGPR | BITS_32 | 95,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_95, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 95,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_95, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 95,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_95, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 95,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_95, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 95,"amdgpu_cdna"); -DEF_REGISTER(vgpr96, Arch_amdgpu_cdna | VGPR | BITS_32 | 96,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_96, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 96,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_96, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 96,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_96, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 96,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_96, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 96,"amdgpu_cdna"); -DEF_REGISTER(vgpr97, Arch_amdgpu_cdna | VGPR | BITS_32 | 97,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_97, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 97,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_97, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 97,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_97, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 97,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_97, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 97,"amdgpu_cdna"); -DEF_REGISTER(vgpr98, Arch_amdgpu_cdna | VGPR | BITS_32 | 98,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_98, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 98,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_98, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 98,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_98, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 98,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_98, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 98,"amdgpu_cdna"); -DEF_REGISTER(vgpr99, Arch_amdgpu_cdna | VGPR | BITS_32 | 99,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_99, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 99,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_99, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 99,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_99, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 99,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_99, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 99,"amdgpu_cdna"); -DEF_REGISTER(vgpr100, Arch_amdgpu_cdna | VGPR | BITS_32 | 100,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_100, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 100,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_100, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 100,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_100, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 100,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_100, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 100,"amdgpu_cdna"); -DEF_REGISTER(vgpr101, Arch_amdgpu_cdna | VGPR | BITS_32 | 101,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_101, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 101,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_101, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 101,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_101, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 101,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_101, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 101,"amdgpu_cdna"); -DEF_REGISTER(vgpr102, Arch_amdgpu_cdna | VGPR | BITS_32 | 102,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_102, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 102,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_102, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 102,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_102, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 102,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_102, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 102,"amdgpu_cdna"); -DEF_REGISTER(vgpr103, Arch_amdgpu_cdna | VGPR | BITS_32 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_103, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_103, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_103, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_103, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 103,"amdgpu_cdna"); -DEF_REGISTER(vgpr104, Arch_amdgpu_cdna | VGPR | BITS_32 | 104,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_104, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 104,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_104, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 104,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_104, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 104,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_104, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 104,"amdgpu_cdna"); -DEF_REGISTER(vgpr105, Arch_amdgpu_cdna | VGPR | BITS_32 | 105,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_105, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 105,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_105, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 105,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_105, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 105,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_105, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 105,"amdgpu_cdna"); -DEF_REGISTER(vgpr106, Arch_amdgpu_cdna | VGPR | BITS_32 | 106,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_106, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 106,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_106, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 106,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_106, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 106,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_106, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 106,"amdgpu_cdna"); -DEF_REGISTER(vgpr107, Arch_amdgpu_cdna | VGPR | BITS_32 | 107,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_107, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 107,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_107, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 107,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_107, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 107,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_107, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 107,"amdgpu_cdna"); -DEF_REGISTER(vgpr108, Arch_amdgpu_cdna | VGPR | BITS_32 | 108,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_108, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 108,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_108, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 108,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_108, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 108,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_108, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 108,"amdgpu_cdna"); -DEF_REGISTER(vgpr109, Arch_amdgpu_cdna | VGPR | BITS_32 | 109,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_109, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 109,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_109, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 109,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_109, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 109,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_109, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 109,"amdgpu_cdna"); -DEF_REGISTER(vgpr110, Arch_amdgpu_cdna | VGPR | BITS_32 | 110,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_110, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 110,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_110, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 110,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_110, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 110,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_110, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 110,"amdgpu_cdna"); -DEF_REGISTER(vgpr111, Arch_amdgpu_cdna | VGPR | BITS_32 | 111,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_111, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 111,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_111, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 111,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_111, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 111,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_111, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 111,"amdgpu_cdna"); -DEF_REGISTER(vgpr112, Arch_amdgpu_cdna | VGPR | BITS_32 | 112,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_112, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 112,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_112, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 112,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_112, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 112,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_112, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 112,"amdgpu_cdna"); -DEF_REGISTER(vgpr113, Arch_amdgpu_cdna | VGPR | BITS_32 | 113,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_113, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 113,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_113, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 113,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_113, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 113,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_113, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 113,"amdgpu_cdna"); -DEF_REGISTER(vgpr114, Arch_amdgpu_cdna | VGPR | BITS_32 | 114,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_114, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 114,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_114, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 114,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_114, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 114,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_114, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 114,"amdgpu_cdna"); -DEF_REGISTER(vgpr115, Arch_amdgpu_cdna | VGPR | BITS_32 | 115,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_115, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 115,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_115, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 115,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_115, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 115,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_115, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 115,"amdgpu_cdna"); -DEF_REGISTER(vgpr116, Arch_amdgpu_cdna | VGPR | BITS_32 | 116,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_116, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 116,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_116, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 116,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_116, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 116,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_116, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 116,"amdgpu_cdna"); -DEF_REGISTER(vgpr117, Arch_amdgpu_cdna | VGPR | BITS_32 | 117,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_117, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 117,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_117, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 117,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_117, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 117,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_117, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 117,"amdgpu_cdna"); -DEF_REGISTER(vgpr118, Arch_amdgpu_cdna | VGPR | BITS_32 | 118,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_118, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 118,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_118, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 118,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_118, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 118,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_118, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 118,"amdgpu_cdna"); -DEF_REGISTER(vgpr119, Arch_amdgpu_cdna | VGPR | BITS_32 | 119,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_119, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 119,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_119, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 119,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_119, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 119,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_119, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 119,"amdgpu_cdna"); -DEF_REGISTER(vgpr120, Arch_amdgpu_cdna | VGPR | BITS_32 | 120,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_120, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 120,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_120, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 120,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_120, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 120,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_120, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 120,"amdgpu_cdna"); -DEF_REGISTER(vgpr121, Arch_amdgpu_cdna | VGPR | BITS_32 | 121,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_121, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 121,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_121, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 121,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_121, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 121,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_121, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 121,"amdgpu_cdna"); -DEF_REGISTER(vgpr122, Arch_amdgpu_cdna | VGPR | BITS_32 | 122,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_122, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 122,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_122, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 122,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_122, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 122,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_122, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 122,"amdgpu_cdna"); -DEF_REGISTER(vgpr123, Arch_amdgpu_cdna | VGPR | BITS_32 | 123,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_123, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 123,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_123, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 123,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_123, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 123,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_123, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 123,"amdgpu_cdna"); -DEF_REGISTER(vgpr124, Arch_amdgpu_cdna | VGPR | BITS_32 | 124,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_124, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 124,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_124, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 124,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_124, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 124,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_124, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 124,"amdgpu_cdna"); -DEF_REGISTER(vgpr125, Arch_amdgpu_cdna | VGPR | BITS_32 | 125,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_125, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 125,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_125, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 125,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_125, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 125,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_125, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 125,"amdgpu_cdna"); -DEF_REGISTER(vgpr126, Arch_amdgpu_cdna | VGPR | BITS_32 | 126,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_126, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 126,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_126, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 126,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_126, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 126,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_126, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 126,"amdgpu_cdna"); -DEF_REGISTER(vgpr127, Arch_amdgpu_cdna | VGPR | BITS_32 | 127,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_127, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 127,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_127, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 127,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_127, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 127,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_127, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 127,"amdgpu_cdna"); -DEF_REGISTER(vgpr128, Arch_amdgpu_cdna | VGPR | BITS_32 | 128,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_128, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 128,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_128, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 128,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_128, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 128,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_128, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 128,"amdgpu_cdna"); -DEF_REGISTER(vgpr129, Arch_amdgpu_cdna | VGPR | BITS_32 | 129,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_129, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 129,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_129, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 129,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_129, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 129,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_129, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 129,"amdgpu_cdna"); -DEF_REGISTER(vgpr130, Arch_amdgpu_cdna | VGPR | BITS_32 | 130,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_130, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 130,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_130, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 130,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_130, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 130,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_130, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 130,"amdgpu_cdna"); -DEF_REGISTER(vgpr131, Arch_amdgpu_cdna | VGPR | BITS_32 | 131,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_131, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 131,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_131, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 131,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_131, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 131,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_131, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 131,"amdgpu_cdna"); -DEF_REGISTER(vgpr132, Arch_amdgpu_cdna | VGPR | BITS_32 | 132,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_132, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 132,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_132, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 132,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_132, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 132,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_132, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 132,"amdgpu_cdna"); -DEF_REGISTER(vgpr133, Arch_amdgpu_cdna | VGPR | BITS_32 | 133,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_133, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 133,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_133, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 133,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_133, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 133,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_133, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 133,"amdgpu_cdna"); -DEF_REGISTER(vgpr134, Arch_amdgpu_cdna | VGPR | BITS_32 | 134,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_134, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 134,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_134, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 134,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_134, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 134,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_134, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 134,"amdgpu_cdna"); -DEF_REGISTER(vgpr135, Arch_amdgpu_cdna | VGPR | BITS_32 | 135,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_135, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 135,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_135, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 135,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_135, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 135,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_135, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 135,"amdgpu_cdna"); -DEF_REGISTER(vgpr136, Arch_amdgpu_cdna | VGPR | BITS_32 | 136,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_136, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 136,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_136, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 136,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_136, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 136,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_136, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 136,"amdgpu_cdna"); -DEF_REGISTER(vgpr137, Arch_amdgpu_cdna | VGPR | BITS_32 | 137,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_137, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 137,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_137, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 137,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_137, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 137,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_137, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 137,"amdgpu_cdna"); -DEF_REGISTER(vgpr138, Arch_amdgpu_cdna | VGPR | BITS_32 | 138,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_138, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 138,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_138, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 138,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_138, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 138,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_138, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 138,"amdgpu_cdna"); -DEF_REGISTER(vgpr139, Arch_amdgpu_cdna | VGPR | BITS_32 | 139,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_139, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 139,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_139, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 139,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_139, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 139,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_139, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 139,"amdgpu_cdna"); -DEF_REGISTER(vgpr140, Arch_amdgpu_cdna | VGPR | BITS_32 | 140,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_140, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 140,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_140, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 140,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_140, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 140,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_140, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 140,"amdgpu_cdna"); -DEF_REGISTER(vgpr141, Arch_amdgpu_cdna | VGPR | BITS_32 | 141,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_141, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 141,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_141, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 141,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_141, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 141,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_141, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 141,"amdgpu_cdna"); -DEF_REGISTER(vgpr142, Arch_amdgpu_cdna | VGPR | BITS_32 | 142,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_142, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 142,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_142, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 142,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_142, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 142,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_142, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 142,"amdgpu_cdna"); -DEF_REGISTER(vgpr143, Arch_amdgpu_cdna | VGPR | BITS_32 | 143,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_143, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 143,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_143, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 143,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_143, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 143,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_143, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 143,"amdgpu_cdna"); -DEF_REGISTER(vgpr144, Arch_amdgpu_cdna | VGPR | BITS_32 | 144,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_144, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 144,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_144, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 144,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_144, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 144,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_144, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 144,"amdgpu_cdna"); -DEF_REGISTER(vgpr145, Arch_amdgpu_cdna | VGPR | BITS_32 | 145,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_145, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 145,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_145, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 145,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_145, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 145,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_145, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 145,"amdgpu_cdna"); -DEF_REGISTER(vgpr146, Arch_amdgpu_cdna | VGPR | BITS_32 | 146,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_146, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 146,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_146, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 146,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_146, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 146,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_146, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 146,"amdgpu_cdna"); -DEF_REGISTER(vgpr147, Arch_amdgpu_cdna | VGPR | BITS_32 | 147,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_147, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 147,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_147, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 147,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_147, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 147,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_147, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 147,"amdgpu_cdna"); -DEF_REGISTER(vgpr148, Arch_amdgpu_cdna | VGPR | BITS_32 | 148,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_148, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 148,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_148, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 148,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_148, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 148,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_148, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 148,"amdgpu_cdna"); -DEF_REGISTER(vgpr149, Arch_amdgpu_cdna | VGPR | BITS_32 | 149,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_149, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 149,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_149, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 149,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_149, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 149,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_149, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 149,"amdgpu_cdna"); -DEF_REGISTER(vgpr150, Arch_amdgpu_cdna | VGPR | BITS_32 | 150,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_150, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 150,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_150, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 150,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_150, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 150,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_150, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 150,"amdgpu_cdna"); -DEF_REGISTER(vgpr151, Arch_amdgpu_cdna | VGPR | BITS_32 | 151,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_151, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 151,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_151, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 151,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_151, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 151,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_151, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 151,"amdgpu_cdna"); -DEF_REGISTER(vgpr152, Arch_amdgpu_cdna | VGPR | BITS_32 | 152,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_152, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 152,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_152, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 152,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_152, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 152,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_152, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 152,"amdgpu_cdna"); -DEF_REGISTER(vgpr153, Arch_amdgpu_cdna | VGPR | BITS_32 | 153,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_153, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 153,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_153, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 153,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_153, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 153,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_153, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 153,"amdgpu_cdna"); -DEF_REGISTER(vgpr154, Arch_amdgpu_cdna | VGPR | BITS_32 | 154,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_154, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 154,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_154, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 154,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_154, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 154,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_154, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 154,"amdgpu_cdna"); -DEF_REGISTER(vgpr155, Arch_amdgpu_cdna | VGPR | BITS_32 | 155,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_155, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 155,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_155, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 155,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_155, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 155,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_155, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 155,"amdgpu_cdna"); -DEF_REGISTER(vgpr156, Arch_amdgpu_cdna | VGPR | BITS_32 | 156,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_156, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 156,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_156, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 156,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_156, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 156,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_156, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 156,"amdgpu_cdna"); -DEF_REGISTER(vgpr157, Arch_amdgpu_cdna | VGPR | BITS_32 | 157,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_157, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 157,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_157, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 157,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_157, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 157,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_157, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 157,"amdgpu_cdna"); -DEF_REGISTER(vgpr158, Arch_amdgpu_cdna | VGPR | BITS_32 | 158,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_158, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 158,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_158, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 158,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_158, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 158,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_158, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 158,"amdgpu_cdna"); -DEF_REGISTER(vgpr159, Arch_amdgpu_cdna | VGPR | BITS_32 | 159,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_159, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 159,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_159, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 159,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_159, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 159,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_159, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 159,"amdgpu_cdna"); -DEF_REGISTER(vgpr160, Arch_amdgpu_cdna | VGPR | BITS_32 | 160,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_160, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 160,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_160, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 160,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_160, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 160,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_160, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 160,"amdgpu_cdna"); -DEF_REGISTER(vgpr161, Arch_amdgpu_cdna | VGPR | BITS_32 | 161,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_161, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 161,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_161, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 161,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_161, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 161,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_161, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 161,"amdgpu_cdna"); -DEF_REGISTER(vgpr162, Arch_amdgpu_cdna | VGPR | BITS_32 | 162,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_162, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 162,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_162, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 162,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_162, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 162,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_162, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 162,"amdgpu_cdna"); -DEF_REGISTER(vgpr163, Arch_amdgpu_cdna | VGPR | BITS_32 | 163,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_163, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 163,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_163, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 163,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_163, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 163,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_163, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 163,"amdgpu_cdna"); -DEF_REGISTER(vgpr164, Arch_amdgpu_cdna | VGPR | BITS_32 | 164,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_164, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 164,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_164, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 164,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_164, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 164,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_164, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 164,"amdgpu_cdna"); -DEF_REGISTER(vgpr165, Arch_amdgpu_cdna | VGPR | BITS_32 | 165,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_165, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 165,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_165, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 165,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_165, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 165,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_165, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 165,"amdgpu_cdna"); -DEF_REGISTER(vgpr166, Arch_amdgpu_cdna | VGPR | BITS_32 | 166,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_166, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 166,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_166, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 166,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_166, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 166,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_166, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 166,"amdgpu_cdna"); -DEF_REGISTER(vgpr167, Arch_amdgpu_cdna | VGPR | BITS_32 | 167,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_167, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 167,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_167, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 167,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_167, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 167,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_167, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 167,"amdgpu_cdna"); -DEF_REGISTER(vgpr168, Arch_amdgpu_cdna | VGPR | BITS_32 | 168,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_168, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 168,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_168, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 168,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_168, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 168,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_168, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 168,"amdgpu_cdna"); -DEF_REGISTER(vgpr169, Arch_amdgpu_cdna | VGPR | BITS_32 | 169,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_169, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 169,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_169, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 169,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_169, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 169,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_169, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 169,"amdgpu_cdna"); -DEF_REGISTER(vgpr170, Arch_amdgpu_cdna | VGPR | BITS_32 | 170,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_170, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 170,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_170, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 170,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_170, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 170,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_170, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 170,"amdgpu_cdna"); -DEF_REGISTER(vgpr171, Arch_amdgpu_cdna | VGPR | BITS_32 | 171,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_171, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 171,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_171, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 171,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_171, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 171,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_171, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 171,"amdgpu_cdna"); -DEF_REGISTER(vgpr172, Arch_amdgpu_cdna | VGPR | BITS_32 | 172,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_172, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 172,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_172, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 172,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_172, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 172,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_172, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 172,"amdgpu_cdna"); -DEF_REGISTER(vgpr173, Arch_amdgpu_cdna | VGPR | BITS_32 | 173,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_173, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 173,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_173, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 173,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_173, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 173,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_173, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 173,"amdgpu_cdna"); -DEF_REGISTER(vgpr174, Arch_amdgpu_cdna | VGPR | BITS_32 | 174,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_174, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 174,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_174, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 174,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_174, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 174,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_174, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 174,"amdgpu_cdna"); -DEF_REGISTER(vgpr175, Arch_amdgpu_cdna | VGPR | BITS_32 | 175,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_175, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 175,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_175, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 175,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_175, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 175,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_175, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 175,"amdgpu_cdna"); -DEF_REGISTER(vgpr176, Arch_amdgpu_cdna | VGPR | BITS_32 | 176,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_176, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 176,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_176, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 176,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_176, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 176,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_176, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 176,"amdgpu_cdna"); -DEF_REGISTER(vgpr177, Arch_amdgpu_cdna | VGPR | BITS_32 | 177,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_177, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 177,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_177, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 177,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_177, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 177,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_177, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 177,"amdgpu_cdna"); -DEF_REGISTER(vgpr178, Arch_amdgpu_cdna | VGPR | BITS_32 | 178,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_178, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 178,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_178, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 178,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_178, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 178,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_178, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 178,"amdgpu_cdna"); -DEF_REGISTER(vgpr179, Arch_amdgpu_cdna | VGPR | BITS_32 | 179,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_179, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 179,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_179, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 179,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_179, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 179,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_179, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 179,"amdgpu_cdna"); -DEF_REGISTER(vgpr180, Arch_amdgpu_cdna | VGPR | BITS_32 | 180,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_180, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 180,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_180, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 180,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_180, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 180,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_180, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 180,"amdgpu_cdna"); -DEF_REGISTER(vgpr181, Arch_amdgpu_cdna | VGPR | BITS_32 | 181,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_181, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 181,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_181, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 181,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_181, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 181,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_181, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 181,"amdgpu_cdna"); -DEF_REGISTER(vgpr182, Arch_amdgpu_cdna | VGPR | BITS_32 | 182,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_182, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 182,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_182, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 182,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_182, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 182,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_182, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 182,"amdgpu_cdna"); -DEF_REGISTER(vgpr183, Arch_amdgpu_cdna | VGPR | BITS_32 | 183,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_183, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 183,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_183, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 183,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_183, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 183,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_183, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 183,"amdgpu_cdna"); -DEF_REGISTER(vgpr184, Arch_amdgpu_cdna | VGPR | BITS_32 | 184,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_184, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 184,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_184, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 184,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_184, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 184,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_184, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 184,"amdgpu_cdna"); -DEF_REGISTER(vgpr185, Arch_amdgpu_cdna | VGPR | BITS_32 | 185,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_185, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 185,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_185, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 185,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_185, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 185,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_185, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 185,"amdgpu_cdna"); -DEF_REGISTER(vgpr186, Arch_amdgpu_cdna | VGPR | BITS_32 | 186,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_186, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 186,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_186, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 186,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_186, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 186,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_186, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 186,"amdgpu_cdna"); -DEF_REGISTER(vgpr187, Arch_amdgpu_cdna | VGPR | BITS_32 | 187,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_187, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 187,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_187, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 187,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_187, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 187,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_187, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 187,"amdgpu_cdna"); -DEF_REGISTER(vgpr188, Arch_amdgpu_cdna | VGPR | BITS_32 | 188,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_188, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 188,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_188, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 188,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_188, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 188,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_188, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 188,"amdgpu_cdna"); -DEF_REGISTER(vgpr189, Arch_amdgpu_cdna | VGPR | BITS_32 | 189,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_189, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 189,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_189, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 189,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_189, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 189,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_189, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 189,"amdgpu_cdna"); -DEF_REGISTER(vgpr190, Arch_amdgpu_cdna | VGPR | BITS_32 | 190,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_190, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 190,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_190, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 190,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_190, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 190,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_190, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 190,"amdgpu_cdna"); -DEF_REGISTER(vgpr191, Arch_amdgpu_cdna | VGPR | BITS_32 | 191,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_191, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 191,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_191, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 191,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_191, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 191,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_191, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 191,"amdgpu_cdna"); -DEF_REGISTER(vgpr192, Arch_amdgpu_cdna | VGPR | BITS_32 | 192,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_192, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 192,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_192, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 192,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_192, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 192,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_192, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 192,"amdgpu_cdna"); -DEF_REGISTER(vgpr193, Arch_amdgpu_cdna | VGPR | BITS_32 | 193,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_193, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 193,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_193, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 193,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_193, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 193,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_193, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 193,"amdgpu_cdna"); -DEF_REGISTER(vgpr194, Arch_amdgpu_cdna | VGPR | BITS_32 | 194,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_194, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 194,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_194, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 194,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_194, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 194,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_194, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 194,"amdgpu_cdna"); -DEF_REGISTER(vgpr195, Arch_amdgpu_cdna | VGPR | BITS_32 | 195,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_195, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 195,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_195, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 195,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_195, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 195,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_195, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 195,"amdgpu_cdna"); -DEF_REGISTER(vgpr196, Arch_amdgpu_cdna | VGPR | BITS_32 | 196,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_196, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 196,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_196, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 196,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_196, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 196,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_196, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 196,"amdgpu_cdna"); -DEF_REGISTER(vgpr197, Arch_amdgpu_cdna | VGPR | BITS_32 | 197,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_197, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 197,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_197, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 197,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_197, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 197,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_197, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 197,"amdgpu_cdna"); -DEF_REGISTER(vgpr198, Arch_amdgpu_cdna | VGPR | BITS_32 | 198,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_198, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 198,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_198, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 198,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_198, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 198,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_198, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 198,"amdgpu_cdna"); -DEF_REGISTER(vgpr199, Arch_amdgpu_cdna | VGPR | BITS_32 | 199,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_199, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 199,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_199, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 199,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_199, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 199,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_199, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 199,"amdgpu_cdna"); -DEF_REGISTER(vgpr200, Arch_amdgpu_cdna | VGPR | BITS_32 | 200,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_200, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 200,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_200, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 200,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_200, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 200,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_200, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 200,"amdgpu_cdna"); -DEF_REGISTER(vgpr201, Arch_amdgpu_cdna | VGPR | BITS_32 | 201,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_201, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 201,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_201, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 201,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_201, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 201,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_201, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 201,"amdgpu_cdna"); -DEF_REGISTER(vgpr202, Arch_amdgpu_cdna | VGPR | BITS_32 | 202,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_202, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 202,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_202, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 202,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_202, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 202,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_202, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 202,"amdgpu_cdna"); -DEF_REGISTER(vgpr203, Arch_amdgpu_cdna | VGPR | BITS_32 | 203,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_203, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 203,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_203, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 203,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_203, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 203,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_203, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 203,"amdgpu_cdna"); -DEF_REGISTER(vgpr204, Arch_amdgpu_cdna | VGPR | BITS_32 | 204,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_204, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 204,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_204, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 204,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_204, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 204,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_204, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 204,"amdgpu_cdna"); -DEF_REGISTER(vgpr205, Arch_amdgpu_cdna | VGPR | BITS_32 | 205,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_205, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 205,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_205, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 205,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_205, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 205,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_205, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 205,"amdgpu_cdna"); -DEF_REGISTER(vgpr206, Arch_amdgpu_cdna | VGPR | BITS_32 | 206,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_206, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 206,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_206, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 206,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_206, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 206,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_206, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 206,"amdgpu_cdna"); -DEF_REGISTER(vgpr207, Arch_amdgpu_cdna | VGPR | BITS_32 | 207,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_207, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 207,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_207, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 207,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_207, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 207,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_207, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 207,"amdgpu_cdna"); -DEF_REGISTER(vgpr208, Arch_amdgpu_cdna | VGPR | BITS_32 | 208,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_208, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 208,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_208, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 208,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_208, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 208,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_208, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 208,"amdgpu_cdna"); -DEF_REGISTER(vgpr209, Arch_amdgpu_cdna | VGPR | BITS_32 | 209,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_209, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 209,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_209, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 209,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_209, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 209,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_209, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 209,"amdgpu_cdna"); -DEF_REGISTER(vgpr210, Arch_amdgpu_cdna | VGPR | BITS_32 | 210,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_210, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 210,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_210, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 210,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_210, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 210,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_210, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 210,"amdgpu_cdna"); -DEF_REGISTER(vgpr211, Arch_amdgpu_cdna | VGPR | BITS_32 | 211,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_211, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 211,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_211, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 211,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_211, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 211,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_211, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 211,"amdgpu_cdna"); -DEF_REGISTER(vgpr212, Arch_amdgpu_cdna | VGPR | BITS_32 | 212,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_212, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 212,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_212, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 212,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_212, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 212,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_212, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 212,"amdgpu_cdna"); -DEF_REGISTER(vgpr213, Arch_amdgpu_cdna | VGPR | BITS_32 | 213,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_213, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 213,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_213, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 213,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_213, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 213,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_213, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 213,"amdgpu_cdna"); -DEF_REGISTER(vgpr214, Arch_amdgpu_cdna | VGPR | BITS_32 | 214,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_214, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 214,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_214, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 214,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_214, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 214,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_214, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 214,"amdgpu_cdna"); -DEF_REGISTER(vgpr215, Arch_amdgpu_cdna | VGPR | BITS_32 | 215,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_215, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 215,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_215, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 215,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_215, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 215,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_215, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 215,"amdgpu_cdna"); -DEF_REGISTER(vgpr216, Arch_amdgpu_cdna | VGPR | BITS_32 | 216,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_216, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 216,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_216, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 216,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_216, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 216,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_216, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 216,"amdgpu_cdna"); -DEF_REGISTER(vgpr217, Arch_amdgpu_cdna | VGPR | BITS_32 | 217,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_217, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 217,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_217, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 217,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_217, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 217,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_217, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 217,"amdgpu_cdna"); -DEF_REGISTER(vgpr218, Arch_amdgpu_cdna | VGPR | BITS_32 | 218,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_218, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 218,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_218, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 218,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_218, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 218,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_218, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 218,"amdgpu_cdna"); -DEF_REGISTER(vgpr219, Arch_amdgpu_cdna | VGPR | BITS_32 | 219,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_219, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 219,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_219, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 219,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_219, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 219,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_219, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 219,"amdgpu_cdna"); -DEF_REGISTER(vgpr220, Arch_amdgpu_cdna | VGPR | BITS_32 | 220,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_220, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 220,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_220, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 220,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_220, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 220,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_220, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 220,"amdgpu_cdna"); -DEF_REGISTER(vgpr221, Arch_amdgpu_cdna | VGPR | BITS_32 | 221,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_221, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 221,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_221, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 221,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_221, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 221,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_221, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 221,"amdgpu_cdna"); -DEF_REGISTER(vgpr222, Arch_amdgpu_cdna | VGPR | BITS_32 | 222,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_222, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 222,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_222, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 222,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_222, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 222,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_222, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 222,"amdgpu_cdna"); -DEF_REGISTER(vgpr223, Arch_amdgpu_cdna | VGPR | BITS_32 | 223,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_223, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 223,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_223, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 223,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_223, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 223,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_223, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 223,"amdgpu_cdna"); -DEF_REGISTER(vgpr224, Arch_amdgpu_cdna | VGPR | BITS_32 | 224,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_224, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 224,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_224, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 224,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_224, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 224,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_224, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 224,"amdgpu_cdna"); -DEF_REGISTER(vgpr225, Arch_amdgpu_cdna | VGPR | BITS_32 | 225,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_225, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 225,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_225, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 225,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_225, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 225,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_225, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 225,"amdgpu_cdna"); -DEF_REGISTER(vgpr226, Arch_amdgpu_cdna | VGPR | BITS_32 | 226,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_226, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 226,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_226, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 226,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_226, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 226,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_226, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 226,"amdgpu_cdna"); -DEF_REGISTER(vgpr227, Arch_amdgpu_cdna | VGPR | BITS_32 | 227,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_227, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 227,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_227, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 227,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_227, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 227,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_227, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 227,"amdgpu_cdna"); -DEF_REGISTER(vgpr228, Arch_amdgpu_cdna | VGPR | BITS_32 | 228,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_228, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 228,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_228, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 228,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_228, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 228,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_228, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 228,"amdgpu_cdna"); -DEF_REGISTER(vgpr229, Arch_amdgpu_cdna | VGPR | BITS_32 | 229,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_229, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 229,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_229, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 229,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_229, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 229,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_229, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 229,"amdgpu_cdna"); -DEF_REGISTER(vgpr230, Arch_amdgpu_cdna | VGPR | BITS_32 | 230,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_230, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 230,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_230, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 230,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_230, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 230,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_230, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 230,"amdgpu_cdna"); -DEF_REGISTER(vgpr231, Arch_amdgpu_cdna | VGPR | BITS_32 | 231,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_231, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 231,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_231, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 231,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_231, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 231,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_231, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 231,"amdgpu_cdna"); -DEF_REGISTER(vgpr232, Arch_amdgpu_cdna | VGPR | BITS_32 | 232,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_232, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 232,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_232, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 232,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_232, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 232,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_232, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 232,"amdgpu_cdna"); -DEF_REGISTER(vgpr233, Arch_amdgpu_cdna | VGPR | BITS_32 | 233,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_233, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 233,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_233, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 233,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_233, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 233,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_233, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 233,"amdgpu_cdna"); -DEF_REGISTER(vgpr234, Arch_amdgpu_cdna | VGPR | BITS_32 | 234,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_234, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 234,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_234, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 234,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_234, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 234,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_234, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 234,"amdgpu_cdna"); -DEF_REGISTER(vgpr235, Arch_amdgpu_cdna | VGPR | BITS_32 | 235,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_235, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 235,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_235, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 235,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_235, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 235,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_235, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 235,"amdgpu_cdna"); -DEF_REGISTER(vgpr236, Arch_amdgpu_cdna | VGPR | BITS_32 | 236,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_236, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 236,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_236, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 236,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_236, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 236,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_236, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 236,"amdgpu_cdna"); -DEF_REGISTER(vgpr237, Arch_amdgpu_cdna | VGPR | BITS_32 | 237,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_237, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 237,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_237, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 237,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_237, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 237,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_237, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 237,"amdgpu_cdna"); -DEF_REGISTER(vgpr238, Arch_amdgpu_cdna | VGPR | BITS_32 | 238,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_238, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 238,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_238, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 238,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_238, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 238,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_238, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 238,"amdgpu_cdna"); -DEF_REGISTER(vgpr239, Arch_amdgpu_cdna | VGPR | BITS_32 | 239,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_239, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 239,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_239, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 239,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_239, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 239,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_239, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 239,"amdgpu_cdna"); -DEF_REGISTER(vgpr240, Arch_amdgpu_cdna | VGPR | BITS_32 | 240,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_240, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 240,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_240, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 240,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_240, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 240,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec16_240, Arch_amdgpu_cdna | VGPR_VEC16 | BITS_512 | 240,"amdgpu_cdna"); -DEF_REGISTER(vgpr241, Arch_amdgpu_cdna | VGPR | BITS_32 | 241,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_241, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 241,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_241, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 241,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_241, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 241,"amdgpu_cdna"); -DEF_REGISTER(vgpr242, Arch_amdgpu_cdna | VGPR | BITS_32 | 242,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_242, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 242,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_242, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 242,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_242, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 242,"amdgpu_cdna"); -DEF_REGISTER(vgpr243, Arch_amdgpu_cdna | VGPR | BITS_32 | 243,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_243, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 243,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_243, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 243,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_243, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 243,"amdgpu_cdna"); -DEF_REGISTER(vgpr244, Arch_amdgpu_cdna | VGPR | BITS_32 | 244,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_244, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 244,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_244, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 244,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_244, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 244,"amdgpu_cdna"); -DEF_REGISTER(vgpr245, Arch_amdgpu_cdna | VGPR | BITS_32 | 245,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_245, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 245,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_245, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 245,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_245, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 245,"amdgpu_cdna"); -DEF_REGISTER(vgpr246, Arch_amdgpu_cdna | VGPR | BITS_32 | 246,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_246, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 246,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_246, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 246,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_246, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 246,"amdgpu_cdna"); -DEF_REGISTER(vgpr247, Arch_amdgpu_cdna | VGPR | BITS_32 | 247,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_247, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 247,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_247, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 247,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_247, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 247,"amdgpu_cdna"); -DEF_REGISTER(vgpr248, Arch_amdgpu_cdna | VGPR | BITS_32 | 248,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_248, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 248,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_248, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 248,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec8_248, Arch_amdgpu_cdna | VGPR_VEC8 | BITS_256 | 248,"amdgpu_cdna"); -DEF_REGISTER(vgpr249, Arch_amdgpu_cdna | VGPR | BITS_32 | 249,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_249, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 249,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_249, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 249,"amdgpu_cdna"); -DEF_REGISTER(vgpr250, Arch_amdgpu_cdna | VGPR | BITS_32 | 250,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_250, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 250,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_250, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 250,"amdgpu_cdna"); -DEF_REGISTER(vgpr251, Arch_amdgpu_cdna | VGPR | BITS_32 | 251,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_251, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 251,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_251, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 251,"amdgpu_cdna"); -DEF_REGISTER(vgpr252, Arch_amdgpu_cdna | VGPR | BITS_32 | 252,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_252, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 252,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec4_252, Arch_amdgpu_cdna | VGPR_VEC4 | BITS_128 | 252,"amdgpu_cdna"); -DEF_REGISTER(vgpr253, Arch_amdgpu_cdna | VGPR | BITS_32 | 253,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_253, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 253,"amdgpu_cdna"); -DEF_REGISTER(vgpr254, Arch_amdgpu_cdna | VGPR | BITS_32 | 254,"amdgpu_cdna"); -DEF_REGISTER(vgpr_vec2_254, Arch_amdgpu_cdna | VGPR_VEC2 | BITS_64 | 254,"amdgpu_cdna"); -DEF_REGISTER(vgpr255, Arch_amdgpu_cdna | VGPR | BITS_32 | 255,"amdgpu_cdna"); -#endif //DYNINST_AMDGPU_CDNA_SYS_REGS_H diff --git a/common/h/dyn_regs.h b/common/h/dyn_regs.h index f4e1cfe06f..d1463d88a3 100644 --- a/common/h/dyn_regs.h +++ b/common/h/dyn_regs.h @@ -1614,7 +1614,7 @@ namespace Dyninst const signed int BITS_256 = 0x00000F00; const signed int BITS_512 = 0x00001000; -#include "amdgpu_vega_sys_regs.h" +#include "AMDGPU/vega/amdgpu_vega_sys_regs.h" } namespace amdgpu_cdna2{ diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index da6d489c55..fcbc935355 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -3007,8 +3007,7 @@ power_op_dxex, aarch64_op_zip1_advsimd, aarch64_op_zip2_advsimd, amdgpu_op_sop1_nop, -#include "amdgpu_op_table.h" -#include "amdgpu_cdna_op_table.h" +#include "AMDGPU/vega/amdgpu_vega_op_table.h" #include "AMDGPU/cdna2/amdgpu_cdna2_op_table.h" cuda_op_general, cuda_op_call, diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h deleted file mode 100644 index 90eb1cb315..0000000000 --- a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h +++ /dev/null @@ -1,1135 +0,0 @@ -amdgpu_cdna2_op_BUFFER_ATOMIC_ADD, -amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F32, -amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_F64, -amdgpu_cdna2_op_BUFFER_ATOMIC_ADD_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_AND, -amdgpu_cdna2_op_BUFFER_ATOMIC_AND_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_BUFFER_ATOMIC_CMPSWAP_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_DEC, -amdgpu_cdna2_op_BUFFER_ATOMIC_DEC_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_INC, -amdgpu_cdna2_op_BUFFER_ATOMIC_INC_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_MAX_F64, -amdgpu_cdna2_op_BUFFER_ATOMIC_MIN_F64, -amdgpu_cdna2_op_BUFFER_ATOMIC_OR, -amdgpu_cdna2_op_BUFFER_ATOMIC_OR_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_PK_ADD_F16, -amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX, -amdgpu_cdna2_op_BUFFER_ATOMIC_SMAX_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN, -amdgpu_cdna2_op_BUFFER_ATOMIC_SMIN_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_SUB, -amdgpu_cdna2_op_BUFFER_ATOMIC_SUB_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP, -amdgpu_cdna2_op_BUFFER_ATOMIC_SWAP_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX, -amdgpu_cdna2_op_BUFFER_ATOMIC_UMAX_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN, -amdgpu_cdna2_op_BUFFER_ATOMIC_UMIN_X2, -amdgpu_cdna2_op_BUFFER_ATOMIC_XOR, -amdgpu_cdna2_op_BUFFER_ATOMIC_XOR_X2, -amdgpu_cdna2_op_BUFFER_INVL2, -amdgpu_cdna2_op_BUFFER_LOAD_DWORD, -amdgpu_cdna2_op_BUFFER_LOAD_DWORDX2, -amdgpu_cdna2_op_BUFFER_LOAD_DWORDX3, -amdgpu_cdna2_op_BUFFER_LOAD_DWORDX4, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_HI_X, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_X, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XY, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZ, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_D16_XYZW, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_X, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XY, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZ, -amdgpu_cdna2_op_BUFFER_LOAD_FORMAT_XYZW, -amdgpu_cdna2_op_BUFFER_LOAD_SBYTE, -amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16, -amdgpu_cdna2_op_BUFFER_LOAD_SBYTE_D16_HI, -amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16, -amdgpu_cdna2_op_BUFFER_LOAD_SHORT_D16_HI, -amdgpu_cdna2_op_BUFFER_LOAD_SSHORT, -amdgpu_cdna2_op_BUFFER_LOAD_UBYTE, -amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16, -amdgpu_cdna2_op_BUFFER_LOAD_UBYTE_D16_HI, -amdgpu_cdna2_op_BUFFER_LOAD_USHORT, -amdgpu_cdna2_op_BUFFER_STORE_BYTE, -amdgpu_cdna2_op_BUFFER_STORE_BYTE_D16_HI, -amdgpu_cdna2_op_BUFFER_STORE_DWORD, -amdgpu_cdna2_op_BUFFER_STORE_DWORDX2, -amdgpu_cdna2_op_BUFFER_STORE_DWORDX3, -amdgpu_cdna2_op_BUFFER_STORE_DWORDX4, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_HI_X, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_X, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XY, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZ, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_D16_XYZW, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_X, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XY, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZ, -amdgpu_cdna2_op_BUFFER_STORE_FORMAT_XYZW, -amdgpu_cdna2_op_BUFFER_STORE_LDS_DWORD, -amdgpu_cdna2_op_BUFFER_STORE_SHORT, -amdgpu_cdna2_op_BUFFER_STORE_SHORT_D16_HI, -amdgpu_cdna2_op_BUFFER_WBINVL1, -amdgpu_cdna2_op_BUFFER_WBINVL1_VOL, -amdgpu_cdna2_op_BUFFER_WBL2, -amdgpu_cdna2_op_DS_ADD_F32, -amdgpu_cdna2_op_DS_ADD_F64, -amdgpu_cdna2_op_DS_ADD_RTN_F32, -amdgpu_cdna2_op_DS_ADD_RTN_F64, -amdgpu_cdna2_op_DS_ADD_RTN_U32, -amdgpu_cdna2_op_DS_ADD_RTN_U64, -amdgpu_cdna2_op_DS_ADD_U32, -amdgpu_cdna2_op_DS_ADD_U64, -amdgpu_cdna2_op_DS_AND_B32, -amdgpu_cdna2_op_DS_AND_B64, -amdgpu_cdna2_op_DS_AND_RTN_B32, -amdgpu_cdna2_op_DS_AND_RTN_B64, -amdgpu_cdna2_op_DS_APPEND, -amdgpu_cdna2_op_DS_BPERMUTE_B32, -amdgpu_cdna2_op_DS_CMPST_B32, -amdgpu_cdna2_op_DS_CMPST_B64, -amdgpu_cdna2_op_DS_CMPST_F32, -amdgpu_cdna2_op_DS_CMPST_F64, -amdgpu_cdna2_op_DS_CMPST_RTN_B32, -amdgpu_cdna2_op_DS_CMPST_RTN_B64, -amdgpu_cdna2_op_DS_CMPST_RTN_F32, -amdgpu_cdna2_op_DS_CMPST_RTN_F64, -amdgpu_cdna2_op_DS_CONDXCHG32_RTN_B64, -amdgpu_cdna2_op_DS_CONSUME, -amdgpu_cdna2_op_DS_DEC_RTN_U32, -amdgpu_cdna2_op_DS_DEC_RTN_U64, -amdgpu_cdna2_op_DS_DEC_U32, -amdgpu_cdna2_op_DS_DEC_U64, -amdgpu_cdna2_op_DS_GWS_BARRIER, -amdgpu_cdna2_op_DS_GWS_INIT, -amdgpu_cdna2_op_DS_GWS_SEMA_BR, -amdgpu_cdna2_op_DS_GWS_SEMA_P, -amdgpu_cdna2_op_DS_GWS_SEMA_RELEASE_ALL, -amdgpu_cdna2_op_DS_GWS_SEMA_V, -amdgpu_cdna2_op_DS_INC_RTN_U32, -amdgpu_cdna2_op_DS_INC_RTN_U64, -amdgpu_cdna2_op_DS_INC_U32, -amdgpu_cdna2_op_DS_INC_U64, -amdgpu_cdna2_op_DS_MAX_F32, -amdgpu_cdna2_op_DS_MAX_F64, -amdgpu_cdna2_op_DS_MAX_I32, -amdgpu_cdna2_op_DS_MAX_I64, -amdgpu_cdna2_op_DS_MAX_RTN_F32, -amdgpu_cdna2_op_DS_MAX_RTN_F64, -amdgpu_cdna2_op_DS_MAX_RTN_I32, -amdgpu_cdna2_op_DS_MAX_RTN_I64, -amdgpu_cdna2_op_DS_MAX_RTN_U32, -amdgpu_cdna2_op_DS_MAX_RTN_U64, -amdgpu_cdna2_op_DS_MAX_U32, -amdgpu_cdna2_op_DS_MAX_U64, -amdgpu_cdna2_op_DS_MIN_F32, -amdgpu_cdna2_op_DS_MIN_F64, -amdgpu_cdna2_op_DS_MIN_I32, -amdgpu_cdna2_op_DS_MIN_I64, -amdgpu_cdna2_op_DS_MIN_RTN_F32, -amdgpu_cdna2_op_DS_MIN_RTN_F64, -amdgpu_cdna2_op_DS_MIN_RTN_I32, -amdgpu_cdna2_op_DS_MIN_RTN_I64, -amdgpu_cdna2_op_DS_MIN_RTN_U32, -amdgpu_cdna2_op_DS_MIN_RTN_U64, -amdgpu_cdna2_op_DS_MIN_U32, -amdgpu_cdna2_op_DS_MIN_U64, -amdgpu_cdna2_op_DS_MSKOR_B32, -amdgpu_cdna2_op_DS_MSKOR_B64, -amdgpu_cdna2_op_DS_MSKOR_RTN_B32, -amdgpu_cdna2_op_DS_MSKOR_RTN_B64, -amdgpu_cdna2_op_DS_NOP, -amdgpu_cdna2_op_DS_OR_B32, -amdgpu_cdna2_op_DS_OR_B64, -amdgpu_cdna2_op_DS_OR_RTN_B32, -amdgpu_cdna2_op_DS_OR_RTN_B64, -amdgpu_cdna2_op_DS_PERMUTE_B32, -amdgpu_cdna2_op_DS_READ2ST64_B32, -amdgpu_cdna2_op_DS_READ2ST64_B64, -amdgpu_cdna2_op_DS_READ2_B32, -amdgpu_cdna2_op_DS_READ2_B64, -amdgpu_cdna2_op_DS_READ_ADDTID_B32, -amdgpu_cdna2_op_DS_READ_B128, -amdgpu_cdna2_op_DS_READ_B32, -amdgpu_cdna2_op_DS_READ_B64, -amdgpu_cdna2_op_DS_READ_B96, -amdgpu_cdna2_op_DS_READ_I16, -amdgpu_cdna2_op_DS_READ_I8, -amdgpu_cdna2_op_DS_READ_I8_D16, -amdgpu_cdna2_op_DS_READ_I8_D16_HI, -amdgpu_cdna2_op_DS_READ_U16, -amdgpu_cdna2_op_DS_READ_U16_D16, -amdgpu_cdna2_op_DS_READ_U16_D16_HI, -amdgpu_cdna2_op_DS_READ_U8, -amdgpu_cdna2_op_DS_READ_U8_D16, -amdgpu_cdna2_op_DS_READ_U8_D16_HI, -amdgpu_cdna2_op_DS_RSUB_RTN_U32, -amdgpu_cdna2_op_DS_RSUB_RTN_U64, -amdgpu_cdna2_op_DS_RSUB_U32, -amdgpu_cdna2_op_DS_RSUB_U64, -amdgpu_cdna2_op_DS_SUB_RTN_U32, -amdgpu_cdna2_op_DS_SUB_RTN_U64, -amdgpu_cdna2_op_DS_SUB_U32, -amdgpu_cdna2_op_DS_SUB_U64, -amdgpu_cdna2_op_DS_SWIZZLE_B32, -amdgpu_cdna2_op_DS_WRAP_RTN_B32, -amdgpu_cdna2_op_DS_WRITE2ST64_B32, -amdgpu_cdna2_op_DS_WRITE2ST64_B64, -amdgpu_cdna2_op_DS_WRITE2_B32, -amdgpu_cdna2_op_DS_WRITE2_B64, -amdgpu_cdna2_op_DS_WRITE_ADDTID_B32, -amdgpu_cdna2_op_DS_WRITE_B128, -amdgpu_cdna2_op_DS_WRITE_B16, -amdgpu_cdna2_op_DS_WRITE_B16_D16_HI, -amdgpu_cdna2_op_DS_WRITE_B32, -amdgpu_cdna2_op_DS_WRITE_B64, -amdgpu_cdna2_op_DS_WRITE_B8, -amdgpu_cdna2_op_DS_WRITE_B8_D16_HI, -amdgpu_cdna2_op_DS_WRITE_B96, -amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B32, -amdgpu_cdna2_op_DS_WRXCHG2ST64_RTN_B64, -amdgpu_cdna2_op_DS_WRXCHG2_RTN_B32, -amdgpu_cdna2_op_DS_WRXCHG2_RTN_B64, -amdgpu_cdna2_op_DS_WRXCHG_RTN_B32, -amdgpu_cdna2_op_DS_WRXCHG_RTN_B64, -amdgpu_cdna2_op_DS_XOR_B32, -amdgpu_cdna2_op_DS_XOR_B64, -amdgpu_cdna2_op_DS_XOR_RTN_B32, -amdgpu_cdna2_op_DS_XOR_RTN_B64, -amdgpu_cdna2_op_FLAT_ATOMIC_ADD, -amdgpu_cdna2_op_FLAT_ATOMIC_ADD_F64, -amdgpu_cdna2_op_FLAT_ATOMIC_ADD_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_AND, -amdgpu_cdna2_op_FLAT_ATOMIC_AND_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_FLAT_ATOMIC_CMPSWAP_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_DEC, -amdgpu_cdna2_op_FLAT_ATOMIC_DEC_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_INC, -amdgpu_cdna2_op_FLAT_ATOMIC_INC_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_MAX_F64, -amdgpu_cdna2_op_FLAT_ATOMIC_MIN_F64, -amdgpu_cdna2_op_FLAT_ATOMIC_OR, -amdgpu_cdna2_op_FLAT_ATOMIC_OR_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_SMAX, -amdgpu_cdna2_op_FLAT_ATOMIC_SMAX_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_SMIN, -amdgpu_cdna2_op_FLAT_ATOMIC_SMIN_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_SUB, -amdgpu_cdna2_op_FLAT_ATOMIC_SUB_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_SWAP, -amdgpu_cdna2_op_FLAT_ATOMIC_SWAP_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_UMAX, -amdgpu_cdna2_op_FLAT_ATOMIC_UMAX_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_UMIN, -amdgpu_cdna2_op_FLAT_ATOMIC_UMIN_X2, -amdgpu_cdna2_op_FLAT_ATOMIC_XOR, -amdgpu_cdna2_op_FLAT_ATOMIC_XOR_X2, -amdgpu_cdna2_op_FLAT_LOAD_DWORD, -amdgpu_cdna2_op_FLAT_LOAD_DWORDX2, -amdgpu_cdna2_op_FLAT_LOAD_DWORDX3, -amdgpu_cdna2_op_FLAT_LOAD_DWORDX4, -amdgpu_cdna2_op_FLAT_LOAD_SBYTE, -amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16, -amdgpu_cdna2_op_FLAT_LOAD_SBYTE_D16_HI, -amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16, -amdgpu_cdna2_op_FLAT_LOAD_SHORT_D16_HI, -amdgpu_cdna2_op_FLAT_LOAD_SSHORT, -amdgpu_cdna2_op_FLAT_LOAD_UBYTE, -amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16, -amdgpu_cdna2_op_FLAT_LOAD_UBYTE_D16_HI, -amdgpu_cdna2_op_FLAT_LOAD_USHORT, -amdgpu_cdna2_op_FLAT_STORE_BYTE, -amdgpu_cdna2_op_FLAT_STORE_BYTE_D16_HI, -amdgpu_cdna2_op_FLAT_STORE_DWORD, -amdgpu_cdna2_op_FLAT_STORE_DWORDX2, -amdgpu_cdna2_op_FLAT_STORE_DWORDX3, -amdgpu_cdna2_op_FLAT_STORE_DWORDX4, -amdgpu_cdna2_op_FLAT_STORE_SHORT, -amdgpu_cdna2_op_FLAT_STORE_SHORT_D16_HI, -amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD, -amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F32, -amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_F64, -amdgpu_cdna2_op_GLOBAL_ATOMIC_ADD_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_AND, -amdgpu_cdna2_op_GLOBAL_ATOMIC_AND_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_GLOBAL_ATOMIC_CMPSWAP_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC, -amdgpu_cdna2_op_GLOBAL_ATOMIC_DEC_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_INC, -amdgpu_cdna2_op_GLOBAL_ATOMIC_INC_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_MAX_F64, -amdgpu_cdna2_op_GLOBAL_ATOMIC_MIN_F64, -amdgpu_cdna2_op_GLOBAL_ATOMIC_OR, -amdgpu_cdna2_op_GLOBAL_ATOMIC_OR_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_PK_ADD_F16, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SMAX_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SMIN_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SUB_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP, -amdgpu_cdna2_op_GLOBAL_ATOMIC_SWAP_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX, -amdgpu_cdna2_op_GLOBAL_ATOMIC_UMAX_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN, -amdgpu_cdna2_op_GLOBAL_ATOMIC_UMIN_X2, -amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR, -amdgpu_cdna2_op_GLOBAL_ATOMIC_XOR_X2, -amdgpu_cdna2_op_GLOBAL_LOAD_DWORD, -amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX2, -amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX3, -amdgpu_cdna2_op_GLOBAL_LOAD_DWORDX4, -amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE, -amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16, -amdgpu_cdna2_op_GLOBAL_LOAD_SBYTE_D16_HI, -amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16, -amdgpu_cdna2_op_GLOBAL_LOAD_SHORT_D16_HI, -amdgpu_cdna2_op_GLOBAL_LOAD_SSHORT, -amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE, -amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16, -amdgpu_cdna2_op_GLOBAL_LOAD_UBYTE_D16_HI, -amdgpu_cdna2_op_GLOBAL_LOAD_USHORT, -amdgpu_cdna2_op_GLOBAL_STORE_BYTE, -amdgpu_cdna2_op_GLOBAL_STORE_BYTE_D16_HI, -amdgpu_cdna2_op_GLOBAL_STORE_DWORD, -amdgpu_cdna2_op_GLOBAL_STORE_DWORDX2, -amdgpu_cdna2_op_GLOBAL_STORE_DWORDX3, -amdgpu_cdna2_op_GLOBAL_STORE_DWORDX4, -amdgpu_cdna2_op_GLOBAL_STORE_SHORT, -amdgpu_cdna2_op_GLOBAL_STORE_SHORT_D16_HI, -amdgpu_cdna2_op_IMAGE_ATOMIC_ADD, -amdgpu_cdna2_op_IMAGE_ATOMIC_AND, -amdgpu_cdna2_op_IMAGE_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_IMAGE_ATOMIC_DEC, -amdgpu_cdna2_op_IMAGE_ATOMIC_INC, -amdgpu_cdna2_op_IMAGE_ATOMIC_OR, -amdgpu_cdna2_op_IMAGE_ATOMIC_SMAX, -amdgpu_cdna2_op_IMAGE_ATOMIC_SMIN, -amdgpu_cdna2_op_IMAGE_ATOMIC_SUB, -amdgpu_cdna2_op_IMAGE_ATOMIC_SWAP, -amdgpu_cdna2_op_IMAGE_ATOMIC_UMAX, -amdgpu_cdna2_op_IMAGE_ATOMIC_UMIN, -amdgpu_cdna2_op_IMAGE_ATOMIC_XOR, -amdgpu_cdna2_op_IMAGE_GET_RESINFO, -amdgpu_cdna2_op_IMAGE_LOAD, -amdgpu_cdna2_op_IMAGE_LOAD_MIP, -amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK, -amdgpu_cdna2_op_IMAGE_LOAD_MIP_PCK_SGN, -amdgpu_cdna2_op_IMAGE_LOAD_PCK, -amdgpu_cdna2_op_IMAGE_LOAD_PCK_SGN, -amdgpu_cdna2_op_IMAGE_SAMPLE, -amdgpu_cdna2_op_IMAGE_STORE, -amdgpu_cdna2_op_IMAGE_STORE_MIP, -amdgpu_cdna2_op_IMAGE_STORE_MIP_PCK, -amdgpu_cdna2_op_IMAGE_STORE_PCK, -amdgpu_cdna2_op_SCRATCH_LOAD_DWORD, -amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX2, -amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX3, -amdgpu_cdna2_op_SCRATCH_LOAD_DWORDX4, -amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE, -amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16, -amdgpu_cdna2_op_SCRATCH_LOAD_SBYTE_D16_HI, -amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16, -amdgpu_cdna2_op_SCRATCH_LOAD_SHORT_D16_HI, -amdgpu_cdna2_op_SCRATCH_LOAD_SSHORT, -amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE, -amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16, -amdgpu_cdna2_op_SCRATCH_LOAD_UBYTE_D16_HI, -amdgpu_cdna2_op_SCRATCH_LOAD_USHORT, -amdgpu_cdna2_op_SCRATCH_STORE_BYTE, -amdgpu_cdna2_op_SCRATCH_STORE_BYTE_D16_HI, -amdgpu_cdna2_op_SCRATCH_STORE_DWORD, -amdgpu_cdna2_op_SCRATCH_STORE_DWORDX2, -amdgpu_cdna2_op_SCRATCH_STORE_DWORDX3, -amdgpu_cdna2_op_SCRATCH_STORE_DWORDX4, -amdgpu_cdna2_op_SCRATCH_STORE_SHORT, -amdgpu_cdna2_op_SCRATCH_STORE_SHORT_D16_HI, -amdgpu_cdna2_op_S_ABSDIFF_I32, -amdgpu_cdna2_op_S_ABS_I32, -amdgpu_cdna2_op_S_ADDC_U32, -amdgpu_cdna2_op_S_ADDK_I32, -amdgpu_cdna2_op_S_ADD_I32, -amdgpu_cdna2_op_S_ADD_U32, -amdgpu_cdna2_op_S_ANDN1_SAVEEXEC_B64, -amdgpu_cdna2_op_S_ANDN1_WREXEC_B64, -amdgpu_cdna2_op_S_ANDN2_B32, -amdgpu_cdna2_op_S_ANDN2_B64, -amdgpu_cdna2_op_S_ANDN2_SAVEEXEC_B64, -amdgpu_cdna2_op_S_ANDN2_WREXEC_B64, -amdgpu_cdna2_op_S_AND_B32, -amdgpu_cdna2_op_S_AND_B64, -amdgpu_cdna2_op_S_AND_SAVEEXEC_B64, -amdgpu_cdna2_op_S_ASHR_I32, -amdgpu_cdna2_op_S_ASHR_I64, -amdgpu_cdna2_op_S_ATC_PROBE, -amdgpu_cdna2_op_S_ATC_PROBE_BUFFER, -amdgpu_cdna2_op_S_ATOMIC_ADD, -amdgpu_cdna2_op_S_ATOMIC_ADD_X2, -amdgpu_cdna2_op_S_ATOMIC_AND, -amdgpu_cdna2_op_S_ATOMIC_AND_X2, -amdgpu_cdna2_op_S_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_S_ATOMIC_CMPSWAP_X2, -amdgpu_cdna2_op_S_ATOMIC_DEC, -amdgpu_cdna2_op_S_ATOMIC_DEC_X2, -amdgpu_cdna2_op_S_ATOMIC_INC, -amdgpu_cdna2_op_S_ATOMIC_INC_X2, -amdgpu_cdna2_op_S_ATOMIC_OR, -amdgpu_cdna2_op_S_ATOMIC_OR_X2, -amdgpu_cdna2_op_S_ATOMIC_SMAX, -amdgpu_cdna2_op_S_ATOMIC_SMAX_X2, -amdgpu_cdna2_op_S_ATOMIC_SMIN, -amdgpu_cdna2_op_S_ATOMIC_SMIN_X2, -amdgpu_cdna2_op_S_ATOMIC_SUB, -amdgpu_cdna2_op_S_ATOMIC_SUB_X2, -amdgpu_cdna2_op_S_ATOMIC_SWAP, -amdgpu_cdna2_op_S_ATOMIC_SWAP_X2, -amdgpu_cdna2_op_S_ATOMIC_UMAX, -amdgpu_cdna2_op_S_ATOMIC_UMAX_X2, -amdgpu_cdna2_op_S_ATOMIC_UMIN, -amdgpu_cdna2_op_S_ATOMIC_UMIN_X2, -amdgpu_cdna2_op_S_ATOMIC_XOR, -amdgpu_cdna2_op_S_ATOMIC_XOR_X2, -amdgpu_cdna2_op_S_BARRIER, -amdgpu_cdna2_op_S_BCNT0_I32_B32, -amdgpu_cdna2_op_S_BCNT0_I32_B64, -amdgpu_cdna2_op_S_BCNT1_I32_B32, -amdgpu_cdna2_op_S_BCNT1_I32_B64, -amdgpu_cdna2_op_S_BFE_I32, -amdgpu_cdna2_op_S_BFE_I64, -amdgpu_cdna2_op_S_BFE_U32, -amdgpu_cdna2_op_S_BFE_U64, -amdgpu_cdna2_op_S_BFM_B32, -amdgpu_cdna2_op_S_BFM_B64, -amdgpu_cdna2_op_S_BITCMP0_B32, -amdgpu_cdna2_op_S_BITCMP0_B64, -amdgpu_cdna2_op_S_BITCMP1_B32, -amdgpu_cdna2_op_S_BITCMP1_B64, -amdgpu_cdna2_op_S_BITREPLICATE_B64_B32, -amdgpu_cdna2_op_S_BITSET0_B32, -amdgpu_cdna2_op_S_BITSET0_B64, -amdgpu_cdna2_op_S_BITSET1_B32, -amdgpu_cdna2_op_S_BITSET1_B64, -amdgpu_cdna2_op_S_BRANCH, -amdgpu_cdna2_op_S_BREV_B32, -amdgpu_cdna2_op_S_BREV_B64, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_ADD_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_AND_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_CMPSWAP_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_DEC_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_INC_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_OR_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMAX_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SMIN_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SUB_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_SWAP_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMAX_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_UMIN_X2, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR, -amdgpu_cdna2_op_S_BUFFER_ATOMIC_XOR_X2, -amdgpu_cdna2_op_S_BUFFER_LOAD_DWORD, -amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX16, -amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX2, -amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX4, -amdgpu_cdna2_op_S_BUFFER_LOAD_DWORDX8, -amdgpu_cdna2_op_S_BUFFER_STORE_DWORD, -amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX2, -amdgpu_cdna2_op_S_BUFFER_STORE_DWORDX4, -amdgpu_cdna2_op_S_CALL_B64, -amdgpu_cdna2_op_S_CBRANCH_CDBGSYS, -amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_AND_USER, -amdgpu_cdna2_op_S_CBRANCH_CDBGSYS_OR_USER, -amdgpu_cdna2_op_S_CBRANCH_CDBGUSER, -amdgpu_cdna2_op_S_CBRANCH_EXECNZ, -amdgpu_cdna2_op_S_CBRANCH_EXECZ, -amdgpu_cdna2_op_S_CBRANCH_G_FORK, -amdgpu_cdna2_op_S_CBRANCH_I_FORK, -amdgpu_cdna2_op_S_CBRANCH_JOIN, -amdgpu_cdna2_op_S_CBRANCH_SCC0, -amdgpu_cdna2_op_S_CBRANCH_SCC1, -amdgpu_cdna2_op_S_CBRANCH_VCCNZ, -amdgpu_cdna2_op_S_CBRANCH_VCCZ, -amdgpu_cdna2_op_S_CMOVK_I32, -amdgpu_cdna2_op_S_CMOV_B32, -amdgpu_cdna2_op_S_CMOV_B64, -amdgpu_cdna2_op_S_CMPK_EQ_I32, -amdgpu_cdna2_op_S_CMPK_EQ_U32, -amdgpu_cdna2_op_S_CMPK_GE_I32, -amdgpu_cdna2_op_S_CMPK_GE_U32, -amdgpu_cdna2_op_S_CMPK_GT_I32, -amdgpu_cdna2_op_S_CMPK_GT_U32, -amdgpu_cdna2_op_S_CMPK_LE_I32, -amdgpu_cdna2_op_S_CMPK_LE_U32, -amdgpu_cdna2_op_S_CMPK_LG_I32, -amdgpu_cdna2_op_S_CMPK_LG_U32, -amdgpu_cdna2_op_S_CMPK_LT_I32, -amdgpu_cdna2_op_S_CMPK_LT_U32, -amdgpu_cdna2_op_S_CMP_EQ_I32, -amdgpu_cdna2_op_S_CMP_EQ_U32, -amdgpu_cdna2_op_S_CMP_EQ_U64, -amdgpu_cdna2_op_S_CMP_GE_I32, -amdgpu_cdna2_op_S_CMP_GE_U32, -amdgpu_cdna2_op_S_CMP_GT_I32, -amdgpu_cdna2_op_S_CMP_GT_U32, -amdgpu_cdna2_op_S_CMP_LE_I32, -amdgpu_cdna2_op_S_CMP_LE_U32, -amdgpu_cdna2_op_S_CMP_LG_I32, -amdgpu_cdna2_op_S_CMP_LG_U32, -amdgpu_cdna2_op_S_CMP_LG_U64, -amdgpu_cdna2_op_S_CMP_LT_I32, -amdgpu_cdna2_op_S_CMP_LT_U32, -amdgpu_cdna2_op_S_CSELECT_B32, -amdgpu_cdna2_op_S_CSELECT_B64, -amdgpu_cdna2_op_S_DCACHE_DISCARD, -amdgpu_cdna2_op_S_DCACHE_DISCARD_X2, -amdgpu_cdna2_op_S_DCACHE_INV, -amdgpu_cdna2_op_S_DCACHE_INV_VOL, -amdgpu_cdna2_op_S_DCACHE_WB, -amdgpu_cdna2_op_S_DCACHE_WB_VOL, -amdgpu_cdna2_op_S_DECPERFLEVEL, -amdgpu_cdna2_op_S_ENDPGM, -amdgpu_cdna2_op_S_ENDPGM_ORDERED_PS_DONE, -amdgpu_cdna2_op_S_ENDPGM_SAVED, -amdgpu_cdna2_op_S_FF0_I32_B32, -amdgpu_cdna2_op_S_FF0_I32_B64, -amdgpu_cdna2_op_S_FF1_I32_B32, -amdgpu_cdna2_op_S_FF1_I32_B64, -amdgpu_cdna2_op_S_FLBIT_I32, -amdgpu_cdna2_op_S_FLBIT_I32_B32, -amdgpu_cdna2_op_S_FLBIT_I32_B64, -amdgpu_cdna2_op_S_FLBIT_I32_I64, -amdgpu_cdna2_op_S_GETPC_B64, -amdgpu_cdna2_op_S_GETREG_B32, -amdgpu_cdna2_op_S_ICACHE_INV, -amdgpu_cdna2_op_S_INCPERFLEVEL, -amdgpu_cdna2_op_S_LOAD_DWORD, -amdgpu_cdna2_op_S_LOAD_DWORDX16, -amdgpu_cdna2_op_S_LOAD_DWORDX2, -amdgpu_cdna2_op_S_LOAD_DWORDX4, -amdgpu_cdna2_op_S_LOAD_DWORDX8, -amdgpu_cdna2_op_S_LSHL1_ADD_U32, -amdgpu_cdna2_op_S_LSHL2_ADD_U32, -amdgpu_cdna2_op_S_LSHL3_ADD_U32, -amdgpu_cdna2_op_S_LSHL4_ADD_U32, -amdgpu_cdna2_op_S_LSHL_B32, -amdgpu_cdna2_op_S_LSHL_B64, -amdgpu_cdna2_op_S_LSHR_B32, -amdgpu_cdna2_op_S_LSHR_B64, -amdgpu_cdna2_op_S_MAX_I32, -amdgpu_cdna2_op_S_MAX_U32, -amdgpu_cdna2_op_S_MEMREALTIME, -amdgpu_cdna2_op_S_MEMTIME, -amdgpu_cdna2_op_S_MIN_I32, -amdgpu_cdna2_op_S_MIN_U32, -amdgpu_cdna2_op_S_MOVK_I32, -amdgpu_cdna2_op_S_MOVRELD_B32, -amdgpu_cdna2_op_S_MOVRELD_B64, -amdgpu_cdna2_op_S_MOVRELS_B32, -amdgpu_cdna2_op_S_MOVRELS_B64, -amdgpu_cdna2_op_S_MOV_B32, -amdgpu_cdna2_op_S_MOV_B64, -amdgpu_cdna2_op_S_MULK_I32, -amdgpu_cdna2_op_S_MUL_HI_I32, -amdgpu_cdna2_op_S_MUL_HI_U32, -amdgpu_cdna2_op_S_MUL_I32, -amdgpu_cdna2_op_S_NAND_B32, -amdgpu_cdna2_op_S_NAND_B64, -amdgpu_cdna2_op_S_NAND_SAVEEXEC_B64, -amdgpu_cdna2_op_S_NOP, -amdgpu_cdna2_op_S_NOR_B32, -amdgpu_cdna2_op_S_NOR_B64, -amdgpu_cdna2_op_S_NOR_SAVEEXEC_B64, -amdgpu_cdna2_op_S_NOT_B32, -amdgpu_cdna2_op_S_NOT_B64, -amdgpu_cdna2_op_S_ORN1_SAVEEXEC_B64, -amdgpu_cdna2_op_S_ORN2_B32, -amdgpu_cdna2_op_S_ORN2_B64, -amdgpu_cdna2_op_S_ORN2_SAVEEXEC_B64, -amdgpu_cdna2_op_S_OR_B32, -amdgpu_cdna2_op_S_OR_B64, -amdgpu_cdna2_op_S_OR_SAVEEXEC_B64, -amdgpu_cdna2_op_S_PACK_HH_B32_B16, -amdgpu_cdna2_op_S_PACK_LH_B32_B16, -amdgpu_cdna2_op_S_PACK_LL_B32_B16, -amdgpu_cdna2_op_S_QUADMASK_B32, -amdgpu_cdna2_op_S_QUADMASK_B64, -amdgpu_cdna2_op_S_RFE_B64, -amdgpu_cdna2_op_S_RFE_RESTORE_B64, -amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORD, -amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX2, -amdgpu_cdna2_op_S_SCRATCH_LOAD_DWORDX4, -amdgpu_cdna2_op_S_SCRATCH_STORE_DWORD, -amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX2, -amdgpu_cdna2_op_S_SCRATCH_STORE_DWORDX4, -amdgpu_cdna2_op_S_SENDMSG, -amdgpu_cdna2_op_S_SENDMSGHALT, -amdgpu_cdna2_op_S_SETHALT, -amdgpu_cdna2_op_S_SETKILL, -amdgpu_cdna2_op_S_SETPC_B64, -amdgpu_cdna2_op_S_SETPRIO, -amdgpu_cdna2_op_S_SETREG_B32, -amdgpu_cdna2_op_S_SETREG_IMM32_B32, -amdgpu_cdna2_op_S_SETVSKIP, -amdgpu_cdna2_op_S_SET_GPR_IDX_IDX, -amdgpu_cdna2_op_S_SET_GPR_IDX_MODE, -amdgpu_cdna2_op_S_SET_GPR_IDX_OFF, -amdgpu_cdna2_op_S_SET_GPR_IDX_ON, -amdgpu_cdna2_op_S_SEXT_I32_I16, -amdgpu_cdna2_op_S_SEXT_I32_I8, -amdgpu_cdna2_op_S_SLEEP, -amdgpu_cdna2_op_S_STORE_DWORD, -amdgpu_cdna2_op_S_STORE_DWORDX2, -amdgpu_cdna2_op_S_STORE_DWORDX4, -amdgpu_cdna2_op_S_SUBB_U32, -amdgpu_cdna2_op_S_SUB_I32, -amdgpu_cdna2_op_S_SUB_U32, -amdgpu_cdna2_op_S_SWAPPC_B64, -amdgpu_cdna2_op_S_TRAP, -amdgpu_cdna2_op_S_TTRACEDATA, -amdgpu_cdna2_op_S_WAITCNT, -amdgpu_cdna2_op_S_WAKEUP, -amdgpu_cdna2_op_S_WQM_B32, -amdgpu_cdna2_op_S_WQM_B64, -amdgpu_cdna2_op_S_XNOR_B32, -amdgpu_cdna2_op_S_XNOR_B64, -amdgpu_cdna2_op_S_XNOR_SAVEEXEC_B64, -amdgpu_cdna2_op_S_XOR_B32, -amdgpu_cdna2_op_S_XOR_B64, -amdgpu_cdna2_op_S_XOR_SAVEEXEC_B64, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_X, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XY, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZ, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_D16_XYZW, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_X, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XY, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZ, -amdgpu_cdna2_op_TBUFFER_LOAD_FORMAT_XYZW, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_X, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XY, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZ, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_D16_XYZW, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_X, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XY, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZ, -amdgpu_cdna2_op_TBUFFER_STORE_FORMAT_XYZW, -amdgpu_cdna2_op_V_ACCVGPR_MOV_B32, -amdgpu_cdna2_op_V_ACCVGPR_READ, -amdgpu_cdna2_op_V_ACCVGPR_WRITE, -amdgpu_cdna2_op_V_ADD3_U32, -amdgpu_cdna2_op_V_ADDC_CO_U32, -amdgpu_cdna2_op_V_ADD_CO_U32, -amdgpu_cdna2_op_V_ADD_F16, -amdgpu_cdna2_op_V_ADD_F32, -amdgpu_cdna2_op_V_ADD_F64, -amdgpu_cdna2_op_V_ADD_I16, -amdgpu_cdna2_op_V_ADD_I32, -amdgpu_cdna2_op_V_ADD_LSHL_U32, -amdgpu_cdna2_op_V_ADD_U16, -amdgpu_cdna2_op_V_ADD_U32, -amdgpu_cdna2_op_V_ALIGNBIT_B32, -amdgpu_cdna2_op_V_ALIGNBYTE_B32, -amdgpu_cdna2_op_V_AND_B32, -amdgpu_cdna2_op_V_AND_OR_B32, -amdgpu_cdna2_op_V_ASHRREV_I16, -amdgpu_cdna2_op_V_ASHRREV_I32, -amdgpu_cdna2_op_V_ASHRREV_I64, -amdgpu_cdna2_op_V_BCNT_U32_B32, -amdgpu_cdna2_op_V_BFE_I32, -amdgpu_cdna2_op_V_BFE_U32, -amdgpu_cdna2_op_V_BFI_B32, -amdgpu_cdna2_op_V_BFM_B32, -amdgpu_cdna2_op_V_BFREV_B32, -amdgpu_cdna2_op_V_CEIL_F16, -amdgpu_cdna2_op_V_CEIL_F32, -amdgpu_cdna2_op_V_CEIL_F64, -amdgpu_cdna2_op_V_CLREXCP, -amdgpu_cdna2_op_V_CMPX_CLASS_F16, -amdgpu_cdna2_op_V_CMPX_CLASS_F32, -amdgpu_cdna2_op_V_CMPX_CLASS_F64, -amdgpu_cdna2_op_V_CMPX_EQ_F16, -amdgpu_cdna2_op_V_CMPX_EQ_F32, -amdgpu_cdna2_op_V_CMPX_EQ_F64, -amdgpu_cdna2_op_V_CMPX_EQ_I16, -amdgpu_cdna2_op_V_CMPX_EQ_I32, -amdgpu_cdna2_op_V_CMPX_EQ_I64, -amdgpu_cdna2_op_V_CMPX_EQ_U16, -amdgpu_cdna2_op_V_CMPX_EQ_U32, -amdgpu_cdna2_op_V_CMPX_EQ_U64, -amdgpu_cdna2_op_V_CMPX_F_F16, -amdgpu_cdna2_op_V_CMPX_F_F32, -amdgpu_cdna2_op_V_CMPX_F_F64, -amdgpu_cdna2_op_V_CMPX_F_I16, -amdgpu_cdna2_op_V_CMPX_F_I32, -amdgpu_cdna2_op_V_CMPX_F_I64, -amdgpu_cdna2_op_V_CMPX_F_U16, -amdgpu_cdna2_op_V_CMPX_F_U32, -amdgpu_cdna2_op_V_CMPX_F_U64, -amdgpu_cdna2_op_V_CMPX_GE_F16, -amdgpu_cdna2_op_V_CMPX_GE_F32, -amdgpu_cdna2_op_V_CMPX_GE_F64, -amdgpu_cdna2_op_V_CMPX_GE_I16, -amdgpu_cdna2_op_V_CMPX_GE_I32, -amdgpu_cdna2_op_V_CMPX_GE_I64, -amdgpu_cdna2_op_V_CMPX_GE_U16, -amdgpu_cdna2_op_V_CMPX_GE_U32, -amdgpu_cdna2_op_V_CMPX_GE_U64, -amdgpu_cdna2_op_V_CMPX_GT_F16, -amdgpu_cdna2_op_V_CMPX_GT_F32, -amdgpu_cdna2_op_V_CMPX_GT_F64, -amdgpu_cdna2_op_V_CMPX_GT_I16, -amdgpu_cdna2_op_V_CMPX_GT_I32, -amdgpu_cdna2_op_V_CMPX_GT_I64, -amdgpu_cdna2_op_V_CMPX_GT_U16, -amdgpu_cdna2_op_V_CMPX_GT_U32, -amdgpu_cdna2_op_V_CMPX_GT_U64, -amdgpu_cdna2_op_V_CMPX_LE_F16, -amdgpu_cdna2_op_V_CMPX_LE_F32, -amdgpu_cdna2_op_V_CMPX_LE_F64, -amdgpu_cdna2_op_V_CMPX_LE_I16, -amdgpu_cdna2_op_V_CMPX_LE_I32, -amdgpu_cdna2_op_V_CMPX_LE_I64, -amdgpu_cdna2_op_V_CMPX_LE_U16, -amdgpu_cdna2_op_V_CMPX_LE_U32, -amdgpu_cdna2_op_V_CMPX_LE_U64, -amdgpu_cdna2_op_V_CMPX_LG_F16, -amdgpu_cdna2_op_V_CMPX_LG_F32, -amdgpu_cdna2_op_V_CMPX_LG_F64, -amdgpu_cdna2_op_V_CMPX_LT_F16, -amdgpu_cdna2_op_V_CMPX_LT_F32, -amdgpu_cdna2_op_V_CMPX_LT_F64, -amdgpu_cdna2_op_V_CMPX_LT_I16, -amdgpu_cdna2_op_V_CMPX_LT_I32, -amdgpu_cdna2_op_V_CMPX_LT_I64, -amdgpu_cdna2_op_V_CMPX_LT_U16, -amdgpu_cdna2_op_V_CMPX_LT_U32, -amdgpu_cdna2_op_V_CMPX_LT_U64, -amdgpu_cdna2_op_V_CMPX_NEQ_F16, -amdgpu_cdna2_op_V_CMPX_NEQ_F32, -amdgpu_cdna2_op_V_CMPX_NEQ_F64, -amdgpu_cdna2_op_V_CMPX_NE_I16, -amdgpu_cdna2_op_V_CMPX_NE_I32, -amdgpu_cdna2_op_V_CMPX_NE_I64, -amdgpu_cdna2_op_V_CMPX_NE_U16, -amdgpu_cdna2_op_V_CMPX_NE_U32, -amdgpu_cdna2_op_V_CMPX_NE_U64, -amdgpu_cdna2_op_V_CMPX_NGE_F16, -amdgpu_cdna2_op_V_CMPX_NGE_F32, -amdgpu_cdna2_op_V_CMPX_NGE_F64, -amdgpu_cdna2_op_V_CMPX_NGT_F16, -amdgpu_cdna2_op_V_CMPX_NGT_F32, -amdgpu_cdna2_op_V_CMPX_NGT_F64, -amdgpu_cdna2_op_V_CMPX_NLE_F16, -amdgpu_cdna2_op_V_CMPX_NLE_F32, -amdgpu_cdna2_op_V_CMPX_NLE_F64, -amdgpu_cdna2_op_V_CMPX_NLG_F16, -amdgpu_cdna2_op_V_CMPX_NLG_F32, -amdgpu_cdna2_op_V_CMPX_NLG_F64, -amdgpu_cdna2_op_V_CMPX_NLT_F16, -amdgpu_cdna2_op_V_CMPX_NLT_F32, -amdgpu_cdna2_op_V_CMPX_NLT_F64, -amdgpu_cdna2_op_V_CMPX_O_F16, -amdgpu_cdna2_op_V_CMPX_O_F32, -amdgpu_cdna2_op_V_CMPX_O_F64, -amdgpu_cdna2_op_V_CMPX_TRU_F16, -amdgpu_cdna2_op_V_CMPX_TRU_F32, -amdgpu_cdna2_op_V_CMPX_TRU_F64, -amdgpu_cdna2_op_V_CMPX_T_I16, -amdgpu_cdna2_op_V_CMPX_T_I32, -amdgpu_cdna2_op_V_CMPX_T_I64, -amdgpu_cdna2_op_V_CMPX_T_U16, -amdgpu_cdna2_op_V_CMPX_T_U32, -amdgpu_cdna2_op_V_CMPX_T_U64, -amdgpu_cdna2_op_V_CMPX_U_F16, -amdgpu_cdna2_op_V_CMPX_U_F32, -amdgpu_cdna2_op_V_CMPX_U_F64, -amdgpu_cdna2_op_V_CMP_CLASS_F16, -amdgpu_cdna2_op_V_CMP_CLASS_F32, -amdgpu_cdna2_op_V_CMP_CLASS_F64, -amdgpu_cdna2_op_V_CMP_EQ_F16, -amdgpu_cdna2_op_V_CMP_EQ_F32, -amdgpu_cdna2_op_V_CMP_EQ_F64, -amdgpu_cdna2_op_V_CMP_EQ_I16, -amdgpu_cdna2_op_V_CMP_EQ_I32, -amdgpu_cdna2_op_V_CMP_EQ_I64, -amdgpu_cdna2_op_V_CMP_EQ_U16, -amdgpu_cdna2_op_V_CMP_EQ_U32, -amdgpu_cdna2_op_V_CMP_EQ_U64, -amdgpu_cdna2_op_V_CMP_F_F16, -amdgpu_cdna2_op_V_CMP_F_F32, -amdgpu_cdna2_op_V_CMP_F_F64, -amdgpu_cdna2_op_V_CMP_F_I16, -amdgpu_cdna2_op_V_CMP_F_I32, -amdgpu_cdna2_op_V_CMP_F_I64, -amdgpu_cdna2_op_V_CMP_F_U16, -amdgpu_cdna2_op_V_CMP_F_U32, -amdgpu_cdna2_op_V_CMP_F_U64, -amdgpu_cdna2_op_V_CMP_GE_F16, -amdgpu_cdna2_op_V_CMP_GE_F32, -amdgpu_cdna2_op_V_CMP_GE_F64, -amdgpu_cdna2_op_V_CMP_GE_I16, -amdgpu_cdna2_op_V_CMP_GE_I32, -amdgpu_cdna2_op_V_CMP_GE_I64, -amdgpu_cdna2_op_V_CMP_GE_U16, -amdgpu_cdna2_op_V_CMP_GE_U32, -amdgpu_cdna2_op_V_CMP_GE_U64, -amdgpu_cdna2_op_V_CMP_GT_F16, -amdgpu_cdna2_op_V_CMP_GT_F32, -amdgpu_cdna2_op_V_CMP_GT_F64, -amdgpu_cdna2_op_V_CMP_GT_I16, -amdgpu_cdna2_op_V_CMP_GT_I32, -amdgpu_cdna2_op_V_CMP_GT_I64, -amdgpu_cdna2_op_V_CMP_GT_U16, -amdgpu_cdna2_op_V_CMP_GT_U32, -amdgpu_cdna2_op_V_CMP_GT_U64, -amdgpu_cdna2_op_V_CMP_LE_F16, -amdgpu_cdna2_op_V_CMP_LE_F32, -amdgpu_cdna2_op_V_CMP_LE_F64, -amdgpu_cdna2_op_V_CMP_LE_I16, -amdgpu_cdna2_op_V_CMP_LE_I32, -amdgpu_cdna2_op_V_CMP_LE_I64, -amdgpu_cdna2_op_V_CMP_LE_U16, -amdgpu_cdna2_op_V_CMP_LE_U32, -amdgpu_cdna2_op_V_CMP_LE_U64, -amdgpu_cdna2_op_V_CMP_LG_F16, -amdgpu_cdna2_op_V_CMP_LG_F32, -amdgpu_cdna2_op_V_CMP_LG_F64, -amdgpu_cdna2_op_V_CMP_LT_F16, -amdgpu_cdna2_op_V_CMP_LT_F32, -amdgpu_cdna2_op_V_CMP_LT_F64, -amdgpu_cdna2_op_V_CMP_LT_I16, -amdgpu_cdna2_op_V_CMP_LT_I32, -amdgpu_cdna2_op_V_CMP_LT_I64, -amdgpu_cdna2_op_V_CMP_LT_U16, -amdgpu_cdna2_op_V_CMP_LT_U32, -amdgpu_cdna2_op_V_CMP_LT_U64, -amdgpu_cdna2_op_V_CMP_NEQ_F16, -amdgpu_cdna2_op_V_CMP_NEQ_F32, -amdgpu_cdna2_op_V_CMP_NEQ_F64, -amdgpu_cdna2_op_V_CMP_NE_I16, -amdgpu_cdna2_op_V_CMP_NE_I32, -amdgpu_cdna2_op_V_CMP_NE_I64, -amdgpu_cdna2_op_V_CMP_NE_U16, -amdgpu_cdna2_op_V_CMP_NE_U32, -amdgpu_cdna2_op_V_CMP_NE_U64, -amdgpu_cdna2_op_V_CMP_NGE_F16, -amdgpu_cdna2_op_V_CMP_NGE_F32, -amdgpu_cdna2_op_V_CMP_NGE_F64, -amdgpu_cdna2_op_V_CMP_NGT_F16, -amdgpu_cdna2_op_V_CMP_NGT_F32, -amdgpu_cdna2_op_V_CMP_NGT_F64, -amdgpu_cdna2_op_V_CMP_NLE_F16, -amdgpu_cdna2_op_V_CMP_NLE_F32, -amdgpu_cdna2_op_V_CMP_NLE_F64, -amdgpu_cdna2_op_V_CMP_NLG_F16, -amdgpu_cdna2_op_V_CMP_NLG_F32, -amdgpu_cdna2_op_V_CMP_NLG_F64, -amdgpu_cdna2_op_V_CMP_NLT_F16, -amdgpu_cdna2_op_V_CMP_NLT_F32, -amdgpu_cdna2_op_V_CMP_NLT_F64, -amdgpu_cdna2_op_V_CMP_O_F16, -amdgpu_cdna2_op_V_CMP_O_F32, -amdgpu_cdna2_op_V_CMP_O_F64, -amdgpu_cdna2_op_V_CMP_TRU_F16, -amdgpu_cdna2_op_V_CMP_TRU_F32, -amdgpu_cdna2_op_V_CMP_TRU_F64, -amdgpu_cdna2_op_V_CMP_T_I16, -amdgpu_cdna2_op_V_CMP_T_I32, -amdgpu_cdna2_op_V_CMP_T_I64, -amdgpu_cdna2_op_V_CMP_T_U16, -amdgpu_cdna2_op_V_CMP_T_U32, -amdgpu_cdna2_op_V_CMP_T_U64, -amdgpu_cdna2_op_V_CMP_U_F16, -amdgpu_cdna2_op_V_CMP_U_F32, -amdgpu_cdna2_op_V_CMP_U_F64, -amdgpu_cdna2_op_V_CNDMASK_B32, -amdgpu_cdna2_op_V_COS_F16, -amdgpu_cdna2_op_V_COS_F32, -amdgpu_cdna2_op_V_CUBEID_F32, -amdgpu_cdna2_op_V_CUBEMA_F32, -amdgpu_cdna2_op_V_CUBESC_F32, -amdgpu_cdna2_op_V_CUBETC_F32, -amdgpu_cdna2_op_V_CVT_F16_F32, -amdgpu_cdna2_op_V_CVT_F16_I16, -amdgpu_cdna2_op_V_CVT_F16_U16, -amdgpu_cdna2_op_V_CVT_F32_F16, -amdgpu_cdna2_op_V_CVT_F32_F64, -amdgpu_cdna2_op_V_CVT_F32_I32, -amdgpu_cdna2_op_V_CVT_F32_U32, -amdgpu_cdna2_op_V_CVT_F32_UBYTE0, -amdgpu_cdna2_op_V_CVT_F32_UBYTE1, -amdgpu_cdna2_op_V_CVT_F32_UBYTE2, -amdgpu_cdna2_op_V_CVT_F32_UBYTE3, -amdgpu_cdna2_op_V_CVT_F64_F32, -amdgpu_cdna2_op_V_CVT_F64_I32, -amdgpu_cdna2_op_V_CVT_F64_U32, -amdgpu_cdna2_op_V_CVT_FLR_I32_F32, -amdgpu_cdna2_op_V_CVT_I16_F16, -amdgpu_cdna2_op_V_CVT_I32_F32, -amdgpu_cdna2_op_V_CVT_I32_F64, -amdgpu_cdna2_op_V_CVT_NORM_I16_F16, -amdgpu_cdna2_op_V_CVT_NORM_U16_F16, -amdgpu_cdna2_op_V_CVT_OFF_F32_I4, -amdgpu_cdna2_op_V_CVT_PKACCUM_U8_F32, -amdgpu_cdna2_op_V_CVT_PKNORM_I16_F16, -amdgpu_cdna2_op_V_CVT_PKNORM_I16_F32, -amdgpu_cdna2_op_V_CVT_PKNORM_U16_F16, -amdgpu_cdna2_op_V_CVT_PKNORM_U16_F32, -amdgpu_cdna2_op_V_CVT_PKRTZ_F16_F32, -amdgpu_cdna2_op_V_CVT_PK_I16_I32, -amdgpu_cdna2_op_V_CVT_PK_U16_U32, -amdgpu_cdna2_op_V_CVT_PK_U8_F32, -amdgpu_cdna2_op_V_CVT_RPI_I32_F32, -amdgpu_cdna2_op_V_CVT_U16_F16, -amdgpu_cdna2_op_V_CVT_U32_F32, -amdgpu_cdna2_op_V_CVT_U32_F64, -amdgpu_cdna2_op_V_DIV_FIXUP_F16, -amdgpu_cdna2_op_V_DIV_FIXUP_F32, -amdgpu_cdna2_op_V_DIV_FIXUP_F64, -amdgpu_cdna2_op_V_DIV_FIXUP_LEGACY_F16, -amdgpu_cdna2_op_V_DIV_FMAS_F32, -amdgpu_cdna2_op_V_DIV_FMAS_F64, -amdgpu_cdna2_op_V_DIV_SCALE_F32, -amdgpu_cdna2_op_V_DIV_SCALE_F64, -amdgpu_cdna2_op_V_DOT2C_F32_F16, -amdgpu_cdna2_op_V_DOT2C_I32_I16, -amdgpu_cdna2_op_V_DOT2_F32_F16, -amdgpu_cdna2_op_V_DOT2_I32_I16, -amdgpu_cdna2_op_V_DOT2_U32_U16, -amdgpu_cdna2_op_V_DOT4C_I32_I8, -amdgpu_cdna2_op_V_DOT4_I32_I8, -amdgpu_cdna2_op_V_DOT4_U32_U8, -amdgpu_cdna2_op_V_DOT8C_I32_I4, -amdgpu_cdna2_op_V_DOT8_I32_I4, -amdgpu_cdna2_op_V_DOT8_U32_U4, -amdgpu_cdna2_op_V_EXP_F16, -amdgpu_cdna2_op_V_EXP_F32, -amdgpu_cdna2_op_V_EXP_LEGACY_F32, -amdgpu_cdna2_op_V_FFBH_I32, -amdgpu_cdna2_op_V_FFBH_U32, -amdgpu_cdna2_op_V_FFBL_B32, -amdgpu_cdna2_op_V_FLOOR_F16, -amdgpu_cdna2_op_V_FLOOR_F32, -amdgpu_cdna2_op_V_FLOOR_F64, -amdgpu_cdna2_op_V_FMAC_F32, -amdgpu_cdna2_op_V_FMAC_F64, -amdgpu_cdna2_op_V_FMA_F16, -amdgpu_cdna2_op_V_FMA_F32, -amdgpu_cdna2_op_V_FMA_F64, -amdgpu_cdna2_op_V_FMA_LEGACY_F16, -amdgpu_cdna2_op_V_FRACT_F16, -amdgpu_cdna2_op_V_FRACT_F32, -amdgpu_cdna2_op_V_FRACT_F64, -amdgpu_cdna2_op_V_FREXP_EXP_I16_F16, -amdgpu_cdna2_op_V_FREXP_EXP_I32_F32, -amdgpu_cdna2_op_V_FREXP_EXP_I32_F64, -amdgpu_cdna2_op_V_FREXP_MANT_F16, -amdgpu_cdna2_op_V_FREXP_MANT_F32, -amdgpu_cdna2_op_V_FREXP_MANT_F64, -amdgpu_cdna2_op_V_LDEXP_F16, -amdgpu_cdna2_op_V_LDEXP_F32, -amdgpu_cdna2_op_V_LDEXP_F64, -amdgpu_cdna2_op_V_LERP_U8, -amdgpu_cdna2_op_V_LOG_F16, -amdgpu_cdna2_op_V_LOG_F32, -amdgpu_cdna2_op_V_LOG_LEGACY_F32, -amdgpu_cdna2_op_V_LSHLREV_B16, -amdgpu_cdna2_op_V_LSHLREV_B32, -amdgpu_cdna2_op_V_LSHLREV_B64, -amdgpu_cdna2_op_V_LSHL_ADD_U32, -amdgpu_cdna2_op_V_LSHL_OR_B32, -amdgpu_cdna2_op_V_LSHRREV_B16, -amdgpu_cdna2_op_V_LSHRREV_B32, -amdgpu_cdna2_op_V_LSHRREV_B64, -amdgpu_cdna2_op_V_MAC_F16, -amdgpu_cdna2_op_V_MAC_F32, -amdgpu_cdna2_op_V_MADAK_F16, -amdgpu_cdna2_op_V_MADAK_F32, -amdgpu_cdna2_op_V_MADMK_F16, -amdgpu_cdna2_op_V_MADMK_F32, -amdgpu_cdna2_op_V_MAD_F16, -amdgpu_cdna2_op_V_MAD_F32, -amdgpu_cdna2_op_V_MAD_I16, -amdgpu_cdna2_op_V_MAD_I32_I16, -amdgpu_cdna2_op_V_MAD_I32_I24, -amdgpu_cdna2_op_V_MAD_I64_I32, -amdgpu_cdna2_op_V_MAD_LEGACY_F16, -amdgpu_cdna2_op_V_MAD_LEGACY_F32, -amdgpu_cdna2_op_V_MAD_LEGACY_I16, -amdgpu_cdna2_op_V_MAD_LEGACY_U16, -amdgpu_cdna2_op_V_MAD_MIXHI_F16, -amdgpu_cdna2_op_V_MAD_MIXLO_F16, -amdgpu_cdna2_op_V_MAD_MIX_F32, -amdgpu_cdna2_op_V_MAD_U16, -amdgpu_cdna2_op_V_MAD_U32_U16, -amdgpu_cdna2_op_V_MAD_U32_U24, -amdgpu_cdna2_op_V_MAD_U64_U32, -amdgpu_cdna2_op_V_MAX3_F16, -amdgpu_cdna2_op_V_MAX3_F32, -amdgpu_cdna2_op_V_MAX3_I16, -amdgpu_cdna2_op_V_MAX3_I32, -amdgpu_cdna2_op_V_MAX3_U16, -amdgpu_cdna2_op_V_MAX3_U32, -amdgpu_cdna2_op_V_MAX_F16, -amdgpu_cdna2_op_V_MAX_F32, -amdgpu_cdna2_op_V_MAX_F64, -amdgpu_cdna2_op_V_MAX_I16, -amdgpu_cdna2_op_V_MAX_I32, -amdgpu_cdna2_op_V_MAX_U16, -amdgpu_cdna2_op_V_MAX_U32, -amdgpu_cdna2_op_V_MBCNT_HI_U32_B32, -amdgpu_cdna2_op_V_MBCNT_LO_U32_B32, -amdgpu_cdna2_op_V_MED3_F16, -amdgpu_cdna2_op_V_MED3_F32, -amdgpu_cdna2_op_V_MED3_I16, -amdgpu_cdna2_op_V_MED3_I32, -amdgpu_cdna2_op_V_MED3_U16, -amdgpu_cdna2_op_V_MED3_U32, -amdgpu_cdna2_op_V_MFMA_F32_16X16X16BF16_1K, -amdgpu_cdna2_op_V_MFMA_F32_16X16X16F16, -amdgpu_cdna2_op_V_MFMA_F32_16X16X1F32, -amdgpu_cdna2_op_V_MFMA_F32_16X16X2BF16, -amdgpu_cdna2_op_V_MFMA_F32_16X16X4BF16_1K, -amdgpu_cdna2_op_V_MFMA_F32_16X16X4F16, -amdgpu_cdna2_op_V_MFMA_F32_16X16X4F32, -amdgpu_cdna2_op_V_MFMA_F32_16X16X8BF16, -amdgpu_cdna2_op_V_MFMA_F32_32X32X1F32, -amdgpu_cdna2_op_V_MFMA_F32_32X32X2BF16, -amdgpu_cdna2_op_V_MFMA_F32_32X32X2F32, -amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16, -amdgpu_cdna2_op_V_MFMA_F32_32X32X4BF16_1K, -amdgpu_cdna2_op_V_MFMA_F32_32X32X4F16, -amdgpu_cdna2_op_V_MFMA_F32_32X32X8BF16_1K, -amdgpu_cdna2_op_V_MFMA_F32_32X32X8F16, -amdgpu_cdna2_op_V_MFMA_F32_4X4X1F32, -amdgpu_cdna2_op_V_MFMA_F32_4X4X2BF16, -amdgpu_cdna2_op_V_MFMA_F32_4X4X4BF16_1K, -amdgpu_cdna2_op_V_MFMA_F32_4X4X4F16, -amdgpu_cdna2_op_V_MFMA_F64_16X16X4F64, -amdgpu_cdna2_op_V_MFMA_F64_4X4X4F64, -amdgpu_cdna2_op_V_MFMA_I32_16X16X16I8, -amdgpu_cdna2_op_V_MFMA_I32_16X16X4I8, -amdgpu_cdna2_op_V_MFMA_I32_32X32X4I8, -amdgpu_cdna2_op_V_MFMA_I32_32X32X8I8, -amdgpu_cdna2_op_V_MFMA_I32_4X4X4I8, -amdgpu_cdna2_op_V_MIN3_F16, -amdgpu_cdna2_op_V_MIN3_F32, -amdgpu_cdna2_op_V_MIN3_I16, -amdgpu_cdna2_op_V_MIN3_I32, -amdgpu_cdna2_op_V_MIN3_U16, -amdgpu_cdna2_op_V_MIN3_U32, -amdgpu_cdna2_op_V_MIN_F16, -amdgpu_cdna2_op_V_MIN_F32, -amdgpu_cdna2_op_V_MIN_F64, -amdgpu_cdna2_op_V_MIN_I16, -amdgpu_cdna2_op_V_MIN_I32, -amdgpu_cdna2_op_V_MIN_U16, -amdgpu_cdna2_op_V_MIN_U32, -amdgpu_cdna2_op_V_MOV_B32, -amdgpu_cdna2_op_V_MQSAD_PK_U16_U8, -amdgpu_cdna2_op_V_MQSAD_U32_U8, -amdgpu_cdna2_op_V_MSAD_U8, -amdgpu_cdna2_op_V_MUL_F16, -amdgpu_cdna2_op_V_MUL_F32, -amdgpu_cdna2_op_V_MUL_F64, -amdgpu_cdna2_op_V_MUL_HI_I32, -amdgpu_cdna2_op_V_MUL_HI_I32_I24, -amdgpu_cdna2_op_V_MUL_HI_U32, -amdgpu_cdna2_op_V_MUL_HI_U32_U24, -amdgpu_cdna2_op_V_MUL_I32_I24, -amdgpu_cdna2_op_V_MUL_LEGACY_F32, -amdgpu_cdna2_op_V_MUL_LO_U16, -amdgpu_cdna2_op_V_MUL_LO_U32, -amdgpu_cdna2_op_V_MUL_U32_U24, -amdgpu_cdna2_op_V_NOP, -amdgpu_cdna2_op_V_NOT_B32, -amdgpu_cdna2_op_V_OR3_B32, -amdgpu_cdna2_op_V_OR_B32, -amdgpu_cdna2_op_V_PACK_B32_F16, -amdgpu_cdna2_op_V_PERM_B32, -amdgpu_cdna2_op_V_PK_ADD_F16, -amdgpu_cdna2_op_V_PK_ADD_F32, -amdgpu_cdna2_op_V_PK_ADD_I16, -amdgpu_cdna2_op_V_PK_ADD_U16, -amdgpu_cdna2_op_V_PK_ASHRREV_I16, -amdgpu_cdna2_op_V_PK_FMAC_F16, -amdgpu_cdna2_op_V_PK_FMA_F16, -amdgpu_cdna2_op_V_PK_FMA_F32, -amdgpu_cdna2_op_V_PK_LSHLREV_B16, -amdgpu_cdna2_op_V_PK_LSHRREV_B16, -amdgpu_cdna2_op_V_PK_MAD_I16, -amdgpu_cdna2_op_V_PK_MAD_U16, -amdgpu_cdna2_op_V_PK_MAX_F16, -amdgpu_cdna2_op_V_PK_MAX_I16, -amdgpu_cdna2_op_V_PK_MAX_U16, -amdgpu_cdna2_op_V_PK_MIN_F16, -amdgpu_cdna2_op_V_PK_MIN_I16, -amdgpu_cdna2_op_V_PK_MIN_U16, -amdgpu_cdna2_op_V_PK_MOV_B32, -amdgpu_cdna2_op_V_PK_MUL_F16, -amdgpu_cdna2_op_V_PK_MUL_F32, -amdgpu_cdna2_op_V_PK_MUL_LO_U16, -amdgpu_cdna2_op_V_PK_SUB_I16, -amdgpu_cdna2_op_V_PK_SUB_U16, -amdgpu_cdna2_op_V_QSAD_PK_U16_U8, -amdgpu_cdna2_op_V_RCP_F16, -amdgpu_cdna2_op_V_RCP_F32, -amdgpu_cdna2_op_V_RCP_F64, -amdgpu_cdna2_op_V_RCP_IFLAG_F32, -amdgpu_cdna2_op_V_READFIRSTLANE_B32, -amdgpu_cdna2_op_V_READLANE_B32, -amdgpu_cdna2_op_V_RNDNE_F16, -amdgpu_cdna2_op_V_RNDNE_F32, -amdgpu_cdna2_op_V_RNDNE_F64, -amdgpu_cdna2_op_V_RSQ_F16, -amdgpu_cdna2_op_V_RSQ_F32, -amdgpu_cdna2_op_V_RSQ_F64, -amdgpu_cdna2_op_V_SAD_HI_U8, -amdgpu_cdna2_op_V_SAD_U16, -amdgpu_cdna2_op_V_SAD_U32, -amdgpu_cdna2_op_V_SAD_U8, -amdgpu_cdna2_op_V_SAT_PK_U8_I16, -amdgpu_cdna2_op_V_SCREEN_PARTITION_4SE_B32, -amdgpu_cdna2_op_V_SIN_F16, -amdgpu_cdna2_op_V_SIN_F32, -amdgpu_cdna2_op_V_SQRT_F16, -amdgpu_cdna2_op_V_SQRT_F32, -amdgpu_cdna2_op_V_SQRT_F64, -amdgpu_cdna2_op_V_SUBBREV_CO_U32, -amdgpu_cdna2_op_V_SUBB_CO_U32, -amdgpu_cdna2_op_V_SUBREV_CO_U32, -amdgpu_cdna2_op_V_SUBREV_F16, -amdgpu_cdna2_op_V_SUBREV_F32, -amdgpu_cdna2_op_V_SUBREV_U16, -amdgpu_cdna2_op_V_SUBREV_U32, -amdgpu_cdna2_op_V_SUB_CO_U32, -amdgpu_cdna2_op_V_SUB_F16, -amdgpu_cdna2_op_V_SUB_F32, -amdgpu_cdna2_op_V_SUB_I16, -amdgpu_cdna2_op_V_SUB_I32, -amdgpu_cdna2_op_V_SUB_U16, -amdgpu_cdna2_op_V_SUB_U32, -amdgpu_cdna2_op_V_SWAP_B32, -amdgpu_cdna2_op_V_TRIG_PREOP_F64, -amdgpu_cdna2_op_V_TRUNC_F16, -amdgpu_cdna2_op_V_TRUNC_F32, -amdgpu_cdna2_op_V_TRUNC_F64, -amdgpu_cdna2_op_V_WRITELANE_B32, -amdgpu_cdna2_op_V_XAD_U32, -amdgpu_cdna2_op_V_XNOR_B32, -amdgpu_cdna2_op_V_XOR_B32, diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h deleted file mode 100644 index 8515f8630b..0000000000 --- a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h +++ /dev/null @@ -1,617 +0,0 @@ -#ifndef DYNINST_AMDGPU_CDNA2_SYS_REGS_H -#define DYNINST_AMDGPU_CDNA2_SYS_REGS_H -DEF_REGISTER(s0, Arch_amdgpu_cdna2| SGPR | BITS_32 | 0 , "amdgpu_cdna2"); -DEF_REGISTER(s1, Arch_amdgpu_cdna2| SGPR | BITS_32 | 1 , "amdgpu_cdna2"); -DEF_REGISTER(s2, Arch_amdgpu_cdna2| SGPR | BITS_32 | 2 , "amdgpu_cdna2"); -DEF_REGISTER(s3, Arch_amdgpu_cdna2| SGPR | BITS_32 | 3 , "amdgpu_cdna2"); -DEF_REGISTER(s4, Arch_amdgpu_cdna2| SGPR | BITS_32 | 4 , "amdgpu_cdna2"); -DEF_REGISTER(s5, Arch_amdgpu_cdna2| SGPR | BITS_32 | 5 , "amdgpu_cdna2"); -DEF_REGISTER(s6, Arch_amdgpu_cdna2| SGPR | BITS_32 | 6 , "amdgpu_cdna2"); -DEF_REGISTER(s7, Arch_amdgpu_cdna2| SGPR | BITS_32 | 7 , "amdgpu_cdna2"); -DEF_REGISTER(s8, Arch_amdgpu_cdna2| SGPR | BITS_32 | 8 , "amdgpu_cdna2"); -DEF_REGISTER(s9, Arch_amdgpu_cdna2| SGPR | BITS_32 | 9 , "amdgpu_cdna2"); -DEF_REGISTER(s10, Arch_amdgpu_cdna2| SGPR | BITS_32 | 10 , "amdgpu_cdna2"); -DEF_REGISTER(s11, Arch_amdgpu_cdna2| SGPR | BITS_32 | 11 , "amdgpu_cdna2"); -DEF_REGISTER(s12, Arch_amdgpu_cdna2| SGPR | BITS_32 | 12 , "amdgpu_cdna2"); -DEF_REGISTER(s13, Arch_amdgpu_cdna2| SGPR | BITS_32 | 13 , "amdgpu_cdna2"); -DEF_REGISTER(s14, Arch_amdgpu_cdna2| SGPR | BITS_32 | 14 , "amdgpu_cdna2"); -DEF_REGISTER(s15, Arch_amdgpu_cdna2| SGPR | BITS_32 | 15 , "amdgpu_cdna2"); -DEF_REGISTER(s16, Arch_amdgpu_cdna2| SGPR | BITS_32 | 16 , "amdgpu_cdna2"); -DEF_REGISTER(s17, Arch_amdgpu_cdna2| SGPR | BITS_32 | 17 , "amdgpu_cdna2"); -DEF_REGISTER(s18, Arch_amdgpu_cdna2| SGPR | BITS_32 | 18 , "amdgpu_cdna2"); -DEF_REGISTER(s19, Arch_amdgpu_cdna2| SGPR | BITS_32 | 19 , "amdgpu_cdna2"); -DEF_REGISTER(s20, Arch_amdgpu_cdna2| SGPR | BITS_32 | 20 , "amdgpu_cdna2"); -DEF_REGISTER(s21, Arch_amdgpu_cdna2| SGPR | BITS_32 | 21 , "amdgpu_cdna2"); -DEF_REGISTER(s22, Arch_amdgpu_cdna2| SGPR | BITS_32 | 22 , "amdgpu_cdna2"); -DEF_REGISTER(s23, Arch_amdgpu_cdna2| SGPR | BITS_32 | 23 , "amdgpu_cdna2"); -DEF_REGISTER(s24, Arch_amdgpu_cdna2| SGPR | BITS_32 | 24 , "amdgpu_cdna2"); -DEF_REGISTER(s25, Arch_amdgpu_cdna2| SGPR | BITS_32 | 25 , "amdgpu_cdna2"); -DEF_REGISTER(s26, Arch_amdgpu_cdna2| SGPR | BITS_32 | 26 , "amdgpu_cdna2"); -DEF_REGISTER(s27, Arch_amdgpu_cdna2| SGPR | BITS_32 | 27 , "amdgpu_cdna2"); -DEF_REGISTER(s28, Arch_amdgpu_cdna2| SGPR | BITS_32 | 28 , "amdgpu_cdna2"); -DEF_REGISTER(s29, Arch_amdgpu_cdna2| SGPR | BITS_32 | 29 , "amdgpu_cdna2"); -DEF_REGISTER(s30, Arch_amdgpu_cdna2| SGPR | BITS_32 | 30 , "amdgpu_cdna2"); -DEF_REGISTER(s31, Arch_amdgpu_cdna2| SGPR | BITS_32 | 31 , "amdgpu_cdna2"); -DEF_REGISTER(s32, Arch_amdgpu_cdna2| SGPR | BITS_32 | 32 , "amdgpu_cdna2"); -DEF_REGISTER(s33, Arch_amdgpu_cdna2| SGPR | BITS_32 | 33 , "amdgpu_cdna2"); -DEF_REGISTER(s34, Arch_amdgpu_cdna2| SGPR | BITS_32 | 34 , "amdgpu_cdna2"); -DEF_REGISTER(s35, Arch_amdgpu_cdna2| SGPR | BITS_32 | 35 , "amdgpu_cdna2"); -DEF_REGISTER(s36, Arch_amdgpu_cdna2| SGPR | BITS_32 | 36 , "amdgpu_cdna2"); -DEF_REGISTER(s37, Arch_amdgpu_cdna2| SGPR | BITS_32 | 37 , "amdgpu_cdna2"); -DEF_REGISTER(s38, Arch_amdgpu_cdna2| SGPR | BITS_32 | 38 , "amdgpu_cdna2"); -DEF_REGISTER(s39, Arch_amdgpu_cdna2| SGPR | BITS_32 | 39 , "amdgpu_cdna2"); -DEF_REGISTER(s40, Arch_amdgpu_cdna2| SGPR | BITS_32 | 40 , "amdgpu_cdna2"); -DEF_REGISTER(s41, Arch_amdgpu_cdna2| SGPR | BITS_32 | 41 , "amdgpu_cdna2"); -DEF_REGISTER(s42, Arch_amdgpu_cdna2| SGPR | BITS_32 | 42 , "amdgpu_cdna2"); -DEF_REGISTER(s43, Arch_amdgpu_cdna2| SGPR | BITS_32 | 43 , "amdgpu_cdna2"); -DEF_REGISTER(s44, Arch_amdgpu_cdna2| SGPR | BITS_32 | 44 , "amdgpu_cdna2"); -DEF_REGISTER(s45, Arch_amdgpu_cdna2| SGPR | BITS_32 | 45 , "amdgpu_cdna2"); -DEF_REGISTER(s46, Arch_amdgpu_cdna2| SGPR | BITS_32 | 46 , "amdgpu_cdna2"); -DEF_REGISTER(s47, Arch_amdgpu_cdna2| SGPR | BITS_32 | 47 , "amdgpu_cdna2"); -DEF_REGISTER(s48, Arch_amdgpu_cdna2| SGPR | BITS_32 | 48 , "amdgpu_cdna2"); -DEF_REGISTER(s49, Arch_amdgpu_cdna2| SGPR | BITS_32 | 49 , "amdgpu_cdna2"); -DEF_REGISTER(s50, Arch_amdgpu_cdna2| SGPR | BITS_32 | 50 , "amdgpu_cdna2"); -DEF_REGISTER(s51, Arch_amdgpu_cdna2| SGPR | BITS_32 | 51 , "amdgpu_cdna2"); -DEF_REGISTER(s52, Arch_amdgpu_cdna2| SGPR | BITS_32 | 52 , "amdgpu_cdna2"); -DEF_REGISTER(s53, Arch_amdgpu_cdna2| SGPR | BITS_32 | 53 , "amdgpu_cdna2"); -DEF_REGISTER(s54, Arch_amdgpu_cdna2| SGPR | BITS_32 | 54 , "amdgpu_cdna2"); -DEF_REGISTER(s55, Arch_amdgpu_cdna2| SGPR | BITS_32 | 55 , "amdgpu_cdna2"); -DEF_REGISTER(s56, Arch_amdgpu_cdna2| SGPR | BITS_32 | 56 , "amdgpu_cdna2"); -DEF_REGISTER(s57, Arch_amdgpu_cdna2| SGPR | BITS_32 | 57 , "amdgpu_cdna2"); -DEF_REGISTER(s58, Arch_amdgpu_cdna2| SGPR | BITS_32 | 58 , "amdgpu_cdna2"); -DEF_REGISTER(s59, Arch_amdgpu_cdna2| SGPR | BITS_32 | 59 , "amdgpu_cdna2"); -DEF_REGISTER(s60, Arch_amdgpu_cdna2| SGPR | BITS_32 | 60 , "amdgpu_cdna2"); -DEF_REGISTER(s61, Arch_amdgpu_cdna2| SGPR | BITS_32 | 61 , "amdgpu_cdna2"); -DEF_REGISTER(s62, Arch_amdgpu_cdna2| SGPR | BITS_32 | 62 , "amdgpu_cdna2"); -DEF_REGISTER(s63, Arch_amdgpu_cdna2| SGPR | BITS_32 | 63 , "amdgpu_cdna2"); -DEF_REGISTER(s64, Arch_amdgpu_cdna2| SGPR | BITS_32 | 64 , "amdgpu_cdna2"); -DEF_REGISTER(s65, Arch_amdgpu_cdna2| SGPR | BITS_32 | 65 , "amdgpu_cdna2"); -DEF_REGISTER(s66, Arch_amdgpu_cdna2| SGPR | BITS_32 | 66 , "amdgpu_cdna2"); -DEF_REGISTER(s67, Arch_amdgpu_cdna2| SGPR | BITS_32 | 67 , "amdgpu_cdna2"); -DEF_REGISTER(s68, Arch_amdgpu_cdna2| SGPR | BITS_32 | 68 , "amdgpu_cdna2"); -DEF_REGISTER(s69, Arch_amdgpu_cdna2| SGPR | BITS_32 | 69 , "amdgpu_cdna2"); -DEF_REGISTER(s70, Arch_amdgpu_cdna2| SGPR | BITS_32 | 70 , "amdgpu_cdna2"); -DEF_REGISTER(s71, Arch_amdgpu_cdna2| SGPR | BITS_32 | 71 , "amdgpu_cdna2"); -DEF_REGISTER(s72, Arch_amdgpu_cdna2| SGPR | BITS_32 | 72 , "amdgpu_cdna2"); -DEF_REGISTER(s73, Arch_amdgpu_cdna2| SGPR | BITS_32 | 73 , "amdgpu_cdna2"); -DEF_REGISTER(s74, Arch_amdgpu_cdna2| SGPR | BITS_32 | 74 , "amdgpu_cdna2"); -DEF_REGISTER(s75, Arch_amdgpu_cdna2| SGPR | BITS_32 | 75 , "amdgpu_cdna2"); -DEF_REGISTER(s76, Arch_amdgpu_cdna2| SGPR | BITS_32 | 76 , "amdgpu_cdna2"); -DEF_REGISTER(s77, Arch_amdgpu_cdna2| SGPR | BITS_32 | 77 , "amdgpu_cdna2"); -DEF_REGISTER(s78, Arch_amdgpu_cdna2| SGPR | BITS_32 | 78 , "amdgpu_cdna2"); -DEF_REGISTER(s79, Arch_amdgpu_cdna2| SGPR | BITS_32 | 79 , "amdgpu_cdna2"); -DEF_REGISTER(s80, Arch_amdgpu_cdna2| SGPR | BITS_32 | 80 , "amdgpu_cdna2"); -DEF_REGISTER(s81, Arch_amdgpu_cdna2| SGPR | BITS_32 | 81 , "amdgpu_cdna2"); -DEF_REGISTER(s82, Arch_amdgpu_cdna2| SGPR | BITS_32 | 82 , "amdgpu_cdna2"); -DEF_REGISTER(s83, Arch_amdgpu_cdna2| SGPR | BITS_32 | 83 , "amdgpu_cdna2"); -DEF_REGISTER(s84, Arch_amdgpu_cdna2| SGPR | BITS_32 | 84 , "amdgpu_cdna2"); -DEF_REGISTER(s85, Arch_amdgpu_cdna2| SGPR | BITS_32 | 85 , "amdgpu_cdna2"); -DEF_REGISTER(s86, Arch_amdgpu_cdna2| SGPR | BITS_32 | 86 , "amdgpu_cdna2"); -DEF_REGISTER(s87, Arch_amdgpu_cdna2| SGPR | BITS_32 | 87 , "amdgpu_cdna2"); -DEF_REGISTER(s88, Arch_amdgpu_cdna2| SGPR | BITS_32 | 88 , "amdgpu_cdna2"); -DEF_REGISTER(s89, Arch_amdgpu_cdna2| SGPR | BITS_32 | 89 , "amdgpu_cdna2"); -DEF_REGISTER(s90, Arch_amdgpu_cdna2| SGPR | BITS_32 | 90 , "amdgpu_cdna2"); -DEF_REGISTER(s91, Arch_amdgpu_cdna2| SGPR | BITS_32 | 91 , "amdgpu_cdna2"); -DEF_REGISTER(s92, Arch_amdgpu_cdna2| SGPR | BITS_32 | 92 , "amdgpu_cdna2"); -DEF_REGISTER(s93, Arch_amdgpu_cdna2| SGPR | BITS_32 | 93 , "amdgpu_cdna2"); -DEF_REGISTER(s94, Arch_amdgpu_cdna2| SGPR | BITS_32 | 94 , "amdgpu_cdna2"); -DEF_REGISTER(s95, Arch_amdgpu_cdna2| SGPR | BITS_32 | 95 , "amdgpu_cdna2"); -DEF_REGISTER(s96, Arch_amdgpu_cdna2| SGPR | BITS_32 | 96 , "amdgpu_cdna2"); -DEF_REGISTER(s97, Arch_amdgpu_cdna2| SGPR | BITS_32 | 97 , "amdgpu_cdna2"); -DEF_REGISTER(s98, Arch_amdgpu_cdna2| SGPR | BITS_32 | 98 , "amdgpu_cdna2"); -DEF_REGISTER(s99, Arch_amdgpu_cdna2| SGPR | BITS_32 | 99 , "amdgpu_cdna2"); -DEF_REGISTER(s100, Arch_amdgpu_cdna2| SGPR | BITS_32 | 100 , "amdgpu_cdna2"); -DEF_REGISTER(s101, Arch_amdgpu_cdna2| SGPR | BITS_32 | 101 , "amdgpu_cdna2"); -DEF_REGISTER(v0, Arch_amdgpu_cdna2| VGPR | BITS_32 | 0 , "amdgpu_cdna2"); -DEF_REGISTER(v1, Arch_amdgpu_cdna2| VGPR | BITS_32 | 1 , "amdgpu_cdna2"); -DEF_REGISTER(v2, Arch_amdgpu_cdna2| VGPR | BITS_32 | 2 , "amdgpu_cdna2"); -DEF_REGISTER(v3, Arch_amdgpu_cdna2| VGPR | BITS_32 | 3 , "amdgpu_cdna2"); -DEF_REGISTER(v4, Arch_amdgpu_cdna2| VGPR | BITS_32 | 4 , "amdgpu_cdna2"); -DEF_REGISTER(v5, Arch_amdgpu_cdna2| VGPR | BITS_32 | 5 , "amdgpu_cdna2"); -DEF_REGISTER(v6, Arch_amdgpu_cdna2| VGPR | BITS_32 | 6 , "amdgpu_cdna2"); -DEF_REGISTER(v7, Arch_amdgpu_cdna2| VGPR | BITS_32 | 7 , "amdgpu_cdna2"); -DEF_REGISTER(v8, Arch_amdgpu_cdna2| VGPR | BITS_32 | 8 , "amdgpu_cdna2"); -DEF_REGISTER(v9, Arch_amdgpu_cdna2| VGPR | BITS_32 | 9 , "amdgpu_cdna2"); -DEF_REGISTER(v10, Arch_amdgpu_cdna2| VGPR | BITS_32 | 10 , "amdgpu_cdna2"); -DEF_REGISTER(v11, Arch_amdgpu_cdna2| VGPR | BITS_32 | 11 , "amdgpu_cdna2"); -DEF_REGISTER(v12, Arch_amdgpu_cdna2| VGPR | BITS_32 | 12 , "amdgpu_cdna2"); -DEF_REGISTER(v13, Arch_amdgpu_cdna2| VGPR | BITS_32 | 13 , "amdgpu_cdna2"); -DEF_REGISTER(v14, Arch_amdgpu_cdna2| VGPR | BITS_32 | 14 , "amdgpu_cdna2"); -DEF_REGISTER(v15, Arch_amdgpu_cdna2| VGPR | BITS_32 | 15 , "amdgpu_cdna2"); -DEF_REGISTER(v16, Arch_amdgpu_cdna2| VGPR | BITS_32 | 16 , "amdgpu_cdna2"); -DEF_REGISTER(v17, Arch_amdgpu_cdna2| VGPR | BITS_32 | 17 , "amdgpu_cdna2"); -DEF_REGISTER(v18, Arch_amdgpu_cdna2| VGPR | BITS_32 | 18 , "amdgpu_cdna2"); -DEF_REGISTER(v19, Arch_amdgpu_cdna2| VGPR | BITS_32 | 19 , "amdgpu_cdna2"); -DEF_REGISTER(v20, Arch_amdgpu_cdna2| VGPR | BITS_32 | 20 , "amdgpu_cdna2"); -DEF_REGISTER(v21, Arch_amdgpu_cdna2| VGPR | BITS_32 | 21 , "amdgpu_cdna2"); -DEF_REGISTER(v22, Arch_amdgpu_cdna2| VGPR | BITS_32 | 22 , "amdgpu_cdna2"); -DEF_REGISTER(v23, Arch_amdgpu_cdna2| VGPR | BITS_32 | 23 , "amdgpu_cdna2"); -DEF_REGISTER(v24, Arch_amdgpu_cdna2| VGPR | BITS_32 | 24 , "amdgpu_cdna2"); -DEF_REGISTER(v25, Arch_amdgpu_cdna2| VGPR | BITS_32 | 25 , "amdgpu_cdna2"); -DEF_REGISTER(v26, Arch_amdgpu_cdna2| VGPR | BITS_32 | 26 , "amdgpu_cdna2"); -DEF_REGISTER(v27, Arch_amdgpu_cdna2| VGPR | BITS_32 | 27 , "amdgpu_cdna2"); -DEF_REGISTER(v28, Arch_amdgpu_cdna2| VGPR | BITS_32 | 28 , "amdgpu_cdna2"); -DEF_REGISTER(v29, Arch_amdgpu_cdna2| VGPR | BITS_32 | 29 , "amdgpu_cdna2"); -DEF_REGISTER(v30, Arch_amdgpu_cdna2| VGPR | BITS_32 | 30 , "amdgpu_cdna2"); -DEF_REGISTER(v31, Arch_amdgpu_cdna2| VGPR | BITS_32 | 31 , "amdgpu_cdna2"); -DEF_REGISTER(v32, Arch_amdgpu_cdna2| VGPR | BITS_32 | 32 , "amdgpu_cdna2"); -DEF_REGISTER(v33, Arch_amdgpu_cdna2| VGPR | BITS_32 | 33 , "amdgpu_cdna2"); -DEF_REGISTER(v34, Arch_amdgpu_cdna2| VGPR | BITS_32 | 34 , "amdgpu_cdna2"); -DEF_REGISTER(v35, Arch_amdgpu_cdna2| VGPR | BITS_32 | 35 , "amdgpu_cdna2"); -DEF_REGISTER(v36, Arch_amdgpu_cdna2| VGPR | BITS_32 | 36 , "amdgpu_cdna2"); -DEF_REGISTER(v37, Arch_amdgpu_cdna2| VGPR | BITS_32 | 37 , "amdgpu_cdna2"); -DEF_REGISTER(v38, Arch_amdgpu_cdna2| VGPR | BITS_32 | 38 , "amdgpu_cdna2"); -DEF_REGISTER(v39, Arch_amdgpu_cdna2| VGPR | BITS_32 | 39 , "amdgpu_cdna2"); -DEF_REGISTER(v40, Arch_amdgpu_cdna2| VGPR | BITS_32 | 40 , "amdgpu_cdna2"); -DEF_REGISTER(v41, Arch_amdgpu_cdna2| VGPR | BITS_32 | 41 , "amdgpu_cdna2"); -DEF_REGISTER(v42, Arch_amdgpu_cdna2| VGPR | BITS_32 | 42 , "amdgpu_cdna2"); -DEF_REGISTER(v43, Arch_amdgpu_cdna2| VGPR | BITS_32 | 43 , "amdgpu_cdna2"); -DEF_REGISTER(v44, Arch_amdgpu_cdna2| VGPR | BITS_32 | 44 , "amdgpu_cdna2"); -DEF_REGISTER(v45, Arch_amdgpu_cdna2| VGPR | BITS_32 | 45 , "amdgpu_cdna2"); -DEF_REGISTER(v46, Arch_amdgpu_cdna2| VGPR | BITS_32 | 46 , "amdgpu_cdna2"); -DEF_REGISTER(v47, Arch_amdgpu_cdna2| VGPR | BITS_32 | 47 , "amdgpu_cdna2"); -DEF_REGISTER(v48, Arch_amdgpu_cdna2| VGPR | BITS_32 | 48 , "amdgpu_cdna2"); -DEF_REGISTER(v49, Arch_amdgpu_cdna2| VGPR | BITS_32 | 49 , "amdgpu_cdna2"); -DEF_REGISTER(v50, Arch_amdgpu_cdna2| VGPR | BITS_32 | 50 , "amdgpu_cdna2"); -DEF_REGISTER(v51, Arch_amdgpu_cdna2| VGPR | BITS_32 | 51 , "amdgpu_cdna2"); -DEF_REGISTER(v52, Arch_amdgpu_cdna2| VGPR | BITS_32 | 52 , "amdgpu_cdna2"); -DEF_REGISTER(v53, Arch_amdgpu_cdna2| VGPR | BITS_32 | 53 , "amdgpu_cdna2"); -DEF_REGISTER(v54, Arch_amdgpu_cdna2| VGPR | BITS_32 | 54 , "amdgpu_cdna2"); -DEF_REGISTER(v55, Arch_amdgpu_cdna2| VGPR | BITS_32 | 55 , "amdgpu_cdna2"); -DEF_REGISTER(v56, Arch_amdgpu_cdna2| VGPR | BITS_32 | 56 , "amdgpu_cdna2"); -DEF_REGISTER(v57, Arch_amdgpu_cdna2| VGPR | BITS_32 | 57 , "amdgpu_cdna2"); -DEF_REGISTER(v58, Arch_amdgpu_cdna2| VGPR | BITS_32 | 58 , "amdgpu_cdna2"); -DEF_REGISTER(v59, Arch_amdgpu_cdna2| VGPR | BITS_32 | 59 , "amdgpu_cdna2"); -DEF_REGISTER(v60, Arch_amdgpu_cdna2| VGPR | BITS_32 | 60 , "amdgpu_cdna2"); -DEF_REGISTER(v61, Arch_amdgpu_cdna2| VGPR | BITS_32 | 61 , "amdgpu_cdna2"); -DEF_REGISTER(v62, Arch_amdgpu_cdna2| VGPR | BITS_32 | 62 , "amdgpu_cdna2"); -DEF_REGISTER(v63, Arch_amdgpu_cdna2| VGPR | BITS_32 | 63 , "amdgpu_cdna2"); -DEF_REGISTER(v64, Arch_amdgpu_cdna2| VGPR | BITS_32 | 64 , "amdgpu_cdna2"); -DEF_REGISTER(v65, Arch_amdgpu_cdna2| VGPR | BITS_32 | 65 , "amdgpu_cdna2"); -DEF_REGISTER(v66, Arch_amdgpu_cdna2| VGPR | BITS_32 | 66 , "amdgpu_cdna2"); -DEF_REGISTER(v67, Arch_amdgpu_cdna2| VGPR | BITS_32 | 67 , "amdgpu_cdna2"); -DEF_REGISTER(v68, Arch_amdgpu_cdna2| VGPR | BITS_32 | 68 , "amdgpu_cdna2"); -DEF_REGISTER(v69, Arch_amdgpu_cdna2| VGPR | BITS_32 | 69 , "amdgpu_cdna2"); -DEF_REGISTER(v70, Arch_amdgpu_cdna2| VGPR | BITS_32 | 70 , "amdgpu_cdna2"); -DEF_REGISTER(v71, Arch_amdgpu_cdna2| VGPR | BITS_32 | 71 , "amdgpu_cdna2"); -DEF_REGISTER(v72, Arch_amdgpu_cdna2| VGPR | BITS_32 | 72 , "amdgpu_cdna2"); -DEF_REGISTER(v73, Arch_amdgpu_cdna2| VGPR | BITS_32 | 73 , "amdgpu_cdna2"); -DEF_REGISTER(v74, Arch_amdgpu_cdna2| VGPR | BITS_32 | 74 , "amdgpu_cdna2"); -DEF_REGISTER(v75, Arch_amdgpu_cdna2| VGPR | BITS_32 | 75 , "amdgpu_cdna2"); -DEF_REGISTER(v76, Arch_amdgpu_cdna2| VGPR | BITS_32 | 76 , "amdgpu_cdna2"); -DEF_REGISTER(v77, Arch_amdgpu_cdna2| VGPR | BITS_32 | 77 , "amdgpu_cdna2"); -DEF_REGISTER(v78, Arch_amdgpu_cdna2| VGPR | BITS_32 | 78 , "amdgpu_cdna2"); -DEF_REGISTER(v79, Arch_amdgpu_cdna2| VGPR | BITS_32 | 79 , "amdgpu_cdna2"); -DEF_REGISTER(v80, Arch_amdgpu_cdna2| VGPR | BITS_32 | 80 , "amdgpu_cdna2"); -DEF_REGISTER(v81, Arch_amdgpu_cdna2| VGPR | BITS_32 | 81 , "amdgpu_cdna2"); -DEF_REGISTER(v82, Arch_amdgpu_cdna2| VGPR | BITS_32 | 82 , "amdgpu_cdna2"); -DEF_REGISTER(v83, Arch_amdgpu_cdna2| VGPR | BITS_32 | 83 , "amdgpu_cdna2"); -DEF_REGISTER(v84, Arch_amdgpu_cdna2| VGPR | BITS_32 | 84 , "amdgpu_cdna2"); -DEF_REGISTER(v85, Arch_amdgpu_cdna2| VGPR | BITS_32 | 85 , "amdgpu_cdna2"); -DEF_REGISTER(v86, Arch_amdgpu_cdna2| VGPR | BITS_32 | 86 , "amdgpu_cdna2"); -DEF_REGISTER(v87, Arch_amdgpu_cdna2| VGPR | BITS_32 | 87 , "amdgpu_cdna2"); -DEF_REGISTER(v88, Arch_amdgpu_cdna2| VGPR | BITS_32 | 88 , "amdgpu_cdna2"); -DEF_REGISTER(v89, Arch_amdgpu_cdna2| VGPR | BITS_32 | 89 , "amdgpu_cdna2"); -DEF_REGISTER(v90, Arch_amdgpu_cdna2| VGPR | BITS_32 | 90 , "amdgpu_cdna2"); -DEF_REGISTER(v91, Arch_amdgpu_cdna2| VGPR | BITS_32 | 91 , "amdgpu_cdna2"); -DEF_REGISTER(v92, Arch_amdgpu_cdna2| VGPR | BITS_32 | 92 , "amdgpu_cdna2"); -DEF_REGISTER(v93, Arch_amdgpu_cdna2| VGPR | BITS_32 | 93 , "amdgpu_cdna2"); -DEF_REGISTER(v94, Arch_amdgpu_cdna2| VGPR | BITS_32 | 94 , "amdgpu_cdna2"); -DEF_REGISTER(v95, Arch_amdgpu_cdna2| VGPR | BITS_32 | 95 , "amdgpu_cdna2"); -DEF_REGISTER(v96, Arch_amdgpu_cdna2| VGPR | BITS_32 | 96 , "amdgpu_cdna2"); -DEF_REGISTER(v97, Arch_amdgpu_cdna2| VGPR | BITS_32 | 97 , "amdgpu_cdna2"); -DEF_REGISTER(v98, Arch_amdgpu_cdna2| VGPR | BITS_32 | 98 , "amdgpu_cdna2"); -DEF_REGISTER(v99, Arch_amdgpu_cdna2| VGPR | BITS_32 | 99 , "amdgpu_cdna2"); -DEF_REGISTER(v100, Arch_amdgpu_cdna2| VGPR | BITS_32 | 100 , "amdgpu_cdna2"); -DEF_REGISTER(v101, Arch_amdgpu_cdna2| VGPR | BITS_32 | 101 , "amdgpu_cdna2"); -DEF_REGISTER(v102, Arch_amdgpu_cdna2| VGPR | BITS_32 | 102 , "amdgpu_cdna2"); -DEF_REGISTER(v103, Arch_amdgpu_cdna2| VGPR | BITS_32 | 103 , "amdgpu_cdna2"); -DEF_REGISTER(v104, Arch_amdgpu_cdna2| VGPR | BITS_32 | 104 , "amdgpu_cdna2"); -DEF_REGISTER(v105, Arch_amdgpu_cdna2| VGPR | BITS_32 | 105 , "amdgpu_cdna2"); -DEF_REGISTER(v106, Arch_amdgpu_cdna2| VGPR | BITS_32 | 106 , "amdgpu_cdna2"); -DEF_REGISTER(v107, Arch_amdgpu_cdna2| VGPR | BITS_32 | 107 , "amdgpu_cdna2"); -DEF_REGISTER(v108, Arch_amdgpu_cdna2| VGPR | BITS_32 | 108 , "amdgpu_cdna2"); -DEF_REGISTER(v109, Arch_amdgpu_cdna2| VGPR | BITS_32 | 109 , "amdgpu_cdna2"); -DEF_REGISTER(v110, Arch_amdgpu_cdna2| VGPR | BITS_32 | 110 , "amdgpu_cdna2"); -DEF_REGISTER(v111, Arch_amdgpu_cdna2| VGPR | BITS_32 | 111 , "amdgpu_cdna2"); -DEF_REGISTER(v112, Arch_amdgpu_cdna2| VGPR | BITS_32 | 112 , "amdgpu_cdna2"); -DEF_REGISTER(v113, Arch_amdgpu_cdna2| VGPR | BITS_32 | 113 , "amdgpu_cdna2"); -DEF_REGISTER(v114, Arch_amdgpu_cdna2| VGPR | BITS_32 | 114 , "amdgpu_cdna2"); -DEF_REGISTER(v115, Arch_amdgpu_cdna2| VGPR | BITS_32 | 115 , "amdgpu_cdna2"); -DEF_REGISTER(v116, Arch_amdgpu_cdna2| VGPR | BITS_32 | 116 , "amdgpu_cdna2"); -DEF_REGISTER(v117, Arch_amdgpu_cdna2| VGPR | BITS_32 | 117 , "amdgpu_cdna2"); -DEF_REGISTER(v118, Arch_amdgpu_cdna2| VGPR | BITS_32 | 118 , "amdgpu_cdna2"); -DEF_REGISTER(v119, Arch_amdgpu_cdna2| VGPR | BITS_32 | 119 , "amdgpu_cdna2"); -DEF_REGISTER(v120, Arch_amdgpu_cdna2| VGPR | BITS_32 | 120 , "amdgpu_cdna2"); -DEF_REGISTER(v121, Arch_amdgpu_cdna2| VGPR | BITS_32 | 121 , "amdgpu_cdna2"); -DEF_REGISTER(v122, Arch_amdgpu_cdna2| VGPR | BITS_32 | 122 , "amdgpu_cdna2"); -DEF_REGISTER(v123, Arch_amdgpu_cdna2| VGPR | BITS_32 | 123 , "amdgpu_cdna2"); -DEF_REGISTER(v124, Arch_amdgpu_cdna2| VGPR | BITS_32 | 124 , "amdgpu_cdna2"); -DEF_REGISTER(v125, Arch_amdgpu_cdna2| VGPR | BITS_32 | 125 , "amdgpu_cdna2"); -DEF_REGISTER(v126, Arch_amdgpu_cdna2| VGPR | BITS_32 | 126 , "amdgpu_cdna2"); -DEF_REGISTER(v127, Arch_amdgpu_cdna2| VGPR | BITS_32 | 127 , "amdgpu_cdna2"); -DEF_REGISTER(v128, Arch_amdgpu_cdna2| VGPR | BITS_32 | 128 , "amdgpu_cdna2"); -DEF_REGISTER(v129, Arch_amdgpu_cdna2| VGPR | BITS_32 | 129 , "amdgpu_cdna2"); -DEF_REGISTER(v130, Arch_amdgpu_cdna2| VGPR | BITS_32 | 130 , "amdgpu_cdna2"); -DEF_REGISTER(v131, Arch_amdgpu_cdna2| VGPR | BITS_32 | 131 , "amdgpu_cdna2"); -DEF_REGISTER(v132, Arch_amdgpu_cdna2| VGPR | BITS_32 | 132 , "amdgpu_cdna2"); -DEF_REGISTER(v133, Arch_amdgpu_cdna2| VGPR | BITS_32 | 133 , "amdgpu_cdna2"); -DEF_REGISTER(v134, Arch_amdgpu_cdna2| VGPR | BITS_32 | 134 , "amdgpu_cdna2"); -DEF_REGISTER(v135, Arch_amdgpu_cdna2| VGPR | BITS_32 | 135 , "amdgpu_cdna2"); -DEF_REGISTER(v136, Arch_amdgpu_cdna2| VGPR | BITS_32 | 136 , "amdgpu_cdna2"); -DEF_REGISTER(v137, Arch_amdgpu_cdna2| VGPR | BITS_32 | 137 , "amdgpu_cdna2"); -DEF_REGISTER(v138, Arch_amdgpu_cdna2| VGPR | BITS_32 | 138 , "amdgpu_cdna2"); -DEF_REGISTER(v139, Arch_amdgpu_cdna2| VGPR | BITS_32 | 139 , "amdgpu_cdna2"); -DEF_REGISTER(v140, Arch_amdgpu_cdna2| VGPR | BITS_32 | 140 , "amdgpu_cdna2"); -DEF_REGISTER(v141, Arch_amdgpu_cdna2| VGPR | BITS_32 | 141 , "amdgpu_cdna2"); -DEF_REGISTER(v142, Arch_amdgpu_cdna2| VGPR | BITS_32 | 142 , "amdgpu_cdna2"); -DEF_REGISTER(v143, Arch_amdgpu_cdna2| VGPR | BITS_32 | 143 , "amdgpu_cdna2"); -DEF_REGISTER(v144, Arch_amdgpu_cdna2| VGPR | BITS_32 | 144 , "amdgpu_cdna2"); -DEF_REGISTER(v145, Arch_amdgpu_cdna2| VGPR | BITS_32 | 145 , "amdgpu_cdna2"); -DEF_REGISTER(v146, Arch_amdgpu_cdna2| VGPR | BITS_32 | 146 , "amdgpu_cdna2"); -DEF_REGISTER(v147, Arch_amdgpu_cdna2| VGPR | BITS_32 | 147 , "amdgpu_cdna2"); -DEF_REGISTER(v148, Arch_amdgpu_cdna2| VGPR | BITS_32 | 148 , "amdgpu_cdna2"); -DEF_REGISTER(v149, Arch_amdgpu_cdna2| VGPR | BITS_32 | 149 , "amdgpu_cdna2"); -DEF_REGISTER(v150, Arch_amdgpu_cdna2| VGPR | BITS_32 | 150 , "amdgpu_cdna2"); -DEF_REGISTER(v151, Arch_amdgpu_cdna2| VGPR | BITS_32 | 151 , "amdgpu_cdna2"); -DEF_REGISTER(v152, Arch_amdgpu_cdna2| VGPR | BITS_32 | 152 , "amdgpu_cdna2"); -DEF_REGISTER(v153, Arch_amdgpu_cdna2| VGPR | BITS_32 | 153 , "amdgpu_cdna2"); -DEF_REGISTER(v154, Arch_amdgpu_cdna2| VGPR | BITS_32 | 154 , "amdgpu_cdna2"); -DEF_REGISTER(v155, Arch_amdgpu_cdna2| VGPR | BITS_32 | 155 , "amdgpu_cdna2"); -DEF_REGISTER(v156, Arch_amdgpu_cdna2| VGPR | BITS_32 | 156 , "amdgpu_cdna2"); -DEF_REGISTER(v157, Arch_amdgpu_cdna2| VGPR | BITS_32 | 157 , "amdgpu_cdna2"); -DEF_REGISTER(v158, Arch_amdgpu_cdna2| VGPR | BITS_32 | 158 , "amdgpu_cdna2"); -DEF_REGISTER(v159, Arch_amdgpu_cdna2| VGPR | BITS_32 | 159 , "amdgpu_cdna2"); -DEF_REGISTER(v160, Arch_amdgpu_cdna2| VGPR | BITS_32 | 160 , "amdgpu_cdna2"); -DEF_REGISTER(v161, Arch_amdgpu_cdna2| VGPR | BITS_32 | 161 , "amdgpu_cdna2"); -DEF_REGISTER(v162, Arch_amdgpu_cdna2| VGPR | BITS_32 | 162 , "amdgpu_cdna2"); -DEF_REGISTER(v163, Arch_amdgpu_cdna2| VGPR | BITS_32 | 163 , "amdgpu_cdna2"); -DEF_REGISTER(v164, Arch_amdgpu_cdna2| VGPR | BITS_32 | 164 , "amdgpu_cdna2"); -DEF_REGISTER(v165, Arch_amdgpu_cdna2| VGPR | BITS_32 | 165 , "amdgpu_cdna2"); -DEF_REGISTER(v166, Arch_amdgpu_cdna2| VGPR | BITS_32 | 166 , "amdgpu_cdna2"); -DEF_REGISTER(v167, Arch_amdgpu_cdna2| VGPR | BITS_32 | 167 , "amdgpu_cdna2"); -DEF_REGISTER(v168, Arch_amdgpu_cdna2| VGPR | BITS_32 | 168 , "amdgpu_cdna2"); -DEF_REGISTER(v169, Arch_amdgpu_cdna2| VGPR | BITS_32 | 169 , "amdgpu_cdna2"); -DEF_REGISTER(v170, Arch_amdgpu_cdna2| VGPR | BITS_32 | 170 , "amdgpu_cdna2"); -DEF_REGISTER(v171, Arch_amdgpu_cdna2| VGPR | BITS_32 | 171 , "amdgpu_cdna2"); -DEF_REGISTER(v172, Arch_amdgpu_cdna2| VGPR | BITS_32 | 172 , "amdgpu_cdna2"); -DEF_REGISTER(v173, Arch_amdgpu_cdna2| VGPR | BITS_32 | 173 , "amdgpu_cdna2"); -DEF_REGISTER(v174, Arch_amdgpu_cdna2| VGPR | BITS_32 | 174 , "amdgpu_cdna2"); -DEF_REGISTER(v175, Arch_amdgpu_cdna2| VGPR | BITS_32 | 175 , "amdgpu_cdna2"); -DEF_REGISTER(v176, Arch_amdgpu_cdna2| VGPR | BITS_32 | 176 , "amdgpu_cdna2"); -DEF_REGISTER(v177, Arch_amdgpu_cdna2| VGPR | BITS_32 | 177 , "amdgpu_cdna2"); -DEF_REGISTER(v178, Arch_amdgpu_cdna2| VGPR | BITS_32 | 178 , "amdgpu_cdna2"); -DEF_REGISTER(v179, Arch_amdgpu_cdna2| VGPR | BITS_32 | 179 , "amdgpu_cdna2"); -DEF_REGISTER(v180, Arch_amdgpu_cdna2| VGPR | BITS_32 | 180 , "amdgpu_cdna2"); -DEF_REGISTER(v181, Arch_amdgpu_cdna2| VGPR | BITS_32 | 181 , "amdgpu_cdna2"); -DEF_REGISTER(v182, Arch_amdgpu_cdna2| VGPR | BITS_32 | 182 , "amdgpu_cdna2"); -DEF_REGISTER(v183, Arch_amdgpu_cdna2| VGPR | BITS_32 | 183 , "amdgpu_cdna2"); -DEF_REGISTER(v184, Arch_amdgpu_cdna2| VGPR | BITS_32 | 184 , "amdgpu_cdna2"); -DEF_REGISTER(v185, Arch_amdgpu_cdna2| VGPR | BITS_32 | 185 , "amdgpu_cdna2"); -DEF_REGISTER(v186, Arch_amdgpu_cdna2| VGPR | BITS_32 | 186 , "amdgpu_cdna2"); -DEF_REGISTER(v187, Arch_amdgpu_cdna2| VGPR | BITS_32 | 187 , "amdgpu_cdna2"); -DEF_REGISTER(v188, Arch_amdgpu_cdna2| VGPR | BITS_32 | 188 , "amdgpu_cdna2"); -DEF_REGISTER(v189, Arch_amdgpu_cdna2| VGPR | BITS_32 | 189 , "amdgpu_cdna2"); -DEF_REGISTER(v190, Arch_amdgpu_cdna2| VGPR | BITS_32 | 190 , "amdgpu_cdna2"); -DEF_REGISTER(v191, Arch_amdgpu_cdna2| VGPR | BITS_32 | 191 , "amdgpu_cdna2"); -DEF_REGISTER(v192, Arch_amdgpu_cdna2| VGPR | BITS_32 | 192 , "amdgpu_cdna2"); -DEF_REGISTER(v193, Arch_amdgpu_cdna2| VGPR | BITS_32 | 193 , "amdgpu_cdna2"); -DEF_REGISTER(v194, Arch_amdgpu_cdna2| VGPR | BITS_32 | 194 , "amdgpu_cdna2"); -DEF_REGISTER(v195, Arch_amdgpu_cdna2| VGPR | BITS_32 | 195 , "amdgpu_cdna2"); -DEF_REGISTER(v196, Arch_amdgpu_cdna2| VGPR | BITS_32 | 196 , "amdgpu_cdna2"); -DEF_REGISTER(v197, Arch_amdgpu_cdna2| VGPR | BITS_32 | 197 , "amdgpu_cdna2"); -DEF_REGISTER(v198, Arch_amdgpu_cdna2| VGPR | BITS_32 | 198 , "amdgpu_cdna2"); -DEF_REGISTER(v199, Arch_amdgpu_cdna2| VGPR | BITS_32 | 199 , "amdgpu_cdna2"); -DEF_REGISTER(v200, Arch_amdgpu_cdna2| VGPR | BITS_32 | 200 , "amdgpu_cdna2"); -DEF_REGISTER(v201, Arch_amdgpu_cdna2| VGPR | BITS_32 | 201 , "amdgpu_cdna2"); -DEF_REGISTER(v202, Arch_amdgpu_cdna2| VGPR | BITS_32 | 202 , "amdgpu_cdna2"); -DEF_REGISTER(v203, Arch_amdgpu_cdna2| VGPR | BITS_32 | 203 , "amdgpu_cdna2"); -DEF_REGISTER(v204, Arch_amdgpu_cdna2| VGPR | BITS_32 | 204 , "amdgpu_cdna2"); -DEF_REGISTER(v205, Arch_amdgpu_cdna2| VGPR | BITS_32 | 205 , "amdgpu_cdna2"); -DEF_REGISTER(v206, Arch_amdgpu_cdna2| VGPR | BITS_32 | 206 , "amdgpu_cdna2"); -DEF_REGISTER(v207, Arch_amdgpu_cdna2| VGPR | BITS_32 | 207 , "amdgpu_cdna2"); -DEF_REGISTER(v208, Arch_amdgpu_cdna2| VGPR | BITS_32 | 208 , "amdgpu_cdna2"); -DEF_REGISTER(v209, Arch_amdgpu_cdna2| VGPR | BITS_32 | 209 , "amdgpu_cdna2"); -DEF_REGISTER(v210, Arch_amdgpu_cdna2| VGPR | BITS_32 | 210 , "amdgpu_cdna2"); -DEF_REGISTER(v211, Arch_amdgpu_cdna2| VGPR | BITS_32 | 211 , "amdgpu_cdna2"); -DEF_REGISTER(v212, Arch_amdgpu_cdna2| VGPR | BITS_32 | 212 , "amdgpu_cdna2"); -DEF_REGISTER(v213, Arch_amdgpu_cdna2| VGPR | BITS_32 | 213 , "amdgpu_cdna2"); -DEF_REGISTER(v214, Arch_amdgpu_cdna2| VGPR | BITS_32 | 214 , "amdgpu_cdna2"); -DEF_REGISTER(v215, Arch_amdgpu_cdna2| VGPR | BITS_32 | 215 , "amdgpu_cdna2"); -DEF_REGISTER(v216, Arch_amdgpu_cdna2| VGPR | BITS_32 | 216 , "amdgpu_cdna2"); -DEF_REGISTER(v217, Arch_amdgpu_cdna2| VGPR | BITS_32 | 217 , "amdgpu_cdna2"); -DEF_REGISTER(v218, Arch_amdgpu_cdna2| VGPR | BITS_32 | 218 , "amdgpu_cdna2"); -DEF_REGISTER(v219, Arch_amdgpu_cdna2| VGPR | BITS_32 | 219 , "amdgpu_cdna2"); -DEF_REGISTER(v220, Arch_amdgpu_cdna2| VGPR | BITS_32 | 220 , "amdgpu_cdna2"); -DEF_REGISTER(v221, Arch_amdgpu_cdna2| VGPR | BITS_32 | 221 , "amdgpu_cdna2"); -DEF_REGISTER(v222, Arch_amdgpu_cdna2| VGPR | BITS_32 | 222 , "amdgpu_cdna2"); -DEF_REGISTER(v223, Arch_amdgpu_cdna2| VGPR | BITS_32 | 223 , "amdgpu_cdna2"); -DEF_REGISTER(v224, Arch_amdgpu_cdna2| VGPR | BITS_32 | 224 , "amdgpu_cdna2"); -DEF_REGISTER(v225, Arch_amdgpu_cdna2| VGPR | BITS_32 | 225 , "amdgpu_cdna2"); -DEF_REGISTER(v226, Arch_amdgpu_cdna2| VGPR | BITS_32 | 226 , "amdgpu_cdna2"); -DEF_REGISTER(v227, Arch_amdgpu_cdna2| VGPR | BITS_32 | 227 , "amdgpu_cdna2"); -DEF_REGISTER(v228, Arch_amdgpu_cdna2| VGPR | BITS_32 | 228 , "amdgpu_cdna2"); -DEF_REGISTER(v229, Arch_amdgpu_cdna2| VGPR | BITS_32 | 229 , "amdgpu_cdna2"); -DEF_REGISTER(v230, Arch_amdgpu_cdna2| VGPR | BITS_32 | 230 , "amdgpu_cdna2"); -DEF_REGISTER(v231, Arch_amdgpu_cdna2| VGPR | BITS_32 | 231 , "amdgpu_cdna2"); -DEF_REGISTER(v232, Arch_amdgpu_cdna2| VGPR | BITS_32 | 232 , "amdgpu_cdna2"); -DEF_REGISTER(v233, Arch_amdgpu_cdna2| VGPR | BITS_32 | 233 , "amdgpu_cdna2"); -DEF_REGISTER(v234, Arch_amdgpu_cdna2| VGPR | BITS_32 | 234 , "amdgpu_cdna2"); -DEF_REGISTER(v235, Arch_amdgpu_cdna2| VGPR | BITS_32 | 235 , "amdgpu_cdna2"); -DEF_REGISTER(v236, Arch_amdgpu_cdna2| VGPR | BITS_32 | 236 , "amdgpu_cdna2"); -DEF_REGISTER(v237, Arch_amdgpu_cdna2| VGPR | BITS_32 | 237 , "amdgpu_cdna2"); -DEF_REGISTER(v238, Arch_amdgpu_cdna2| VGPR | BITS_32 | 238 , "amdgpu_cdna2"); -DEF_REGISTER(v239, Arch_amdgpu_cdna2| VGPR | BITS_32 | 239 , "amdgpu_cdna2"); -DEF_REGISTER(v240, Arch_amdgpu_cdna2| VGPR | BITS_32 | 240 , "amdgpu_cdna2"); -DEF_REGISTER(v241, Arch_amdgpu_cdna2| VGPR | BITS_32 | 241 , "amdgpu_cdna2"); -DEF_REGISTER(v242, Arch_amdgpu_cdna2| VGPR | BITS_32 | 242 , "amdgpu_cdna2"); -DEF_REGISTER(v243, Arch_amdgpu_cdna2| VGPR | BITS_32 | 243 , "amdgpu_cdna2"); -DEF_REGISTER(v244, Arch_amdgpu_cdna2| VGPR | BITS_32 | 244 , "amdgpu_cdna2"); -DEF_REGISTER(v245, Arch_amdgpu_cdna2| VGPR | BITS_32 | 245 , "amdgpu_cdna2"); -DEF_REGISTER(v246, Arch_amdgpu_cdna2| VGPR | BITS_32 | 246 , "amdgpu_cdna2"); -DEF_REGISTER(v247, Arch_amdgpu_cdna2| VGPR | BITS_32 | 247 , "amdgpu_cdna2"); -DEF_REGISTER(v248, Arch_amdgpu_cdna2| VGPR | BITS_32 | 248 , "amdgpu_cdna2"); -DEF_REGISTER(v249, Arch_amdgpu_cdna2| VGPR | BITS_32 | 249 , "amdgpu_cdna2"); -DEF_REGISTER(v250, Arch_amdgpu_cdna2| VGPR | BITS_32 | 250 , "amdgpu_cdna2"); -DEF_REGISTER(v251, Arch_amdgpu_cdna2| VGPR | BITS_32 | 251 , "amdgpu_cdna2"); -DEF_REGISTER(v252, Arch_amdgpu_cdna2| VGPR | BITS_32 | 252 , "amdgpu_cdna2"); -DEF_REGISTER(v253, Arch_amdgpu_cdna2| VGPR | BITS_32 | 253 , "amdgpu_cdna2"); -DEF_REGISTER(v254, Arch_amdgpu_cdna2| VGPR | BITS_32 | 254 , "amdgpu_cdna2"); -DEF_REGISTER(v255, Arch_amdgpu_cdna2| VGPR | BITS_32 | 255 , "amdgpu_cdna2"); -DEF_REGISTER(acc0, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 0 , "amdgpu_cdna2"); -DEF_REGISTER(acc1, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 1 , "amdgpu_cdna2"); -DEF_REGISTER(acc2, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 2 , "amdgpu_cdna2"); -DEF_REGISTER(acc3, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 3 , "amdgpu_cdna2"); -DEF_REGISTER(acc4, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 4 , "amdgpu_cdna2"); -DEF_REGISTER(acc5, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 5 , "amdgpu_cdna2"); -DEF_REGISTER(acc6, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 6 , "amdgpu_cdna2"); -DEF_REGISTER(acc7, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 7 , "amdgpu_cdna2"); -DEF_REGISTER(acc8, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 8 , "amdgpu_cdna2"); -DEF_REGISTER(acc9, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 9 , "amdgpu_cdna2"); -DEF_REGISTER(acc10, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 10 , "amdgpu_cdna2"); -DEF_REGISTER(acc11, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 11 , "amdgpu_cdna2"); -DEF_REGISTER(acc12, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 12 , "amdgpu_cdna2"); -DEF_REGISTER(acc13, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 13 , "amdgpu_cdna2"); -DEF_REGISTER(acc14, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 14 , "amdgpu_cdna2"); -DEF_REGISTER(acc15, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 15 , "amdgpu_cdna2"); -DEF_REGISTER(acc16, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 16 , "amdgpu_cdna2"); -DEF_REGISTER(acc17, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 17 , "amdgpu_cdna2"); -DEF_REGISTER(acc18, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 18 , "amdgpu_cdna2"); -DEF_REGISTER(acc19, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 19 , "amdgpu_cdna2"); -DEF_REGISTER(acc20, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 20 , "amdgpu_cdna2"); -DEF_REGISTER(acc21, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 21 , "amdgpu_cdna2"); -DEF_REGISTER(acc22, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 22 , "amdgpu_cdna2"); -DEF_REGISTER(acc23, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 23 , "amdgpu_cdna2"); -DEF_REGISTER(acc24, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 24 , "amdgpu_cdna2"); -DEF_REGISTER(acc25, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 25 , "amdgpu_cdna2"); -DEF_REGISTER(acc26, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 26 , "amdgpu_cdna2"); -DEF_REGISTER(acc27, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 27 , "amdgpu_cdna2"); -DEF_REGISTER(acc28, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 28 , "amdgpu_cdna2"); -DEF_REGISTER(acc29, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 29 , "amdgpu_cdna2"); -DEF_REGISTER(acc30, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 30 , "amdgpu_cdna2"); -DEF_REGISTER(acc31, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 31 , "amdgpu_cdna2"); -DEF_REGISTER(acc32, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 32 , "amdgpu_cdna2"); -DEF_REGISTER(acc33, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 33 , "amdgpu_cdna2"); -DEF_REGISTER(acc34, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 34 , "amdgpu_cdna2"); -DEF_REGISTER(acc35, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 35 , "amdgpu_cdna2"); -DEF_REGISTER(acc36, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 36 , "amdgpu_cdna2"); -DEF_REGISTER(acc37, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 37 , "amdgpu_cdna2"); -DEF_REGISTER(acc38, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 38 , "amdgpu_cdna2"); -DEF_REGISTER(acc39, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 39 , "amdgpu_cdna2"); -DEF_REGISTER(acc40, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 40 , "amdgpu_cdna2"); -DEF_REGISTER(acc41, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 41 , "amdgpu_cdna2"); -DEF_REGISTER(acc42, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 42 , "amdgpu_cdna2"); -DEF_REGISTER(acc43, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 43 , "amdgpu_cdna2"); -DEF_REGISTER(acc44, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 44 , "amdgpu_cdna2"); -DEF_REGISTER(acc45, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 45 , "amdgpu_cdna2"); -DEF_REGISTER(acc46, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 46 , "amdgpu_cdna2"); -DEF_REGISTER(acc47, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 47 , "amdgpu_cdna2"); -DEF_REGISTER(acc48, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 48 , "amdgpu_cdna2"); -DEF_REGISTER(acc49, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 49 , "amdgpu_cdna2"); -DEF_REGISTER(acc50, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 50 , "amdgpu_cdna2"); -DEF_REGISTER(acc51, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 51 , "amdgpu_cdna2"); -DEF_REGISTER(acc52, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 52 , "amdgpu_cdna2"); -DEF_REGISTER(acc53, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 53 , "amdgpu_cdna2"); -DEF_REGISTER(acc54, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 54 , "amdgpu_cdna2"); -DEF_REGISTER(acc55, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 55 , "amdgpu_cdna2"); -DEF_REGISTER(acc56, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 56 , "amdgpu_cdna2"); -DEF_REGISTER(acc57, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 57 , "amdgpu_cdna2"); -DEF_REGISTER(acc58, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 58 , "amdgpu_cdna2"); -DEF_REGISTER(acc59, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 59 , "amdgpu_cdna2"); -DEF_REGISTER(acc60, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 60 , "amdgpu_cdna2"); -DEF_REGISTER(acc61, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 61 , "amdgpu_cdna2"); -DEF_REGISTER(acc62, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 62 , "amdgpu_cdna2"); -DEF_REGISTER(acc63, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 63 , "amdgpu_cdna2"); -DEF_REGISTER(acc64, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 64 , "amdgpu_cdna2"); -DEF_REGISTER(acc65, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 65 , "amdgpu_cdna2"); -DEF_REGISTER(acc66, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 66 , "amdgpu_cdna2"); -DEF_REGISTER(acc67, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 67 , "amdgpu_cdna2"); -DEF_REGISTER(acc68, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 68 , "amdgpu_cdna2"); -DEF_REGISTER(acc69, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 69 , "amdgpu_cdna2"); -DEF_REGISTER(acc70, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 70 , "amdgpu_cdna2"); -DEF_REGISTER(acc71, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 71 , "amdgpu_cdna2"); -DEF_REGISTER(acc72, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 72 , "amdgpu_cdna2"); -DEF_REGISTER(acc73, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 73 , "amdgpu_cdna2"); -DEF_REGISTER(acc74, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 74 , "amdgpu_cdna2"); -DEF_REGISTER(acc75, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 75 , "amdgpu_cdna2"); -DEF_REGISTER(acc76, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 76 , "amdgpu_cdna2"); -DEF_REGISTER(acc77, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 77 , "amdgpu_cdna2"); -DEF_REGISTER(acc78, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 78 , "amdgpu_cdna2"); -DEF_REGISTER(acc79, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 79 , "amdgpu_cdna2"); -DEF_REGISTER(acc80, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 80 , "amdgpu_cdna2"); -DEF_REGISTER(acc81, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 81 , "amdgpu_cdna2"); -DEF_REGISTER(acc82, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 82 , "amdgpu_cdna2"); -DEF_REGISTER(acc83, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 83 , "amdgpu_cdna2"); -DEF_REGISTER(acc84, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 84 , "amdgpu_cdna2"); -DEF_REGISTER(acc85, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 85 , "amdgpu_cdna2"); -DEF_REGISTER(acc86, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 86 , "amdgpu_cdna2"); -DEF_REGISTER(acc87, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 87 , "amdgpu_cdna2"); -DEF_REGISTER(acc88, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 88 , "amdgpu_cdna2"); -DEF_REGISTER(acc89, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 89 , "amdgpu_cdna2"); -DEF_REGISTER(acc90, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 90 , "amdgpu_cdna2"); -DEF_REGISTER(acc91, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 91 , "amdgpu_cdna2"); -DEF_REGISTER(acc92, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 92 , "amdgpu_cdna2"); -DEF_REGISTER(acc93, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 93 , "amdgpu_cdna2"); -DEF_REGISTER(acc94, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 94 , "amdgpu_cdna2"); -DEF_REGISTER(acc95, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 95 , "amdgpu_cdna2"); -DEF_REGISTER(acc96, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 96 , "amdgpu_cdna2"); -DEF_REGISTER(acc97, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 97 , "amdgpu_cdna2"); -DEF_REGISTER(acc98, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 98 , "amdgpu_cdna2"); -DEF_REGISTER(acc99, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 99 , "amdgpu_cdna2"); -DEF_REGISTER(acc100, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 100 , "amdgpu_cdna2"); -DEF_REGISTER(acc101, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 101 , "amdgpu_cdna2"); -DEF_REGISTER(acc102, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 102 , "amdgpu_cdna2"); -DEF_REGISTER(acc103, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 103 , "amdgpu_cdna2"); -DEF_REGISTER(acc104, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 104 , "amdgpu_cdna2"); -DEF_REGISTER(acc105, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 105 , "amdgpu_cdna2"); -DEF_REGISTER(acc106, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 106 , "amdgpu_cdna2"); -DEF_REGISTER(acc107, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 107 , "amdgpu_cdna2"); -DEF_REGISTER(acc108, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 108 , "amdgpu_cdna2"); -DEF_REGISTER(acc109, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 109 , "amdgpu_cdna2"); -DEF_REGISTER(acc110, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 110 , "amdgpu_cdna2"); -DEF_REGISTER(acc111, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 111 , "amdgpu_cdna2"); -DEF_REGISTER(acc112, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 112 , "amdgpu_cdna2"); -DEF_REGISTER(acc113, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 113 , "amdgpu_cdna2"); -DEF_REGISTER(acc114, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 114 , "amdgpu_cdna2"); -DEF_REGISTER(acc115, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 115 , "amdgpu_cdna2"); -DEF_REGISTER(acc116, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 116 , "amdgpu_cdna2"); -DEF_REGISTER(acc117, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 117 , "amdgpu_cdna2"); -DEF_REGISTER(acc118, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 118 , "amdgpu_cdna2"); -DEF_REGISTER(acc119, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 119 , "amdgpu_cdna2"); -DEF_REGISTER(acc120, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 120 , "amdgpu_cdna2"); -DEF_REGISTER(acc121, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 121 , "amdgpu_cdna2"); -DEF_REGISTER(acc122, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 122 , "amdgpu_cdna2"); -DEF_REGISTER(acc123, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 123 , "amdgpu_cdna2"); -DEF_REGISTER(acc124, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 124 , "amdgpu_cdna2"); -DEF_REGISTER(acc125, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 125 , "amdgpu_cdna2"); -DEF_REGISTER(acc126, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 126 , "amdgpu_cdna2"); -DEF_REGISTER(acc127, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 127 , "amdgpu_cdna2"); -DEF_REGISTER(acc128, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 128 , "amdgpu_cdna2"); -DEF_REGISTER(acc129, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 129 , "amdgpu_cdna2"); -DEF_REGISTER(acc130, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 130 , "amdgpu_cdna2"); -DEF_REGISTER(acc131, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 131 , "amdgpu_cdna2"); -DEF_REGISTER(acc132, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 132 , "amdgpu_cdna2"); -DEF_REGISTER(acc133, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 133 , "amdgpu_cdna2"); -DEF_REGISTER(acc134, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 134 , "amdgpu_cdna2"); -DEF_REGISTER(acc135, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 135 , "amdgpu_cdna2"); -DEF_REGISTER(acc136, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 136 , "amdgpu_cdna2"); -DEF_REGISTER(acc137, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 137 , "amdgpu_cdna2"); -DEF_REGISTER(acc138, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 138 , "amdgpu_cdna2"); -DEF_REGISTER(acc139, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 139 , "amdgpu_cdna2"); -DEF_REGISTER(acc140, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 140 , "amdgpu_cdna2"); -DEF_REGISTER(acc141, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 141 , "amdgpu_cdna2"); -DEF_REGISTER(acc142, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 142 , "amdgpu_cdna2"); -DEF_REGISTER(acc143, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 143 , "amdgpu_cdna2"); -DEF_REGISTER(acc144, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 144 , "amdgpu_cdna2"); -DEF_REGISTER(acc145, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 145 , "amdgpu_cdna2"); -DEF_REGISTER(acc146, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 146 , "amdgpu_cdna2"); -DEF_REGISTER(acc147, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 147 , "amdgpu_cdna2"); -DEF_REGISTER(acc148, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 148 , "amdgpu_cdna2"); -DEF_REGISTER(acc149, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 149 , "amdgpu_cdna2"); -DEF_REGISTER(acc150, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 150 , "amdgpu_cdna2"); -DEF_REGISTER(acc151, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 151 , "amdgpu_cdna2"); -DEF_REGISTER(acc152, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 152 , "amdgpu_cdna2"); -DEF_REGISTER(acc153, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 153 , "amdgpu_cdna2"); -DEF_REGISTER(acc154, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 154 , "amdgpu_cdna2"); -DEF_REGISTER(acc155, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 155 , "amdgpu_cdna2"); -DEF_REGISTER(acc156, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 156 , "amdgpu_cdna2"); -DEF_REGISTER(acc157, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 157 , "amdgpu_cdna2"); -DEF_REGISTER(acc158, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 158 , "amdgpu_cdna2"); -DEF_REGISTER(acc159, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 159 , "amdgpu_cdna2"); -DEF_REGISTER(acc160, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 160 , "amdgpu_cdna2"); -DEF_REGISTER(acc161, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 161 , "amdgpu_cdna2"); -DEF_REGISTER(acc162, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 162 , "amdgpu_cdna2"); -DEF_REGISTER(acc163, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 163 , "amdgpu_cdna2"); -DEF_REGISTER(acc164, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 164 , "amdgpu_cdna2"); -DEF_REGISTER(acc165, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 165 , "amdgpu_cdna2"); -DEF_REGISTER(acc166, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 166 , "amdgpu_cdna2"); -DEF_REGISTER(acc167, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 167 , "amdgpu_cdna2"); -DEF_REGISTER(acc168, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 168 , "amdgpu_cdna2"); -DEF_REGISTER(acc169, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 169 , "amdgpu_cdna2"); -DEF_REGISTER(acc170, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 170 , "amdgpu_cdna2"); -DEF_REGISTER(acc171, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 171 , "amdgpu_cdna2"); -DEF_REGISTER(acc172, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 172 , "amdgpu_cdna2"); -DEF_REGISTER(acc173, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 173 , "amdgpu_cdna2"); -DEF_REGISTER(acc174, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 174 , "amdgpu_cdna2"); -DEF_REGISTER(acc175, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 175 , "amdgpu_cdna2"); -DEF_REGISTER(acc176, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 176 , "amdgpu_cdna2"); -DEF_REGISTER(acc177, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 177 , "amdgpu_cdna2"); -DEF_REGISTER(acc178, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 178 , "amdgpu_cdna2"); -DEF_REGISTER(acc179, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 179 , "amdgpu_cdna2"); -DEF_REGISTER(acc180, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 180 , "amdgpu_cdna2"); -DEF_REGISTER(acc181, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 181 , "amdgpu_cdna2"); -DEF_REGISTER(acc182, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 182 , "amdgpu_cdna2"); -DEF_REGISTER(acc183, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 183 , "amdgpu_cdna2"); -DEF_REGISTER(acc184, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 184 , "amdgpu_cdna2"); -DEF_REGISTER(acc185, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 185 , "amdgpu_cdna2"); -DEF_REGISTER(acc186, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 186 , "amdgpu_cdna2"); -DEF_REGISTER(acc187, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 187 , "amdgpu_cdna2"); -DEF_REGISTER(acc188, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 188 , "amdgpu_cdna2"); -DEF_REGISTER(acc189, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 189 , "amdgpu_cdna2"); -DEF_REGISTER(acc190, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 190 , "amdgpu_cdna2"); -DEF_REGISTER(acc191, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 191 , "amdgpu_cdna2"); -DEF_REGISTER(acc192, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 192 , "amdgpu_cdna2"); -DEF_REGISTER(acc193, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 193 , "amdgpu_cdna2"); -DEF_REGISTER(acc194, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 194 , "amdgpu_cdna2"); -DEF_REGISTER(acc195, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 195 , "amdgpu_cdna2"); -DEF_REGISTER(acc196, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 196 , "amdgpu_cdna2"); -DEF_REGISTER(acc197, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 197 , "amdgpu_cdna2"); -DEF_REGISTER(acc198, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 198 , "amdgpu_cdna2"); -DEF_REGISTER(acc199, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 199 , "amdgpu_cdna2"); -DEF_REGISTER(acc200, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 200 , "amdgpu_cdna2"); -DEF_REGISTER(acc201, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 201 , "amdgpu_cdna2"); -DEF_REGISTER(acc202, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 202 , "amdgpu_cdna2"); -DEF_REGISTER(acc203, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 203 , "amdgpu_cdna2"); -DEF_REGISTER(acc204, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 204 , "amdgpu_cdna2"); -DEF_REGISTER(acc205, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 205 , "amdgpu_cdna2"); -DEF_REGISTER(acc206, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 206 , "amdgpu_cdna2"); -DEF_REGISTER(acc207, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 207 , "amdgpu_cdna2"); -DEF_REGISTER(acc208, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 208 , "amdgpu_cdna2"); -DEF_REGISTER(acc209, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 209 , "amdgpu_cdna2"); -DEF_REGISTER(acc210, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 210 , "amdgpu_cdna2"); -DEF_REGISTER(acc211, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 211 , "amdgpu_cdna2"); -DEF_REGISTER(acc212, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 212 , "amdgpu_cdna2"); -DEF_REGISTER(acc213, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 213 , "amdgpu_cdna2"); -DEF_REGISTER(acc214, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 214 , "amdgpu_cdna2"); -DEF_REGISTER(acc215, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 215 , "amdgpu_cdna2"); -DEF_REGISTER(acc216, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 216 , "amdgpu_cdna2"); -DEF_REGISTER(acc217, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 217 , "amdgpu_cdna2"); -DEF_REGISTER(acc218, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 218 , "amdgpu_cdna2"); -DEF_REGISTER(acc219, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 219 , "amdgpu_cdna2"); -DEF_REGISTER(acc220, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 220 , "amdgpu_cdna2"); -DEF_REGISTER(acc221, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 221 , "amdgpu_cdna2"); -DEF_REGISTER(acc222, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 222 , "amdgpu_cdna2"); -DEF_REGISTER(acc223, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 223 , "amdgpu_cdna2"); -DEF_REGISTER(acc224, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 224 , "amdgpu_cdna2"); -DEF_REGISTER(acc225, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 225 , "amdgpu_cdna2"); -DEF_REGISTER(acc226, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 226 , "amdgpu_cdna2"); -DEF_REGISTER(acc227, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 227 , "amdgpu_cdna2"); -DEF_REGISTER(acc228, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 228 , "amdgpu_cdna2"); -DEF_REGISTER(acc229, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 229 , "amdgpu_cdna2"); -DEF_REGISTER(acc230, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 230 , "amdgpu_cdna2"); -DEF_REGISTER(acc231, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 231 , "amdgpu_cdna2"); -DEF_REGISTER(acc232, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 232 , "amdgpu_cdna2"); -DEF_REGISTER(acc233, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 233 , "amdgpu_cdna2"); -DEF_REGISTER(acc234, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 234 , "amdgpu_cdna2"); -DEF_REGISTER(acc235, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 235 , "amdgpu_cdna2"); -DEF_REGISTER(acc236, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 236 , "amdgpu_cdna2"); -DEF_REGISTER(acc237, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 237 , "amdgpu_cdna2"); -DEF_REGISTER(acc238, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 238 , "amdgpu_cdna2"); -DEF_REGISTER(acc239, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 239 , "amdgpu_cdna2"); -DEF_REGISTER(acc240, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 240 , "amdgpu_cdna2"); -DEF_REGISTER(acc241, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 241 , "amdgpu_cdna2"); -DEF_REGISTER(acc242, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 242 , "amdgpu_cdna2"); -DEF_REGISTER(acc243, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 243 , "amdgpu_cdna2"); -DEF_REGISTER(acc244, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 244 , "amdgpu_cdna2"); -DEF_REGISTER(acc245, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 245 , "amdgpu_cdna2"); -DEF_REGISTER(acc246, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 246 , "amdgpu_cdna2"); -DEF_REGISTER(acc247, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 247 , "amdgpu_cdna2"); -DEF_REGISTER(acc248, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 248 , "amdgpu_cdna2"); -DEF_REGISTER(acc249, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 249 , "amdgpu_cdna2"); -DEF_REGISTER(acc250, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 250 , "amdgpu_cdna2"); -DEF_REGISTER(acc251, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 251 , "amdgpu_cdna2"); -DEF_REGISTER(acc252, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 252 , "amdgpu_cdna2"); -DEF_REGISTER(acc253, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 253 , "amdgpu_cdna2"); -DEF_REGISTER(acc254, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 254 , "amdgpu_cdna2"); -DEF_REGISTER(acc255, Arch_amdgpu_cdna2| ACC_VGPR | BITS_32 | 255 , "amdgpu_cdna2"); -#endif From 2e08788d6215cf361eb2b9e7d332eb31a29c57d1 Mon Sep 17 00:00:00 2001 From: bbiiggppiigg Date: Thu, 3 Mar 2022 23:14:50 +0000 Subject: [PATCH 081/505] Fix potential buffer overrun in AMDGPU decoders (#1208) * add assert to check for potential buffer overun * add assert to check for potential buffer overrun in vega --- .../AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C | 110 ++- .../AMDGPU/vega/amdgpu_vega_decoder_impl.C | 921 +++++++++--------- 2 files changed, 563 insertions(+), 468 deletions(-) diff --git a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C index 66947766d8..645f938477 100644 --- a/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C +++ b/instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C @@ -1628,6 +1628,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SOP1(){ layout.OP = longfield<8,15>(insn_long); layout.SDST = longfield<16,22>(insn_long); layout.SSRC0 = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SOP1Operands(); @@ -1640,6 +1641,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPC(){ layout.OP = longfield<16,22>(insn_long); layout.SSRC0 = longfield<0,7>(insn_long); layout.SSRC1 = longfield<8,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SOPCOperands(); @@ -1651,6 +1653,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPP(){ layout.ENCODING = longfield<23,31>(insn_long); layout.OP = longfield<16,22>(insn_long); layout.SIMM16 = longfield<0,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SOPPOperands(); @@ -1663,6 +1666,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SOPK(){ layout.OP = longfield<23,27>(insn_long); layout.SDST = longfield<16,22>(insn_long); layout.SIMM16 = longfield<0,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SOPKOperands(); @@ -1676,6 +1680,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SOP2(){ layout.SDST = longfield<16,22>(insn_long); layout.SSRC0 = longfield<0,7>(insn_long); layout.SSRC1 = longfield<8,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SOP2Operands(); @@ -1694,6 +1699,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_SMEM(){ layout.SDATA = longfield<6,12>(insn_long); layout.SOFFSET = longfield<57,63>(insn_long); layout.SOFFSET_EN = longfield<14,14>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_SMEMOperands(); @@ -1706,6 +1712,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP1(){ layout.OP = longfield<9,16>(insn_long); layout.SRC0 = longfield<0,8>(insn_long); layout.VDST = longfield<17,24>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP1Operands(); @@ -1718,6 +1725,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOPC(){ layout.OP = longfield<17,24>(insn_long); layout.SRC0 = longfield<0,8>(insn_long); layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOPCOperands(); @@ -1731,6 +1739,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2(){ layout.SRC0 = longfield<0,8>(insn_long); layout.VDST = longfield<17,24>(insn_long); layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP2Operands(); @@ -1745,6 +1754,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VINTRP(){ layout.OP = longfield<16,17>(insn_long); layout.VDST = longfield<18,25>(insn_long); layout.VSRC = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VINTRPOperands(); @@ -1765,6 +1775,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P(){ layout.SRC1 = longfield<41,49>(insn_long); layout.SRC2 = longfield<50,58>(insn_long); layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP3POperands(); @@ -1784,6 +1795,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3(){ layout.SRC1 = longfield<41,49>(insn_long); layout.SRC2 = longfield<50,58>(insn_long); layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP3Operands(); @@ -1802,6 +1814,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_DS(){ layout.OFFSET1 = longfield<8,15>(insn_long); layout.OP = longfield<17,24>(insn_long); layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_DS_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_DS_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_DS_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_DSOperands(); @@ -1824,6 +1837,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_MUBUF(){ layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; layout.VADDR = longfield<32,39>(insn_long); layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_MUBUFOperands(); @@ -1847,6 +1861,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_MTBUF(){ layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; layout.VADDR = longfield<32,39>(insn_long); layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_MTBUFOperands(); @@ -1872,6 +1887,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_MIMG(){ layout.UNORM = longfield<12,12>(insn_long); layout.VADDR = longfield<32,39>(insn_long); layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_MIMGOperands(); @@ -1893,6 +1909,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT(){ layout.SEG = longfield<14,15>(insn_long); layout.SLC = longfield<17,17>(insn_long); layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_FLATOperands(); @@ -1914,6 +1931,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_GLBL(){ layout.SEG = longfield<14,15>(insn_long); layout.SLC = longfield<17,17>(insn_long); layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_FLAT_GLBLOperands(); @@ -1935,6 +1953,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_FLAT_SCRATCH(){ layout.SEG = longfield<14,15>(insn_long); layout.SLC = longfield<17,17>(insn_long); layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_FLAT_SCRATCHOperands(); @@ -1949,6 +1968,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP2_LITERAL(){ layout.SRC0 = longfield<0,8>(insn_long); layout.VDST = longfield<17,24>(insn_long); layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP2_LITERALOperands(); @@ -1967,6 +1987,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3B(){ layout.SRC1 = longfield<41,49>(insn_long); layout.SRC2 = longfield<50,58>(insn_long); layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP3BOperands(); @@ -1986,6 +2007,7 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P_MFMA(){ layout.SRC1 = longfield<41,49>(insn_long); layout.SRC2 = longfield<50,58>(insn_long); layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[0]) && "Opcode over or underflow"); const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[layout.OP]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); finalizeENC_VOP3P_MFMAOperands(); @@ -1994,133 +2016,177 @@ void InstructionDecoder_amdgpu_cdna2::decodeENC_VOP3P_MFMA(){ void InstructionDecoder_amdgpu_cdna2::mainDecodeOpcode(){ if(IS_ENC_SOP1(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[longfield<8,15>(insn_long)]; + uint32_t op_value = longfield<8,15>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP1_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SOP1; } else if(IS_ENC_SOPC(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[longfield<16,22>(insn_long)]; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPC_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SOPC; } else if(IS_ENC_SOPP(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[longfield<16,22>(insn_long)]; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPP_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SOPP; } else if(IS_ENC_SOPK(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[longfield<23,27>(insn_long)]; + uint32_t op_value = longfield<23,27>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOPK_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SOPK; } else if(IS_ENC_SOP2(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[longfield<23,29>(insn_long)]; + uint32_t op_value = longfield<23,29>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SOP2_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SOP2; } else if(IS_ENC_SMEM(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[longfield<18,25>(insn_long)]; + uint32_t op_value = longfield<18,25>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_SMEM_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_SMEM; } else if(IS_ENC_VOP1(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[longfield<9,16>(insn_long)]; + uint32_t op_value = longfield<9,16>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP1_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP1; } else if(IS_ENC_VOPC(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[longfield<17,24>(insn_long)]; + uint32_t op_value = longfield<17,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOPC_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOPC; } else if(IS_ENC_VOP2(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[longfield<25,30>(insn_long)]; + uint32_t op_value = longfield<25,30>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP2; } else if(IS_ENC_VINTRP(insn_long)){ insn_size = 4; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[longfield<16,17>(insn_long)]; + uint32_t op_value = longfield<16,17>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VINTRP_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VINTRP; } else if(IS_ENC_VOP3P(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[longfield<16,22>(insn_long)]; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP3P; } else if(IS_ENC_VOP3(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[longfield<16,25>(insn_long)]; + uint32_t op_value = longfield<16,25>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP3; } else if(IS_ENC_DS(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_DS_insn_table[longfield<17,24>(insn_long)]; + uint32_t op_value = longfield<17,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_DS_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_DS_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_DS_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_DS; } else if(IS_ENC_MUBUF(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[longfield<18,24>(insn_long)]; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MUBUF_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_MUBUF; } else if(IS_ENC_MTBUF(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[longfield<15,18>(insn_long)]; + uint32_t op_value = longfield<15,18>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MTBUF_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_MTBUF; } else if(IS_ENC_MIMG(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[longfield<18,24>(insn_long)]; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_MIMG_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_MIMG; } else if(IS_ENC_FLAT(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[longfield<18,24>(insn_long)]; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_FLAT; } else if(IS_ENC_FLAT_GLBL(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[longfield<18,24>(insn_long)]; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_GLBL_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_FLAT_GLBL; } else if(IS_ENC_FLAT_SCRATCH(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[longfield<18,24>(insn_long)]; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_FLAT_SCRATCH_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_FLAT_SCRATCH; } else if(IS_ENC_VOP2_LITERAL(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[longfield<25,30>(insn_long)]; + uint32_t op_value = longfield<25,30>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP2_LITERAL_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP2_LITERAL; } else if(IS_ENC_VOP3B(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[longfield<16,25>(insn_long)]; + uint32_t op_value = longfield<16,25>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3B_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP3B; } else if(IS_ENC_VOP3P_MFMA(insn_long)){ insn_size = 8; - const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[longfield<16,22>(insn_long)]; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table) / sizeof(amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_cdna2_insn_entry &insn_entry = amdgpu_cdna2_insn_entry::ENC_VOP3P_MFMA_insn_table[op]; this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); instr_family = ENC_VOP3P_MFMA; } diff --git a/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C index 9506a7661d..3c5874fe3d 100644 --- a/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C +++ b/instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C @@ -1,484 +1,513 @@ +#define CHECK(t) assert(layout.op >= 0 && layout.op < LEN(ARR(t)) && "layout.op overflow or underflow ") + +#define DECODE_AND_CHECK(t,l,h) \ + uint32_t op_value = longfield(insn_long); \ + CHECK2(t); \ + const amdgpu_vega_insn_entry & insn_entry = ARR(t) [op_value]; + +#define CHECK2(t) assert( op_value < LEN(ARR(t)) && "layout.op overflow or underflow ") +#define ARR(t) amdgpu_vega_insn_entry::TABLE(t) +#define TABLE(t) t##_insn_table +#define LEN(A) sizeof(A)/sizeof(A[0]) + void InstructionDecoder_amdgpu_vega::decodeSOP2(){ - unsigned insn_size_ = 4; - layout_sop2 & layout = insn_layout.sop2; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.ssrc1 = longfield<8,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - layout.op = longfield<23,29>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop2_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOP2Operands(); + unsigned insn_size_ = 4; + layout_sop2 & layout = insn_layout.sop2; + layout.ssrc0 = longfield<0,7>(insn_long); + layout.ssrc1 = longfield<8,15>(insn_long); + layout.sdst = longfield<16,22>(insn_long); + layout.op = longfield<23,29>(insn_long); + CHECK(sop2); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop2_insn_table[layout.op]; + decodeOperands(insn_entry); + + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSOP2Operands(); } void InstructionDecoder_amdgpu_vega::decodeSOP1(){ - unsigned insn_size_ = 4; - layout_sop1 & layout = insn_layout.sop1; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.op = longfield<8,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop1_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOP1Operands(); + unsigned insn_size_ = 4; + layout_sop1 & layout = insn_layout.sop1; + layout.ssrc0 = longfield<0,7>(insn_long); + layout.op = longfield<8,15>(insn_long); + layout.sdst = longfield<16,22>(insn_long); + CHECK(sop1); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop1_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSOP1Operands(); } void InstructionDecoder_amdgpu_vega::decodeSOPK(){ - unsigned insn_size_ = 4; - layout_sopk & layout = insn_layout.sopk; - layout.simm16 = longfield<0,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - layout.op = longfield<23,27>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopk_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPKOperands(); + unsigned insn_size_ = 4; + layout_sopk & layout = insn_layout.sopk; + layout.simm16 = longfield<0,15>(insn_long); + layout.sdst = longfield<16,22>(insn_long); + layout.op = longfield<23,27>(insn_long); + CHECK(sopk); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopk_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSOPKOperands(); } void InstructionDecoder_amdgpu_vega::decodeSOPC(){ - unsigned insn_size_ = 4; - layout_sopc & layout = insn_layout.sopc; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.ssrc1 = longfield<8,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopc_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPCOperands(); + unsigned insn_size_ = 4; + layout_sopc & layout = insn_layout.sopc; + layout.ssrc0 = longfield<0,7>(insn_long); + layout.ssrc1 = longfield<8,15>(insn_long); + layout.op = longfield<16,22>(insn_long); + CHECK(sopc); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopc_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSOPCOperands(); } void InstructionDecoder_amdgpu_vega::decodeSOPP(){ - unsigned insn_size_ = 4; - layout_sopp & layout = insn_layout.sopp; - layout.simm16 = longfield<0,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopp_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPPOperands(); + unsigned insn_size_ = 4; + layout_sopp & layout = insn_layout.sopp; + layout.simm16 = longfield<0,15>(insn_long); + layout.op = longfield<16,22>(insn_long); + CHECK(sopp); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopp_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSOPPOperands(); } void InstructionDecoder_amdgpu_vega::decodeSMEM(){ - unsigned insn_size_ = 8; - layout_smem & layout = insn_layout.smem; - layout.sbase = longfield<0,5>(insn_long); - layout.sdata = longfield<6,12>(insn_long); - layout.soe = longfield<14,14>(insn_long); - layout.nv = longfield<15,15>(insn_long); - layout.glc = longfield<16,16>(insn_long); - layout.imm = longfield<17,17>(insn_long); - layout.op = longfield<18,25>(insn_long); - layout.offset = longfield<32,52>(insn_long); - layout.soffset = longfield<57,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::smem_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSMEMOperands(); + unsigned insn_size_ = 8; + layout_smem & layout = insn_layout.smem; + layout.sbase = longfield<0,5>(insn_long); + layout.sdata = longfield<6,12>(insn_long); + layout.soe = longfield<14,14>(insn_long); + layout.nv = longfield<15,15>(insn_long); + layout.glc = longfield<16,16>(insn_long); + layout.imm = longfield<17,17>(insn_long); + layout.op = longfield<18,25>(insn_long); + layout.offset = longfield<32,52>(insn_long); + layout.soffset = longfield<57,63>(insn_long); + CHECK(smem); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::smem_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeSMEMOperands(); } void InstructionDecoder_amdgpu_vega::decodeVOP2(){ - unsigned insn_size_ = 4; - layout_vop2 & layout = insn_layout.vop2; - layout.src0 = longfield<0,8>(insn_long); - layout.vsrc1 = longfield<9,16>(insn_long); - layout.vdst = longfield<17,24>(insn_long); - layout.op = longfield<25,30>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dst_sel = longfield<40,42>(insn_long); - vop_literal.dst_u = longfield<43,44>(insn_long); - vop_literal.clmp = longfield<45,45>(insn_long); - vop_literal.omod = longfield<46,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop2_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP2Operands(); + unsigned insn_size_ = 4; + layout_vop2 & layout = insn_layout.vop2; + layout.src0 = longfield<0,8>(insn_long); + layout.vsrc1 = longfield<9,16>(insn_long); + layout.vdst = longfield<17,24>(insn_long); + layout.op = longfield<25,30>(insn_long); + if (layout.src0 == 249){ + vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.dst_sel = longfield<40,42>(insn_long); + vop_literal.dst_u = longfield<43,44>(insn_long); + vop_literal.clmp = longfield<45,45>(insn_long); + vop_literal.omod = longfield<46,47>(insn_long); + vop_literal.src0_sel = longfield<48,50>(insn_long); + vop_literal.src0_next = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.s0 = longfield<55,55>(insn_long); + vop_literal.src1_sel = longfield<56,58>(insn_long); + vop_literal.src_sext = longfield<59,59>(insn_long); + vop_literal.src1_neg = longfield<60,60>(insn_long); + vop_literal.s1 = longfield<63,63>(insn_long); + } + if (layout.src0 == 250){ + vop_literal_layout_dpp &vop_literal = layout.literal.dpp; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.dpp_ctrl = longfield<40,48>(insn_long); + vop_literal.bc = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.src1_neg = longfield<54,54>(insn_long); + vop_literal.src1_abs = longfield<55,55>(insn_long); + vop_literal.bank_mask = longfield<56,59>(insn_long); + vop_literal.row_mask = longfield<60,63>(insn_long); + } + CHECK(vop2); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop2_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVOP2Operands(); } void InstructionDecoder_amdgpu_vega::decodeVOP1(){ - unsigned insn_size_ = 4; - layout_vop1 & layout = insn_layout.vop1; - layout.src0 = longfield<0,8>(insn_long); - layout.op = longfield<9,16>(insn_long); - layout.vdst = longfield<17,24>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dst_sel = longfield<40,42>(insn_long); - vop_literal.dst_u = longfield<43,44>(insn_long); - vop_literal.clmp = longfield<45,45>(insn_long); - vop_literal.omod = longfield<46,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop1_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP1Operands(); + unsigned insn_size_ = 4; + layout_vop1 & layout = insn_layout.vop1; + layout.src0 = longfield<0,8>(insn_long); + layout.op = longfield<9,16>(insn_long); + layout.vdst = longfield<17,24>(insn_long); + if (layout.src0 == 249){ + vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.dst_sel = longfield<40,42>(insn_long); + vop_literal.dst_u = longfield<43,44>(insn_long); + vop_literal.clmp = longfield<45,45>(insn_long); + vop_literal.omod = longfield<46,47>(insn_long); + vop_literal.src0_sel = longfield<48,50>(insn_long); + vop_literal.src0_next = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.s0 = longfield<55,55>(insn_long); + vop_literal.src1_sel = longfield<56,58>(insn_long); + vop_literal.src_sext = longfield<59,59>(insn_long); + vop_literal.src1_neg = longfield<60,60>(insn_long); + vop_literal.s1 = longfield<63,63>(insn_long); + } + if (layout.src0 == 250){ + vop_literal_layout_dpp &vop_literal = layout.literal.dpp; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.dpp_ctrl = longfield<40,48>(insn_long); + vop_literal.bc = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.src1_neg = longfield<54,54>(insn_long); + vop_literal.src1_abs = longfield<55,55>(insn_long); + vop_literal.bank_mask = longfield<56,59>(insn_long); + vop_literal.row_mask = longfield<60,63>(insn_long); + } + CHECK(vop1); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop1_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVOP1Operands(); } void InstructionDecoder_amdgpu_vega::decodeVOPC(){ - unsigned insn_size_ = 4; - layout_vopc & layout = insn_layout.vopc; - layout.src0 = longfield<0,8>(insn_long); - layout.vsrc1 = longfield<9,16>(insn_long); - layout.op = longfield<17,24>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwab &vop_literal = layout.literal.sdwab; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.sdst = longfield<40,46>(insn_long); - vop_literal.sd = longfield<47,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vopc_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOPCOperands(); + unsigned insn_size_ = 4; + layout_vopc & layout = insn_layout.vopc; + layout.src0 = longfield<0,8>(insn_long); + layout.vsrc1 = longfield<9,16>(insn_long); + layout.op = longfield<17,24>(insn_long); + if (layout.src0 == 249){ + vop_literal_layout_sdwab &vop_literal = layout.literal.sdwab; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.sdst = longfield<40,46>(insn_long); + vop_literal.sd = longfield<47,47>(insn_long); + vop_literal.src0_sel = longfield<48,50>(insn_long); + vop_literal.src0_next = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.s0 = longfield<55,55>(insn_long); + vop_literal.src1_sel = longfield<56,58>(insn_long); + vop_literal.src_sext = longfield<59,59>(insn_long); + vop_literal.src1_neg = longfield<60,60>(insn_long); + vop_literal.s1 = longfield<63,63>(insn_long); + } + if (layout.src0 == 250){ + vop_literal_layout_dpp &vop_literal = layout.literal.dpp; + vop_literal.src0 = longfield<32,39>(insn_long); + vop_literal.dpp_ctrl = longfield<40,48>(insn_long); + vop_literal.bc = longfield<51,51>(insn_long); + vop_literal.src0_neg = longfield<52,52>(insn_long); + vop_literal.src0_abs = longfield<53,53>(insn_long); + vop_literal.src1_neg = longfield<54,54>(insn_long); + vop_literal.src1_abs = longfield<55,55>(insn_long); + vop_literal.bank_mask = longfield<56,59>(insn_long); + vop_literal.row_mask = longfield<60,63>(insn_long); + } + CHECK(vopc); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vopc_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVOPCOperands(); } void InstructionDecoder_amdgpu_vega::decodeVINTRP(){ - unsigned insn_size_ = 4; - layout_vintrp & layout = insn_layout.vintrp; - layout.vsrc = longfield<0,7>(insn_long); - layout.attr_chan = longfield<8,9>(insn_long); - layout.attr = longfield<10,15>(insn_long); - layout.op = longfield<16,17>(insn_long); - layout.vdst = longfield<18,25>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vintrp_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVINTRPOperands(); + unsigned insn_size_ = 4; + layout_vintrp & layout = insn_layout.vintrp; + layout.vsrc = longfield<0,7>(insn_long); + layout.attr_chan = longfield<8,9>(insn_long); + layout.attr = longfield<10,15>(insn_long); + layout.op = longfield<16,17>(insn_long); + layout.vdst = longfield<18,25>(insn_long); + CHECK(vintrp); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vintrp_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVINTRPOperands(); } void InstructionDecoder_amdgpu_vega::decodeDS(){ - unsigned insn_size_ = 8; - layout_ds & layout = insn_layout.ds; - layout.offset0 = longfield<0,7>(insn_long); - layout.offset1 = longfield<8,15>(insn_long); - layout.gds = longfield<16,16>(insn_long); - layout.op = longfield<17,24>(insn_long); - layout.addr = longfield<32,39>(insn_long); - layout.data0 = longfield<40,47>(insn_long); - layout.data1 = longfield<48,55>(insn_long); - layout.vdst = longfield<56,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::ds_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeDSOperands(); + unsigned insn_size_ = 8; + layout_ds & layout = insn_layout.ds; + layout.offset0 = longfield<0,7>(insn_long); + layout.offset1 = longfield<8,15>(insn_long); + layout.gds = longfield<16,16>(insn_long); + layout.op = longfield<17,24>(insn_long); + layout.addr = longfield<32,39>(insn_long); + layout.data0 = longfield<40,47>(insn_long); + layout.data1 = longfield<48,55>(insn_long); + layout.vdst = longfield<56,63>(insn_long); + CHECK(ds); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::ds_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeDSOperands(); } void InstructionDecoder_amdgpu_vega::decodeMTBUF(){ - unsigned insn_size_ = 8; - layout_mtbuf & layout = insn_layout.mtbuf; - layout.offset = longfield<0,11>(insn_long); - layout.offen = longfield<12,12>(insn_long); - layout.idxen = longfield<13,13>(insn_long); - layout.glc = longfield<14,14>(insn_long); - layout.op = longfield<15,18>(insn_long); - layout.dfmt = longfield<19,22>(insn_long); - layout.nfmt = longfield<23,25>(insn_long); - layout.vaddr = longfield<32,39>(insn_long); - layout.vdata = longfield<40,47>(insn_long); - layout.srsrc = longfield<48,52>(insn_long); - layout.slc = longfield<54,54>(insn_long); - layout.tfe = longfield<55,55>(insn_long); - layout.soffset = longfield<56,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mtbuf_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeMTBUFOperands(); + unsigned insn_size_ = 8; + layout_mtbuf & layout = insn_layout.mtbuf; + layout.offset = longfield<0,11>(insn_long); + layout.offen = longfield<12,12>(insn_long); + layout.idxen = longfield<13,13>(insn_long); + layout.glc = longfield<14,14>(insn_long); + layout.op = longfield<15,18>(insn_long); + layout.dfmt = longfield<19,22>(insn_long); + layout.nfmt = longfield<23,25>(insn_long); + layout.vaddr = longfield<32,39>(insn_long); + layout.vdata = longfield<40,47>(insn_long); + layout.srsrc = longfield<48,52>(insn_long); + layout.slc = longfield<54,54>(insn_long); + layout.tfe = longfield<55,55>(insn_long); + layout.soffset = longfield<56,63>(insn_long); + CHECK(mtbuf); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mtbuf_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeMTBUFOperands(); } void InstructionDecoder_amdgpu_vega::decodeMUBUF(){ - unsigned insn_size_ = 8; - layout_mubuf & layout = insn_layout.mubuf; - layout.offset = longfield<0,11>(insn_long); - layout.offen = longfield<12,12>(insn_long); - layout.idxen = longfield<13,13>(insn_long); - layout.glc = longfield<14,14>(insn_long); - layout.lds = longfield<16,16>(insn_long); - layout.slc = longfield<17,17>(insn_long); - layout.op = longfield<18,24>(insn_long); - layout.vaddr = longfield<32,39>(insn_long); - layout.vdata = longfield<40,47>(insn_long); - layout.srsrc = longfield<48,52>(insn_long); - layout.tfe = longfield<55,55>(insn_long); - layout.soffset = longfield<56,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mubuf_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeMUBUFOperands(); + unsigned insn_size_ = 8; + layout_mubuf & layout = insn_layout.mubuf; + layout.offset = longfield<0,11>(insn_long); + layout.offen = longfield<12,12>(insn_long); + layout.idxen = longfield<13,13>(insn_long); + layout.glc = longfield<14,14>(insn_long); + layout.lds = longfield<16,16>(insn_long); + layout.slc = longfield<17,17>(insn_long); + layout.op = longfield<18,24>(insn_long); + layout.vaddr = longfield<32,39>(insn_long); + layout.vdata = longfield<40,47>(insn_long); + layout.srsrc = longfield<48,52>(insn_long); + layout.tfe = longfield<55,55>(insn_long); + layout.soffset = longfield<56,63>(insn_long); + CHECK(mubuf); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mubuf_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeMUBUFOperands(); } void InstructionDecoder_amdgpu_vega::decodeVOP3AB(){ - unsigned insn_size_ = 8; - layout_vop3ab & layout = insn_layout.vop3ab; - layout.op = longfield<16,25>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3ab_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP3ABOperands(); + unsigned insn_size_ = 8; + layout_vop3ab & layout = insn_layout.vop3ab; + layout.op = longfield<16,25>(insn_long); + CHECK(vop3ab); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3ab_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVOP3ABOperands(); } void InstructionDecoder_amdgpu_vega::decodeVOP3P(){ - unsigned insn_size_ = 8; - layout_vop3p & layout = insn_layout.vop3p; - layout.vdst = longfield<0,7>(insn_long); - layout.neg_hi = longfield<8,10>(insn_long); - layout.opsel = longfield<11,13>(insn_long); - layout.opsel_hi2 = longfield<14,14>(insn_long); - layout.clmp = longfield<15,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - layout.src0 = longfield<32,40>(insn_long); - layout.src1 = longfield<41,49>(insn_long); - layout.src2 = longfield<50,58>(insn_long); - layout.opsel_hi = longfield<59,60>(insn_long); - layout.neg = longfield<61,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3p_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP3POperands(); + unsigned insn_size_ = 8; + layout_vop3p & layout = insn_layout.vop3p; + layout.vdst = longfield<0,7>(insn_long); + layout.neg_hi = longfield<8,10>(insn_long); + layout.opsel = longfield<11,13>(insn_long); + layout.opsel_hi2 = longfield<14,14>(insn_long); + layout.clmp = longfield<15,15>(insn_long); + layout.op = longfield<16,22>(insn_long); + layout.src0 = longfield<32,40>(insn_long); + layout.src1 = longfield<41,49>(insn_long); + layout.src2 = longfield<50,58>(insn_long); + layout.opsel_hi = longfield<59,60>(insn_long); + layout.neg = longfield<61,63>(insn_long); + CHECK(vop3p); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3p_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeVOP3POperands(); } void InstructionDecoder_amdgpu_vega::decodeFLAT(){ - unsigned insn_size_ = 8; - layout_flat & layout = insn_layout.flat; - layout.offset = longfield<0,12>(insn_long); - layout.lds = longfield<13,13>(insn_long); - layout.seg = longfield<14,15>(insn_long); - layout.glc = longfield<16,16>(insn_long); - layout.slc = longfield<17,17>(insn_long); - layout.op = longfield<18,24>(insn_long); - layout.addr = longfield<32,39>(insn_long); - layout.data = longfield<40,47>(insn_long); - layout.saddr = longfield<48,54>(insn_long); - layout.nv = longfield<55,55>(insn_long); - layout.vdst = longfield<56,63>(insn_long); - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::flat_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeFLATOperands(); + unsigned insn_size_ = 8; + layout_flat & layout = insn_layout.flat; + layout.offset = longfield<0,12>(insn_long); + layout.lds = longfield<13,13>(insn_long); + layout.seg = longfield<14,15>(insn_long); + layout.glc = longfield<16,16>(insn_long); + layout.slc = longfield<17,17>(insn_long); + layout.op = longfield<18,24>(insn_long); + layout.addr = longfield<32,39>(insn_long); + layout.data = longfield<40,47>(insn_long); + layout.saddr = longfield<48,54>(insn_long); + layout.nv = longfield<55,55>(insn_long); + layout.vdst = longfield<56,63>(insn_long); + CHECK(flat); + const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::flat_insn_table[layout.op]; + decodeOperands(insn_entry); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + finalizeFLATOperands(); } void InstructionDecoder_amdgpu_vega::mainDecode(InstructionDecoder::buffer &b){ - if(IS_SOP2(insn_long)){ - setUseImm<0,7,255>(b,4); - setUseImm<8,15,255>(b,4); - decodeSOP2(); - } - else if(IS_SOP1(insn_long)){ - setUseImm<0,7,255>(b,4); - decodeSOP1(); - } - else if(IS_SOPK(insn_long)){ - decodeSOPK(); - } - else if(IS_SOPC(insn_long)){ - decodeSOPC(); - } - else if(IS_SOPP(insn_long)){ - decodeSOPP(); - } - else if(IS_SMEM(insn_long)){ - decodeSMEM(); - } - else if(IS_VOP2(insn_long)){ - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - decodeVOP2(); - } - else if(IS_VOP1(insn_long)){ - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - decodeVOP1(); - } - else if(IS_VOPC(insn_long)){ - setUseImm<0,8,255>(b,4); - decodeVOPC(); - } - else if(IS_VINTRP(insn_long)){ - decodeVINTRP(); - } - else if(IS_DS(insn_long)){ - decodeDS(); - } - else if(IS_MTBUF(insn_long)){ - decodeMTBUF(); - } - else if(IS_MUBUF(insn_long)){ - decodeMUBUF(); - } - else if(IS_VOP3AB(insn_long)){ - decodeVOP3AB(); - } - else if(IS_VOP3P(insn_long)){ - decodeVOP3P(); - } - else if(IS_FLAT(insn_long)){ - decodeFLAT(); - } - else{ - assert(0); - } + if(IS_SOP2(insn_long)){ + setUseImm<0,7,255>(b,4); + setUseImm<8,15,255>(b,4); + decodeSOP2(); + } + else if(IS_SOP1(insn_long)){ + setUseImm<0,7,255>(b,4); + decodeSOP1(); + } + else if(IS_SOPK(insn_long)){ + decodeSOPK(); + } + else if(IS_SOPC(insn_long)){ + decodeSOPC(); + } + else if(IS_SOPP(insn_long)){ + decodeSOPP(); + } + else if(IS_SMEM(insn_long)){ + decodeSMEM(); + } + else if(IS_VOP2(insn_long)){ + setUseImm<0,8,249>(b,4); + setUseImm<0,8,250>(b,4); + setUseImm<0,8,255>(b,4); + decodeVOP2(); + } + else if(IS_VOP1(insn_long)){ + setUseImm<0,8,249>(b,4); + setUseImm<0,8,250>(b,4); + setUseImm<0,8,255>(b,4); + decodeVOP1(); + } + else if(IS_VOPC(insn_long)){ + setUseImm<0,8,255>(b,4); + decodeVOPC(); + } + else if(IS_VINTRP(insn_long)){ + decodeVINTRP(); + } + else if(IS_DS(insn_long)){ + decodeDS(); + } + else if(IS_MTBUF(insn_long)){ + decodeMTBUF(); + } + else if(IS_MUBUF(insn_long)){ + decodeMUBUF(); + } + else if(IS_VOP3AB(insn_long)){ + decodeVOP3AB(); + } + else if(IS_VOP3P(insn_long)){ + decodeVOP3P(); + } + else if(IS_FLAT(insn_long)){ + decodeFLAT(); + } + else{ + assert(0); + } } void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer &b){ - if(IS_SOP2(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop2_insn_table[longfield<23,29>(insn_long)]; - setUseImm<0,7,255>(b,4); - setUseImm<8,15,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOP2; - } - else if(IS_SOP1(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sop1_insn_table[longfield<8,15>(insn_long)]; - setUseImm<0,7,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOP1; - } - else if(IS_SOPK(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopk_insn_table[longfield<23,27>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPK; - } - else if(IS_SOPC(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopc_insn_table[longfield<16,22>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPC; - } - else if(IS_SOPP(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::sopp_insn_table[longfield<16,22>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPP; - } - else if(IS_SMEM(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::smem_insn_table[longfield<18,25>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SMEM; - } - else if(IS_VOP2(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop2_insn_table[longfield<25,30>(insn_long)]; - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP2; - } - else if(IS_VOP1(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop1_insn_table[longfield<9,16>(insn_long)]; - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP1; - } - else if(IS_VOPC(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vopc_insn_table[longfield<17,24>(insn_long)]; - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOPC; - } - else if(IS_VINTRP(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vintrp_insn_table[longfield<16,17>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VINTRP; - } - else if(IS_DS(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::ds_insn_table[longfield<17,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = DS; - } - else if(IS_MTBUF(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mtbuf_insn_table[longfield<15,18>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = MTBUF; - } - else if(IS_MUBUF(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::mubuf_insn_table[longfield<18,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = MUBUF; - } - else if(IS_VOP3AB(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3ab_insn_table[longfield<16,25>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP3AB; - } - else if(IS_VOP3P(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::vop3p_insn_table[longfield<11,13>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP3P; - } - else if(IS_FLAT(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_vega_insn_entry &insn_entry = amdgpu_vega_insn_entry::flat_insn_table[longfield<18,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = FLAT; - } - else{ - assert(0); - } + if(IS_SOP2(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(sop2,23,29); + setUseImm<0,7,255>(b,4); + setUseImm<8,15,255>(b,4); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SOP2; + } + else if(IS_SOP1(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(sop1,8,15); + setUseImm<0,7,255>(b,4); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SOP1; + } + else if(IS_SOPK(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(sopk,23,27); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SOPK; + } + else if(IS_SOPC(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(sopc,16,22); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SOPC; + } + else if(IS_SOPP(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(sopp,16,22); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SOPP; + } + else if(IS_SMEM(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(smem,18,25); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = SMEM; + } + else if(IS_VOP2(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(vop2,25,30); + setUseImm<0,8,249>(b,4); + setUseImm<0,8,250>(b,4); + setUseImm<0,8,255>(b,4); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VOP2; + } + else if(IS_VOP1(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(vop1,9,16); + setUseImm<0,8,249>(b,4); + setUseImm<0,8,250>(b,4); + setUseImm<0,8,255>(b,4); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VOP1; + } + else if(IS_VOPC(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(vopc,17,24); + setUseImm<0,8,255>(b,4); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VOPC; + } + else if(IS_VINTRP(insn_long)){ + unsigned insn_size_ = 4; + DECODE_AND_CHECK(vintrp,16,17); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VINTRP; + } + else if(IS_DS(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(ds,17,24); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = DS; + } + else if(IS_MTBUF(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(mtbuf,15,18); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = MTBUF; + } + else if(IS_MUBUF(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(mubuf,18,24); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = MUBUF; + } + else if(IS_VOP3AB(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(vop3ab,16,25); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VOP3AB; + } + else if(IS_VOP3P(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(vop3p,11,13); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = VOP3P; + } + else if(IS_FLAT(insn_long)){ + unsigned insn_size_ = 8; + DECODE_AND_CHECK(flat,18,24); + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); + instr_family = FLAT; + } + else{ + assert(0); + } } From 922a7103b06867b19ba364cd7199ded3ac697763 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 7 Mar 2022 11:28:17 -0600 Subject: [PATCH 082/505] Docker: use more OS packages (#1211) * Use perl from OS package * Use CMake from OS package * Use Boost from OS package * Use TBB from OS package * Mark all external packages as not buildable --- docker/Dockerfile | 48 ++++++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 36ff99d7ba..4483cc77d7 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -10,28 +10,24 @@ ENV DEBIAN_FRONTEND=noninteractive ENV TZ=America/Los_Angeles # We can use build args to populate the specific versions of dependencies (with defaults here) -ARG BOOST_VERSION=1.73.0 +ARG BOOST_VERSION=1.71.0 ARG ELFUTILS_VERSION=0.186 ARG LIBIBERTY_VERSION=2.33.1 -ARG INTELTBB_VERSION=2020.2 -ARG PERL_VERSION=5.32.1 - -# Sort of separate from dyninst (but used to build/test) -ARG CMAKE_VERSION=3.21.2 -ENV CMAKE_VERSION=${CMAKE_VERSION} +ARG INTELTBB_VERSION=2020.3 +ARG PERL_VERSION=5.30.0 +ARG CMAKE_VERSION=3.16.3 # Set the branch name for spack to use (should be master even for PR) ARG DYNINST_BRANCH=master ENV DYNINST_BRANCH=${DYNINST_BRANCH} -# Note that perl 5.30.0 is provided by ubuntu - # Args need to be passed into envars to be used in RUN ENV BOOST_VERSION=${BOOST_VERSION} ENV ELFUTILS_VERSION=${ELFUTILS_VERSION} ENV LIBIBERTY_VERSION=${LIBIBERTY_VERSION} ENV INTELTBB_VERSION=${INTELTBB_VERSION} ENV PERL_VERSION=${PERL_VERSION} +ENV CMAKE_VERSION=${CMAKE_VERSION} RUN apt-get -qq update && \ apt-get -qq install -fy tzdata && \ @@ -53,7 +49,10 @@ RUN apt-get -qq update && \ valgrind \ vim \ wget \ - xsltproc + xsltproc \ + cmake \ + libboost1.71-all-dev \ + libtbb-dev # Install Clingo for Spack RUN python3 -m pip install --upgrade pip && \ @@ -81,17 +80,22 @@ RUN python3 -m pip install botocore boto3 && \ spack gpg trust key.pub # Find packages already installed on system, e.g. autoconf -RUN spack external find gcc@11.0.1 autoconf bzip2 git tar xz perl && \ - spack config add 'packages:all:target:[x86_64]' && \ - # Install a new CMake (Tim originally wanted 3.17.1 but spack doesn't have it) - spack install cmake@${CMAKE_VERSION} perl - -# Add cmake to a view -RUN spack view --dependencies no symlink --ignore-conflicts /opt/view cmake@${CMAKE_VERSION} perl -ENV PATH=/opt/view/bin:$PATH - -RUN spack external find cmake && \ - spack config add 'packages:cmake:buildable:False' +RUN spack external find --not-buildable gcc@11.0.1 autoconf bzip2 git tar xz perl cmake && \ + spack config add 'packages:all:target:[x86_64]' + +# 'spack external find' doesn't work on libraries +RUN printf "\n\ + boost:\n\ + externals:\n\ + - spec: boost@${BOOST_VERSION}\n\ + prefix: /usr\n\ + buildable: false\n\ + intel-tbb:\n\ + externals:\n\ + - spec: intel-tbb@${INTELTBB_VERSION}\n\ + prefix: /usr\n\ + buildable: false\n\ +" >> ~/.spack/packages.yaml # Add Dyninst source code here (e.g., from PR or master) WORKDIR /code @@ -114,6 +118,8 @@ RUN . /opt/spack/share/spack/setup-env.sh && \ spack add dyninst@${DYNINST_BRANCH} && \ # Add our hard coded versions here. + spack add cmake@${CMAKE_VERSION} && \ + spack add perl@${PERL_VERSION} && \ spack add boost@${BOOST_VERSION} && \ spack add elfutils@${ELFUTILS_VERSION} && \ spack add libiberty@${LIBIBERTY_VERSION} && \ From 76c7bc2564fa1aeeba3b832ac7245d1e8e1dbd47 Mon Sep 17 00:00:00 2001 From: William Cohen Date: Mon, 7 Mar 2022 13:54:18 -0500 Subject: [PATCH 083/505] Make a couple constant 64-bit ULL to avoid getting truncated during shifts (#1207) * Ensure ROR work with data types larger than 32 bits. * Ensure upper 32-bits of 64-bit aarch64 SIMD operand generated. --- instructionAPI/h/BinaryFunction.h | 2 +- instructionAPI/src/InstructionDecoder-aarch64.C | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/instructionAPI/h/BinaryFunction.h b/instructionAPI/h/BinaryFunction.h index 9b15def92f..34fdaa42c2 100644 --- a/instructionAPI/h/BinaryFunction.h +++ b/instructionAPI/h/BinaryFunction.h @@ -263,7 +263,7 @@ namespace Dyninst } Result one(u64, 1); - Result rot = arg1 & (Result(u64, (1<appendOperand(Immediate::makeImmediate(Result(u64, imm)), true, false); } From 9b5ffe39187cc0de148a7ca686c1548396e496c4 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 7 Mar 2022 17:37:50 -0600 Subject: [PATCH 084/505] Docker: simplify build script (#1212) * Use CMake's -S instead of undocumented -H * Remove log captures The reports are best used within the context of the PR, so storing them in the dashboard wouldn't be much use. * Reduce duplication of directory names * Use CMake commands to build/install * Separate build and install trees for Dyninst * Separate build and install directories for test suite * Simplify 'git pull' for test suite * Explicitly override test suite install directory The test suite reads Dyninst's cache which poisons the CMAKE_INSTALL_PREFIX. This overrides that and then puts the test files in the root install directory. --- docker/build.sh | 42 +++++++++++++++++++++++++----------------- docker/test.sh | 6 +++--- 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/docker/build.sh b/docker/build.sh index 4d86095e55..b002397089 100644 --- a/docker/build.sh +++ b/docker/build.sh @@ -6,33 +6,41 @@ set -euo pipefail printf "⭐️ Setting up spack environment for Dyninst\n" . /opt/spack/share/spack/setup-env.sh spack env activate . -mkdir -p build/dyninst # 1. Build Dyninst printf "⭐️ Preparing to build Dyninst\n" -echo "::group::build dyninst" -cd build/dyninst -cmake -H/code -B. -DCMAKE_INSTALL_PREFIX=. > >(tee config.out) 2> >(tee config.err >&2) -make VERBOSE=1 -j2 > >(tee build.out) 2> >(tee build.err >&2) -make install VERBOSE=1 -j2 > >(tee build-install.out) 2> >(tee build-install.err >&2) +echo "::group::build dyninst" + +DYNINST_BUILD_DIR=/opt/dyninst-env/build/dyninst +mkdir -p $DYNINST_BUILD_DIR + +DYNINST_INSTALL_DIR=/opt/dyninst-env/install/dyninst +mkdir -p $DYNINST_INSTALL_DIR + +cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR +cmake --build $DYNINST_BUILD_DIR -- -j2 +cmake --install $DYNINST_BUILD_DIR + echo "::endgroup::" # 2. Update the test suite printf "⭐️ Updating the testsuite\n" echo "::group::update testsuite" -cd /opt/testsuite -git pull origin master -cd - +git -C /opt/testsuite pull origin master echo "::endgroup::" # 3. Build the test suite printf "⭐️ Preparing to build the testsuite\n" -echo "::group::build tests" -cd /opt/dyninst-env/ -mkdir -p build/testsuite/tests -cd build/testsuite - -cmake -H/opt/testsuite -B. -DCMAKE_INSTALL_PREFIX=$PWD/tests -DDyninst_DIR=/opt/dyninst-env/build/dyninst/lib/cmake/Dyninst > >(tee config.out) 2> >(tee config.err >&2) -make VERBOSE=1 -j2 > >(tee build.out) 2> >(tee build.err >&2) -make install VERBOSE=1 -j2 > >(tee build-install.out) 2> >(tee build-install.err >&2) +echo "::group::build tests" + +TESTSUITE_BUILD_DIR=/opt/dyninst-env/build/testsuite +mkdir -p $TESTSUITE_BUILD_DIR + +TESTSUITE_INSTALL_DIR=/opt/dyninst-env/install/testsuite +mkdir -p $TESTSUITE_INSTALL_DIR + +cmake -S /opt/testsuite -B $TESTSUITE_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$TESTSUITE_INSTALL_DIR -DDyninst_DIR=$DYNINST_INSTALL_DIR/lib/cmake/Dyninst +cmake --build $TESTSUITE_BUILD_DIR -- -j2 +cmake --install $TESTSUITE_BUILD_DIR --prefix $TESTSUITE_INSTALL_DIR +mv $TESTSUITE_INSTALL_DIR/bin/testsuite/* $TESTSUITE_INSTALL_DIR echo "::endgroup::" diff --git a/docker/test.sh b/docker/test.sh index 072cc69960..9a749b96d3 100755 --- a/docker/test.sh +++ b/docker/test.sh @@ -7,10 +7,10 @@ spack env activate . # 3. Run the tests printf "⭐️ Running tests...\n" -cd /opt/dyninst-env/build/testsuite -export DYNINSTAPI_RT_LIB=/opt/dyninst-env/build/dyninst/lib/libdyninstAPI_RT.so +cd /opt/dyninst-env/install/testsuite +export DYNINSTAPI_RT_LIB=/opt/dyninst-env/install/dyninst/lib/libdyninstAPI_RT.so export OMP_NUM_THREADS=2 -export LD_LIBRARY_PATH=/opt/dyninst-env/build/dyninst/lib:$PWD:$LD_LIBRARY_PATH +export LD_LIBRARY_PATH=/opt/dyninst-env/install/dyninst/lib:$PWD:$LD_LIBRARY_PATH ./runTests -64 -all -log test.log -j1 > >(tee stdout.log) 2> >(tee stderr.log >&2) # TODO will update here to upload given merge to master From 8b400af59bad0ef9c25072a6b9774171db012bb1 Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 9 Mar 2022 15:38:46 -0600 Subject: [PATCH 085/505] Correctly handle DWARF subroutines during parallel parsing (#1215) Fix to only process the DWARF for a function (subprogram) once if it is defined in multiple compilation units within a library or executable. This prevents duplication of parameters, local variables and use of thread-unsafe data structures from concurrent threads. --- symtabAPI/src/dwarfWalker.C | 64 +++++++++++++++++++++++++++++++------ symtabAPI/src/dwarfWalker.h | 19 ++++++++--- 2 files changed, 69 insertions(+), 14 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index a0c5b14996..14376ebe36 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -80,8 +80,9 @@ using namespace std; } while (0) #define DWARF_CHECK_RET(x) DWARF_CHECK_RET_VAL(x, false) -DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf * dbg) : +DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf *dbg, std::shared_ptr pf) : DwarfParseActions(symtab, dbg), + parsedFuncs(pf), is_mangled_name_(false), modLow(0), modHigh(0), @@ -96,6 +97,9 @@ DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf * dbg) : next_cu_header(0), compile_offset(0) { + if (!parsedFuncs) { + parsedFuncs = std::make_shared(); + } } DwarfWalker::~DwarfWalker() { @@ -180,7 +184,7 @@ bool DwarfWalker::parse() { } else { #pragma omp parallel { - DwarfWalker w(symtab(), dbg()); + DwarfWalker w(symtab(), dbg(), parsedFuncs); #pragma omp for reduction(leftmost:fixUnknownMod) \ schedule(dynamic) nowait for (unsigned int i = 0; i < module_dies.size(); i++) { @@ -610,6 +614,28 @@ void DwarfParseActions::addPrettyFuncName(std::string name) curFunc()->addPrettyName(name, true, true); } + +// helper class to set and restore currentSubprogramFunction +namespace { +class SetAndRestoreFunction +{ + public: + SetAndRestoreFunction(FunctionBase* &v, FunctionBase* newFunc) : var(v) + { + savedFunc = var; + var = newFunc; + } + ~SetAndRestoreFunction() + { + var = savedFunc; + } + private: + FunctionBase* &var; + FunctionBase* savedFunc; +}; +} + + bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { bool name_result; @@ -645,15 +671,29 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { return true; } - if (parsedFuncs.find(func) != parsedFuncs.end()) { - dwarf_printf("(0x%lx) parseSubprogram not parsing children b/c curFunc() not in parsedFuncs\n", id()); - if(name_result) { - dwarf_printf("\tname is %s\n", curName().c_str()); - } - setParseChild(false); - return true; + // this function's accessor lock to check if parsed and/or parse it + ParsedFuncs::accessor funcParsed; + + // recursive if parsing a specification or abstract origin, + // accessor is already locked + bool isRecursiveSubprogramParse = (func == currentSubprogramFunction); + + if (!isRecursiveSubprogramParse) { + // check if function is parsed, hold mutex until scope is left + parsedFuncs->insert(funcParsed, func); + if (funcParsed->second) { + dwarf_printf("(0x%lx) parseSubprogram not parsing children b/c curFunc() marked parsed in parsedFuncs\n", id()); + if(name_result) { + dwarf_printf("\tname is %s\n", curName().c_str()); + } + setParseChild(false); + return true; + } } + // set the current function being parsed and restore old value on return + SetAndRestoreFunction setAndRestore(currentSubprogramFunction, func); + if (name_result && !curName().empty()) { dwarf_printf("(0x%lx) Identified function name as %s\n", id(), curName().c_str()); if (isMangledName()) { @@ -711,7 +751,11 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { return false; } - parsedFuncs.insert(func); + if (!isRecursiveSubprogramParse) { + // the function is now parsed + funcParsed->second = true; + } + if (func_type == InlinedFunc) { dwarf_printf("End parseSubprogram for inlined func at 0x%p\n", (void*)func->getOffset()); } diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 545fa9b0b3..705896fb26 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -214,6 +214,10 @@ class DwarfParseActions { Symtab *symtab_; virtual Object * obj() const ; + // Function object of current subprogram being parsed; used to detect + // parseSubprogram recursion + FunctionBase *currentSubprogramFunction = nullptr; + }; // class DwarfParseActions struct ContextGuard { @@ -233,7 +237,9 @@ class DwarfWalker : public DwarfParseActions { } Error; - DwarfWalker(Symtab *symtab, Dwarf* dbg); + using ParsedFuncs = tbb::concurrent_hash_map; + + DwarfWalker(Symtab *symtab, Dwarf* dbg, std::shared_ptr pf = nullptr); DwarfWalker(const DwarfWalker& o) : DwarfParseActions(o), @@ -254,7 +260,12 @@ class DwarfWalker : public DwarfParseActions { compile_offset(o.compile_offset), info_type_ids_(o.info_type_ids_), types_type_ids_(o.types_type_ids_), - sig8_type_ids_(o.sig8_type_ids_) {} + sig8_type_ids_(o.sig8_type_ids_) + { + if (!parsedFuncs) { + parsedFuncs = std::make_shared(); + } + } virtual ~DwarfWalker(); @@ -400,8 +411,8 @@ class DwarfWalker : public DwarfParseActions { Dwarf_Sword listLength); - // Header-only functions get multiple parsed. - std::set parsedFuncs; + // Map of Function* to bool (indicates function parsed) + std::shared_ptr parsedFuncs; private: std::string name_; bool is_mangled_name_; From 14d9d44f0c03199d76333b9571b1f6ed9e183e46 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 9 Mar 2022 16:41:45 -0600 Subject: [PATCH 086/505] Documentation update for v12.1.0 (#1216) --- CHANGELOG.md | 34 +++++++++++++++++++++++++- cmake/shared.cmake | 4 +-- common/doc/manual_frontpage.tex | 4 +-- dataflowAPI/doc/dataflowAPI.pdf | Bin 349805 -> 349841 bytes dynC_API/doc/dynC_API.pdf | Bin 298512 -> 298532 bytes dyninstAPI/doc/dyninstAPI.docx | Bin 151312 -> 151289 bytes dyninstAPI/doc/dyninstAPI.pdf | Bin 409466 -> 422213 bytes instructionAPI/doc/instructionAPI.pdf | Bin 563428 -> 563447 bytes parseAPI/doc/parseAPI.pdf | Bin 404138 -> 404163 bytes patchAPI/doc/patchAPI.pdf | Bin 614185 -> 614110 bytes proccontrol/doc/proccontrol.docx | Bin 105765 -> 107962 bytes proccontrol/doc/proccontrol.pdf | Bin 355537 -> 370176 bytes stackwalk/doc/stackwalk.pdf | Bin 318588 -> 318611 bytes symtabAPI/doc/symtabAPI.pdf | Bin 457426 -> 457106 bytes 14 files changed, 37 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5003fd307b..53a9fc29b5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,38 @@ # Change Log -## [12.0.1](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-23) +## [12.1.0](https://github.com/dyninst/dyninst/tree/v12.1.0) (2022-03-09) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.1...v12.1.0) + +- Correctly handle DWARF subroutines during parallel parsing ([1215](https://github.com/dyninst/dyninst/issues/1215)) +- Docker: simplify build script ([1212](https://github.com/dyninst/dyninst/issues/1212)) +- Make a couple constant 64-bit ULL to avoid getting truncated during shifts ([1207](https://github.com/dyninst/dyninst/issues/1207)) +- Docker: use more OS packages ([1211](https://github.com/dyninst/dyninst/issues/1211)) +- Fix potential buffer overrun in AMDGPU decoders ([1208](https://github.com/dyninst/dyninst/issues/1208)) +- Code clean up for AMDGPU ([1205](https://github.com/dyninst/dyninst/issues/1205)) +- Tidy up classes in AMDGPU ([1204](https://github.com/dyninst/dyninst/issues/1204)) +- Fix compiler warnings in amdgpu cdna2 code ([1198](https://github.com/dyninst/dyninst/issues/1198)) +- Build fixes for amdgpu/cdna2 ([1203](https://github.com/dyninst/dyninst/issues/1203)) +- Add Support for AMDGPU CDNA2 Architectures based on XML ISA spec ([1107](https://github.com/dyninst/dyninst/issues/1107)) +- fix building of symlite ([1197](https://github.com/dyninst/dyninst/issues/1197)) +- Additional cleanup of memory emulation for hybrid analysis ([1172](https://github.com/dyninst/dyninst/issues/1172)) +- Allow zero-length ELF program headers ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- Remove dead code and variables related to Symtab::data_ptr_ and Symtab::code_ptr_ ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- Remove dead code Object::elf_vaddr_to_ptr ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- glibc r_debug extensions to support multiple namespaces ([1175](https://github.com/dyninst/dyninst/issues/1175)) +- Symtab::module documentation cleanup ([1189](https://github.com/dyninst/dyninst/issues/1189)) +- Dockerfile: use explicit packages for 'spack external find' ([1195](https://github.com/dyninst/dyninst/issues/1195)) +- ParseAPI: Speed up the case where a function is called from many locations ([1190](https://github.com/dyninst/dyninst/issues/1190)) +- ELF+DWARF: always parse first entry in source file table ([1184](https://github.com/dyninst/dyninst/issues/1184)) +- Remove interposed definition of _r_debug ([1176](https://github.com/dyninst/dyninst/issues/1176)) +- start of work to add automated testing to dyninst! ([1183](https://github.com/dyninst/dyninst/issues/1183)) +- adding dyninst release trigger ([1181](https://github.com/dyninst/dyninst/issues/1181)) +- fixing workflow trigger ([1182](https://github.com/dyninst/dyninst/issues/1182)) +- Adding first stage of automated docker build ([1180](https://github.com/dyninst/dyninst/issues/1180)) +- Remove erroneous use of realloc in symtabAPI/Type-mem.h ([1170](https://github.com/dyninst/dyninst/issues/1170)) +- Clean up memoryTracker usage in binaryEdit ([877](https://github.com/dyninst/dyninst/issues/877)) + + +## [12.0.1](https://github.com/dyninst/dyninst/tree/v12.0.1) (2021-11-23) [Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.0...v12.0.1) **Build Changes** diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 0c3f6afcd1..a95a9d4ba5 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,6 +1,6 @@ set (DYNINST_MAJOR_VERSION 12) -set (DYNINST_MINOR_VERSION 0) -set (DYNINST_PATCH_VERSION 1) +set (DYNINST_MINOR_VERSION 1) +set (DYNINST_PATCH_VERSION 0) set (SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") set (LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") diff --git a/common/doc/manual_frontpage.tex b/common/doc/manual_frontpage.tex index 60796bf0f6..9690a3de53 100644 --- a/common/doc/manual_frontpage.tex +++ b/common/doc/manual_frontpage.tex @@ -42,9 +42,9 @@ % }; \node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$) - {\fontsize{24}{32}\selectfont 12.0 Release}; + {\fontsize{24}{32}\selectfont 12.1 Release}; \node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$) - {\fontsize{24}{32}\selectfont November 2021}; + {\fontsize{24}{32}\selectfont March 2022}; % Contact information % \matrix (UWaddress) [% diff --git a/dataflowAPI/doc/dataflowAPI.pdf b/dataflowAPI/doc/dataflowAPI.pdf index 8f613b960252a3d8b6cf2573eae31507f40d9f7a..d46da3275b58e4edf807f9b342040783eb9fefdf 100644 GIT binary patch delta 18076 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Haines Date: Thu, 10 Mar 2022 10:58:32 -0600 Subject: [PATCH 087/505] Update dependency versions in base container config This should have been part of #1211 --- .github/workflows/base-containers.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml index 74522bbf18..c7a51814b2 100644 --- a/.github/workflows/base-containers.yaml +++ b/.github/workflows/base-containers.yaml @@ -28,10 +28,11 @@ jobs: # 2. Generate matrix programatically and pipe in (recommended) # perl is 5.30.0 provided by 20.04 container base ubuntu: ["20.04"] - boost: ["1.73.0"] + boost: ["1.71.0"] elfutils: ["0.186"] libiberty: ["2.33.1"] - inteltbb: ["2020.2"] + inteltbb: ["2020.3"] + cmake: ["3.16.3"] runs-on: ubuntu-latest name: Build @@ -65,6 +66,7 @@ jobs: --build-arg ELFUTILS_VERSION=${{ matrix.elfutils }} \ --build-arg LIBIBERTY_VERSION=${{ matrix.libiberty }} \ --build-arg INTELTBB_VERSION=${{ matrix.inteltbb }} \ + --build-arg CMAKE_VERSION=${{ matrix.cmake }} \ -f Dockerfile \ -t ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest ../ From 7690abf3ddfbbf5e324a3906c4c3878bf8e40428 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Fri, 11 Mar 2022 16:52:45 -0700 Subject: [PATCH 088/505] Docker: adding a workflow for release (#1219) Currently we do the entire build from scratch for release, and this strategy was chosen for the cleanest build. However we can use the same strategy as we do for testing and take advantage of the base container. This PR adds a workflow to do that Signed-off-by: vsoch Co-authored-by: vsoch --- .github/workflows/base-containers.yaml | 12 ------- .github/workflows/release.yaml | 48 ++++++++++++++++++++++++++ docker/Dockerfile.release | 37 ++++++++++++++++++++ 3 files changed, 85 insertions(+), 12 deletions(-) create mode 100644 .github/workflows/release.yaml create mode 100644 docker/Dockerfile.release diff --git a/.github/workflows/base-containers.yaml b/.github/workflows/base-containers.yaml index c7a51814b2..9579d11bd9 100644 --- a/.github/workflows/base-containers.yaml +++ b/.github/workflows/base-containers.yaml @@ -6,10 +6,6 @@ on: schedule: - cron: 0 3 * * * - # Publish packages on release - release: - types: [published] - # On push to main we build and deploy images push: branches: @@ -78,14 +74,6 @@ jobs: username: ${{ github.actor }} password: ${{ secrets.GITHUB_TOKEN }} - - name: Tag and Push Release Image - if: (github.event_name == 'release') - run: | - tag=${GITHUB_REF#refs/tags/} - echo "Tagging and releasing ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag}" - docker tag ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag} - docker push ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:${tag} - - name: Deploy if: (github.event_name != 'pull_request') run: docker push ghcr.io/${org}/dyninst-ubuntu-${{ matrix.ubuntu }}:latest diff --git a/.github/workflows/release.yaml b/.github/workflows/release.yaml new file mode 100644 index 0000000000..94f89e127b --- /dev/null +++ b/.github/workflows/release.yaml @@ -0,0 +1,48 @@ +name: Build Container on Release + +on: + + # Publish packages on release + release: + types: [published] + +jobs: + build: + permissions: + packages: write + + # Note this inherits the arguments for dependencies from the base container + # If you move this release trigger to the base-containers workflow you + # can tweak this, however the release will take longer. + runs-on: ubuntu-latest + name: Build + steps: + - name: Checkout + uses: actions/checkout@v2 + + - name: Make Space For Build + run: | + sudo rm -rf /usr/share/dotnet + sudo rm -rf /opt/ghc + + - name: Build Dyninst Release Container + run: | + cd docker/ + docker build -f Dockerfile.release -t ghcr.io/dyninst/dyninst-ubuntu-20.04:latest ../ + + - name: GHCR Login + uses: docker/login-action@v1 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Tag and Push Release Image + run: | + tag=${GITHUB_REF#refs/tags/} + echo "Tagging and releasing ghcr.io/dyninst/dyninst-ubuntu-20.04:${tag}" + docker tag ghcr.io/dyninst/dyninst-ubuntu-20.04:latest ghcr.io/dyninst/dyninst-ubuntu-20.04:${tag} + docker push ghcr.io/dyninst/dyninst-ubuntu-20.04:${tag} + + - name: Deploy + run: docker push ghcr.io/dyninst/dyninst-ubuntu-20.04:latest diff --git a/docker/Dockerfile.release b/docker/Dockerfile.release new file mode 100644 index 0000000000..32d4b0cb6b --- /dev/null +++ b/docker/Dockerfile.release @@ -0,0 +1,37 @@ +ARG dyninst_base=ghcr.io/dyninst/dyninst-ubuntu-20.04:latest +FROM ${dyninst_base} as builder + +# docker build -f Dockerfile.release -t ghcr.io/dyninst/dyninst-ubuntu-20.04:${tag} ../ + +# Add updated Dyninst code +COPY . /code + +# Add testing and build script to run +COPY ./docker/build.sh /opt/dyninst-env/build.sh + +# Previous WORKDIR, just to be careful - reinstall dyninst at release +WORKDIR /opt/dyninst-env +RUN /bin/bash build.sh && \ + spack gc -y + +# Strip all the binaries +RUN find -L /opt/dyninst-env/* -type f -exec readlink -f '{}' \; | \ + xargs file -i | \ + grep 'charset=binary' | \ + grep 'x-executable\|x-archive\|x-sharedlib' | \ + awk -F: '{print $1}' | xargs strip -s + +# Modifications to the environment that are necessary to run +RUN cd /opt/dyninst-env && \ + spack env activate --sh -d . >> /etc/profile.d/z10_spack_environment.sh + +# Bare OS image to run the installed executables +FROM ubuntu:20.04 + +ENV PATH=/opt/dyninst-env/.spack-env/bin:/opt/spack/bin:$PATH + +COPY --from=builder /opt/dyninst-env /opt/dyninst-env +COPY --from=builder /opt/spack /opt/spack +COPY --from=builder /etc/profile.d/z10_spack_environment.sh /etc/profile.d/z10_spack_environment.sh + +ENTRYPOINT ["/bin/bash", "--rcfile", "/etc/profile", "-l", "-c"] From 72b45571777aa0a44a03155409c979fb8b7df443 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sat, 12 Mar 2022 21:56:29 -0600 Subject: [PATCH 089/505] Remove usage of DW_AT_MIPS_linkage_name (#1223) This isn't part of DWARF4 or DWARF5. Co-authored-by: Tim Haines --- symtabAPI/src/dwarfWalker.C | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 14376ebe36..8b908cd466 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -1634,10 +1634,8 @@ bool DwarfWalker::findFuncName() { Dwarf_Attribute linkageNameAttr; Dwarf_Die e = entry(); - auto status = dwarf_attr_integrate(&e, DW_AT_MIPS_linkage_name, &linkageNameAttr); - if (status == 0) - status = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); + auto status = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); if ( status != 0 ) { // previously ==1 const char *dwarfName = dwarf_formstring(&linkageNameAttr); //DWARF_FAIL_RET(dwarfName); From 0a0ff0923b0ab50ff6d73baab613ed4df9b232f9 Mon Sep 17 00:00:00 2001 From: Vanessasaurus <814322+vsoch@users.noreply.github.com> Date: Sun, 13 Mar 2022 18:52:43 -0600 Subject: [PATCH 090/505] Docker: testing workflow to run libabigail (#1220) Run libabigail's abidiff to detect ABI breakages between the current PR and the last successful build as well as the current PR and the last release. * testing workflow to run libabigail! I am not sure if the artifact is extracted relative or not, so will need to update the workflow to account for that. This is also a new strategy that will try to do the new build/retrieval of artifacts from previous containers - have not tried this yet! Signed-off-by: vsoch Co-authored-by: vsoch Co-authored-by: Tim Haines --- .github/workflows/libabigail.yaml | 95 +++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 .github/workflows/libabigail.yaml diff --git a/.github/workflows/libabigail.yaml b/.github/workflows/libabigail.yaml new file mode 100644 index 0000000000..36ab118611 --- /dev/null +++ b/.github/workflows/libabigail.yaml @@ -0,0 +1,95 @@ +name: Libabigail ABI Checks +on: + pull_request: [] + +jobs: + get-release: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:v12.1.0 + runs-on: ubuntu-latest + steps: + - name: Upload Libs + uses: actions/upload-artifact@v2-preview + with: + name: release-libs + path: /opt/dyninst-env/install/dyninst/lib + + get-latest: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:latest + runs-on: ubuntu-latest + steps: + - name: Upload Libs + uses: actions/upload-artifact@v2-preview + with: + name: latest-libs + path: /opt/dyninst-env/install/dyninst/lib + + get-pr: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:latest + runs-on: ubuntu-latest + steps: + - name: Build Pull Request + uses: actions/checkout@v3 + - name: Build + run: | + rm -rf /code + cp -R $PWD /code + ls /code + cd /opt/dyninst-env + /bin/bash build.sh + + - name: Upload results + uses: actions/upload-artifact@v2-preview + with: + name: pr-libs + path: /opt/dyninst-env/install/dyninst/lib + + abi: + runs-on: ubuntu-latest + needs: [get-latest, get-release, get-pr] + strategy: + fail-fast: false + matrix: + + # Testing every paired library for release vs pr and main vs. pr + libs: ["libcommon.so", + "libdynC_API.so", + "libdynDwarf.so", + "libdynElf.so", + "libdyninstAPI_RT.so", + "libdyninstAPI.so", + "libinstructionAPI.so", + "libparseAPI.so", + "libpatchAPI.so", + "libpcontrol.so", + "libstackwalk.so", + "libsymLite.so", + "libsymtabAPI.so"] + + # Artifact pairs (named) for comparison) + artifacts: [["pr-libs", "latest-libs"], + ["pr-libs", "release-libs"]] + + steps: + - name: Download Previous Version + uses: actions/download-artifact@v2 + with: + name: ${{ matrix.artifacts[1] }} + path: previous/ + + - name: Download Pull Request Version + uses: actions/download-artifact@v2 + with: + name: ${{ matrix.artifacts[0] }} + path: current/ + + - name: Show Files + run: | + ls current/ + ls previous/ + + - name: Run Libabigail + uses: buildsi/libabigail-action@main + env: + lib: ${{ matrix.libs }} + with: + abidiff: previous/${{ env.lib }} current/${{ env.lib }} From 8454ff504cc96c64768aba741b66e3bc681bc64b Mon Sep 17 00:00:00 2001 From: kupsch Date: Mon, 21 Mar 2022 06:54:26 -0500 Subject: [PATCH 091/505] Correctly propagate pc ranges for blocks and local variables (#1226) - fix valid pc address ranges for local variables that are declared in a sub-block (brace, try and catch blocks) of their function - fix Context class's constructors so they correctly initialize and copy all member (use in-class initialize and default constructors) --- symtabAPI/src/dwarfWalker.C | 16 +++++++++++++ symtabAPI/src/dwarfWalker.h | 45 ++++++++++++------------------------- 2 files changed, 30 insertions(+), 31 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 8b908cd466..d3070fcf13 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -381,6 +381,12 @@ bool DwarfWalker::parse_int(Dwarf_Die e, bool parseSib, bool dissociate_context) case DW_TAG_lexical_block: ret = parseLexicalBlock(); break; + case DW_TAG_try_block: + ret = parseTryBlock(); + break; + case DW_TAG_catch_block: + ret = parseCatchBlock(); + break; case DW_TAG_common_block: ret = parseCommonBlock(); break; @@ -859,6 +865,16 @@ bool DwarfWalker::parseLexicalBlock() { return parseRangeTypes(dbg(), entry()); } +bool DwarfWalker::parseTryBlock() { + dwarf_printf("(0x%lx) Parsing try block ranges\n", id()); + return parseRangeTypes(dbg(), entry()); +} + +bool DwarfWalker::parseCatchBlock() { + dwarf_printf("(0x%lx) Parsing catch block ranges\n", id()); + return parseRangeTypes(dbg(), entry()); +} + bool DwarfWalker::parseCommonBlock() { dwarf_printf("(0x%lx) Parsing common block\n", id()); diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 705896fb26..f8e54493eb 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -98,37 +98,18 @@ class DwarfParseActions { typedef boost::shared_ptr > > range_set_ptr; private: struct Context { - FunctionBase *func; - boost::shared_ptr commonBlock; - boost::shared_ptr enumType; - boost::shared_ptr enclosure; - bool parseSibling; - bool parseChild; - Dwarf_Die offset; - Dwarf_Die specEntry; - Dwarf_Die abstractEntry; - unsigned int tag; - Address base; - range_set_ptr ranges; - Context() : - func(NULL), commonBlock(NULL), - enumType(NULL), enclosure(NULL), - parseSibling(true), parseChild(true), - tag(0), base(0) { - } - Context(const Context& o) noexcept : - func(o.func), - commonBlock(o.commonBlock), - enumType(o.enumType), - enclosure(o.enclosure), - parseSibling(o.parseSibling), - parseChild(o.parseChild), - offset(o.offset), - specEntry(o.specEntry), - abstractEntry(o.specEntry), - tag(o.tag), - base(o.base) - {} + FunctionBase *func{}; + boost::shared_ptr commonBlock{}; + boost::shared_ptr enumType{}; + boost::shared_ptr enclosure{}; + bool parseSibling{true}; + bool parseChild{true}; + Dwarf_Die offset{}; + Dwarf_Die specEntry{}; + Dwarf_Die abstractEntry{}; + unsigned int tag{}; + Address base{}; + range_set_ptr ranges{}; }; std::stack c; @@ -290,6 +271,8 @@ class DwarfWalker : public DwarfParseActions { bool parseSubprogram(inline_t func_type); bool parseLexicalBlock(); + bool parseTryBlock(); + bool parseCatchBlock(); bool parseRangeTypes(Dwarf* dbg, Dwarf_Die die); bool parseCommonBlock(); bool parseConstant(); From 474ab1e480147fc2583e192e77a2a7526b88514f Mon Sep 17 00:00:00 2001 From: kupsch Date: Sun, 27 Mar 2022 13:56:27 -0500 Subject: [PATCH 092/505] Fix warnings with cmake's MINSIZEREL build type (#1235) - Explicitly define optimization flags for cmake's MINSIZEREL build type. Cmake by default includes -DNDEBUG. This results in assert being defined to do nothing. Dyninst use asserts as a fatal error reporting mechanism and expects assert to not return if the condition is always false. If assert can return then many warnings are produced due to this unexpect path. - Remove defining NDEBUG for REL build types if using the MSC compiler --- cmake/optimization.cmake | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/cmake/optimization.cmake b/cmake/optimization.cmake index 1308bbcc31..a15f24084a 100644 --- a/cmake/optimization.cmake +++ b/cmake/optimization.cmake @@ -18,6 +18,9 @@ set (CMAKE_CXX_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") set (CMAKE_C_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") +set (CMAKE_C_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") +set (CMAKE_CXX_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") + set (FORCE_FRAME_POINTER "-fno-omit-frame-pointer") # Ensure each library is fully linked set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined") @@ -35,11 +38,14 @@ endif() set (CMAKE_C_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") set (CMAKE_CXX_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") -set (CMAKE_C_FLAGS_RELEASE "/MP /O2 /MD /D NDEBUG ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELEASE "/MP /O2 /MD /D NDEBUG ${LTO_FLAGS}") +set (CMAKE_C_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") +set (CMAKE_CXX_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") + +set (CMAKE_C_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") +set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") -set (CMAKE_C_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD /D NDEBUG ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD /D NDEBUG ${LTO_FLAGS}") +set (CMAKE_C_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") +set (CMAKE_CXX_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") set (FORCE_FRAME_POINTER "/Oy-") From 908b7c1d1279ada1312a03c14bf25ec19026582f Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 29 Mar 2022 15:19:51 -0500 Subject: [PATCH 093/505] Remove BUILD_RT option (#1238) When not enabled, the dyninstAPI_RT/cmake_install.cmake isn't present. This has been broken since it was implemented by e1afc6918 in 2016. --- CMakeLists.txt | 4 ---- cmake/options.cmake | 1 - 2 files changed, 5 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a4c6d7d76e..eacbb0b793 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -106,7 +106,6 @@ if(${SYMREADER} MATCHES symtabAPI) add_subdirectory (parseThat) endif() -if(BUILD_RTLIB) # Build the RT library as a separate project so we can change compilers message(STATUS "Configuring DyninstAPI_RT in ${RT_BINARY_DIR}") file(REMOVE_RECURSE ${RT_BINARY_DIR}/CMakeCache.txt ${RT_BINARY_DIR}/CMakeFiles ${RT_BINARY_DIR}/Makefile) @@ -156,9 +155,6 @@ if(BUILD_RTLIB) install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") -else() - message(STATUS "Skipping DyninstAPI_RT. Be sure to build this library if you're using instrumentation.") -endif() set (VERSION_STRING "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") set (DYNINST_NAME "DyninstAPI-${VERSION_STRING}") diff --git a/cmake/options.cmake b/cmake/options.cmake index 1f46d90df2..39e046a237 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -10,7 +10,6 @@ option (SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" option (BUILD_TARBALLS "Build Dyninst package tarballs. Requires git archive, tar, gzip." OFF) option (BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) -option(BUILD_RTLIB "Building runtime library (can be disabled safely for component-level builds)" ON) option(BUILD_DOCS "Build manuals from LaTeX sources" ON) option (ENABLE_LTO "Enable Link-Time Optimization" OFF) From cbd35bd28beea489a2d286c5fe95136ae2115954 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 29 Mar 2022 15:21:52 -0500 Subject: [PATCH 094/505] Add parsing of names for inlined functions in DWARF (#1237) * Clean up and enhance debug messages * Add parsing of names for inlined functions Co-authored-by: Tim Haines --- symtabAPI/src/dwarfWalker.C | 61 ++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 14 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index d3070fcf13..6459910a46 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -1645,26 +1645,59 @@ std::string DwarfWalker::die_name() { bool DwarfWalker::findFuncName() { - dwarf_printf("(0x%lx) Checking for linkage name\n", id()); - /* Prefer linkage names. */ + dwarf_printf("(0x%lx) Checking for function name\n", id()); - Dwarf_Attribute linkageNameAttr; Dwarf_Die e = entry(); - auto status = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); - if ( status != 0 ) { // previously ==1 - const char *dwarfName = dwarf_formstring(&linkageNameAttr); - //DWARF_FAIL_RET(dwarfName); - if(dwarfName==NULL) return false; - curName() = dwarfName; - setMangledName(true); - dwarf_printf("(0x%lx) Found DW_AT_linkage_name of %s, using\n", id(), curName().c_str()); - return true; + // Does this function have a linkage name? + { + Dwarf_Attribute linkageNameAttr{}; + Dwarf_Attribute *attr = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); + if (attr) { + char const* dwarfName = dwarf_formstring(attr); + if(!dwarfName) { + dwarf_printf("(0x%lx) Found 'DW_AT_linkage_name', but formstring is empty\n", id()); + return false; + } + curName() = dwarfName; + setMangledName(true); + dwarf_printf("(0x%lx) Found DW_AT_linkage_name of %s\n", id(), curName().c_str()); + return true; + } } - dwarf_printf("(0x%lx) DW_AT_linkage_name name not found\n", id()); - setMangledName(false); + // Is this an inlined function? + { + int const is_inline = dwarf_hasattr(&e, DW_AT_inline); + if(is_inline != -1) { + // Find the 'DW_AT_name' for this DIE. Do not traverse this as an abstract + // instance root (if it is one)- i.e., don't use dwarf_attr_integrate here. + Dwarf_Attribute nameAttr{}; + Dwarf_Attribute *res = dwarf_attr(&e, DW_AT_name, &nameAttr); + if(!res) { + dwarf_printf("(0x%lx) Found an inlined subroutine, but has no 'DW_AT_name'\n", id()); + return false; + } + char const* dwarfName = dwarf_formstring(&nameAttr); + if(!dwarfName) { + dwarf_printf("(0x%lx) Found an inlined subroutine, but formstring is empty\n", id()); + return false; + } + curName() = dwarfName; + + // Section 2.15 of the DWARF5 spec suggests that DW_AT_name should be the name as it + // appears in the source- not mangled. + setMangledName(false); + + dwarf_printf("(0x%lx) Found inline DW_AT_name '%s'\n", id(), curName().c_str()); + return true; + } + } + + // Assume the name is the unmangled name associated with the current DIE, if any curName() = std::move(die_name(entry())); + setMangledName(false); + dwarf_printf("(0x%lx) No explicit function name found; using most-recently found name '%s'\n", id(), curName().c_str()); return true; } From 10e1cebcf413b1d47f260aa7e3e115fe5f4c779f Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 29 Mar 2022 15:24:43 -0500 Subject: [PATCH 095/505] Remove void pointer arithmetic when using Valgrind annotations (#1236) gcc allows this as an extension by considering sizeof(void) to be 1 (http://gcc.gnu.org/onlinedocs/gcc/Pointer-Arith.html). --- common/src/concurrent.C | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/src/concurrent.C b/common/src/concurrent.C index da959985b5..c3037ce69c 100644 --- a/common/src/concurrent.C +++ b/common/src/concurrent.C @@ -75,18 +75,18 @@ void dyn_c_annotations::rwdeinit(void* ptr) { } void dyn_c_annotations::wlock(void* ptr) { ANNOTATE_RWLOCK_ACQUIRED(ptr, 1 /* writer mode */); - ANNOTATE_HAPPENS_AFTER(ptr + 1); // After all the readers + ANNOTATE_HAPPENS_AFTER(static_cast(ptr) + 1); // After all the readers } void dyn_c_annotations::wunlock(void* ptr) { - ANNOTATE_HAPPENS_BEFORE(ptr + 2); + ANNOTATE_HAPPENS_BEFORE(static_cast(ptr) + 2); ANNOTATE_RWLOCK_RELEASED(ptr, 1 /* writer mode */); } void dyn_c_annotations::rlock(void* ptr) { ANNOTATE_RWLOCK_ACQUIRED(ptr, 0 /* reader mode */); - ANNOTATE_HAPPENS_AFTER(ptr + 2); // After the last writer + ANNOTATE_HAPPENS_AFTER(static_cast(ptr) + 2); // After the last writer } void dyn_c_annotations::runlock(void* ptr) { - ANNOTATE_HAPPENS_BEFORE(ptr + 1); + ANNOTATE_HAPPENS_BEFORE(static_cast(ptr) + 1); ANNOTATE_RWLOCK_RELEASED(ptr, 0 /* reader mode */); } #endif From ba15a859243898e5c84dc2c316d7d7fe78edd4c4 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 30 Mar 2022 17:19:21 -0500 Subject: [PATCH 096/505] Docker: use more OS packages for dependencies (#1221) * Docker: use more OS packages for dependencies This should have been part of #1211. --- docker/Dockerfile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 4483cc77d7..299f16d99b 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -52,7 +52,10 @@ RUN apt-get -qq update && \ xsltproc \ cmake \ libboost1.71-all-dev \ - libtbb-dev + libtbb-dev \ + libxml2-dev \ + m4 \ + libncurses-dev # Install Clingo for Spack RUN python3 -m pip install --upgrade pip && \ @@ -80,7 +83,7 @@ RUN python3 -m pip install botocore boto3 && \ spack gpg trust key.pub # Find packages already installed on system, e.g. autoconf -RUN spack external find --not-buildable gcc@11.0.1 autoconf bzip2 git tar xz perl cmake && \ +RUN spack external find --not-buildable gcc@11.0.1 autoconf bzip2 git tar xz perl cmake m4 ncurses && \ spack config add 'packages:all:target:[x86_64]' # 'spack external find' doesn't work on libraries @@ -95,6 +98,11 @@ RUN printf "\n\ - spec: intel-tbb@${INTELTBB_VERSION}\n\ prefix: /usr\n\ buildable: false\n\ + libxml2:\n\ + externals:\n\ + - spec: libxml2@2.19.10\n\ + prefix: /usr\n\ + buildable: false\n\ " >> ~/.spack/packages.yaml # Add Dyninst source code here (e.g., from PR or master) From ceeffa67b5e7e06e76bee70c19ccf30b9ae54328 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sat, 2 Apr 2022 21:00:42 -0500 Subject: [PATCH 097/505] Docker: don't build Dyninst through spack for the environment (#1222) This results in two installations: one in /opt/dyninst-dev/.spack/include and one in /opt/dyninst-dev/install/dyninst. The former is not updated when testing a PR, so causes public header conflicts. --- docker/Dockerfile | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 299f16d99b..9c42954c24 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -118,19 +118,11 @@ RUN . /opt/spack/share/spack/setup-env.sh && \ spack env create -d . && \ echo " concretization: together" >> spack.yaml && \ spack env activate . && \ - - # This adds metadata for dyninst to spack.yaml - spack develop --path /code dyninst@${DYNINST_BRANCH} && \ - - # ...but we need spack add to add to the install list! - spack add dyninst@${DYNINST_BRANCH} && \ - - # Add our hard coded versions here. spack add cmake@${CMAKE_VERSION} && \ spack add perl@${PERL_VERSION} && \ spack add boost@${BOOST_VERSION} && \ spack add elfutils@${ELFUTILS_VERSION} && \ - spack add libiberty@${LIBIBERTY_VERSION} && \ + spack add libiberty@${LIBIBERTY_VERSION}+pic && \ spack add intel-tbb@${INTELTBB_VERSION} && \ spack install --reuse From 7a3964e2f64a8882b36a705af02f09c177826860 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Sun, 3 Apr 2022 23:21:21 -0500 Subject: [PATCH 098/505] Docker: use external-tests instead of testsuite in base image (#1209) This is in preparation for using -Werror when building Dyninst in the Github workflow. The test suite does not currently build cleanly, so we need a different set of tests. --- docker/Dockerfile | 5 +---- docker/Dockerfile.test | 18 +++++++++++++----- docker/build.sh | 26 +------------------------- docker/test.sh | 28 +++++++++++++++++----------- 4 files changed, 32 insertions(+), 45 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 9c42954c24..4339aba4bc 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -109,9 +109,6 @@ RUN printf "\n\ WORKDIR /code COPY . /code -# Add test code to base container so we can build tests here -RUN git clone https://github.com/dyninst/testsuite /opt/testsuite - # Install Dyninst to its own view WORKDIR /opt/dyninst-env RUN . /opt/spack/share/spack/setup-env.sh && \ @@ -126,6 +123,6 @@ RUN . /opt/spack/share/spack/setup-env.sh && \ spack add intel-tbb@${INTELTBB_VERSION} && \ spack install --reuse -# Build tests (but don't run) +# Build Dyninst COPY ./docker/build.sh build.sh RUN /bin/bash build.sh diff --git a/docker/Dockerfile.test b/docker/Dockerfile.test index fb1ed8c763..3ebb608b0c 100644 --- a/docker/Dockerfile.test +++ b/docker/Dockerfile.test @@ -6,12 +6,20 @@ FROM ${dyninst_base} # Add updated Dyninst code COPY . /code -# Add testing and build script to run +# Add external tests code +#------ +# A key element of these tests is to be able to _build_ against a Dyninst installation +# As such, we don't need to keep them in the base image +RUN git clone --depth=1 https://github.com/dyninst/external-tests /opt/external-tests + +# Add build scripts to run COPY ./docker/build.sh /opt/dyninst-env/build.sh COPY ./docker/test.sh /opt/dyninst-env/test.sh -# Previous WORKDIR, just to be careful - reinstall dyninst if needed -# Thenbuild and run the test suite WORKDIR /opt/dyninst-env -RUN /bin/bash build.sh && \ - /bin/bash test.sh + +# Build Dyninst +RUN /bin/bash build.sh + +# Run the tests +RUN /bin/bash test.sh diff --git a/docker/build.sh b/docker/build.sh index b002397089..58dd67a23e 100644 --- a/docker/build.sh +++ b/docker/build.sh @@ -1,8 +1,6 @@ #!/bin/bash set -euo pipefail -# This script builds dyninst and the test suite (but does not run tests) - printf "⭐️ Setting up spack environment for Dyninst\n" . /opt/spack/share/spack/setup-env.sh spack env activate . @@ -17,30 +15,8 @@ mkdir -p $DYNINST_BUILD_DIR DYNINST_INSTALL_DIR=/opt/dyninst-env/install/dyninst mkdir -p $DYNINST_INSTALL_DIR -cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR +cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR cmake --build $DYNINST_BUILD_DIR -- -j2 cmake --install $DYNINST_BUILD_DIR echo "::endgroup::" - -# 2. Update the test suite -printf "⭐️ Updating the testsuite\n" -echo "::group::update testsuite" -git -C /opt/testsuite pull origin master -echo "::endgroup::" - -# 3. Build the test suite -printf "⭐️ Preparing to build the testsuite\n" -echo "::group::build tests" - -TESTSUITE_BUILD_DIR=/opt/dyninst-env/build/testsuite -mkdir -p $TESTSUITE_BUILD_DIR - -TESTSUITE_INSTALL_DIR=/opt/dyninst-env/install/testsuite -mkdir -p $TESTSUITE_INSTALL_DIR - -cmake -S /opt/testsuite -B $TESTSUITE_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$TESTSUITE_INSTALL_DIR -DDyninst_DIR=$DYNINST_INSTALL_DIR/lib/cmake/Dyninst -cmake --build $TESTSUITE_BUILD_DIR -- -j2 -cmake --install $TESTSUITE_BUILD_DIR --prefix $TESTSUITE_INSTALL_DIR -mv $TESTSUITE_INSTALL_DIR/bin/testsuite/* $TESTSUITE_INSTALL_DIR -echo "::endgroup::" diff --git a/docker/test.sh b/docker/test.sh index 9a749b96d3..e4bdde02d1 100755 --- a/docker/test.sh +++ b/docker/test.sh @@ -5,15 +5,21 @@ printf "⭐️ Setting up spack environment for Dyninst\n" . /opt/spack/share/spack/setup-env.sh spack env activate . -# 3. Run the tests -printf "⭐️ Running tests...\n" -cd /opt/dyninst-env/install/testsuite -export DYNINSTAPI_RT_LIB=/opt/dyninst-env/install/dyninst/lib/libdyninstAPI_RT.so -export OMP_NUM_THREADS=2 -export LD_LIBRARY_PATH=/opt/dyninst-env/install/dyninst/lib:$PWD:$LD_LIBRARY_PATH -./runTests -64 -all -log test.log -j1 > >(tee stdout.log) 2> >(tee stderr.log >&2) +# Build the tests +# NB: There are no tests to execute (yet), so building is the actual test +printf "⭐️ Building external-tests\n" +echo "::group::build external-tests" -# TODO will update here to upload given merge to master -# Run the build script to collect and process the logs then upload them -# cd /opt/dyninst-env && \ -# perl /opt/testsuite/scripts/build/build.pl --hostname=ci-github --quiet --restart=build --no-run-tests --upload --auth-token=xxxxxxxxxxxxxxxxxxx +DYNINST_INSTALL_DIR=/opt/dyninst-env/install/dyninst + +TESTS_BUILD_DIR=/opt/dyninst-env/build/external-tests +mkdir -p $TESTS_BUILD_DIR + +TESTS_INSTALL_DIR=/opt/dyninst-env/install/external-tests +mkdir -p $TESTS_INSTALL_DIR + +cmake -S /opt/external-tests -B $TESTS_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$TESTS_INSTALL_DIR -DDyninst_DIR=$DYNINST_INSTALL_DIR/lib/cmake/Dyninst +cmake --build $TESTS_BUILD_DIR +cmake --install $TESTS_BUILD_DIR + +echo "::endgroup::" From 8f8497e56108d6e7228756d317197a4dda8819c5 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 4 Apr 2022 11:15:00 -0500 Subject: [PATCH 099/505] Docker: make compile warnings fatal (#1242) --- docker/build.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docker/build.sh b/docker/build.sh index 58dd67a23e..804aa60215 100644 --- a/docker/build.sh +++ b/docker/build.sh @@ -15,7 +15,8 @@ mkdir -p $DYNINST_BUILD_DIR DYNINST_INSTALL_DIR=/opt/dyninst-env/install/dyninst mkdir -p $DYNINST_INSTALL_DIR -cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR +CMAKE_WERROR_FLAGS='-DCMAKE_C_FLAGS="-Werror" -DCMAKE_CXX_FLAGS="-Werror"' +cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR $CMAKE_WERROR_FLAGS cmake --build $DYNINST_BUILD_DIR -- -j2 cmake --install $DYNINST_BUILD_DIR From 74320b0184de52f91dbf6c1dba2d0f54aa2475c6 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 4 Apr 2022 13:05:59 -0500 Subject: [PATCH 100/505] Remove unused git files (#1244) .gitmodules hasn't been used since the test suite was moved to its own repository. .github_changelog_generate hasn't been used since v10.0.0 --- .github_changelog_generator | 3 --- .gitmodules | 3 --- 2 files changed, 6 deletions(-) delete mode 100644 .github_changelog_generator delete mode 100644 .gitmodules diff --git a/.github_changelog_generator b/.github_changelog_generator deleted file mode 100644 index 913f54fa8f..0000000000 --- a/.github_changelog_generator +++ /dev/null @@ -1,3 +0,0 @@ -unreleased=true -future-release=10.1.0 -since-tag=10.0.0 diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index d6a81b84ba..0000000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "testsuite"] - path = testsuite - url = https://github.com/dyninst/testsuite From 0d9b8e4c5ba6dfa5d5666956aca4404d49f2160a Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 29 Mar 2022 22:51:18 -0500 Subject: [PATCH 101/505] Improve compiler diagnostic suppression handling (#1239) - Create compiler specific diagnostic suppression macros to suppress a type of warning for a region of code that are consistently defined based on the build environment. - Replace current multi-line preprocessor #if and #pragma statements with one macro. - Add suppression for warnings in instructionAPI/src/Register.C when using gcc 6-8. --- common/h/compiler_diagnostics.h | 146 ++++++++++++++++++++++++++++++++ dyninstAPI/src/inst-x86.C | 36 +++----- dyninstAPI_RT/h/dyninstAPI_RT.h | 19 ++--- instructionAPI/src/Register.C | 9 ++ 4 files changed, 176 insertions(+), 34 deletions(-) create mode 100644 common/h/compiler_diagnostics.h diff --git a/common/h/compiler_diagnostics.h b/common/h/compiler_diagnostics.h new file mode 100644 index 0000000000..0bafeb4f64 --- /dev/null +++ b/common/h/compiler_diagnostics.h @@ -0,0 +1,146 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef COMPILER_DIAGNOSTICS_H +#define COMPILER_DIAGNOSTICS_H + +// This file defines macros to suppress compiler diagnostics for a region of +// code. They are used to suppress diagnostic that are due to 1) non-standard +// code and 2) the compiler produced false positives. They expand to nothing +// if not applicable with the current compiler. +// +// The macros to begin and end the region take the form: +// +// DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_ +// DYNINST_DIAGNOSTIC_END_SUPPRESS_ +// +// They should be place on a lines of their own without trailing '()' or ';'. +// +// Currently defined value for are +// +// FLEX_ARRAY +// warning about C flexible arrays in C++ +// LOGICAL_OP +// warning about duplicate subexpressions in a logical expression +// Is a false positive due compiler checks after macro/constant +// propagation (eg. (x == a && x == b) if a and b are distinct +// constants with the same physical value. Only gcc 6-8. +// DUPLICATED_BRANCHES +// similar to LOGICAL_OP except the expressions are the +// conditionals of a chain of if/then/else's. Only gcc 7-8. +// +// Define DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS to prevents suppressions. + + +// Define compiler specific suppression codes, an undefined value represents no +// suppression required. Suppression code macro names have the form +// +// DYNINST_SUPPRESS_CODE_ +// +#if defined(__GNUC__) && !defined(__clang__) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY "-Wpedantic" + #if __GNUC__ < 9 + #define DYNINST_SUPPRESS_CODE_LOGICAL_OP "-Wlogical-op" + #endif + #if __GNUC__ >= 7 && __GNUC__ < 9 + #define DYNINST_SUPPRESS_CODE_DUPLICATED_BRANCHES "-Wduplicated-branches" + #endif +#elif defined(__clang__) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY "-Wpedantic" +#elif defined(_MSC_VER) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY 4200 +#endif + +// Define DYNISNT_DIAGNOSTIC_BEGIN/END macros, expands to nothing if code undefined +#ifdef DYNINST_SUPPRESS_CODE_FLEX_ARRAY + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(FLEX_ARRAY) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY +#endif + +#ifdef DYNINST_SUPPRESS_CODE_LOGICAL_OP + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(LOGICAL_OP) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP +#endif + +#ifdef DYNINST_SUPPRESS_CODE_DUPLICATED_BRANCHES + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(DUPLICATED_BRANCHES) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES +#endif + + +// Create pragma from parameters +#define DYNINST_Pragma(x) _Pragma(#x) + +// Create compiler specific macros +// +// DYNINST_DIAGNOSTIC_Pragma(x) - diagnostic pragma for x which is unquoted +// DYNINST_DIAGNOSTIC_SUPPRESS(x) - diagnostic pragma to suppress warning x: +// quoted string (gcc), number (MSVC) + +#ifndef DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS + #if defined(__GNUC__) + #define DYNINST_DIAGNOSTIC_Pragma(x) DYNINST_Pragma(GCC diagnostic x) + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) DYNINST_DIAGNOSTIC_Pragma(ignored x) + #elif defined(_MSC_VER) + #define DYNINST_DIAGNOSTIC_Pragma(x) DYNINST_Pragma(warning(x)) + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) DYNINST_DIAGNOSTIC_Pragma(disable:x) + #endif +#endif + +// if not defined, expand to nothing +#ifndef DYNINST_DIAGNOSTIC_Pragma + #define DYNINST_DIAGNOSTIC_Pragma(x) +#endif +#ifndef DYNINST_DIAGNOSTIC_SUPPRESS + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) +#endif + +// Define macros in terms of compiler specific macros +// +// DYNINST_DIAGNOSTIC_POP - pop stack of pushed diagnostic state +// DYNINST_DIAGNOSTIC_PUSH - push current diagnostic state on stack +// DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(x) - push diagnostic state and add suppression x + +#define DYNINST_DIAGNOSTIC_POP DYNINST_DIAGNOSTIC_Pragma(pop) +#define DYNINST_DIAGNOSTIC_PUSH DYNINST_DIAGNOSTIC_Pragma(push) +#define DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(x) DYNINST_DIAGNOSTIC_PUSH \ + DYNINST_DIAGNOSTIC_SUPPRESS(x) +#define DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(x) DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(DYNINST_SUPPRESS_CODE_##x) + +#endif /* COMPILER_DIAGNOSTICS_H */ diff --git a/dyninstAPI/src/inst-x86.C b/dyninstAPI/src/inst-x86.C index ead580f940..1ccda1aa98 100644 --- a/dyninstAPI/src/inst-x86.C +++ b/dyninstAPI/src/inst-x86.C @@ -37,6 +37,7 @@ #include #include "common/src/headers.h" #include "compiler_annotations.h" +#include "compiler_diagnostics.h" #include #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" @@ -1532,19 +1533,15 @@ stackItemLocation getHeightOf(stackItem sitem, codeGen &gen) RealRegister reg; int addr_width = gen.addrSpace()->getAddressWidth(); -#if defined(__GNUC__) - #pragma GCC diagnostic push - #if __GNUC__ >= 7 - // disable warning as the registers numbers are identical for 32-bit - // and 64-bit but use semantically distinct names - #pragma GCC diagnostic ignored "-Wduplicated-branches" - #endif -#endif + + // Suppress warning (for compilers where it is a false positive) + // The value of REGNUM_EBP and REGNUM_RBP are identical + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + RealRegister plat_bp(addr_width == 4 ? REGNUM_EBP : REGNUM_RBP); RealRegister plat_sp(addr_width == 4 ? REGNUM_ESP : REGNUM_RSP); -#if defined(__GNUC__) - #pragma GCC diagnostic pop -#endif + + DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES if (sitem.item == stackItem::reg_item && sitem.reg.reg() == plat_sp.reg()) { @@ -2382,18 +2379,13 @@ Emitter *AddressSpace::getEmitter() #if defined(arch_x86_64) int registerSpace::framePointer() { -#if defined(__GNUC__) - #pragma GCC diagnostic push - #if __GNUC__ >= 7 - // disable warning as the registers numbers are identical for 32-bit - // and 64-bit but use semantically distinct names - #pragma GCC diagnostic ignored "-Wduplicated-branches" - #endif -#endif + // Suppress warning (for compilers where it is a false positive) + // The value of REGNUM_EBP and REGNUM_RBP are identical + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + return addr_width == 8 ? REGNUM_RBP : REGNUM_EBP; -#if defined(__GNUC__) - #pragma GCC diagnostic pop -#endif + + DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES } #elif defined(arch_x86) int registerSpace::framePointer() { diff --git a/dyninstAPI_RT/h/dyninstAPI_RT.h b/dyninstAPI_RT/h/dyninstAPI_RT.h index f5f8cda93e..0229ad5321 100644 --- a/dyninstAPI_RT/h/dyninstAPI_RT.h +++ b/dyninstAPI_RT/h/dyninstAPI_RT.h @@ -56,6 +56,7 @@ #include #include "dyninstRTExport.h" #include "common/src/Types.h" +#include "common/h/compiler_diagnostics.h" /* If we must make up a boolean type, we should make it unique */ typedef unsigned char RT_Boolean; @@ -166,15 +167,10 @@ typedef struct { #define TRAP_HEADER_SIG 0x759191D6 #define DT_DYNINST 0x6D191957 -#if defined(_MSC_VER) -#pragma warning(disable:4200) -#endif -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -// Disable warning about flexible array members in C++ -// FIXME: Flexible array member, traps[], in structure below -#endif +// Suppress warning about flexible array members not valid in C++ +// FIXME: invalid flexible array member, traps[], in structure below +DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY + struct trap_mapping_header { uint32_t signature; uint32_t num_entries; @@ -184,9 +180,8 @@ struct trap_mapping_header { uint64_t high_entry; trapMapping_t traps[]; //Don't change this to a pointer, despite any compiler warnings }; -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif + +DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY #define MAX_MEMORY_MAPPER_ELEMENTS 1024 diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index beaea43b0a..f70ebcf9c7 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -38,6 +38,7 @@ #include "InstructionDecoder-power.h" #include "dyn_regs.h" #include "ArchSpecificFormatters.h" +#include "../../common/h/compiler_diagnostics.h" using namespace std; @@ -110,6 +111,12 @@ namespace Dyninst uint32_t id = m_Reg & 0xff ; uint32_t regClass = m_Reg.regClass(); uint32_t size = (m_High - m_Low ) / 32; + + // Suppress warning (for compilers where it is a false positive) + // The values of the two *::SGPR constants are identical, as + // are the two *::VGPR constants + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + if( regClass == amdgpu_cdna2::SGPR || regClass == amdgpu_vega::SGPR){ return "S["+to_string(id) + ":" + to_string(id+size-1)+"]"; } @@ -118,6 +125,8 @@ namespace Dyninst return "V["+to_string(id) + ":" + to_string(id+size-1)+"]"; } + DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP + if(regClass == amdgpu_cdna2::ACC_VGPR){ return "ACC["+to_string(id) + ":" + to_string(id+size-1)+"]"; } From c004b33915051bd1eed99edc81b49956dc8a1f8c Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 29 Mar 2022 22:53:24 -0500 Subject: [PATCH 102/505] Remove MSC compiler warning suppressions (#1239) Likely no longer needed with current MSC compiler and will hide problems if MSC is used. - Removed diagnostic suppressing pragmas - Removed compiler command line suppression options --- cmake/warnings.cmake | 2 -- common/h/Annotatable.h | 6 ------ common/h/Graph.h | 3 --- common/h/Node.h | 3 --- common/h/util.h | 4 ---- common/src/arch-x86.h | 5 ----- common/src/debug_common.C | 10 ---------- common/src/ntHeaders.h | 2 -- dataflowAPI/src/debug_dataflow.C | 8 -------- dyninstAPI/h/BPatch.h | 8 -------- dyninstAPI/h/BPatch_dll.h | 12 ------------ dyninstAPI/h/BPatch_function.h | 9 --------- dyninstAPI/h/BPatch_image.h | 7 ------- dyninstAPI/h/BPatch_point.h | 9 --------- instructionAPI/h/BinaryFunction.h | 4 ---- instructionAPI/h/InstructionAST.h | 9 --------- instructionAPI/h/InstructionDecoder.h | 4 ---- parseAPI/src/debug_parse.C | 9 --------- proccontrol/src/handler.C | 4 ---- proccontrol/src/irpc.C | 4 ---- proccontrol/src/process.C | 4 ---- proccontrol/src/processplat.C | 4 ---- proccontrol/src/procset.C | 3 --- proccontrol/src/windows_process.h | 1 - proccontrol/src/x86_process.C | 4 ---- symtabAPI/src/debug.C | 10 ---------- 26 files changed, 148 deletions(-) diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index 6927782b16..e9e7c10e6a 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -132,8 +132,6 @@ unset(CMAKE_REQUIRED_FLAGS) if (MSVC) message(STATUS "TODO: Set up custom warning flags for MSVC") - string(APPEND CMAKE_C_FLAGS "/wd4251 /wd4091 /wd4503") - string(APPEND CMAKE_CXX_FLAGS "/wd4251 /wd4091 /wd4503") endif() message(STATUS "Using C warning flags: ${SUPPORTED_C_WARNING_FLAGS}") diff --git a/common/h/Annotatable.h b/common/h/Annotatable.h index 1f4f4b9d36..8d3d5a111f 100644 --- a/common/h/Annotatable.h +++ b/common/h/Annotatable.h @@ -351,8 +351,6 @@ class COMMON_EXPORT AnnotatableSparse #if defined (_MSC_VER) typedef dyn_hash_map annos_by_type_t; -#pragma warning (push) -#pragma warning (disable:4251) #else typedef dyn_hash_map annos_by_type_t; #endif @@ -748,8 +746,4 @@ class COMMON_EXPORT AnnotatableSparse } // namespace -#ifdef _MSC_VER -#pragma warning(pop) -#endif - #endif diff --git a/common/h/Graph.h b/common/h/Graph.h index d6c94c5a79..815a726b8c 100644 --- a/common/h/Graph.h +++ b/common/h/Graph.h @@ -46,9 +46,6 @@ #include "Annotatable.h" #include "Node.h" -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif namespace Dyninst { class Edge; diff --git a/common/h/Node.h b/common/h/Node.h index 6b0dbb595c..f2ceb9c0e5 100644 --- a/common/h/Node.h +++ b/common/h/Node.h @@ -39,9 +39,6 @@ #include "dyntypes.h" #include "boost/shared_ptr.hpp" -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif class BPatch_function; class BPatch_basicBlock; diff --git a/common/h/util.h b/common/h/util.h index eb0a1dc912..a76885e0a3 100644 --- a/common/h/util.h +++ b/common/h/util.h @@ -204,10 +204,6 @@ #include #include "dyntypes.h" -#if defined(_MSC_VER) -#pragma warning(disable: 4251 4275 4396 4996) -#endif - namespace Dyninst { diff --git a/common/src/arch-x86.h b/common/src/arch-x86.h index 21a168dd7d..e78f0844aa 100644 --- a/common/src/arch-x86.h +++ b/common/src/arch-x86.h @@ -44,11 +44,6 @@ #include "common/src/ia32_locations.h" -#if defined(i386_unknown_nt4_0) -// disable VC++ warning C4800: (performance warning) -// forcing 'unsigned int' value to bool 'true' or 'false' -#pragma warning (disable : 4800) -#endif namespace NS_x86 { diff --git a/common/src/debug_common.C b/common/src/debug_common.C index ee5b69e800..b2bbed4b47 100644 --- a/common/src/debug_common.C +++ b/common/src/debug_common.C @@ -40,11 +40,6 @@ int common_debug_lineinfo = 0; int common_debug_parsing = 0; int common_debug_initialized = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - bool init_debug_common() { if (common_debug_initialized) return true; common_debug_initialized = 1; @@ -125,8 +120,3 @@ int common_parsing_printf_int(const char *format, ...) return ret; } - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - diff --git a/common/src/ntHeaders.h b/common/src/ntHeaders.h index 55e0228bcc..4bcd626875 100644 --- a/common/src/ntHeaders.h +++ b/common/src/ntHeaders.h @@ -34,8 +34,6 @@ #if !defined(pd_nt_headers_h) #define pd_nt_headers_h -#pragma warning( disable : 4996 ) - #include #include diff --git a/dataflowAPI/src/debug_dataflow.C b/dataflowAPI/src/debug_dataflow.C index 35a17b4c80..dbfd47f143 100644 --- a/dataflowAPI/src/debug_dataflow.C +++ b/dataflowAPI/src/debug_dataflow.C @@ -57,10 +57,6 @@ static int check_debug_flag(int &flag) { static std::once_flag initialized; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif std::call_once(initialized, []() { @@ -91,10 +87,6 @@ static int check_debug_flag(int &flag) }); -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - return flag; } diff --git a/dyninstAPI/h/BPatch.h b/dyninstAPI/h/BPatch.h index afceef77fd..acbadb34f2 100644 --- a/dyninstAPI/h/BPatch.h +++ b/dyninstAPI/h/BPatch.h @@ -73,10 +73,6 @@ class func_instance; #define DYNINST_MINOR DYNINST_MINOR_VERSION #define DYNINST_SUBMINOR DYNINST_PATCH_VERSION -#ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4251) -#endif // BPatch_stats is a collection of instrumentation statistics. // Introduced to export this information to paradyn, which @@ -679,9 +675,5 @@ class BPATCH_DLL_EXPORT BPatch { void addNonReturningFunc(std::string name); }; -#ifdef _MSC_VER -#pragma warning(pop) -#endif - #endif /* _BPatch_h_ */ diff --git a/dyninstAPI/h/BPatch_dll.h b/dyninstAPI/h/BPatch_dll.h index 1621c7d7ff..0c350567d0 100644 --- a/dyninstAPI/h/BPatch_dll.h +++ b/dyninstAPI/h/BPatch_dll.h @@ -28,10 +28,6 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif - #ifndef _BPatch_dll_h_ #define _BPatch_dll_h_ @@ -44,14 +40,6 @@ #define BPATCH_DLL_EXPORT #else #if defined(_MSC_VER) -// we get numerous spurious warnings about having some template classes -// needing to have a dll-interface if instances of these classes are -// to be used by classes whose public interfaces are exported from a DLL. -// Specifing the template classes with a DLL export interface doesn't -// satisfy the compiler. Until the compiler handles instantiated -// templates exported from DLLs better, we disable the warning when building -// or using the dyninstAPI DLL. -#pragma warning(disable:4251) #ifdef BPATCH_DLL_BUILD // we are building the dyninstAPI DLL diff --git a/dyninstAPI/h/BPatch_function.h b/dyninstAPI/h/BPatch_function.h index dccfd47070..5ec5cb2e32 100644 --- a/dyninstAPI/h/BPatch_function.h +++ b/dyninstAPI/h/BPatch_function.h @@ -102,17 +102,8 @@ class BPATCH_DLL_EXPORT BPatch_function : void identifyParamDependencies(BPatch_function* callee, void* calleeAddress); -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif - // Disable warning that these vectors cannot be used externally, - // which is irrelevant since the vectors are private std::map local_vars; BPatch_Vector params; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif public: //dynC internal use only diff --git a/dyninstAPI/h/BPatch_image.h b/dyninstAPI/h/BPatch_image.h index e1aaca42a7..15b2a7bbd6 100644 --- a/dyninstAPI/h/BPatch_image.h +++ b/dyninstAPI/h/BPatch_image.h @@ -300,10 +300,6 @@ class BPATCH_DLL_EXPORT BPatch_image: public BPatch_sourceObj { void removeObject(BPatch_object *obj); void removeAllModules(); -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif typedef std::map ModMap; typedef std::map ObjMap; @@ -315,9 +311,6 @@ class BPATCH_DLL_EXPORT BPatch_image: public BPatch_sourceObj { BPatch_Vector removed_list; BPatch_Vector unresolvedCF; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif // These private "find" functions convert from internal func_instance // representation to the exported BPatch_Function type diff --git a/dyninstAPI/h/BPatch_point.h b/dyninstAPI/h/BPatch_point.h index 70075720d4..db63f68e13 100644 --- a/dyninstAPI/h/BPatch_point.h +++ b/dyninstAPI/h/BPatch_point.h @@ -147,18 +147,9 @@ class BPATCH_DLL_EXPORT BPatch_point { AddressSpace *getAS(); private: -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif - // Disable warning that these vectors cannot be used externally, - // which is irrelevant since the vectors are private BPatch_Vector preSnippets; BPatch_Vector postSnippets; BPatch_Vector allSnippets; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif public: //~BPatch_point() { delete memacc; }; diff --git a/instructionAPI/h/BinaryFunction.h b/instructionAPI/h/BinaryFunction.h index 34fdaa42c2..e3a217af1d 100644 --- a/instructionAPI/h/BinaryFunction.h +++ b/instructionAPI/h/BinaryFunction.h @@ -37,10 +37,6 @@ #include "ArchSpecificFormatters.h" #include -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif - namespace Dyninst { namespace InstructionAPI diff --git a/instructionAPI/h/InstructionAST.h b/instructionAPI/h/InstructionAST.h index 93a7b63b05..206e8b8a26 100644 --- a/instructionAPI/h/InstructionAST.h +++ b/instructionAPI/h/InstructionAST.h @@ -31,12 +31,6 @@ #if !defined(INSTRUCTIONAST_H) #define INSTRUCTIONAST_H -#if defined(_MSC_VER) -// Exported class inheriting from non-exported class. This is by design; don't -// use the shared_from_this externally! -#pragma warning(push) -#pragma warning(disable:4251) -#endif #include "util.h" #include @@ -126,9 +120,6 @@ namespace Dyninst }; } } -#if defined(_MSC_VER) -#pragma warning(pop) -#endif #endif //!defined(INSTRUCTIONAST_H) diff --git a/instructionAPI/h/InstructionDecoder.h b/instructionAPI/h/InstructionDecoder.h index 7dc4b93bd4..d3d125296a 100644 --- a/instructionAPI/h/InstructionDecoder.h +++ b/instructionAPI/h/InstructionDecoder.h @@ -33,10 +33,6 @@ #include "Instruction.h" -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif - namespace Dyninst { namespace InstructionAPI diff --git a/parseAPI/src/debug_parse.C b/parseAPI/src/debug_parse.C index 498dc5f5e5..eea6b94019 100644 --- a/parseAPI/src/debug_parse.C +++ b/parseAPI/src/debug_parse.C @@ -40,11 +40,6 @@ int Dyninst::ParseAPI::dyn_debug_malware = 0; int Dyninst::ParseAPI::dyn_debug_indirect_collect = 0; int Dyninst::ParseAPI::dyn_debug_initialized = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - #if defined(_OPENMP) #include #endif @@ -139,7 +134,3 @@ const std::string PARSE_TAILCALL_FAIL("isTailcallFail"); const std::string PARSE_TOTAL_TIME("parseTotalTime"); const std::string PARSE_JUMPTABLE_TIME("parseJumpTableTime"); - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif diff --git a/proccontrol/src/handler.C b/proccontrol/src/handler.C index 9f7d667057..c7efb1d64b 100644 --- a/proccontrol/src/handler.C +++ b/proccontrol/src/handler.C @@ -53,10 +53,6 @@ using namespace std; #include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - Handler::Handler(std::string name_) : name(name_) { diff --git a/proccontrol/src/irpc.C b/proccontrol/src/irpc.C index 8be07974a2..cb40eeb65c 100644 --- a/proccontrol/src/irpc.C +++ b/proccontrol/src/irpc.C @@ -48,10 +48,6 @@ #include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - using namespace std; unsigned long int_iRPC::next_id; diff --git a/proccontrol/src/process.C b/proccontrol/src/process.C index 1fb3da15ee..8b68f265ea 100644 --- a/proccontrol/src/process.C +++ b/proccontrol/src/process.C @@ -59,10 +59,6 @@ #include #include -#if defined(os_windows) -#pragma warning(disable:4355 4477) -#endif - using namespace Dyninst; using namespace ProcControlAPI; using namespace std; diff --git a/proccontrol/src/processplat.C b/proccontrol/src/processplat.C index fd411ce9da..a8f7895038 100644 --- a/proccontrol/src/processplat.C +++ b/proccontrol/src/processplat.C @@ -35,10 +35,6 @@ #include "processplat.h" #include "int_event.h" -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - using namespace Dyninst; using namespace ProcControlAPI; using namespace std; diff --git a/proccontrol/src/procset.C b/proccontrol/src/procset.C index b4b1b353d2..9e5f0c3a81 100644 --- a/proccontrol/src/procset.C +++ b/proccontrol/src/procset.C @@ -52,9 +52,6 @@ #include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif using namespace Dyninst; using namespace ProcControlAPI; diff --git a/proccontrol/src/windows_process.h b/proccontrol/src/windows_process.h index 6a46144415..d815cffd67 100644 --- a/proccontrol/src/windows_process.h +++ b/proccontrol/src/windows_process.h @@ -36,7 +36,6 @@ class windows_thread; -#pragma warning (disable: 4250) class windows_process : virtual public x86_process, virtual public hybrid_lwp_control_process { public: diff --git a/proccontrol/src/x86_process.C b/proccontrol/src/x86_process.C index bcf4a73e3e..ac0d162c63 100644 --- a/proccontrol/src/x86_process.C +++ b/proccontrol/src/x86_process.C @@ -32,10 +32,6 @@ #include "int_event.h" #include "Event.h" -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - x86_process::x86_process(Dyninst::PID p, std::string e, std::vector a, std::vector envp, std::map f) : int_process(p, e, a, envp, f) { diff --git a/symtabAPI/src/debug.C b/symtabAPI/src/debug.C index 98e9a0bff9..376b9b5f4d 100644 --- a/symtabAPI/src/debug.C +++ b/symtabAPI/src/debug.C @@ -42,11 +42,6 @@ int sym_debug_types = 0; int sym_debug_translate = 0; int sym_debug_rewrite = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - bool init_debug_symtabAPI() { static bool initialized = false; if (initialized) return true; @@ -154,8 +149,3 @@ int rewrite_printf(const char *format, ...) return ret; } - - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif From 59f82f2ba4c3ba2c2416e461fc45b1e8b5f48b58 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Tue, 22 Mar 2022 23:20:05 -0500 Subject: [PATCH 103/505] Fix frame-larger-than warning (#1239) - Increase frame size max when using gcc 6 for non-debug builds and for all debug builds (needed for rhel's gcc) to compile instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C --- cmake/warnings.cmake | 11 +++++++++-- instructionAPI/CMakeLists.txt | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index e9e7c10e6a..0776612248 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -103,10 +103,12 @@ if (CMAKE_CXX_COMPILER_ID MATCHES "^(GNU|Clang)$") endif() # If -Wframe-larger-than is available adjust the value to allow for larger -# frames based on compiler version and build type for the following two files: +# frames based on compiler version and build type for the following 3 files: # # instructionAPI/src/InstructionDecoder-power.C -# (includes instructionAPI/src/InstructionDecoder-power.C) +# (includes instructionAPI/src/power-opcode-table.C) +# instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +# (includes instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C) # common/src/MachSyscall.C # (includes common/src/SyscallInformation.C) # @@ -126,6 +128,11 @@ if (HAS_CPP_FLAG_Wframe_larger_than) if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[7](\.|$)") set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38912) endif() + # most gcc's are under the default using -Og, but rhel's requires 30000 + set(debugMaxFrameSizeOverrideFinalizeOperands 30000) + if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[6](\.|$)") + set(nonDebugMaxFrameSizeOverrideFinalizeOperands 30000) + endif() endif() unset(CMAKE_REQUIRED_FLAGS) diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index baf647eb03..f780902f1f 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -58,6 +58,21 @@ if (NOT instructionDecoderPowerExtraFlags STREQUAL "") PROPERTIES COMPILE_FLAGS "${instructionDecoderPowerExtraFlags}") endif() +set(finalizeOperandsExtraFlags "") +if (debugMaxFrameSizeOverrideFinalizeOperands) + string(APPEND finalizeOperandsExtraFlags + " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideFinalizeOperands}>") +endif() +if (nonDebugMaxFrameSizeOverrideFinalizeOperands) + string(APPEND finalizeOperandsExtraFlags + " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideFinalizeOperands}>") +endif() + +if (NOT finalizeOperandsExtraFlags STREQUAL "") + SET_SOURCE_FILES_PROPERTIES(src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") +endif() + ADD_DEFINITIONS(-DINSTRUCTION_LIB) dyninst_library(instructionAPI common) From d333a836c48a02afb31de58b9068f1f844a88244 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Thu, 31 Mar 2022 13:58:27 -0500 Subject: [PATCH 104/505] Add cmake option to disable diagnostic suppressions (#1239) - DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS option: if set, disable all warning suppressions and frame size limit overrides --- CMakeLists.txt | 25 +++++++++++++------------ cmake/warnings.cmake | 15 ++++++++++++++- 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index eacbb0b793..66c65c6a76 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -116,18 +116,19 @@ endif() execute_process(WORKING_DIRECTORY ${RT_BINARY_DIR} COMMAND ${CMAKE_COMMAND} - -DCMAKE_C_COMPILER=${RT_C_COMPILER} - -DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE} - -DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX} - -DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH} - -DINSTALL_LIB_DIR=${INSTALL_LIB_DIR} - -DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR} - -DCMAKE_C_FLAGS=${CMAKE_C_FLAGS} - -DBUILD_RTLIB_32=${BUILD_RTLIB_32} - -DPLATFORM=${PLATFORM} - -G ${CMAKE_GENERATOR} - -B ${RT_BINARY_DIR} - -S ${RT_SOURCE_DIR}) + "-DCMAKE_C_COMPILER=${RT_C_COMPILER}" + "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}" + "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}" + "-DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH}" + "-DINSTALL_LIB_DIR=${INSTALL_LIB_DIR}" + "-DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR}" + "-DCMAKE_C_FLAGS=${CMAKE_C_FLAGS}" + "-DBUILD_RTLIB_32=${BUILD_RTLIB_32}" + "-DPLATFORM=${PLATFORM}" + "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" + -G "${CMAKE_GENERATOR}" + -B "${RT_BINARY_DIR}" + -S "${RT_SOURCE_DIR}") find_file(${RT_MAKEFILE} Makefile PATHS ${RT_BINARY_DIR} NO_DEFAULT_PATH) message(STATUS "RTlib Makefile: ${RT_MAKEFILE}") if(MSVC) diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index 0776612248..a940b0ace3 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -1,3 +1,16 @@ +# +# cmake warning options +# + +option(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS "Disable all warning suppressions and frame size overrides." OFF) + + +if (DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + add_definitions(-DDYNINST_DIAGNOSTIC_NO_SUPPRESSIONS) + message(STATUS "DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS set: disabling all dyninst warning suppressions and frame size overrides") +endif() + + # Frame sizes are larger for debug build, so adjust based on build type # files with functions containing large frames are adjust below # (the value could be made significantly maller if more files are adjusted). @@ -112,7 +125,7 @@ endif() # common/src/MachSyscall.C # (includes common/src/SyscallInformation.C) # -if (HAS_CPP_FLAG_Wframe_larger_than) +if (HAS_CPP_FLAG_Wframe_larger_than AND NOT DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) # Override the default frame size maximum for DEBUG (-O0) build types # as there stack frames are larger: # From 2a16fb4a46579e5b83a4289e7ecea0559400b70e Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Mon, 4 Apr 2022 09:43:15 -0500 Subject: [PATCH 105/505] Add compiler warning related cmake options (#1239) - DYNINST_WARNINGS_AS_ERRORS option: if set, treat warnings as errors - DYNINST_EXTRA_WARNINGS option: additional warning options to test for and use if valid with the current compiler --- CMakeLists.txt | 2 ++ cmake/warnings.cmake | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 66c65c6a76..e184bdb5f2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -126,6 +126,8 @@ endif() "-DBUILD_RTLIB_32=${BUILD_RTLIB_32}" "-DPLATFORM=${PLATFORM}" "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" + "-DDYNINST_EXTRA_WARNINGS=${DYNINST_EXTRA_WARNINGS}" + "-DDYNINST_WARNINGS_AS_ERRORS=${DYNINST_WARNINGS_AS_ERRORS}" -G "${CMAKE_GENERATOR}" -B "${RT_BINARY_DIR}" -S "${RT_SOURCE_DIR}") diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index a940b0ace3..f9f5c7f827 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -4,6 +4,10 @@ option(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS "Disable all warning suppressions and frame size overrides." OFF) +set(DYNINST_EXTRA_WARNINGS "" CACHE STRING "Additional warning options to enable if available. ;-separated without leading '-' (Wopt1[;Wopt2]...).") + +option(DYNINST_WARNINGS_AS_ERRORS "Treat compilation warnings as errors" OFF) + if (DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) add_definitions(-DDYNINST_DIAGNOSTIC_NO_SUPPRESSIONS) @@ -79,6 +83,16 @@ list(APPEND REQUESTED_WARNING_FLAGS #list(APPEND REQUESTED_WARNING_FLAGS Wold-style-cast) #list(APPEND REQUESTED_WARNING_FLAGS Walloc-zero) +if (DYNINST_EXTRA_WARNINGS) + list(APPEND REQUESTED_WARNING_FLAGS ${DYNINST_EXTRA_WARNINGS}) + message(STATUS "DYNINST_EXTRA_WARNINGS set, adding extra warnings: ${DYNINST_EXTRA_WARNINGS}") +endif() + +if (DYNINST_WARNINGS_AS_ERRORS) + list(APPEND REQUESTED_WARNING_FLAGS "Werror") + message(STATUS "DYNINST_WARNINGS_AS_ERRORS set: treating warnings as errors") +endif() + if (CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") include(CheckCCompilerFlag) foreach (f IN LISTS REQUESTED_WARNING_FLAGS) From d0e2f3e2b02c3e61a9dd5457bbb618417469ade6 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Thu, 31 Mar 2022 09:02:15 -0500 Subject: [PATCH 106/505] Remove unneeded #pragma's (#1240) - Remove once and interface pragmas - Replace use of "external/stdint-win.h" and "external/inttypes.h" with and --- common/src/Pair.h | 4 ---- dataflowAPI/rose/SgAsmExpression.h | 9 --------- dataflowAPI/rose/semanticsModule.h | 6 ------ dataflowAPI/rose/typedefs.h | 4 ---- dataflowAPI/rose/util/StringUtility.h | 4 ---- dataflowAPI/src/ExpressionConversionVisitor.h | 5 ----- dataflowAPI/src/RoseInsnFactory.h | 6 ------ dataflowAPI/src/SymEvalPolicy.h | 4 ---- dyninstAPI/h/BPatch_Set.h | 4 ---- proccontrol/src/procset.C | 4 ---- 10 files changed, 50 deletions(-) diff --git a/common/src/Pair.h b/common/src/Pair.h index 4e02316d7f..891196eff2 100644 --- a/common/src/Pair.h +++ b/common/src/Pair.h @@ -32,10 +32,6 @@ * Pair.h: definition of pairs for dictionaries and sets. ************************************************************************/ -#if defined(external_templates) -#pragma interface -#endif - #if !defined(_Pair_h_) #define _Pair_h_ diff --git a/dataflowAPI/rose/SgAsmExpression.h b/dataflowAPI/rose/SgAsmExpression.h index f52d2dd6d6..98a4933c6e 100644 --- a/dataflowAPI/rose/SgAsmExpression.h +++ b/dataflowAPI/rose/SgAsmExpression.h @@ -7,17 +7,8 @@ #include "SgAsmType.h" #include "external/rose/powerpcInstructionEnum.h" - -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#else - -#include #include -#endif - class SgAsmExpression : public SgAsmNode { public: diff --git a/dataflowAPI/rose/semanticsModule.h b/dataflowAPI/rose/semanticsModule.h index 93bd7497a8..d31fcdaffb 100644 --- a/dataflowAPI/rose/semanticsModule.h +++ b/dataflowAPI/rose/semanticsModule.h @@ -4,13 +4,7 @@ #include "SgAsmType.h" //#include "rose.h" -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#else -#include #include -#endif #ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS diff --git a/dataflowAPI/rose/typedefs.h b/dataflowAPI/rose/typedefs.h index 65ecf0fe57..b56ad5799e 100644 --- a/dataflowAPI/rose/typedefs.h +++ b/dataflowAPI/rose/typedefs.h @@ -2,11 +2,7 @@ #define ROSE_TYPEDEFS_H #include -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif typedef std::vector SgUnsignedCharList; diff --git a/dataflowAPI/rose/util/StringUtility.h b/dataflowAPI/rose/util/StringUtility.h index 23e81ddd57..0d9b75153c 100644 --- a/dataflowAPI/rose/util/StringUtility.h +++ b/dataflowAPI/rose/util/StringUtility.h @@ -12,10 +12,6 @@ #include "../rose.h" -#if ROSE_MICROSOFT_OS -// This is the boost solution for lack of support for stdint.h (e.g. types such as "uint64_t") -#include "external/stdint-win.h" -#endif /** Functions for operating on strings. * diff --git a/dataflowAPI/src/ExpressionConversionVisitor.h b/dataflowAPI/src/ExpressionConversionVisitor.h index 6c24b2dcce..7a39b2a239 100644 --- a/dataflowAPI/src/ExpressionConversionVisitor.h +++ b/dataflowAPI/src/ExpressionConversionVisitor.h @@ -27,7 +27,6 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#pragma once #if !defined(_EXPRESSION_CONVERSION_VISITOR_H_) #define _EXPRESSION_CONVERSION_VISITOR_H_ @@ -46,11 +45,7 @@ class SgAsmPowerpcRegisterReferenceExpression; #include "external/rose/powerpcInstructionEnum.h" #include "Visitor.h" -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif #include diff --git a/dataflowAPI/src/RoseInsnFactory.h b/dataflowAPI/src/RoseInsnFactory.h index b3d671c720..c4c8ca3701 100644 --- a/dataflowAPI/src/RoseInsnFactory.h +++ b/dataflowAPI/src/RoseInsnFactory.h @@ -27,7 +27,6 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#pragma once #if !defined(_ROSE_INSN_FACTORY_H_) #define _ROSE_INSN_FACTORY_H_ @@ -43,13 +42,8 @@ #include "boost/shared_ptr.hpp" #include -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else - #include -#endif class SgAsmInstruction; diff --git a/dataflowAPI/src/SymEvalPolicy.h b/dataflowAPI/src/SymEvalPolicy.h index 06836aa007..47a8174571 100644 --- a/dataflowAPI/src/SymEvalPolicy.h +++ b/dataflowAPI/src/SymEvalPolicy.h @@ -60,11 +60,7 @@ #include #include -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif #include "../rose/SgAsmx86Instruction.h" diff --git a/dyninstAPI/h/BPatch_Set.h b/dyninstAPI/h/BPatch_Set.h index 8b36f68207..ae0ed2e198 100644 --- a/dyninstAPI/h/BPatch_Set.h +++ b/dyninstAPI/h/BPatch_Set.h @@ -31,10 +31,6 @@ #ifndef _BPatch_Set_h_ #define _BPatch_Set_h_ -#if defined(external_templates) -#pragma interface -#endif - /*******************************************************/ /* header files */ /*******************************************************/ diff --git a/proccontrol/src/procset.C b/proccontrol/src/procset.C index 9e5f0c3a81..773cce8c44 100644 --- a/proccontrol/src/procset.C +++ b/proccontrol/src/procset.C @@ -45,10 +45,6 @@ #include #include -#if defined(os_windows) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#endif #include #include From 3e830389ab6d753551b0daa9f94b676a5ab52ee8 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Thu, 31 Mar 2022 09:03:20 -0500 Subject: [PATCH 107/505] remove unused files containing pragmas (#1240) --- common/src/refCounter.h | 130 ----------------- external/inttypes-win.h | 311 ---------------------------------------- external/stdint-win.h | 245 ------------------------------- 3 files changed, 686 deletions(-) delete mode 100644 common/src/refCounter.h delete mode 100644 external/inttypes-win.h delete mode 100644 external/stdint-win.h diff --git a/common/src/refCounter.h b/common/src/refCounter.h deleted file mode 100644 index 51ebd90e80..0000000000 --- a/common/src/refCounter.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -// $Id: refCounter.h,v 1.7 2007/05/30 19:20:03 legendre Exp $ -// refCounter.h -// Ariel Tamches - -#ifndef _REF_COUNTER_H_ -#define _REF_COUNTER_H_ - -#ifdef external_templates -#pragma interface -#endif - -#include - -template -class refCounter { - private: - class actualData { - private: - mutable unsigned refCount; - T data; - public: - actualData(const T &src) : data(src) {refCount=0;} - ~actualData() {} - void reference() const {refCount++;} - bool dereference() const { - assert(refCount > 0); - return (--refCount == 0); - } - T &getData() {return data;} - const T &getData() const {return data;} - }; - actualData *theData; - // allocated with new, but not necessarily by us. _Never_ NULL. - - private: - void reference() const { - assert(theData); - theData->reference(); - } - void dereference() const { - assert(theData); - if (theData->dereference()) - delete theData; - } - - // explicitly disallowed - // (Visual C++ still requires a body, however) - refCounter() {} - - public: - refCounter(const T &src) { - // examples: - // T y; (y is initialized somehow...) - // refCounter x = y; or - // refCounter x(y); - theData = new actualData(src); - assert(theData); - reference(); - } - refCounter(const refCounter &src) { - // This constructor is what this whole class revolves around. It's fast. - // examples: - // refCounter y; (y is initialized somehow...) - // refCounter x = y; or - // refCounter x(y); - src.reference(); // just bumps up a ref count --> fast - theData = src.theData; // just a ptr assignment --> fast - } - ~refCounter() { - dereference(); - } - refCounter &operator=(const refCounter &src) { - if (this == &src) - return *this; // protect against x=x - - dereference(); - - // ...and attach to the new stuff efficiently - theData = src.theData; // just a ptr assignment --> fast - reference(); // just bumps a ref cnt --> fast - return *this; - } - refCounter &operator=(const T &src) { - dereference(); - theData = new actualData(src); - reference(); - return *this; - } - T &getData() { - assert(theData); - return theData->getData(); - } - const T &getData() const { - assert(theData); - return theData->getData(); - } -}; - -#endif diff --git a/external/inttypes-win.h b/external/inttypes-win.h deleted file mode 100644 index cd530cf719..0000000000 --- a/external/inttypes-win.h +++ /dev/null @@ -1,311 +0,0 @@ -// ISO C9x compliant inttypes.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -// Modern Visual Studio has sane inttypes.h -#if _MSC_VER >= 1900 -#include -#define _MSC_INTTYPES_H_ -#endif - -#ifndef _MSC_INTTYPES_H_ // [ -#define _MSC_INTTYPES_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include "stdint-win.h" - -// 7.8 Format conversion of integer types - -typedef struct { - intmax_t quot; - intmax_t rem; -} imaxdiv_t; - -// 7.8.1 Macros for format specifiers - -#if !defined(__cplusplus) || defined(__STDC_FORMAT_MACROS) // [ See footnote 185 at page 198 - -// The fprintf macros for signed integers are: -#define PRId8 "d" -#define PRIi8 "i" -#define PRIdLEAST8 "d" -#define PRIiLEAST8 "i" -#define PRIdFAST8 "d" -#define PRIiFAST8 "i" - -#define PRId16 "hd" -#define PRIi16 "hi" -#define PRIdLEAST16 "hd" -#define PRIiLEAST16 "hi" -#define PRIdFAST16 "hd" -#define PRIiFAST16 "hi" - -#define PRId32 "I32d" -#define PRIi32 "I32i" -#define PRIdLEAST32 "I32d" -#define PRIiLEAST32 "I32i" -#define PRIdFAST32 "I32d" -#define PRIiFAST32 "I32i" - -#define PRId64 "I64d" -#define PRIi64 "I64i" -#define PRIdLEAST64 "I64d" -#define PRIiLEAST64 "I64i" -#define PRIdFAST64 "I64d" -#define PRIiFAST64 "I64i" - -#define PRIdMAX "I64d" -#define PRIiMAX "I64i" - -#define PRIdPTR "Id" -#define PRIiPTR "Ii" - -// The fprintf macros for unsigned integers are: -#define PRIo8 "o" -#define PRIu8 "u" -#define PRIx8 "x" -#define PRIX8 "X" -#define PRIoLEAST8 "o" -#define PRIuLEAST8 "u" -#define PRIxLEAST8 "x" -#define PRIXLEAST8 "X" -#define PRIoFAST8 "o" -#define PRIuFAST8 "u" -#define PRIxFAST8 "x" -#define PRIXFAST8 "X" - -#define PRIo16 "ho" -#define PRIu16 "hu" -#define PRIx16 "hx" -#define PRIX16 "hX" -#define PRIoLEAST16 "ho" -#define PRIuLEAST16 "hu" -#define PRIxLEAST16 "hx" -#define PRIXLEAST16 "hX" -#define PRIoFAST16 "ho" -#define PRIuFAST16 "hu" -#define PRIxFAST16 "hx" -#define PRIXFAST16 "hX" - -#define PRIo32 "I32o" -#define PRIu32 "I32u" -#define PRIx32 "I32x" -#define PRIX32 "I32X" -#define PRIoLEAST32 "I32o" -#define PRIuLEAST32 "I32u" -#define PRIxLEAST32 "I32x" -#define PRIXLEAST32 "I32X" -#define PRIoFAST32 "I32o" -#define PRIuFAST32 "I32u" -#define PRIxFAST32 "I32x" -#define PRIXFAST32 "I32X" - -#define PRIo64 "I64o" -#define PRIu64 "I64u" -#define PRIx64 "I64x" -#define PRIX64 "I64X" -#define PRIoLEAST64 "I64o" -#define PRIuLEAST64 "I64u" -#define PRIxLEAST64 "I64x" -#define PRIXLEAST64 "I64X" -#define PRIoFAST64 "I64o" -#define PRIuFAST64 "I64u" -#define PRIxFAST64 "I64x" -#define PRIXFAST64 "I64X" - -#define PRIoMAX "I64o" -#define PRIuMAX "I64u" -#define PRIxMAX "I64x" -#define PRIXMAX "I64X" - -#define PRIoPTR "Io" -#define PRIuPTR "Iu" -#define PRIxPTR "Ix" -#define PRIXPTR "IX" - -// The fscanf macros for signed integers are: -#define SCNd8 "d" -#define SCNi8 "i" -#define SCNdLEAST8 "d" -#define SCNiLEAST8 "i" -#define SCNdFAST8 "d" -#define SCNiFAST8 "i" - -#define SCNd16 "hd" -#define SCNi16 "hi" -#define SCNdLEAST16 "hd" -#define SCNiLEAST16 "hi" -#define SCNdFAST16 "hd" -#define SCNiFAST16 "hi" - -#define SCNd32 "ld" -#define SCNi32 "li" -#define SCNdLEAST32 "ld" -#define SCNiLEAST32 "li" -#define SCNdFAST32 "ld" -#define SCNiFAST32 "li" - -#define SCNd64 "I64d" -#define SCNi64 "I64i" -#define SCNdLEAST64 "I64d" -#define SCNiLEAST64 "I64i" -#define SCNdFAST64 "I64d" -#define SCNiFAST64 "I64i" - -#define SCNdMAX "I64d" -#define SCNiMAX "I64i" - -#ifdef _WIN64 // [ -# define SCNdPTR "I64d" -# define SCNiPTR "I64i" -#else // _WIN64 ][ -# define SCNdPTR "ld" -# define SCNiPTR "li" -#endif // _WIN64 ] - -// The fscanf macros for unsigned integers are: -#define SCNo8 "o" -#define SCNu8 "u" -#define SCNx8 "x" -#define SCNX8 "X" -#define SCNoLEAST8 "o" -#define SCNuLEAST8 "u" -#define SCNxLEAST8 "x" -#define SCNXLEAST8 "X" -#define SCNoFAST8 "o" -#define SCNuFAST8 "u" -#define SCNxFAST8 "x" -#define SCNXFAST8 "X" - -#define SCNo16 "ho" -#define SCNu16 "hu" -#define SCNx16 "hx" -#define SCNX16 "hX" -#define SCNoLEAST16 "ho" -#define SCNuLEAST16 "hu" -#define SCNxLEAST16 "hx" -#define SCNXLEAST16 "hX" -#define SCNoFAST16 "ho" -#define SCNuFAST16 "hu" -#define SCNxFAST16 "hx" -#define SCNXFAST16 "hX" - -#define SCNo32 "lo" -#define SCNu32 "lu" -#define SCNx32 "lx" -#define SCNX32 "lX" -#define SCNoLEAST32 "lo" -#define SCNuLEAST32 "lu" -#define SCNxLEAST32 "lx" -#define SCNXLEAST32 "lX" -#define SCNoFAST32 "lo" -#define SCNuFAST32 "lu" -#define SCNxFAST32 "lx" -#define SCNXFAST32 "lX" - -#define SCNo64 "I64o" -#define SCNu64 "I64u" -#define SCNx64 "I64x" -#define SCNX64 "I64X" -#define SCNoLEAST64 "I64o" -#define SCNuLEAST64 "I64u" -#define SCNxLEAST64 "I64x" -#define SCNXLEAST64 "I64X" -#define SCNoFAST64 "I64o" -#define SCNuFAST64 "I64u" -#define SCNxFAST64 "I64x" -#define SCNXFAST64 "I64X" - -#define SCNoMAX "I64o" -#define SCNuMAX "I64u" -#define SCNxMAX "I64x" -#define SCNXMAX "I64X" - -#ifdef _WIN64 // [ -# define SCNoPTR "I64o" -# define SCNuPTR "I64u" -# define SCNxPTR "I64x" -# define SCNXPTR "I64X" -#else // _WIN64 ][ -# define SCNoPTR "lo" -# define SCNuPTR "lu" -# define SCNxPTR "lx" -# define SCNXPTR "lX" -#endif // _WIN64 ] - -#endif // __STDC_FORMAT_MACROS ] - -// 7.8.2 Functions for greatest-width integer types - -// 7.8.2.1 The imaxabs function -#define imaxabs _abs64 - -// 7.8.2.2 The imaxdiv function - -// This is modified version of div() function from Microsoft's div.c found -// in %MSVC.NET%\crt\src\div.c -#ifdef STATIC_IMAXDIV // [ -static -#else // STATIC_IMAXDIV ][ -_inline -#endif // STATIC_IMAXDIV ] -imaxdiv_t __cdecl imaxdiv(intmax_t numer, intmax_t denom) -{ - imaxdiv_t result; - - result.quot = numer / denom; - result.rem = numer % denom; - - if (numer < 0 && result.rem > 0) { - // did division wrong; must fix up - ++result.quot; - result.rem -= denom; - } - - return result; -} - -// 7.8.2.3 The strtoimax and strtoumax functions -#define strtoimax _strtoi64 -#define strtoumax _strtoui64 - -// 7.8.2.4 The wcstoimax and wcstoumax functions -#define wcstoimax _wcstoi64 -#define wcstoumax _wcstoui64 - - -#endif // _MSC_INTTYPES_H_ ] diff --git a/external/stdint-win.h b/external/stdint-win.h deleted file mode 100644 index 9d0d6f9eb1..0000000000 --- a/external/stdint-win.h +++ /dev/null @@ -1,245 +0,0 @@ -// ISO C9x compliant stdint.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006-2008 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -// Modern Visual Studio has sane stdint.h -#if _MSC_VER >= 1900 -#include -#define _MSC_STDINT_H_ -#endif - -#ifndef _MSC_STDINT_H_ // [ -#define _MSC_STDINT_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include - -// For Visual Studio 6 in C++ mode and for many Visual Studio versions when -// compiling for ARM we should wrap include with 'extern "C++" {}' -// or compiler give many errors like this: -// error C2733: second C linkage of overloaded function 'wmemchr' not allowed -#ifdef __cplusplus -extern "C" { -#endif -# include -#ifdef __cplusplus -} -#endif - -// Define _W64 macros to mark types changing their size, like intptr_t. -#ifndef _W64 -# if !defined(__midl) && (defined(_X86_) || defined(_M_IX86)) && _MSC_VER >= 1300 -# define _W64 __w64 -# else -# define _W64 -# endif -#endif - - -// 7.18.1 Integer types - -// 7.18.1.1 Exact-width integer types - -// Visual Studio 6 and Embedded Visual C++ 4 doesn't -// realize that, e.g. char has the same size as __int8 -// so we give up on __intX for them. -#if (_MSC_VER < 1300) - typedef signed char int8_t; - typedef signed short int16_t; - typedef signed int int32_t; - typedef unsigned char uint8_t; - typedef unsigned short uint16_t; - typedef unsigned int uint32_t; -#else - typedef signed __int8 int8_t; - typedef signed __int16 int16_t; - typedef signed __int32 int32_t; - typedef unsigned __int8 uint8_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int32 uint32_t; -#endif -typedef signed __int64 int64_t; -typedef unsigned __int64 uint64_t; - - -// 7.18.1.2 Minimum-width integer types -typedef int8_t int_least8_t; -typedef int16_t int_least16_t; -typedef int32_t int_least32_t; -typedef int64_t int_least64_t; -typedef uint8_t uint_least8_t; -typedef uint16_t uint_least16_t; -typedef uint32_t uint_least32_t; -typedef uint64_t uint_least64_t; - -// 7.18.1.3 Fastest minimum-width integer types - -// 7.18.1.4 Integer types capable of holding object pointers -#ifdef _WIN64 // [ - typedef signed __int64 intptr_t; - typedef unsigned __int64 uintptr_t; -#else // _WIN64 ][ - typedef _W64 signed int intptr_t; - typedef _W64 unsigned int uintptr_t; -#endif // _WIN64 ] - -// 7.18.1.5 Greatest-width integer types -typedef int64_t intmax_t; -typedef uint64_t uintmax_t; - - -// 7.18.2 Limits of specified-width integer types - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) // [ See footnote 220 at page 257 and footnote 221 at page 259 - -// 7.18.2.1 Limits of exact-width integer types -#define INT8_MIN ((int8_t)_I8_MIN) -#define INT8_MAX _I8_MAX -#define INT16_MIN ((int16_t)_I16_MIN) -#define INT16_MAX _I16_MAX -#define INT32_MIN ((int32_t)_I32_MIN) -#define INT32_MAX _I32_MAX -#define INT64_MIN ((int64_t)_I64_MIN) -#define INT64_MAX _I64_MAX -#define UINT8_MAX _UI8_MAX -#define UINT16_MAX _UI16_MAX -#define UINT32_MAX _UI32_MAX -#define UINT64_MAX _UI64_MAX - -// 7.18.2.2 Limits of minimum-width integer types -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST8_MAX UINT8_MAX -#define UINT_LEAST16_MAX UINT16_MAX -#define UINT_LEAST32_MAX UINT32_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -// 7.18.2.3 Limits of fastest minimum-width integer types -#define INT_FAST8_MIN INT8_MIN -#define INT_FAST8_MAX INT8_MAX -#define INT_FAST16_MIN INT16_MIN -#define INT_FAST16_MAX INT16_MAX -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST8_MAX UINT8_MAX -#define UINT_FAST16_MAX UINT16_MAX -#define UINT_FAST32_MAX UINT32_MAX -#define UINT_FAST64_MAX UINT64_MAX - -// 7.18.2.4 Limits of integer types capable of holding object pointers -#ifdef _WIN64 // [ -# define INTPTR_MIN INT64_MIN -# define INTPTR_MAX INT64_MAX -# define UINTPTR_MAX UINT64_MAX -#else // _WIN64 ][ -# define INTPTR_MIN INT32_MIN -# define INTPTR_MAX INT32_MAX -# define UINTPTR_MAX UINT32_MAX -#endif // _WIN64 ] - -// 7.18.2.5 Limits of greatest-width integer types -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -// 7.18.3 Limits of other integer types - -#ifdef _WIN64 // [ -# define PTRDIFF_MIN _I64_MIN -# define PTRDIFF_MAX _I64_MAX -#else // _WIN64 ][ -# define PTRDIFF_MIN _I32_MIN -# define PTRDIFF_MAX _I32_MAX -#endif // _WIN64 ] - -#define SIG_ATOMIC_MIN INT_MIN -#define SIG_ATOMIC_MAX INT_MAX - -#ifndef SIZE_MAX // [ -# ifdef _WIN64 // [ -# define SIZE_MAX _UI64_MAX -# else // _WIN64 ][ -# define SIZE_MAX _UI32_MAX -# endif // _WIN64 ] -#endif // SIZE_MAX ] - -// WCHAR_MIN and WCHAR_MAX are also defined in -#ifndef WCHAR_MIN // [ -# define WCHAR_MIN 0 -#endif // WCHAR_MIN ] -#ifndef WCHAR_MAX // [ -# define WCHAR_MAX _UI16_MAX -#endif // WCHAR_MAX ] - -#define WINT_MIN 0 -#define WINT_MAX _UI16_MAX - -#endif // __STDC_LIMIT_MACROS ] - - -// 7.18.4 Limits of other integer types - -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) && (_MSC_VER < 1600) // [ See footnote 224 at page 260 - -// 7.18.4.1 Macros for minimum-width integer constants - -#define INT8_C(val) val##i8 -#define INT16_C(val) val##i16 -#define INT32_C(val) val##i32 -#define INT64_C(val) val##i64 - -#define UINT8_C(val) val##ui8 -#define UINT16_C(val) val##ui16 -#define UINT32_C(val) val##ui32 -#define UINT64_C(val) val##ui64 - -// 7.18.4.2 Macros for greatest-width integer constants -#define INTMAX_C INT64_C -#define UINTMAX_C UINT64_C - -#endif // __STDC_CONSTANT_MACROS ] - - -#endif // _MSC_STDINT_H_ ] From 42416989fb088bcce043397835dfa6677bbacbe6 Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 6 Apr 2022 10:21:30 -0500 Subject: [PATCH 108/505] Cleanup (remove) ancient linux kernel support (#1241) - Remove check and message for ancient linux kernel - Remove support for old mechanism to find process's tasks --- common/src/linuxKludges.C | 47 +----------------------- dyninstAPI/src/BPatch_process.C | 65 --------------------------------- 2 files changed, 1 insertion(+), 111 deletions(-) diff --git a/common/src/linuxKludges.C b/common/src/linuxKludges.C index 195337c98f..aa7db217d5 100644 --- a/common/src/linuxKludges.C +++ b/common/src/linuxKludges.C @@ -941,51 +941,6 @@ bool findProcLWPs(pid_t pid, std::vector &lwps) closedir(dirhandle); return true; } - /** - * Linux 2.4: - * - * PIDs that are created by pthreads have a '.' prepending their name - * in /proc. We'll check all of those for the ones that have this lwp - * as a parent pid. - **/ - dirhandle = opendir("/proc"); - if (!dirhandle) - { - //No /proc directory. I give up. No threads for you. - return false; - } - while ((direntry = readdir(dirhandle)) != NULL) - { - if (direntry->d_name[0] != '.') { - //fprintf(stderr, "%s[%d]: Skipping entry %s\n", FILE__, __LINE__, direntry->d_name); - continue; - } - unsigned lwp_id = atoi(direntry->d_name+1); - int lwp_ppid = 0; - if (!lwp_id) - continue; - sprintf(name, "/proc/%u/status", lwp_id); - FILE *fd = P_fopen(name, "r"); - if (!fd) { - continue; - } - char buffer[1024]; - while (fgets(buffer, 1024, fd)) { - if (strncmp(buffer, "Tgid", 4) == 0) { - sscanf(buffer, "%*s %d", &lwp_ppid); - break; - } - } - - fclose(fd); - - if (lwp_ppid != pid) { - continue; - } - lwps.push_back(lwp_id); - } - closedir(dirhandle); - lwps.push_back(pid); - return true; + return false; } diff --git a/dyninstAPI/src/BPatch_process.C b/dyninstAPI/src/BPatch_process.C index cad51d86c0..5b4b8d5370 100644 --- a/dyninstAPI/src/BPatch_process.C +++ b/dyninstAPI/src/BPatch_process.C @@ -230,54 +230,6 @@ BPatch_process::BPatch_process(const char *path, const char *argv[], startup_cerr << "BPatch_process::BPatch_process, completed." << endl; } -#if defined(os_linux) -/* Particular linux kernels running dyninst in particular patterns - (namely, with a single process having spawned the mutator and the - mutatee) are susceptible to a kernel bug that will cause a panic - if the mutator exits before the mutatee. See the comment above - class ForkNewProcessCallback : public DBICallbackBase in - debuggerinterface.h for details. -*/ -bool LinuxConsideredHarmful(pid_t pid) // PUSH -{ - int major, minor, sub, subsub; // version numbers - pid_t my_ppid, my_pid, mutatee_ppid = 0; - FILE *fd; - char buf[1024]; - char filename[64]; - - get_linux_version(major,minor,sub,subsub); - - if( major == 2 && minor == 6 && - (sub < 11 || (sub == 11 && subsub <= 11)) ) - { - my_ppid = getppid(); - my_pid = getpid(); - // If anybody knows a better way to get the parent pid, be my - // guest to change this. - snprintf(filename, 64, "/proc/%d/status", pid); - fd = fopen(filename, "r"); - if (!fd) { - startup_printf("Failed to open %s, assuming no linux kernel bug\n", - filename); - return false; - } - while (fgets(buf, 1024, fd)) { - if (strncmp(buf, "PPid", 4) == 0) { - sscanf(buf, "%*s %d", &mutatee_ppid); - break; - } - } - fclose(fd); - - if(my_ppid == mutatee_ppid || - my_pid == mutatee_ppid) - return true; - } - - return false; -} -#endif /* * BPatch_process::BPatch_process * @@ -298,23 +250,6 @@ BPatch_process::BPatch_process image = NULL; pendingInsertions = NULL; -#if defined(os_linux) - /* We need to test whether we are in kernel 2.6.9 - 2.6.11.11 (inclusive). - If so, and if the mutatee's parent and our parent are one and the same, - we are exposing the user to a potential kernel panic. - */ - startup_printf("Checking for potential Linux kernel bug...\n"); - if(LinuxConsideredHarmful(pid)) - { - fprintf(stderr, - "\nWARNING: You are running a Linux kernel between 2.6.9 and \n" - "2.6.11.11 (inclusive). Executing Dyninst under this kernel \n" - "may exercise a bug in the Linux kernel and lead to a panic \n" - "under some conditions. We STRONGLY suggest that you upgrade \n" - "your kernel to 2.6.11.12 or higher.\n\n"); - } -#endif - assert(BPatch::bpatch != NULL); startup_printf("%s[%d]: creating new BPatch_image...\n", FILE__, __LINE__); From 929dc3980115df721995d030f65b40075e50bacc Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 7 Apr 2022 11:20:58 -0500 Subject: [PATCH 109/505] Use bfd linker for LTO (#1248) The gold linker crashes and is no longer supported. --- cmake/optimization.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/optimization.cmake b/cmake/optimization.cmake index a15f24084a..a06912707e 100644 --- a/cmake/optimization.cmake +++ b/cmake/optimization.cmake @@ -4,7 +4,7 @@ if (CMAKE_COMPILER_IS_GNUCXX OR ${CMAKE_C_COMPILER_ID} MATCHES Intel) if(ENABLE_LTO) set(LTO_FLAGS "-flto") - set(LTO_LINK_FLAGS "-fuse-ld=gold") + set(LTO_LINK_FLAGS "-fuse-ld=bfd") else() set(LTO_FLAGS "") set(LTO_LINK_FLAGS "") From eda8c25a56d179455c5ddb0535ec6fd1ea163c8b Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Mon, 4 Apr 2022 16:38:49 -0500 Subject: [PATCH 110/505] Add cmake options for C/C++ language standards (#1246) Add cmake options to set C/C++ language standard versions used to build to facilitate testing. - DYNINST_C_LANGUAGE_STANDARD cmake option: C Standard version - DYNINST_CXX_LANGUAGE_STANDARD cmake option: C++ Standard version --- CMakeLists.txt | 2 ++ cmake/LanguageStandards.cmake | 13 +++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index e184bdb5f2..42850ad0bd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -128,6 +128,8 @@ endif() "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" "-DDYNINST_EXTRA_WARNINGS=${DYNINST_EXTRA_WARNINGS}" "-DDYNINST_WARNINGS_AS_ERRORS=${DYNINST_WARNINGS_AS_ERRORS}" + "-DDYNINST_CXX_LANGUAGE_STANDARD=${DYNINST_CXX_LANGUAGE_STANDARD}" + "-DDYNINST_C_LANGUAGE_STANDARD=${DYNINST_C_LANGUAGE_STANDARD}" -G "${CMAKE_GENERATOR}" -B "${RT_BINARY_DIR}" -S "${RT_SOURCE_DIR}") diff --git a/cmake/LanguageStandards.cmake b/cmake/LanguageStandards.cmake index d538c2b036..6d16fae3a4 100644 --- a/cmake/LanguageStandards.cmake +++ b/cmake/LanguageStandards.cmake @@ -5,6 +5,13 @@ # #========================================================================= +# +# C/C++ language standard cmake options. +# + +set(DYNINST_CXX_LANGUAGE_STANDARD "11" CACHE STRING "C++ language standard version.") +set(DYNINST_C_LANGUAGE_STANDARD "11" CACHE STRING "C language standard version.") + # # -------- C++ language features ---------------- # @@ -13,7 +20,8 @@ set(CMAKE_CXX_EXTENSIONS OFF) # Require C++11 support -set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD ${DYNINST_CXX_LANGUAGE_STANDARD}) +message(STATUS "C++ language standard: ${DYNINST_CXX_LANGUAGE_STANDARD}") set(CMAKE_CXX_STANDARD_REQUIRED ON) # Require the standards-compliant C++11 ABI for gcc @@ -32,5 +40,6 @@ endif() set(CMAKE_C_EXTENSIONS OFF) # Require C11 support -set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD ${DYNINST_C_LANGUAGE_STANDARD}) +message(STATUS "C language standard: ${DYNINST_C_LANGUAGE_STANDARD}") set(CMAKE_C_STANDARD_REQUIRED ON) From 3c5b576bd56814abf934730f6519d51a2df3d36f Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Wed, 6 Apr 2022 16:26:02 -0500 Subject: [PATCH 111/505] Make dyninstAPI_RT files build with standard C (#1246) - use same language standards as the rest of Dyninst - define _DEFAULT_SOURCE in some dyninstAPI_RT source files so functions and macros used are defined when using standard C --- dyninstAPI_RT/CMakeLists.txt | 1 + dyninstAPI_RT/src/RTheap-linux.c | 2 ++ dyninstAPI_RT/src/RTheap.c | 2 ++ dyninstAPI_RT/src/RTlinux.c | 2 ++ dyninstAPI_RT/src/RTposix.c | 2 ++ dyninstAPI_RT/src/RTsignal.c | 4 +++- 6 files changed, 12 insertions(+), 1 deletion(-) diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index 983a5ab8da..b454688d79 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -4,6 +4,7 @@ project (DyninstRT C) set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}/..) +include (${DYNINST_ROOT}/cmake/LanguageStandards.cmake) include (${DYNINST_ROOT}/cmake/shared.cmake) include_directories ( diff --git a/dyninstAPI_RT/src/RTheap-linux.c b/dyninstAPI_RT/src/RTheap-linux.c index 64cfb06bfb..3968b6b8ee 100644 --- a/dyninstAPI_RT/src/RTheap-linux.c +++ b/dyninstAPI_RT/src/RTheap-linux.c @@ -31,6 +31,8 @@ /* $Id: RTheap-linux.c,v 1.9 2008/01/31 18:01:54 legendre Exp $ */ /* RTheap-linux.c: Linux-specific heap components */ +#define _DEFAULT_SOURCE + #include #include #include /* str* */ diff --git a/dyninstAPI_RT/src/RTheap.c b/dyninstAPI_RT/src/RTheap.c index 33195e06e3..57b5e55fab 100644 --- a/dyninstAPI_RT/src/RTheap.c +++ b/dyninstAPI_RT/src/RTheap.c @@ -31,6 +31,8 @@ /* $Id: RTheap.c,v 1.25 2006/05/03 00:31:25 jodom Exp $ */ /* RTheap.c: platform-generic heap management */ +#define _DEFAULT_SOURCE + #include #include #if !defined(os_windows) /* ccw 15 may 2000 : 29 mar 2001 */ diff --git a/dyninstAPI_RT/src/RTlinux.c b/dyninstAPI_RT/src/RTlinux.c index 0ca7a41d43..55d7772d61 100644 --- a/dyninstAPI_RT/src/RTlinux.c +++ b/dyninstAPI_RT/src/RTlinux.c @@ -33,6 +33,8 @@ * RTlinux.c: mutatee-side library function specific to Linux ************************************************************************/ +#define _DEFAULT_SOURCE + #include "dyninstAPI_RT/h/dyninstAPI_RT.h" #include "dyninstAPI_RT/src/RTthread.h" #include "dyninstAPI_RT/src/RTcommon.h" diff --git a/dyninstAPI_RT/src/RTposix.c b/dyninstAPI_RT/src/RTposix.c index 8277c3d09a..d1f7e16fb8 100644 --- a/dyninstAPI_RT/src/RTposix.c +++ b/dyninstAPI_RT/src/RTposix.c @@ -33,6 +33,8 @@ * RTposix.c: runtime instrumentation functions for generic posix. ************************************************************************/ +#define _DEFAULT_SOURCE + #include #include #include diff --git a/dyninstAPI_RT/src/RTsignal.c b/dyninstAPI_RT/src/RTsignal.c index 1aab0ee3d0..b78ab71270 100644 --- a/dyninstAPI_RT/src/RTsignal.c +++ b/dyninstAPI_RT/src/RTsignal.c @@ -30,7 +30,9 @@ /************************************************************************ * RTsignal.c: C-language signal handling code -************************************************************************/ + ************************************************************************/ + +#define _DEFAULT_SOURCE #include #include From b5763c339d0b22ddb858fe93e340367e8e45efb8 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 7 Apr 2022 15:44:55 -0500 Subject: [PATCH 112/505] Fix format string errors in stackwalk/callchecker.C (#1250) These are only present when SW_ANALYSIS_STEPPER=OFF. --- stackwalk/src/callchecker.C | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/stackwalk/src/callchecker.C b/stackwalk/src/callchecker.C index 48cd52d006..ac4b36523e 100644 --- a/stackwalk/src/callchecker.C +++ b/stackwalk/src/callchecker.C @@ -44,12 +44,12 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) bool result; unsigned char buffer[max_call_length]; - sw_printf("[%s:%u] - isPrevInstrACall on %lx\n", FILE__, __LINE__, addr); + sw_printf("[%s:%d] - isPrevInstrACall on %lx\n", FILE__, __LINE__, addr); Address start = addr - max_call_length; result = proc->readMem(buffer, start, max_call_length); if (!result) { - sw_printf("[%s:%u] - Address 0x%lx is not a call--unreadable\n", + sw_printf("[%s:%d] - Address 0x%lx is not a call--unreadable\n", FILE__, __LINE__, addr); return false; } @@ -57,7 +57,7 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) if (buffer[max_call_length - 5] == 0xe8) { int32_t disp = *((int32_t *) (buffer+1)); target = addr + disp; - sw_printf("[%s:%u] - Found call encoded by %x to %lx (addr = %lx, disp = %lx)\n", + sw_printf("[%s:%d] - Found call encoded by %x to %lx (addr = %lx, disp = %dx)\n", FILE__, __LINE__, (int) buffer[0], target, addr, disp); return true; @@ -102,7 +102,7 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) if (i + size == max_call_length) { - sw_printf("[%s:%u] - Found call of size %d encoded by: ", + sw_printf("[%s:%d] - Found call of size %u encoded by: ", FILE__, __LINE__, size); for (unsigned j=i; j Date: Thu, 7 Apr 2022 16:24:10 -0500 Subject: [PATCH 113/505] Redo finalization to get correct function boundiaries when (#1249) there are many tail call correction --- parseAPI/src/Parser.C | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index a1654672a2..047164b4bc 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -1010,6 +1010,21 @@ Parser::finalize() finalize_funcs(discover_funcs); clean_bogus_funcs(discover_funcs); + // We need to redo finalization one more time to get correct + // function boundaries. This is intended to handle tail call + // correction. Suppose function A contains function B, and + // function B tail calls C. + // Further, we assume that parseAPI fails to identify the tail call + // in B. Then during finalizaiton, we can correct the tail call + // either when we finalize A or B, but not both. Therefore, + // after finalization, either A or B would have incorrect function + // boundary. Therefore, we recompute function boundary. + // In addition, there is no need for a loop to redo finalization + // as there would be no more tail call correction. + // We only need to get correct function boundaries. + finalize_funcs(hint_funcs); + finalize_funcs(discover_funcs); + for (auto it = hint_funcs.begin(); it != hint_funcs.end(); ++it) if (deleted_func.find(*it) == deleted_func.end()) { sorted_funcs.insert(*it); From c7372633a036c91f731098e538609e55866e6cf8 Mon Sep 17 00:00:00 2001 From: kupsch Date: Fri, 8 Apr 2022 17:12:20 -0500 Subject: [PATCH 114/505] Fix dyninstAPI_RT files to build with older glibc (#1252) Replace feature test macro _DEFAULT_SOURCE with _GNU_SOURCE to support older version of glibc --- dyninstAPI_RT/src/RTheap-linux.c | 2 +- dyninstAPI_RT/src/RTheap.c | 2 +- dyninstAPI_RT/src/RTlinux.c | 2 +- dyninstAPI_RT/src/RTposix.c | 2 +- dyninstAPI_RT/src/RTsignal.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/dyninstAPI_RT/src/RTheap-linux.c b/dyninstAPI_RT/src/RTheap-linux.c index 3968b6b8ee..e3dfb7399a 100644 --- a/dyninstAPI_RT/src/RTheap-linux.c +++ b/dyninstAPI_RT/src/RTheap-linux.c @@ -31,7 +31,7 @@ /* $Id: RTheap-linux.c,v 1.9 2008/01/31 18:01:54 legendre Exp $ */ /* RTheap-linux.c: Linux-specific heap components */ -#define _DEFAULT_SOURCE +#define _GNU_SOURCE #include #include diff --git a/dyninstAPI_RT/src/RTheap.c b/dyninstAPI_RT/src/RTheap.c index 57b5e55fab..829a537e12 100644 --- a/dyninstAPI_RT/src/RTheap.c +++ b/dyninstAPI_RT/src/RTheap.c @@ -31,7 +31,7 @@ /* $Id: RTheap.c,v 1.25 2006/05/03 00:31:25 jodom Exp $ */ /* RTheap.c: platform-generic heap management */ -#define _DEFAULT_SOURCE +#define _GNU_SOURCE #include #include diff --git a/dyninstAPI_RT/src/RTlinux.c b/dyninstAPI_RT/src/RTlinux.c index 55d7772d61..5661994813 100644 --- a/dyninstAPI_RT/src/RTlinux.c +++ b/dyninstAPI_RT/src/RTlinux.c @@ -33,7 +33,7 @@ * RTlinux.c: mutatee-side library function specific to Linux ************************************************************************/ -#define _DEFAULT_SOURCE +#define _GNU_SOURCE #include "dyninstAPI_RT/h/dyninstAPI_RT.h" #include "dyninstAPI_RT/src/RTthread.h" diff --git a/dyninstAPI_RT/src/RTposix.c b/dyninstAPI_RT/src/RTposix.c index d1f7e16fb8..8f27edbb18 100644 --- a/dyninstAPI_RT/src/RTposix.c +++ b/dyninstAPI_RT/src/RTposix.c @@ -33,7 +33,7 @@ * RTposix.c: runtime instrumentation functions for generic posix. ************************************************************************/ -#define _DEFAULT_SOURCE +#define _GNU_SOURCE #include #include diff --git a/dyninstAPI_RT/src/RTsignal.c b/dyninstAPI_RT/src/RTsignal.c index b78ab71270..69c0339965 100644 --- a/dyninstAPI_RT/src/RTsignal.c +++ b/dyninstAPI_RT/src/RTsignal.c @@ -32,7 +32,7 @@ * RTsignal.c: C-language signal handling code ************************************************************************/ -#define _DEFAULT_SOURCE +#define _GNU_SOURCE #include #include From 5165d8ce5eda38f94eb7c4f12497ef4aefad3f4b Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 12 Apr 2022 14:06:30 -0500 Subject: [PATCH 115/505] Remove unused build options (#1253) * Remove BUILD_DOCS This isn't sufficient to create the documentation as some of it is contained in MS Word files. * Remove BUILD_TARBALLS We don't distrubute tarballs anymore. That's handled by GitHub. --- CMakeLists.txt | 72 --------------------------------------------- cmake/options.cmake | 3 -- 2 files changed, 75 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 42850ad0bd..59de33a237 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -163,78 +163,6 @@ endif() set (VERSION_STRING "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") set (DYNINST_NAME "DyninstAPI-${VERSION_STRING}") -if(BUILD_TARBALLS) - find_package(Git) - if(GIT_FOUND) - if(EXISTS "${DYNINST_ROOT}/.git/") - message(STATUS "Source tree is repository, building archive target") - add_custom_target(package ALL) - add_custom_command(TARGET package - COMMAND ${GIT_EXECUTABLE} archive --prefix="${DYNINST_NAME}/" --format=tar.gz -o "${CMAKE_BINARY_DIR}/${DYNINST_NAME}.tgz" HEAD - WORKING_DIRECTORY ${DYNINST_ROOT} - COMMENT "Packaging Dyninst") - endif() - endif() -endif() -if(BUILD_DOCS) - add_custom_target(doc) - set(LATEX_DOCS dynC_API dataflowAPI instructionAPI parseAPI patchAPI symtabAPI stackwalk) - set(WORD_DOCS proccontrol dyninstAPI) - add_custom_target(proccontrol-doc - DEPENDS ${CMAKE_SOURCE_DIR}/proccontrol/doc/proccontrol.pdf) - add_custom_target(dyninstAPI-doc - DEPENDS ${CMAKE_SOURCE_DIR}/dyninstAPI/doc/dyninstAPI.pdf) - foreach(COMPONENT ${WORD_DOCS}) - add_dependencies(doc ${COMPONENT}-doc) - set_target_properties(${COMPONENT}-doc PROPERTIES EXCLUDE_FROM_DEFAULT_BUILD 1) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.pdf - DESTINATION ${INSTALL_DOC_DIR} - RENAME ${COMPONENT}-${VERSION_STRING}.pdf - OPTIONAL - ) - endforeach() - - find_package(LATEX) - if(PDFLATEX_COMPILER) - file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/common/doc - DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/common) - foreach(COMPONENT ${LATEX_DOCS}) - file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/${COMPONENT}/doc - DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}) - set (DEPS "") - file(GLOB_RECURSE DEPS ${CMAKE_CURRENT_SOURCE_DIR}/${COMPONENT}/doc/*.tex ${CMAKE_CURRENT_SOURCE_DIR}/common/doc/*.tex) - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.aux - DEPENDS ${DEPS} - COMMAND ${PDFLATEX_COMPILER} - ARGS -interaction=batchmode ${COMPONENT}.tex - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc - COMMENT "Latex (first pass)" - ) - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.log - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.aux - COMMAND ${PDFLATEX_COMPILER} - ARGS -interaction=batchmode ${COMPONENT}.tex - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc - COMMENT "Latex (second pass)" - ) - add_custom_target(${COMPONENT}-doc echo - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.log - ) - add_dependencies(doc ${COMPONENT}-doc) - set_target_properties(${COMPONENT}-doc PROPERTIES EXCLUDE_FROM_DEFAULT_BUILD 1) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.pdf - DESTINATION ${INSTALL_DOC_DIR} - RENAME ${COMPONENT}-${VERSION_STRING}.pdf - OPTIONAL - ) - endforeach() - else() - message(STATUS "LaTeX not found") - endif() -endif() - if(TARGET boost) add_dependencies(common boost) endif() diff --git a/cmake/options.cmake b/cmake/options.cmake index 39e046a237..35ec0779e0 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -7,11 +7,8 @@ option (LIGHTWEIGHT_SYMTAB "Use lightweight symtab interface for ParseAPI, ProcC # Use ParseAPI analysis in Stackwalker? option (SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" ON) -option (BUILD_TARBALLS "Build Dyninst package tarballs. Requires git archive, tar, gzip." OFF) option (BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) -option(BUILD_DOCS "Build manuals from LaTeX sources" ON) - option (ENABLE_LTO "Enable Link-Time Optimization" OFF) option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) From 83936c0ddac64a010fdfd689a082ba3cefcd310e Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 26 Apr 2022 23:03:56 -0500 Subject: [PATCH 116/505] Docker: don't use autamus cache (#1259) The public keys have been removed. --- docker/Dockerfile | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 4339aba4bc..63a6c50e57 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -75,12 +75,9 @@ WORKDIR /opt RUN git clone --depth 1 https://github.com/spack/spack ENV PATH=/opt/spack/bin:$PATH -# Use the autamus build cache for faster install -# Note that autamus currently uses 18.04 -RUN python3 -m pip install botocore boto3 && \ - spack mirror add autamus s3://autamus-cache && \ - curl http://s3.amazonaws.com/autamus-cache/build_cache/_pgp/FFEB24B0A9D81F6D5597F9900B59588C86C41BE7.pub > key.pub && \ - spack gpg trust key.pub +# Install the boto3 package for using AWS services +# spack uses this for its binary caches +RUN python3 -m pip install botocore boto3 # Find packages already installed on system, e.g. autoconf RUN spack external find --not-buildable gcc@11.0.1 autoconf bzip2 git tar xz perl cmake m4 ncurses && \ From b35fbc04f6bead711ae7c3e0952b34ec20ddee35 Mon Sep 17 00:00:00 2001 From: John Mellor-Crummey Date: Tue, 3 May 2022 13:33:58 -0500 Subject: [PATCH 117/505] Fix decoding of DWARF expressions into machine registers for Intel GPUs (#1262) We ignore the encoding as we do for all of the other GPUs. This case was missing and so hit the assert. --- common/src/dyn_regs.C | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index 7cfd5aa0d4..88be3da518 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -1834,10 +1834,12 @@ MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arc break; case Arch_amdgpu_vega: case Arch_amdgpu_cdna2: - // ignore CUDA register encodings for now + // ignore AMD register encodings for now + return Dyninst::InvalidReg; + break; + case Arch_intelGen9: return Dyninst::InvalidReg; break; - case Arch_none: return Dyninst::InvalidReg; break; From b9067359529c578815fa471e5334d5bf5d0b10d0 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 5 May 2022 00:27:45 -0500 Subject: [PATCH 118/505] Fix bug in processing library paths in FindLibIberty.cmake (#1266) This was originally part of #1263 Co-authored-by: Jonathan R. Madsen --- cmake/Modules/FindLibIberty.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/Modules/FindLibIberty.cmake b/cmake/Modules/FindLibIberty.cmake index c52a342d6a..88b60d1150 100644 --- a/cmake/Modules/FindLibIberty.cmake +++ b/cmake/Modules/FindLibIberty.cmake @@ -71,7 +71,7 @@ find_package_handle_standard_args(LibIberty set(IBERTY_FOUND ${LibIberty_FOUND}) if(LibIberty_FOUND) - foreach(l in ${LibIberty_LIBRARIES}) + foreach(l ${LibIberty_LIBRARIES}) get_filename_component(_dir ${l} DIRECTORY) list(APPEND LibIberty_LIBRARY_DIRS ${_dir}) endforeach() From 55c45cca8b2ae90f07bbb3098c2f53285be7c90e Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 5 May 2022 14:38:54 -0500 Subject: [PATCH 119/505] Update and enforce formatting of CMake files (#1267) Co-authored-by: Jonathan R. Madsen --- .cmake-format.yaml | 85 + .github/workflows/cmake-formatting.yaml | 29 + CMakeLists.txt | 197 +- DyninstConfigVersion.cmake | 8 +- cmake/Boost.cmake | 324 +- cmake/DyninstConfig.cmake.in | 40 +- cmake/DyninstConfigVersion.cmake.in | 8 +- cmake/ElfUtils.cmake | 191 +- cmake/LanguageStandards.cmake | 15 +- cmake/LibIberty.cmake | 38 +- cmake/Modules/DyninstSystemPaths.cmake | 15 +- cmake/Modules/FindBoost.cmake | 3804 +++++++++++-------- cmake/Modules/FindLibDebuginfod.cmake | 66 +- cmake/Modules/FindLibDwarf.cmake | 68 +- cmake/Modules/FindLibElf.cmake | 68 +- cmake/Modules/FindLibIberty.cmake | 57 +- cmake/Modules/FindTBB.cmake | 318 +- cmake/Modules/FindThreadDB.cmake | 75 +- cmake/Modules/FindValgrind.cmake | 24 +- cmake/ThreadingBuildingBlocks.cmake | 215 +- cmake/ThreadingBuildingBlocks.install.cmake | 12 +- cmake/cap_arch_def.cmake | 204 +- cmake/endian.cmake | 8 +- cmake/optimization.cmake | 108 +- cmake/options.cmake | 23 +- cmake/platform.cmake | 8 +- cmake/platform_unix.cmake | 51 +- cmake/platform_windows.cmake | 2 +- cmake/shared.cmake | 233 +- cmake/visibility.cmake | 7 +- cmake/warnings.cmake | 266 +- common/CMakeLists.txt | 193 +- dwarf/CMakeLists.txt | 20 +- dynC_API/CMakeLists.txt | 10 +- dyninstAPI/CMakeLists.txt | 378 +- dyninstAPI_RT/CMakeLists.txt | 409 +- elf/CMakeLists.txt | 17 +- instructionAPI/CMakeLists.txt | 113 +- parseAPI/CMakeLists.txt | 206 +- parseThat/CMakeLists.txt | 34 +- patchAPI/CMakeLists.txt | 43 +- proccontrol/CMakeLists.txt | 127 +- stackwalk/CMakeLists.txt | 125 +- symlite/CMakeLists.txt | 33 +- symtabAPI/CMakeLists.txt | 140 +- 45 files changed, 4523 insertions(+), 3892 deletions(-) create mode 100644 .cmake-format.yaml create mode 100644 .github/workflows/cmake-formatting.yaml diff --git a/.cmake-format.yaml b/.cmake-format.yaml new file mode 100644 index 0000000000..e748a79944 --- /dev/null +++ b/.cmake-format.yaml @@ -0,0 +1,85 @@ +parse: + additional_commands: + dyninst_library: + flags: + - BUILD_SHARED + - BUILD_STATIC + kwargs: + HEADERS: '*' + SOURCES: '*' + DEPENDS: '*' + COMPILE_DEFINITIONS: '*' + COMPILE_FEATURES: '*' + COMPILE_OPTIONS: '*' + DESTINATION: '*' + DEFAULT_VISIBILITY: '*' + INCLUDE_DIRECTORIES: '*' + LINK_LIBRARIES: '*' + LINK_OPTIONS: '*' + PROPERTIES: '*' + dyninst_add_cache_option: + kwargs: + CACHE: '*' + override_spec: {} + vartags: [] + proptags: [] +format: + disable: false + line_width: 90 + tab_size: 4 + use_tabchars: false + fractional_tab_policy: use-space + max_subgroups_hwrap: 2 + max_pargs_hwrap: 6 + max_rows_cmdline: 2 + separate_ctrl_name_with_space: false + separate_fn_name_with_space: false + dangle_parens: false + dangle_align: child + min_prefix_chars: 4 + max_prefix_chars: 10 + max_lines_hwrap: 2 + line_ending: unix + command_case: lower + keyword_case: upper + always_wrap: [] + enable_sort: true + autosort: false + require_valid_layout: false + layout_passes: {} +markup: + bullet_char: '-' + enum_char: '*' + first_comment_is_literal: true + literal_comment_pattern: ^# + fence_pattern: ^\s*([`~]{3}[`~]*)(.*)$ + ruler_pattern: ^\s*[^\w\s]{3}.*[^\w\s]{3}$ + explicit_trailing_pattern: '#<' + hashruler_min_length: 10 + canonicalize_hashrulers: true + enable_markup: true +lint: + disabled_codes: [] + function_pattern: '[0-9a-z_]+' + macro_pattern: '[0-9A-Z_]+' + global_var_pattern: '[A-Z][0-9A-Z_]+' + internal_var_pattern: _[A-Z][0-9A-Z_]+ + local_var_pattern: '[a-z][a-z0-9_]+' + private_var_pattern: _[0-9a-z_]+ + public_var_pattern: '[A-Z][0-9A-Z_]+' + argument_var_pattern: '[a-z][a-z0-9_]+' + keyword_pattern: '[A-Z][0-9A-Z_]+' + max_conditionals_custom_parser: 2 + min_statement_spacing: 1 + max_statement_spacing: 2 + max_returns: 6 + max_branches: 12 + max_arguments: 5 + max_localvars: 15 + max_statements: 50 +encode: + emit_byteorder_mark: false + input_encoding: utf-8 + output_encoding: utf-8 +misc: + per_command: {} diff --git a/.github/workflows/cmake-formatting.yaml b/.github/workflows/cmake-formatting.yaml new file mode 100644 index 0000000000..e99b9aa06a --- /dev/null +++ b/.github/workflows/cmake-formatting.yaml @@ -0,0 +1,29 @@ + +name: Formatting + +on: + pull_request: + branches: [ master ] + +jobs: + cmake-formatting: + runs-on: ubuntu-20.04 + + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: | + sudo apt-get update + sudo apt-get install -y python3-pip + python3 -m pip install cmake-format + - name: cmake-format + run: | + set +e + cmake-format -i $(find . -type f | egrep 'CMakeLists.txt|\.cmake$') + if [ $(git diff | wc -l) -gt 0 ]; then + echo -e "\nError! CMake files not formatted." + echo -e "\nRun the following to fix:" + for f in $(git diff --name-only); do echo -e " cmake-format -i $f"; done + echo + exit 1 + fi diff --git a/CMakeLists.txt b/CMakeLists.txt index 59de33a237..72cab2e837 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,30 +1,33 @@ -cmake_minimum_required (VERSION 3.4.0) +cmake_minimum_required(VERSION 3.4.0) # There is a bug in 3.19.0 that causes .S files to be treated like C files if(CMAKE_VERSION VERSION_EQUAL "3.19.0") - message(FATAL_ERROR "Dyninst cannot use CMake version 3.19.0") + message(FATAL_ERROR "Dyninst cannot use CMake version 3.19.0") endif() -project (Dyninst) +project(Dyninst) -set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}) -set (CMAKE_SKIP_BUILD_RPATH FALSE) -set (CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) -set (CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) -set (CMAKE_EXPORT_COMPILE_COMMANDS ON) +set(DYNINST_ROOT ${PROJECT_SOURCE_DIR}) +set(CMAKE_SKIP_BUILD_RPATH FALSE) +set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) +set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) -set(STERILE_BUILD ON CACHE BOOL "Do not download/build any third-party dependencies from source") +set(STERILE_BUILD + ON + CACHE BOOL "Do not download/build any third-party dependencies from source") -LIST(FIND CMAKE_PLATFORM_IMPLICIT_LINK_DIRECTORIES - "${CMAKE_INSTALL_PREFIX}/lib" isSystemDir) -IF("${isSystemDir}" STREQUAL "-1") - set (CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") -ENDIF() +list(FIND CMAKE_PLATFORM_IMPLICIT_LINK_DIRECTORIES "${CMAKE_INSTALL_PREFIX}/lib" + isSystemDir) +if("${isSystemDir}" STREQUAL "-1") + set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") +endif() set(RT_SOURCE_DIR ${DYNINST_ROOT}/dyninstAPI_RT) set(RT_BINARY_DIR ${PROJECT_BINARY_DIR}/dyninstAPI_RT) -set (CMAKE_MODULE_PATH "${DYNINST_ROOT}/cmake" "${DYNINST_ROOT}/cmake/Modules" ${CMAKE_MODULE_PATH}) +set(CMAKE_MODULE_PATH "${DYNINST_ROOT}/cmake" "${DYNINST_ROOT}/cmake/Modules" + ${CMAKE_MODULE_PATH}) # Set the C and C++ language standards include(LanguageStandards) @@ -37,19 +40,20 @@ include(ThreadingBuildingBlocks) include(ElfUtils) if(UNIX) - include(LibIberty REQUIRED) + include(LibIberty REQUIRED) endif() include(shared) if(USE_OpenMP) - find_package(OpenMP REQUIRED) + find_package(OpenMP REQUIRED) endif() configure_file(cmake/version.h.in common/h/dyninstversion.h) include_directories(${PROJECT_BINARY_DIR}) include_directories(${PROJECT_BINARY_DIR}/common/h) -set (HEADER_DIRS common +set(HEADER_DIRS + common dataflowAPI dyninstAPI instructionAPI @@ -57,117 +61,114 @@ set (HEADER_DIRS common patchAPI proccontrol stackwalk - symtabAPI - ) + symtabAPI) if(NOT ${PLATFORM} MATCHES nt) - set (HEADER_DIRS ${HEADER_DIRS} - dwarf - elf - symlite - ) + set(HEADER_DIRS ${HEADER_DIRS} dwarf elf symlite) endif() - - -foreach (dir ${HEADER_DIRS}) - include_directories ( ${DYNINST_ROOT}/${dir}/h ) +foreach(dir ${HEADER_DIRS}) + include_directories(${DYNINST_ROOT}/${dir}/h) endforeach() -set(ADD_VALGRIND_ANNOTATIONS OFF CACHE BOOL "Enable annotations for Valgrind analysis") +set(ADD_VALGRIND_ANNOTATIONS + OFF + CACHE BOOL "Enable annotations for Valgrind analysis") if(ADD_VALGRIND_ANNOTATIONS) - find_package(Valgrind REQUIRED) - include_directories(${Valgrind_INCLUDE_DIRS}) - add_definitions(-DENABLE_VG_ANNOTATIONS) + find_package(Valgrind REQUIRED) + include_directories(${Valgrind_INCLUDE_DIRS}) + add_definitions(-DENABLE_VG_ANNOTATIONS) endif() -include_directories ( - ${DYNINST_ROOT} - ${DYNINST_ROOT}/external - ${TBB_INCLUDE_DIRS} - ) +include_directories(${DYNINST_ROOT} ${DYNINST_ROOT}/external ${TBB_INCLUDE_DIRS}) # Component time -add_subdirectory (common) +add_subdirectory(common) if(NOT ${PLATFORM} MATCHES nt) - add_subdirectory (elf) - add_subdirectory (dwarf) - add_subdirectory (symlite) + add_subdirectory(elf) + add_subdirectory(dwarf) + add_subdirectory(symlite) endif() -add_subdirectory (instructionAPI) -add_subdirectory (symtabAPI) -add_subdirectory (parseAPI) -add_subdirectory (proccontrol) -add_subdirectory (stackwalk) -add_subdirectory (patchAPI) +add_subdirectory(instructionAPI) +add_subdirectory(symtabAPI) +add_subdirectory(parseAPI) +add_subdirectory(proccontrol) +add_subdirectory(stackwalk) +add_subdirectory(patchAPI) if(${SYMREADER} MATCHES symtabAPI) - add_subdirectory (dyninstAPI) - add_subdirectory (dynC_API) - add_subdirectory (parseThat) + add_subdirectory(dyninstAPI) + add_subdirectory(dynC_API) + add_subdirectory(parseThat) endif() - # Build the RT library as a separate project so we can change compilers - message(STATUS "Configuring DyninstAPI_RT in ${RT_BINARY_DIR}") - file(REMOVE_RECURSE ${RT_BINARY_DIR}/CMakeCache.txt ${RT_BINARY_DIR}/CMakeFiles ${RT_BINARY_DIR}/Makefile) - file(MAKE_DIRECTORY ${RT_BINARY_DIR}) - set (RT_C_COMPILER ${CMAKE_C_COMPILER} CACHE STRING "Compiler for runtime library") - set (ENABLE_STATIC_LIBS NO CACHE STRING "Build static libraries as well?") - message(STATUS "Configuring RT library") - - execute_process(WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMAND ${CMAKE_COMMAND} - "-DCMAKE_C_COMPILER=${RT_C_COMPILER}" - "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}" - "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}" - "-DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH}" - "-DINSTALL_LIB_DIR=${INSTALL_LIB_DIR}" - "-DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR}" - "-DCMAKE_C_FLAGS=${CMAKE_C_FLAGS}" - "-DBUILD_RTLIB_32=${BUILD_RTLIB_32}" - "-DPLATFORM=${PLATFORM}" - "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" - "-DDYNINST_EXTRA_WARNINGS=${DYNINST_EXTRA_WARNINGS}" - "-DDYNINST_WARNINGS_AS_ERRORS=${DYNINST_WARNINGS_AS_ERRORS}" - "-DDYNINST_CXX_LANGUAGE_STANDARD=${DYNINST_CXX_LANGUAGE_STANDARD}" - "-DDYNINST_C_LANGUAGE_STANDARD=${DYNINST_C_LANGUAGE_STANDARD}" - -G "${CMAKE_GENERATOR}" - -B "${RT_BINARY_DIR}" - -S "${RT_SOURCE_DIR}") - find_file(${RT_MAKEFILE} Makefile PATHS ${RT_BINARY_DIR} NO_DEFAULT_PATH) - message(STATUS "RTlib Makefile: ${RT_MAKEFILE}") - if(MSVC) - include_external_msproject(DyninstAPI_RT dyninstAPI_RT/dyninstAPI_RT.vcxproj) - include_external_msproject(DyninstAPI_RT_static dyninstAPI_RT/dyninstAPI_RT_static.vcxproj) - else() - add_custom_target(DyninstRT - ALL - $(MAKE) - WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMENT "Building DyninstRT") +# Build the RT library as a separate project so we can change compilers +message(STATUS "Configuring DyninstAPI_RT in ${RT_BINARY_DIR}") +file(REMOVE_RECURSE ${RT_BINARY_DIR}/CMakeCache.txt ${RT_BINARY_DIR}/CMakeFiles + ${RT_BINARY_DIR}/Makefile) +file(MAKE_DIRECTORY ${RT_BINARY_DIR}) +set(RT_C_COMPILER + ${CMAKE_C_COMPILER} + CACHE STRING "Compiler for runtime library") +set(ENABLE_STATIC_LIBS + NO + CACHE STRING "Build static libraries as well?") +message(STATUS "Configuring RT library") + +execute_process( + WORKING_DIRECTORY ${RT_BINARY_DIR} + COMMAND + ${CMAKE_COMMAND} "-DCMAKE_C_COMPILER=${RT_C_COMPILER}" + "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}" + "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}" + "-DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH}" "-DINSTALL_LIB_DIR=${INSTALL_LIB_DIR}" + "-DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR}" "-DCMAKE_C_FLAGS=${CMAKE_C_FLAGS}" + "-DBUILD_RTLIB_32=${BUILD_RTLIB_32}" "-DPLATFORM=${PLATFORM}" + "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" + "-DDYNINST_EXTRA_WARNINGS=${DYNINST_EXTRA_WARNINGS}" + "-DDYNINST_WARNINGS_AS_ERRORS=${DYNINST_WARNINGS_AS_ERRORS}" + "-DDYNINST_CXX_LANGUAGE_STANDARD=${DYNINST_CXX_LANGUAGE_STANDARD}" + "-DDYNINST_C_LANGUAGE_STANDARD=${DYNINST_C_LANGUAGE_STANDARD}" -G + "${CMAKE_GENERATOR}" -B "${RT_BINARY_DIR}" -S "${RT_SOURCE_DIR}") +find_file( + ${RT_MAKEFILE} Makefile + PATHS ${RT_BINARY_DIR} + NO_DEFAULT_PATH) +message(STATUS "RTlib Makefile: ${RT_MAKEFILE}") +if(MSVC) + include_external_msproject(DyninstAPI_RT dyninstAPI_RT/dyninstAPI_RT.vcxproj) + include_external_msproject(DyninstAPI_RT_static + dyninstAPI_RT/dyninstAPI_RT_static.vcxproj) +else() + add_custom_target( + DyninstRT ALL + $(MAKE) + WORKING_DIRECTORY ${RT_BINARY_DIR} + COMMENT "Building DyninstRT") if(TARGET TBB) - add_dependencies(DyninstRT TBB) + add_dependencies(DyninstRT TBB) endif() if(TARGET dyninstAPI) - add_dependencies(dyninstAPI DyninstRT) + add_dependencies(dyninstAPI DyninstRT) endif() if(TARGET dyninstAPI-static) - add_dependencies(dyninstAPI-static DyninstRT) + add_dependencies(dyninstAPI-static DyninstRT) endif() if(TARGET boost) - add_dependencies(DyninstRT boost) + add_dependencies(DyninstRT boost) endif() - endif() +endif() - install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") +install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") -set (VERSION_STRING "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") -set (DYNINST_NAME "DyninstAPI-${VERSION_STRING}") +set(VERSION_STRING + "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") +set(DYNINST_NAME "DyninstAPI-${VERSION_STRING}") if(TARGET boost) add_dependencies(common boost) endif() -#add_subdirectory(testsuite) +# add_subdirectory(testsuite) # Copy out all of the cmake files so they can be used by the Testsuite install(DIRECTORY ${DYNINST_ROOT}/cmake/ DESTINATION ${INSTALL_CMAKE_DIR}) diff --git a/DyninstConfigVersion.cmake b/DyninstConfigVersion.cmake index 8da8c28f64..37eb114574 100644 --- a/DyninstConfigVersion.cmake +++ b/DyninstConfigVersion.cmake @@ -1,7 +1,7 @@ -set (PACKAGE_VERSION "8.2.0") +set(PACKAGE_VERSION "8.2.0") -if ("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") - set (PACKAGE_VERSION_COMPATIBLE FALSE) +if("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") + set(PACKAGE_VERSION_COMPATIBLE FALSE) else() - set (PACKAGE_VERSION_COMPATIBLE TRUE) + set(PACKAGE_VERSION_COMPATIBLE TRUE) endif() diff --git a/cmake/Boost.cmake b/cmake/Boost.cmake index 53fe321ef4..11458e3be3 100644 --- a/cmake/Boost.cmake +++ b/cmake/Boost.cmake @@ -21,7 +21,7 @@ # Advanced options: # # Boost_DEBUG - Enable debug output from FindBoost -# Boost_NO_SYSTEM_PATHS - Disable searching in locations not specified by hint variables +# Boost_NO_SYSTEM_PATHS - Disable searching in locations not specified by hint variables # # Exports the following CMake cache variables # @@ -47,59 +47,72 @@ #======================================================================================================== if(Boost_FOUND) - return() + return() endif() # Need at least Boost-1.67 because of deprecated headers set(_boost_min_version 1.70.0) # Provide a default, if the user didn't specify -set(Boost_MIN_VERSION ${_boost_min_version} CACHE STRING "Minimum Boost version") +set(Boost_MIN_VERSION + ${_boost_min_version} + CACHE STRING "Minimum Boost version") # Enforce minimum version if(${Boost_MIN_VERSION} VERSION_LESS ${_boost_min_version}) - message(FATAL_ERROR "Requested Boost-${Boost_MIN_VERSION} is less than minimum supported version (${_boost_min_version})") + message( + FATAL_ERROR + "Requested Boost-${Boost_MIN_VERSION} is less than minimum supported version (${_boost_min_version})" + ) endif() # -------------- RUNTIME CONFIGURATION ---------------------------------------- -# Use the multithreaded version of Boost -# NB: This _must_ be a cache variable as it -# controls the tagged layout of Boost library names -set(Boost_USE_MULTITHREADED ON CACHE BOOL "Enable multithreaded Boost libraries") +# Use the multithreaded version of Boost NB: This _must_ be a cache variable as it +# controls the tagged layout of Boost library names +set(Boost_USE_MULTITHREADED + ON + CACHE BOOL "Enable multithreaded Boost libraries") -# Don't use libraries linked statically to the C++ runtime -# NB: This _must_ be a cache variable as it -# controls the tagged layout of Boost library names -set(Boost_USE_STATIC_RUNTIME OFF CACHE BOOL - "Enable usage of libraries statically linked to C++ runtime") +# Don't use libraries linked statically to the C++ runtime NB: This _must_ be a cache +# variable as it controls the tagged layout of Boost library names +set(Boost_USE_STATIC_RUNTIME + OFF + CACHE BOOL "Enable usage of libraries statically linked to C++ runtime") # If using multithreaded Boost, make sure Threads has been intialized if(Boost_USE_MULTITHREADED AND NOT DEFINED CMAKE_THREAD_LIBS_INIT) - find_package(Threads) + find_package(Threads) endif() # Enable debug output from FindBoost -set(Boost_DEBUG OFF CACHE BOOL "Enable debug output from FindBoost") +set(Boost_DEBUG + OFF + CACHE BOOL "Enable debug output from FindBoost") # -------------- PATHS -------------------------------------------------------- # By default, search system paths -set(Boost_NO_SYSTEM_PATHS OFF CACHE BOOL "Disable searching in locations not specified by hint variables") +set(Boost_NO_SYSTEM_PATHS + OFF + CACHE BOOL "Disable searching in locations not specified by hint variables") -# A sanity check -# This must be done _before_ the cache variables are set +# A sanity check This must be done _before_ the cache variables are set if(PATH_BOOST AND Boost_ROOT_DIR) - message(FATAL_ERROR "PATH_BOOST AND Boost_ROOT_DIR both specified. Please provide only one") + message( + FATAL_ERROR + "PATH_BOOST AND Boost_ROOT_DIR both specified. Please provide only one") endif() # Provide a default root directory if(NOT PATH_BOOST AND NOT Boost_ROOT_DIR) - set(PATH_BOOST "/usr") + set(PATH_BOOST "/usr") endif() # Set the default location to look for Boost -set(Boost_ROOT_DIR ${PATH_BOOST} CACHE PATH "Base directory the of Boost installation") +set(Boost_ROOT_DIR + ${PATH_BOOST} + CACHE PATH "Base directory the of Boost installation") # In FindBoost, Boost_ROOT_DIR is spelled BOOST_ROOT set(BOOST_ROOT ${Boost_ROOT_DIR}) @@ -113,25 +126,26 @@ list(APPEND _boost_defines -DBOOST_ALL_NO_LIB=1) # Disable generating serialization code in boost::multi_index list(APPEND _boost_defines -DBOOST_MULTI_INDEX_DISABLE_SERIALIZATION) - -# There are broken versions of MSVC that won't handle variadic templates -# correctly (despite the C++11 test case passing). + +# There are broken versions of MSVC that won't handle variadic templates correctly +# (despite the C++11 test case passing). if(MSVC) - list(APPEND _boost_defines -DBOOST_NO_CXX11_VARIADIC_TEMPLATES) + list(APPEND _boost_defines -DBOOST_NO_CXX11_VARIADIC_TEMPLATES) endif() -set(Boost_DEFINES ${_boost_defines} CACHE STRING "Boost compiler defines") +set(Boost_DEFINES + ${_boost_defines} + CACHE STRING "Boost compiler defines") add_definitions(${Boost_DEFINES}) # -------------- INTERNALS ---------------------------------------------------- -# Disable Boost's own CMake as it's known to be buggy -# NB: This should not be a cache variable +# Disable Boost's own CMake as it's known to be buggy NB: This should not be a cache +# variable set(Boost_NO_BOOST_CMAKE ON) -# The required Boost library components -# NB: These are just the ones that require compilation/linking -# This should _not_ be a cache variable +# The required Boost library components NB: These are just the ones that require +# compilation/linking This should _not_ be a cache variable set(_boost_components atomic chrono date_time filesystem thread timer) find_package(Boost ${Boost_MIN_VERSION} COMPONENTS ${_boost_components}) @@ -139,120 +153,142 @@ find_package(Boost ${Boost_MIN_VERSION} COMPONENTS ${_boost_components}) # -------------- SOURCE BUILD ------------------------------------------------- if(Boost_FOUND) - # Force the cache entries to be updated - # Normally, these would not be exported. However, we need them in the Testsuite - set(Boost_INCLUDE_DIRS ${Boost_INCLUDE_DIRS} CACHE PATH "Boost include directory" FORCE) - set(Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIRS} CACHE PATH "Boost library directory" FORCE) - set(Boost_INCLUDE_DIR ${Boost_INCLUDE_DIR} CACHE PATH "Boost include directory" FORCE) - add_library(boost SHARED IMPORTED) + # Force the cache entries to be updated Normally, these would not be exported. + # However, we need them in the Testsuite + set(Boost_INCLUDE_DIRS + ${Boost_INCLUDE_DIRS} + CACHE PATH "Boost include directory" FORCE) + set(Boost_LIBRARY_DIRS + ${Boost_LIBRARY_DIRS} + CACHE PATH "Boost library directory" FORCE) + set(Boost_INCLUDE_DIR + ${Boost_INCLUDE_DIR} + CACHE PATH "Boost include directory" FORCE) + add_library(boost SHARED IMPORTED) elseif(NOT Boost_FOUND AND STERILE_BUILD) - message(FATAL_ERROR "Boost not found and cannot be downloaded because build is sterile.") + message( + FATAL_ERROR "Boost not found and cannot be downloaded because build is sterile.") else() - # If we didn't find a suitable version on the system, then download one from the web - set(_boost_download_version "1.69.0") - - # If the user specifies a version other than _boost_download_version, use that version. - # NB: We know Boost_MIN_VERSION is >= _boost_min_version from earlier checks - if(${Boost_MIN_VERSION} VERSION_LESS ${_boost_download_version} OR - ${Boost_MIN_VERSION} VERSION_GREATER ${_boost_download_version}) - set(_boost_download_version ${Boost_MIN_VERSION}) - endif() - message(STATUS "${Boost_ERROR_REASON}") - message(STATUS "Attempting to build ${_boost_download_version} as external project") - - # This is an internal consistency check. Normal users should not trip this since - # they cannot affect _boost_download_version. - if(${_boost_download_version} VERSION_LESS ${Boost_MIN_VERSION}) - message(FATAL_ERROR "Download version of Boost (${_boost_download_version}) " + # If we didn't find a suitable version on the system, then download one from the web + set(_boost_download_version "1.69.0") + + # If the user specifies a version other than _boost_download_version, use that + # version. NB: We know Boost_MIN_VERSION is >= _boost_min_version from earlier checks + if(${Boost_MIN_VERSION} VERSION_LESS ${_boost_download_version} + OR ${Boost_MIN_VERSION} VERSION_GREATER ${_boost_download_version}) + set(_boost_download_version ${Boost_MIN_VERSION}) + endif() + message(STATUS "${Boost_ERROR_REASON}") + message(STATUS "Attempting to build ${_boost_download_version} as external project") + + # This is an internal consistency check. Normal users should not trip this since they + # cannot affect _boost_download_version. + if(${_boost_download_version} VERSION_LESS ${Boost_MIN_VERSION}) + message( + FATAL_ERROR "Download version of Boost (${_boost_download_version}) " "is older than minimum allowed version (${Boost_MIN_VERSION})") - endif() - - if(Boost_USE_MULTITHREADED) - set(_boost_threading multi) - else() - set(_boost_threading single) - endif() - - if(Boost_USE_STATIC_RUNTIME) - set(_boost_runtime_link static) - else() - set(_boost_runtime_link shared) - endif() - - # Change the base directory - set(Boost_ROOT_DIR ${CMAKE_INSTALL_PREFIX} CACHE PATH "Base directory the of Boost installation" FORCE) - - # Update the exported variables - set(Boost_INCLUDE_DIRS ${Boost_ROOT_DIR}/include CACHE PATH "Boost include directory" FORCE) - set(Boost_LIBRARY_DIRS ${Boost_ROOT_DIR}/lib CACHE PATH "Boost library directory" FORCE) - set(Boost_INCLUDE_DIR ${Boost_INCLUDE_DIRS} CACHE PATH "Boost include directory" FORCE) - - set(BOOST_ARGS - --ignore-site-config - --link=static - --runtime-link=${_boost_runtime_link} - --threading=${_boost_threading}) - if(WIN32) - # NB: We need to build both debug/release on windows - # as we don't use CMAKE_BUILD_TYPE - set(BOOST_BOOTSTRAP call bootstrap.bat) - set(BOOST_BUILD ".\\b2") - if(CMAKE_SIZEOF_VOID_P STREQUAL "8") - list(APPEND BOOST_ARGS address-model=64) endif() - else() - set(BOOST_BOOTSTRAP "./bootstrap.sh") - set(BOOST_BUILD "./b2") - if(CMAKE_BUILD_TYPE STREQUAL "Debug") - list(APPEND BOOST_ARGS variant=debug) + + if(Boost_USE_MULTITHREADED) + set(_boost_threading multi) else() - list(APPEND BOOST_ARGS variant=release) + set(_boost_threading single) endif() - endif() - - # Join the component names together to pass to --with-libraries during bootstrap - set(_boost_lib_names "") - foreach(c ${_boost_components}) - # list(JOIN ...) is in cmake 3.12 - string(CONCAT _boost_lib_names "${_boost_lib_names}${c},") - endforeach() - - include(ExternalProject) - string(REPLACE "." "_" _boost_download_filename ${_boost_download_version}) - ExternalProject_Add( - boost - PREFIX ${CMAKE_BINARY_DIR}/boost - URL http://downloads.sourceforge.net/project/boost/boost/${_boost_download_version}/boost_${_boost_download_filename}.zip - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} ${BOOST_BOOTSTRAP} --prefix=${Boost_ROOT_DIR} --with-libraries=${_boost_lib_names} - BUILD_COMMAND ${BOOST_BUILD} ${BOOST_ARGS} install - INSTALL_COMMAND "" - ) - - if(WIN32) - # We need to specify different library names for debug vs release - set(Boost_LIBRARIES "") - foreach(c ${_boost_components}) - list(APPEND Boost_LIBRARIES "optimized libboost_${c} debug libboost_${c}-gd ") - - # Also export cache variables for the file location of each library - string(TOUPPER ${c} _basename) - set(Boost_${_basename}_LIBRARY_RELEASE "${Boost_LIBRARY_DIRS}/libboost_${c}.dll" CACHE FILEPATH "" FORCE) - set(Boost_${_basename}_LIBRARY_DEBUG "${Boost_LIBRARY_DIRS}/libboost_${c}-gd.dll" CACHE FILEPATH "" FORCE) - endforeach() - else() - # Transform the component names into the library filenames - # e.g., system -> boost_system - set(Boost_LIBRARIES "") + + if(Boost_USE_STATIC_RUNTIME) + set(_boost_runtime_link static) + else() + set(_boost_runtime_link shared) + endif() + + # Change the base directory + set(Boost_ROOT_DIR + ${CMAKE_INSTALL_PREFIX} + CACHE PATH "Base directory the of Boost installation" FORCE) + + # Update the exported variables + set(Boost_INCLUDE_DIRS + ${Boost_ROOT_DIR}/include + CACHE PATH "Boost include directory" FORCE) + set(Boost_LIBRARY_DIRS + ${Boost_ROOT_DIR}/lib + CACHE PATH "Boost library directory" FORCE) + set(Boost_INCLUDE_DIR + ${Boost_INCLUDE_DIRS} + CACHE PATH "Boost include directory" FORCE) + + set(BOOST_ARGS --ignore-site-config --link=static + --runtime-link=${_boost_runtime_link} --threading=${_boost_threading}) + if(WIN32) + # NB: We need to build both debug/release on windows as we don't use + # CMAKE_BUILD_TYPE + set(BOOST_BOOTSTRAP call bootstrap.bat) + set(BOOST_BUILD ".\\b2") + if(CMAKE_SIZEOF_VOID_P STREQUAL "8") + list(APPEND BOOST_ARGS address-model=64) + endif() + else() + set(BOOST_BOOTSTRAP "./bootstrap.sh") + set(BOOST_BUILD "./b2") + if(CMAKE_BUILD_TYPE STREQUAL "Debug") + list(APPEND BOOST_ARGS variant=debug) + else() + list(APPEND BOOST_ARGS variant=release) + endif() + endif() + + # Join the component names together to pass to --with-libraries during bootstrap + set(_boost_lib_names "") foreach(c ${_boost_components}) - list(APPEND Boost_LIBRARIES "${Boost_LIBRARY_DIRS}/libboost_${c}.so") - - # Also export cache variables for the file location of each library - string(TOUPPER ${c} _basename) - set(Boost_${_basename}_LIBRARY_RELEASE "${Boost_LIBRARY_DIRS}/libboost_${c}.so" CACHE FILEPATH "" FORCE) - set(Boost_${_basename}_LIBRARY_DEBUG "${Boost_LIBRARY_DIRS}/libboost_${c}.so" CACHE FILEPATH "" FORCE) + # list(JOIN ...) is in cmake 3.12 + string(CONCAT _boost_lib_names "${_boost_lib_names}${c},") endforeach() - endif() + + include(ExternalProject) + string(REPLACE "." "_" _boost_download_filename ${_boost_download_version}) + externalproject_add( + boost + PREFIX ${CMAKE_BINARY_DIR}/boost + URL http://downloads.sourceforge.net/project/boost/boost/${_boost_download_version}/boost_${_boost_download_filename}.zip + BUILD_IN_SOURCE 1 + CONFIGURE_COMMAND + CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} ${BOOST_BOOTSTRAP} + --prefix=${Boost_ROOT_DIR} --with-libraries=${_boost_lib_names} + BUILD_COMMAND ${BOOST_BUILD} ${BOOST_ARGS} install + INSTALL_COMMAND "") + + if(WIN32) + # We need to specify different library names for debug vs release + set(Boost_LIBRARIES "") + foreach(c ${_boost_components}) + list(APPEND Boost_LIBRARIES "optimized libboost_${c} debug libboost_${c}-gd ") + + # Also export cache variables for the file location of each library + string(TOUPPER ${c} _basename) + set(Boost_${_basename}_LIBRARY_RELEASE + "${Boost_LIBRARY_DIRS}/libboost_${c}.dll" + CACHE FILEPATH "" FORCE) + set(Boost_${_basename}_LIBRARY_DEBUG + "${Boost_LIBRARY_DIRS}/libboost_${c}-gd.dll" + CACHE FILEPATH "" FORCE) + endforeach() + else() + # Transform the component names into the library filenames e.g., system -> + # boost_system + set(Boost_LIBRARIES "") + foreach(c ${_boost_components}) + list(APPEND Boost_LIBRARIES "${Boost_LIBRARY_DIRS}/libboost_${c}.so") + + # Also export cache variables for the file location of each library + string(TOUPPER ${c} _basename) + set(Boost_${_basename}_LIBRARY_RELEASE + "${Boost_LIBRARY_DIRS}/libboost_${c}.so" + CACHE FILEPATH "" FORCE) + set(Boost_${_basename}_LIBRARY_DEBUG + "${Boost_LIBRARY_DIRS}/libboost_${c}.so" + CACHE FILEPATH "" FORCE) + endforeach() + endif() endif() # -------------- EXPORT VARIABLES --------------------------------------------- @@ -260,18 +296,22 @@ endif() # Export Boost_THREAD_LIBRARY list(FIND _boost_components "thread" _building_threads) if(Boost_USE_MULTITHREADED AND ${_building_threads}) - # On Windows, always use the debug version - # On Linux, we don't use tagged builds, so the debug/release filenames are the same - set(Boost_THREAD_LIBRARY ${Boost_THREAD_LIBRARY_DEBUG} CACHE FILEPATH "Boost thread library") + # On Windows, always use the debug version On Linux, we don't use tagged builds, so + # the debug/release filenames are the same + set(Boost_THREAD_LIBRARY + ${Boost_THREAD_LIBRARY_DEBUG} + CACHE FILEPATH "Boost thread library") endif() # Add the system thread library if(Boost_USE_MULTITHREADED) - list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) + list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) endif() # Export the complete set of libraries -set(Boost_LIBRARIES ${Boost_LIBRARIES} CACHE FILEPATH "Boost library files" FORCE) +set(Boost_LIBRARIES + ${Boost_LIBRARIES} + CACHE FILEPATH "Boost library files" FORCE) link_directories(${Boost_LIBRARY_DIRS}) include_directories(SYSTEM ${Boost_INCLUDE_DIRS}) diff --git a/cmake/DyninstConfig.cmake.in b/cmake/DyninstConfig.cmake.in index 7578e4687c..9fa155d3fc 100644 --- a/cmake/DyninstConfig.cmake.in +++ b/cmake/DyninstConfig.cmake.in @@ -8,37 +8,35 @@ # compute paths get_filename_component(DYNINST_CMAKE_DIR "${CMAKE_CURRENT_LIST_FILE}" PATH) -set (DYNINST_INCLUDE_DIR @CONF_INCLUDE_DIRS@) +set(DYNINST_INCLUDE_DIR @CONF_INCLUDE_DIRS@) -# Library dependencies -#include ("${DYNINST_CMAKE_DIR}/DyninstTargets.cmake") +# Library dependencies include ("${DYNINST_CMAKE_DIR}/DyninstTargets.cmake") foreach(TARG @ALL_DYNINST_TARGETS@) - include ("${DYNINST_CMAKE_DIR}/${TARG}Targets.cmake" OPTIONAL) + include("${DYNINST_CMAKE_DIR}/${TARG}Targets.cmake" OPTIONAL) endforeach() -set (DYNINST_LIBRARIES "dyninstAPI") +set(DYNINST_LIBRARIES "dyninstAPI") # Other variables Dyninst mutators may depend on -set (DYNINST_PLATFORM "@PLATFORM@") -set (DYNINST_INTERNAL_DEFINES @UNIFIED_DEFINES@) +set(DYNINST_PLATFORM "@PLATFORM@") +set(DYNINST_INTERNAL_DEFINES @UNIFIED_DEFINES@) if(DYNINST_FIND_COMPONENTS) - foreach(COMP DYNINST_FIND_COMPONENTS) - if(NOT TARGET ${COMP}) - set(DYNINST_${COMP}_FOUND 0) - if(DYNINST_FIND_REQUIRED_${COMP}) - MESSAGE(ERROR "${COMP} was not part of the Dyninst build") - endif() - else() - set(DYNINST_${COMP}_FOUND 1) - MESSAGE(STATUS "Found ${COMP}") - endif() - endforeach() + foreach(COMP DYNINST_FIND_COMPONENTS) + if(NOT TARGET ${COMP}) + set(DYNINST_${COMP}_FOUND 0) + if(DYNINST_FIND_REQUIRED_${COMP}) + message(ERROR "${COMP} was not part of the Dyninst build") + endif() + else() + set(DYNINST_${COMP}_FOUND 1) + message(STATUS "Found ${COMP}") + endif() + endforeach() endif() if(TARGET dyninstAPI) - set(Dyninst_FOUND 1) + set(Dyninst_FOUND 1) else() - set(Dyninst_FOUND 0) + set(Dyninst_FOUND 0) endif() - diff --git a/cmake/DyninstConfigVersion.cmake.in b/cmake/DyninstConfigVersion.cmake.in index 8090b4e768..985c4c4281 100644 --- a/cmake/DyninstConfigVersion.cmake.in +++ b/cmake/DyninstConfigVersion.cmake.in @@ -1,7 +1,7 @@ -set (PACKAGE_VERSION "@DYNINST_VERSION@") +set(PACKAGE_VERSION "@DYNINST_VERSION@") -if ("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") - set (PACKAGE_VERSION_COMPATIBLE FALSE) +if("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") + set(PACKAGE_VERSION_COMPATIBLE FALSE) else() - set (PACKAGE_VERSION_COMPATIBLE TRUE) + set(PACKAGE_VERSION_COMPATIBLE TRUE) endif() diff --git a/cmake/ElfUtils.cmake b/cmake/ElfUtils.cmake index 7eeb3f1b84..fcea960ed8 100644 --- a/cmake/ElfUtils.cmake +++ b/cmake/ElfUtils.cmake @@ -28,46 +28,52 @@ # #====================================================================================== -if(LibElf_FOUND AND LibDwarf_FOUND AND NOT ENABLE_DEBUGINFOD) - return() +if(LibElf_FOUND + AND LibDwarf_FOUND + AND NOT ENABLE_DEBUGINFOD) + return() endif() if(NOT UNIX) - return() + return() endif() -# Minimum acceptable version of elfutils -# NB: We need >=0.186 because of NVIDIA line map extensions +# Minimum acceptable version of elfutils NB: We need >=0.186 because of NVIDIA line map +# extensions set(_min_version 0.186) -set(ElfUtils_MIN_VERSION ${_min_version} +set(ElfUtils_MIN_VERSION + ${_min_version} CACHE STRING "Minimum acceptable elfutils version") if(${ElfUtils_MIN_VERSION} VERSION_LESS ${_min_version}) - message( - FATAL_ERROR - "Requested version ${ElfUtils_MIN_VERSION} is less than minimum supported version (${_min_version})" - ) + message( + FATAL_ERROR + "Requested version ${ElfUtils_MIN_VERSION} is less than minimum supported version (${_min_version})" + ) endif() # -------------- PATHS -------------------------------------------------------- # Base directory the of elfutils installation -set(ElfUtils_ROOT_DIR "/usr" +set(ElfUtils_ROOT_DIR + "/usr" CACHE PATH "Base directory the of elfutils installation") # Hint directory that contains the elfutils headers files -set(ElfUtils_INCLUDEDIR "${ElfUtils_ROOT_DIR}/include" +set(ElfUtils_INCLUDEDIR + "${ElfUtils_ROOT_DIR}/include" CACHE PATH "Hint directory that contains the elfutils headers files") # Hint directory that contains the elfutils library files -set(ElfUtils_LIBRARYDIR "${ElfUtils_ROOT_DIR}/lib" +set(ElfUtils_LIBRARYDIR + "${ElfUtils_ROOT_DIR}/lib" CACHE PATH "Hint directory that contains the elfutils library files") # libelf/dwarf-specific directory hints foreach(l LibElf LibDwarf LibDebuginfod) - foreach(d ROOT_DIR INCLUDEDIR LIBRARYDIR) - set(${l}_${d} ${ElfUtils_${d}}) - endforeach() + foreach(d ROOT_DIR INCLUDEDIR LIBRARYDIR) + set(${l}_${d} ${ElfUtils_${d}}) + endforeach() endforeach() # -------------- PACKAGES------------------------------------------------------ @@ -76,89 +82,94 @@ find_package(LibElf ${ElfUtils_MIN_VERSION}) # Don't search for libdw or libdebuginfod if we didn't find a suitable libelf if(LibElf_FOUND) - find_package(LibDwarf ${ElfUtils_MIN_VERSION}) - if (ENABLE_DEBUGINFOD) - find_package(LibDebuginfod ${ElfUtils_MIN_VERSION} REQUIRED) - endif() + find_package(LibDwarf ${ElfUtils_MIN_VERSION}) + if(ENABLE_DEBUGINFOD) + find_package(LibDebuginfod ${ElfUtils_MIN_VERSION} REQUIRED) + endif() endif() # -------------- SOURCE BUILD ------------------------------------------------- -if(LibElf_FOUND AND LibDwarf_FOUND AND (NOT ENABLE_DEBUGINFOD OR LibDebuginfod_FOUND)) - if(ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) - set(_eu_root ${ElfUtils_ROOT_DIR}) - set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS} ${LibDebuginfod_INCLUDE_DIRS}) - set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS} ${LibDebuginfod_LIBRARY_DIRS}) - set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES} ${LibDebuginfod_LIBRARIES}) - else() - set(_eu_root ${ElfUtils_ROOT_DIR}) - set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS}) - set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS}) - set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES}) - endif() - add_library(ElfUtils SHARED IMPORTED) +if(LibElf_FOUND + AND LibDwarf_FOUND + AND (NOT ENABLE_DEBUGINFOD OR LibDebuginfod_FOUND)) + if(ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) + set(_eu_root ${ElfUtils_ROOT_DIR}) + set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS} + ${LibDebuginfod_INCLUDE_DIRS}) + set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS} + ${LibDebuginfod_LIBRARY_DIRS}) + set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES} ${LibDebuginfod_LIBRARIES}) + else() + set(_eu_root ${ElfUtils_ROOT_DIR}) + set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS}) + set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS}) + set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES}) + endif() + add_library(ElfUtils SHARED IMPORTED) elseif(NOT (LibElf_FOUND AND LibDwarf_FOUND) AND STERILE_BUILD) - message(FATAL_ERROR "Elfutils not found and cannot be downloaded because build is sterile.") + message( + FATAL_ERROR + "Elfutils not found and cannot be downloaded because build is sterile.") else() - # If we didn't find a suitable version on the system, then download one from the web - # NB: When building from source, we need at least elfutils-0.176 in order to use - # the --enable-install-elf option - set(_elfutils_download_version 0.176) - - # If the user specified a version newer than _elfutils_download_version, use that version. - # NB: We know ElfUtils_MIN_VERSION is >= _min_version from earlier checks - if(${ElfUtils_MIN_VERSION} VERSION_GREATER ${_elfutils_download_version}) - set(_elfutils_download_version ${ElfUtils_MIN_VERSION}) - endif() - - message(STATUS "${ElfUtils_ERROR_REASON}") - message( STATUS "Attempting to build elfutils(${_elfutils_download_version}) as external project") - - if(NOT (${CMAKE_CXX_COMPILER_ID} STREQUAL "GNU") OR NOT (${CMAKE_C_COMPILER_ID} STREQUAL "GNU")) - message(FATAL_ERROR "ElfUtils will only build with the GNU compiler") - endif() - - include(ExternalProject) - externalproject_add( - ElfUtils - PREFIX ${CMAKE_BINARY_DIR}/elfutils - URL https://sourceware.org/elfutils/ftp/${_elfutils_download_version}/elfutils-${_elfutils_download_version}.tar.bz2 - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND - CFLAGS=-g - CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} - /configure - --enable-install-elfh - --prefix=${CMAKE_INSTALL_PREFIX} - --disable-debuginfod - BUILD_COMMAND make install - INSTALL_COMMAND "" - ) - - set(_eu_root ${CMAKE_INSTALL_PREFIX}) - set(_eu_inc_dirs ${CMAKE_INSTALL_PREFIX}/include - ${CMAKE_INSTALL_PREFIX}/include/elfutils) - set(_eu_lib_dirs ${CMAKE_INSTALL_PREFIX}/lib - ${CMAKE_INSTALL_PREFIX}/lib/elfutils) - set(_eu_libs ${_eu_root}/lib/libelf.so ${_eu_root}/lib/libdw.so) + # If we didn't find a suitable version on the system, then download one from the web + # NB: When building from source, we need at least elfutils-0.176 in order to use the + # --enable-install-elf option + set(_elfutils_download_version 0.176) + + # If the user specified a version newer than _elfutils_download_version, use that + # version. NB: We know ElfUtils_MIN_VERSION is >= _min_version from earlier checks + if(${ElfUtils_MIN_VERSION} VERSION_GREATER ${_elfutils_download_version}) + set(_elfutils_download_version ${ElfUtils_MIN_VERSION}) + endif() + + message(STATUS "${ElfUtils_ERROR_REASON}") + message( + STATUS + "Attempting to build elfutils(${_elfutils_download_version}) as external project" + ) + + if(NOT (${CMAKE_CXX_COMPILER_ID} STREQUAL "GNU") OR NOT (${CMAKE_C_COMPILER_ID} + STREQUAL "GNU")) + message(FATAL_ERROR "ElfUtils will only build with the GNU compiler") + endif() + + include(ExternalProject) + externalproject_add( + ElfUtils + PREFIX ${CMAKE_BINARY_DIR}/elfutils + URL https://sourceware.org/elfutils/ftp/${_elfutils_download_version}/elfutils-${_elfutils_download_version}.tar.bz2 + BUILD_IN_SOURCE 1 + CONFIGURE_COMMAND + CFLAGS=-g CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} + /configure --enable-install-elfh --prefix=${CMAKE_INSTALL_PREFIX} + --disable-debuginfod + BUILD_COMMAND make install + INSTALL_COMMAND "") + + set(_eu_root ${CMAKE_INSTALL_PREFIX}) + set(_eu_inc_dirs ${CMAKE_INSTALL_PREFIX}/include + ${CMAKE_INSTALL_PREFIX}/include/elfutils) + set(_eu_lib_dirs ${CMAKE_INSTALL_PREFIX}/lib ${CMAKE_INSTALL_PREFIX}/lib/elfutils) + set(_eu_libs ${_eu_root}/lib/libelf.so ${_eu_root}/lib/libdw.so) endif() # -------------- EXPORT VARIABLES --------------------------------------------- -set(ElfUtils_ROOT_DIR ${_eu_root} - CACHE PATH "Base directory the of elfutils installation" - FORCE) -set(ElfUtils_INCLUDE_DIRS ${_eu_inc_dirs} - CACHE PATH "elfutils include directory" - FORCE) -set(ElfUtils_LIBRARY_DIRS ${_eu_lib_dirs} - CACHE PATH "elfutils library directory" - FORCE) -set(ElfUtils_INCLUDE_DIR ${ElfUtils_INCLUDE_DIRS} - CACHE PATH "elfutils include directory" - FORCE) -set(ElfUtils_LIBRARIES ${_eu_libs} - CACHE FILEPATH "elfutils library files" - FORCE) +set(ElfUtils_ROOT_DIR + ${_eu_root} + CACHE PATH "Base directory the of elfutils installation" FORCE) +set(ElfUtils_INCLUDE_DIRS + ${_eu_inc_dirs} + CACHE PATH "elfutils include directory" FORCE) +set(ElfUtils_LIBRARY_DIRS + ${_eu_lib_dirs} + CACHE PATH "elfutils library directory" FORCE) +set(ElfUtils_INCLUDE_DIR + ${ElfUtils_INCLUDE_DIRS} + CACHE PATH "elfutils include directory" FORCE) +set(ElfUtils_LIBRARIES + ${_eu_libs} + CACHE FILEPATH "elfutils library files" FORCE) link_directories(${ElfUtils_LIBRARY_DIRS}) include_directories(${ElfUtils_INCLUDE_DIRS}) diff --git a/cmake/LanguageStandards.cmake b/cmake/LanguageStandards.cmake index 6d16fae3a4..66fece8784 100644 --- a/cmake/LanguageStandards.cmake +++ b/cmake/LanguageStandards.cmake @@ -9,8 +9,12 @@ # C/C++ language standard cmake options. # -set(DYNINST_CXX_LANGUAGE_STANDARD "11" CACHE STRING "C++ language standard version.") -set(DYNINST_C_LANGUAGE_STANDARD "11" CACHE STRING "C language standard version.") +set(DYNINST_CXX_LANGUAGE_STANDARD + "11" + CACHE STRING "C++ language standard version.") +set(DYNINST_C_LANGUAGE_STANDARD + "11" + CACHE STRING "C language standard version.") # # -------- C++ language features ---------------- @@ -26,12 +30,11 @@ set(CMAKE_CXX_STANDARD_REQUIRED ON) # Require the standards-compliant C++11 ABI for gcc if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") - if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS "6.0") - message(FATAL_ERROR "Dyninst requires gcc >= 6.0") - endif() + if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS "6.0") + message(FATAL_ERROR "Dyninst requires gcc >= 6.0") + endif() endif() - # # -------- C language features ---------------- # diff --git a/cmake/LibIberty.cmake b/cmake/LibIberty.cmake index 1d2ff1c537..02ed6fb18b 100644 --- a/cmake/LibIberty.cmake +++ b/cmake/LibIberty.cmake @@ -22,46 +22,48 @@ #====================================================================================== if(LibIberty_FOUND) - return() + return() endif() if(NOT UNIX) - return() + return() endif() # -------------- PATHS -------------------------------------------------------- # Base directory the of LibIberty installation -set(LibIberty_ROOT_DIR "/usr" +set(LibIberty_ROOT_DIR + "/usr" CACHE PATH "Base directory the of LibIberty installation") # Hint directory that contains the LibIberty library files -set(LibIberty_LIBRARYDIR "${LibIberty_ROOT_DIR}/lib" +set(LibIberty_LIBRARYDIR + "${LibIberty_ROOT_DIR}/lib" CACHE PATH "Hint directory that contains the LibIberty library files") # -------------- PACKAGES ----------------------------------------------------- find_package(LibIberty REQUIRED) - # -------------- EXPORT VARIABLES --------------------------------------------- add_library(LibIberty STATIC IMPORTED GLOBAL) set_target_properties(LibIberty PROPERTIES IMPORTED_LOCATION ${LibIberty_LIBRARIES}) -set_target_properties(LibIberty PROPERTIES INTERFACE_INCLUDE_DIRECTORIES ${LibIberty_INCLUDE_DIRS}) +set_target_properties(LibIberty PROPERTIES INTERFACE_INCLUDE_DIRECTORIES + ${LibIberty_INCLUDE_DIRS}) -set(LibIberty_ROOT_DIR ${LibIberty_ROOT_DIR} - CACHE PATH "Base directory the of LibIberty installation" - FORCE) -set(LibIberty_INCLUDE_DIRS ${LibIberty_INCLUDE_DIRS} - CACHE PATH "LibIberty include directories" - FORCE) -set(LibIberty_LIBRARY_DIRS ${LibIberty_LIBRARY_DIRS} - CACHE PATH "LibIberty library directory" - FORCE) -set(LibIberty_LIBRARIES ${LibIberty_LIBRARIES} - CACHE FILEPATH "LibIberty library files" - FORCE) +set(LibIberty_ROOT_DIR + ${LibIberty_ROOT_DIR} + CACHE PATH "Base directory the of LibIberty installation" FORCE) +set(LibIberty_INCLUDE_DIRS + ${LibIberty_INCLUDE_DIRS} + CACHE PATH "LibIberty include directories" FORCE) +set(LibIberty_LIBRARY_DIRS + ${LibIberty_LIBRARY_DIRS} + CACHE PATH "LibIberty library directory" FORCE) +set(LibIberty_LIBRARIES + ${LibIberty_LIBRARIES} + CACHE FILEPATH "LibIberty library files" FORCE) # For backward compatibility only set(IBERTY_LIBRARIES ${LibIberty_LIBRARIES}) diff --git a/cmake/Modules/DyninstSystemPaths.cmake b/cmake/Modules/DyninstSystemPaths.cmake index ebabc6451d..6046632817 100644 --- a/cmake/Modules/DyninstSystemPaths.cmake +++ b/cmake/Modules/DyninstSystemPaths.cmake @@ -5,8 +5,10 @@ set(DYNINST_SYSTEM_INCLUDE_PATHS /opt/include /opt/local/include /sw/include - ENV CPATH - ENV PATH) + ENV + CPATH + ENV + PATH) set(DYNINST_SYSTEM_LIBRARY_PATHS /usr/lib @@ -17,6 +19,9 @@ set(DYNINST_SYSTEM_LIBRARY_PATHS /opt/local/lib /opt/local/lib64 /sw/lib - ENV LIBRARY_PATH - ENV LD_LIBRARY_PATH - ENV PATH) + ENV + LIBRARY_PATH + ENV + LD_LIBRARY_PATH + ENV + PATH) diff --git a/cmake/Modules/FindBoost.cmake b/cmake/Modules/FindBoost.cmake index 77c4bb9591..b3115e1dba 100644 --- a/cmake/Modules/FindBoost.cmake +++ b/cmake/Modules/FindBoost.cmake @@ -242,46 +242,45 @@ cmake_policy(PUSH) cmake_policy(SET CMP0057 NEW) # if IN_LIST -#------------------------------------------------------------------------------- -# Before we go searching, check whether boost-cmake is available, unless the -# user specifically asked NOT to search for boost-cmake. +# ------------------------------------------------------------------------------- +# Before we go searching, check whether boost-cmake is available, unless the user +# specifically asked NOT to search for boost-cmake. # -# If Boost_DIR is set, this behaves as any find_package call would. If not, -# it looks at BOOST_ROOT and BOOSTROOT to find Boost. +# If Boost_DIR is set, this behaves as any find_package call would. If not, it looks at +# BOOST_ROOT and BOOSTROOT to find Boost. # -if (NOT Boost_NO_BOOST_CMAKE) - # If Boost_DIR is not set, look for BOOSTROOT and BOOST_ROOT as alternatives, - # since these are more conventional for Boost. - if ("$ENV{Boost_DIR}" STREQUAL "") - if (NOT "$ENV{BOOST_ROOT}" STREQUAL "") - set(ENV{Boost_DIR} $ENV{BOOST_ROOT}) - elseif (NOT "$ENV{BOOSTROOT}" STREQUAL "") - set(ENV{Boost_DIR} $ENV{BOOSTROOT}) - endif() - endif() - - # Do the same find_package call but look specifically for the CMake version. - # Note that args are passed in the Boost_FIND_xxxxx variables, so there is no - # need to delegate them to this find_package call. - find_package(Boost QUIET NO_MODULE) - mark_as_advanced(Boost_DIR) - - # If we found boost-cmake, then we're done. Print out what we found. - # Otherwise let the rest of the module try to find it. - if (Boost_FOUND) - message(STATUS "Boost ${Boost_FIND_VERSION} found.") - if (Boost_FIND_COMPONENTS) - message(STATUS "Found Boost components:\n ${Boost_FIND_COMPONENTS}") - endif() - # Restore project's policies - cmake_policy(POP) - return() - endif() -endif() +if(NOT Boost_NO_BOOST_CMAKE) + # If Boost_DIR is not set, look for BOOSTROOT and BOOST_ROOT as alternatives, since + # these are more conventional for Boost. + if("$ENV{Boost_DIR}" STREQUAL "") + if(NOT "$ENV{BOOST_ROOT}" STREQUAL "") + set(ENV{Boost_DIR} $ENV{BOOST_ROOT}) + elseif(NOT "$ENV{BOOSTROOT}" STREQUAL "") + set(ENV{Boost_DIR} $ENV{BOOSTROOT}) + endif() + endif() + # Do the same find_package call but look specifically for the CMake version. Note that + # args are passed in the Boost_FIND_xxxxx variables, so there is no need to delegate + # them to this find_package call. + find_package(Boost QUIET NO_MODULE) + mark_as_advanced(Boost_DIR) + + # If we found boost-cmake, then we're done. Print out what we found. Otherwise let + # the rest of the module try to find it. + if(Boost_FOUND) + message(STATUS "Boost ${Boost_FIND_VERSION} found.") + if(Boost_FIND_COMPONENTS) + message(STATUS "Found Boost components:\n ${Boost_FIND_COMPONENTS}") + endif() + # Restore project's policies + cmake_policy(POP) + return() + endif() +endif() -#------------------------------------------------------------------------------- -# FindBoost functions & macros +# ------------------------------------------------------------------------------- +# FindBoost functions & macros # ############################################ @@ -297,1890 +296,2461 @@ endif() ######################################################################### macro(_Boost_ADJUST_LIB_VARS basename) - if(Boost_INCLUDE_DIR ) - if(Boost_${basename}_LIBRARY_DEBUG AND Boost_${basename}_LIBRARY_RELEASE) - # if the generator is multi-config or if CMAKE_BUILD_TYPE is set for - # single-config generators, set optimized and debug libraries - get_property(_isMultiConfig GLOBAL PROPERTY GENERATOR_IS_MULTI_CONFIG) - if(_isMultiConfig OR CMAKE_BUILD_TYPE) - set(Boost_${basename}_LIBRARY optimized ${Boost_${basename}_LIBRARY_RELEASE} debug ${Boost_${basename}_LIBRARY_DEBUG}) - else() - # For single-config generators where CMAKE_BUILD_TYPE has no value, - # just use the release libraries - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE} ) - endif() - # FIXME: This probably should be set for both cases - set(Boost_${basename}_LIBRARIES optimized ${Boost_${basename}_LIBRARY_RELEASE} debug ${Boost_${basename}_LIBRARY_DEBUG}) - endif() - - # if only the release version was found, set the debug variable also to the release version - if(Boost_${basename}_LIBRARY_RELEASE AND NOT Boost_${basename}_LIBRARY_DEBUG) - set(Boost_${basename}_LIBRARY_DEBUG ${Boost_${basename}_LIBRARY_RELEASE}) - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE}) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE}) - endif() - - # if only the debug version was found, set the release variable also to the debug version - if(Boost_${basename}_LIBRARY_DEBUG AND NOT Boost_${basename}_LIBRARY_RELEASE) - set(Boost_${basename}_LIBRARY_RELEASE ${Boost_${basename}_LIBRARY_DEBUG}) - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_DEBUG}) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_DEBUG}) - endif() - - # If the debug & release library ends up being the same, omit the keywords - if("${Boost_${basename}_LIBRARY_RELEASE}" STREQUAL "${Boost_${basename}_LIBRARY_DEBUG}") - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE} ) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE} ) - endif() - - if(Boost_${basename}_LIBRARY AND Boost_${basename}_HEADER) - set(Boost_${basename}_FOUND ON) - if("x${basename}" STREQUAL "xTHREAD" AND NOT TARGET Threads::Threads) - string(APPEND Boost_ERROR_REASON_THREAD " (missing dependency: Threads)") - set(Boost_THREAD_FOUND OFF) - endif() - endif() - - endif() - # Make variables changeable to the advanced user - mark_as_advanced( - Boost_${basename}_LIBRARY_RELEASE - Boost_${basename}_LIBRARY_DEBUG - ) + if(Boost_INCLUDE_DIR) + if(Boost_${basename}_LIBRARY_DEBUG AND Boost_${basename}_LIBRARY_RELEASE) + # if the generator is multi-config or if CMAKE_BUILD_TYPE is set for + # single-config generators, set optimized and debug libraries + get_property(_isMultiConfig GLOBAL PROPERTY GENERATOR_IS_MULTI_CONFIG) + if(_isMultiConfig OR CMAKE_BUILD_TYPE) + set(Boost_${basename}_LIBRARY + optimized ${Boost_${basename}_LIBRARY_RELEASE} debug + ${Boost_${basename}_LIBRARY_DEBUG}) + else() + # For single-config generators where CMAKE_BUILD_TYPE has no value, just + # use the release libraries + set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE}) + endif() + # FIXME: This probably should be set for both cases + set(Boost_${basename}_LIBRARIES + optimized ${Boost_${basename}_LIBRARY_RELEASE} debug + ${Boost_${basename}_LIBRARY_DEBUG}) + endif() + + # if only the release version was found, set the debug variable also to the + # release version + if(Boost_${basename}_LIBRARY_RELEASE AND NOT Boost_${basename}_LIBRARY_DEBUG) + set(Boost_${basename}_LIBRARY_DEBUG ${Boost_${basename}_LIBRARY_RELEASE}) + set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE}) + set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE}) + endif() + + # if only the debug version was found, set the release variable also to the debug + # version + if(Boost_${basename}_LIBRARY_DEBUG AND NOT Boost_${basename}_LIBRARY_RELEASE) + set(Boost_${basename}_LIBRARY_RELEASE ${Boost_${basename}_LIBRARY_DEBUG}) + set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_DEBUG}) + set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_DEBUG}) + endif() + + # If the debug & release library ends up being the same, omit the keywords + if("${Boost_${basename}_LIBRARY_RELEASE}" STREQUAL + "${Boost_${basename}_LIBRARY_DEBUG}") + set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE}) + set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE}) + endif() + + if(Boost_${basename}_LIBRARY AND Boost_${basename}_HEADER) + set(Boost_${basename}_FOUND ON) + if("x${basename}" STREQUAL "xTHREAD" AND NOT TARGET Threads::Threads) + string(APPEND Boost_ERROR_REASON_THREAD " (missing dependency: Threads)") + set(Boost_THREAD_FOUND OFF) + endif() + endif() + + endif() + # Make variables changeable to the advanced user + mark_as_advanced(Boost_${basename}_LIBRARY_RELEASE Boost_${basename}_LIBRARY_DEBUG) endmacro() -# Detect changes in used variables. -# Compares the current variable value with the last one. -# In short form: -# v != v_LAST -> CHANGED = 1 -# v is defined, v_LAST not -> CHANGED = 1 -# v is not defined, but v_LAST is -> CHANGED = 1 -# otherwise -> CHANGED = 0 +# Detect changes in used variables. Compares the current variable value with the last one. +# In short form: v != v_LAST -> CHANGED = 1 v is defined, v_LAST not +# -> CHANGED = 1 v is not defined, but v_LAST is -> CHANGED = 1 otherwise -> CHANGED = 0 # CHANGED is returned in variable named ${changed_var} macro(_Boost_CHANGE_DETECT changed_var) - set(${changed_var} 0) - foreach(v ${ARGN}) - if(DEFINED _Boost_COMPONENTS_SEARCHED) - if(${v}) - if(_${v}_LAST) - string(COMPARE NOTEQUAL "${${v}}" "${_${v}_LAST}" _${v}_CHANGED) + set(${changed_var} 0) + foreach(v ${ARGN}) + if(DEFINED _Boost_COMPONENTS_SEARCHED) + if(${v}) + if(_${v}_LAST) + string(COMPARE NOTEQUAL "${${v}}" "${_${v}_LAST}" _${v}_CHANGED) + else() + set(_${v}_CHANGED 1) + endif() + elseif(_${v}_LAST) + set(_${v}_CHANGED 1) + endif() + if(_${v}_CHANGED) + set(${changed_var} 1) + endif() else() - set(_${v}_CHANGED 1) + set(_${v}_CHANGED 0) endif() - elseif(_${v}_LAST) - set(_${v}_CHANGED 1) - endif() - if(_${v}_CHANGED) - set(${changed_var} 1) - endif() - else() - set(_${v}_CHANGED 0) - endif() - endforeach() + endforeach() endmacro() # -# Find the given library (var). -# Use 'build_type' to support different lib paths for RELEASE or DEBUG builds +# Find the given library (var). Use 'build_type' to support different lib paths for +# RELEASE or DEBUG builds # macro(_Boost_FIND_LIBRARY var build_type) - find_library(${var} ${ARGN}) + find_library(${var} ${ARGN}) - if(${var}) - # If this is the first library found then save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. - if(NOT Boost_LIBRARY_DIR_${build_type}) - get_filename_component(_dir "${${var}}" PATH) - set(Boost_LIBRARY_DIR_${build_type} "${_dir}" CACHE PATH "Boost library directory ${build_type}" FORCE) + if(${var}) + # If this is the first library found then save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. + if(NOT Boost_LIBRARY_DIR_${build_type}) + get_filename_component(_dir "${${var}}" PATH) + set(Boost_LIBRARY_DIR_${build_type} + "${_dir}" + CACHE PATH "Boost library directory ${build_type}" FORCE) + endif() + elseif(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) + # Try component-specific hints but do not save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. + find_library(${var} HINTS ${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT} ${ARGN}) endif() - elseif(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - # Try component-specific hints but do not save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. - find_library(${var} HINTS ${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT} ${ARGN}) - endif() - # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is known then search only there. - if(Boost_LIBRARY_DIR_${build_type}) - set(_boost_LIBRARY_SEARCH_DIRS_${build_type} ${Boost_LIBRARY_DIR_${build_type}} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " Boost_LIBRARY_DIR_${build_type} = ${Boost_LIBRARY_DIR_${build_type}}" - " _boost_LIBRARY_SEARCH_DIRS_${build_type} = ${_boost_LIBRARY_SEARCH_DIRS_${build_type}}") + # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is known then search only there. + if(Boost_LIBRARY_DIR_${build_type}) + set(_boost_LIBRARY_SEARCH_DIRS_${build_type} + ${Boost_LIBRARY_DIR_${build_type}} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) + if(Boost_DEBUG) + message( + STATUS + "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " Boost_LIBRARY_DIR_${build_type} = ${Boost_LIBRARY_DIR_${build_type}}" + " _boost_LIBRARY_SEARCH_DIRS_${build_type} = ${_boost_LIBRARY_SEARCH_DIRS_${build_type}}" + ) + endif() endif() - endif() endmacro() -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- # Convert CMAKE_CXX_COMPILER_VERSION to boost compiler suffix version. -function(_Boost_COMPILER_DUMPVERSION _OUTPUT_VERSION _OUTPUT_VERSION_MAJOR _OUTPUT_VERSION_MINOR) - string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\1" - _boost_COMPILER_VERSION_MAJOR "${CMAKE_CXX_COMPILER_VERSION}") - string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\2" - _boost_COMPILER_VERSION_MINOR "${CMAKE_CXX_COMPILER_VERSION}") - - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}${_boost_COMPILER_VERSION_MINOR}") - - set(${_OUTPUT_VERSION} ${_boost_COMPILER_VERSION} PARENT_SCOPE) - set(${_OUTPUT_VERSION_MAJOR} ${_boost_COMPILER_VERSION_MAJOR} PARENT_SCOPE) - set(${_OUTPUT_VERSION_MINOR} ${_boost_COMPILER_VERSION_MINOR} PARENT_SCOPE) +function(_Boost_COMPILER_DUMPVERSION _OUTPUT_VERSION _OUTPUT_VERSION_MAJOR + _OUTPUT_VERSION_MINOR) + string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\1" + _boost_COMPILER_VERSION_MAJOR "${CMAKE_CXX_COMPILER_VERSION}") + string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\2" + _boost_COMPILER_VERSION_MINOR "${CMAKE_CXX_COMPILER_VERSION}") + + set(_boost_COMPILER_VERSION + "${_boost_COMPILER_VERSION_MAJOR}${_boost_COMPILER_VERSION_MINOR}") + + set(${_OUTPUT_VERSION} + ${_boost_COMPILER_VERSION} + PARENT_SCOPE) + set(${_OUTPUT_VERSION_MAJOR} + ${_boost_COMPILER_VERSION_MAJOR} + PARENT_SCOPE) + set(${_OUTPUT_VERSION_MINOR} + ${_boost_COMPILER_VERSION_MINOR} + PARENT_SCOPE) endfunction() # -# Take a list of libraries with "thread" in it -# and prepend duplicates with "thread_${Boost_THREADAPI}" -# at the front of the list +# Take a list of libraries with "thread" in it and prepend duplicates with +# "thread_${Boost_THREADAPI}" at the front of the list # function(_Boost_PREPEND_LIST_WITH_THREADAPI _output) - set(_orig_libnames ${ARGN}) - string(REPLACE "thread" "thread_${Boost_THREADAPI}" _threadapi_libnames "${_orig_libnames}") - set(${_output} ${_threadapi_libnames} ${_orig_libnames} PARENT_SCOPE) + set(_orig_libnames ${ARGN}) + string(REPLACE "thread" "thread_${Boost_THREADAPI}" _threadapi_libnames + "${_orig_libnames}") + set(${_output} + ${_threadapi_libnames} ${_orig_libnames} + PARENT_SCOPE) endfunction() # # If a library is found, replace its cache entry with its REALPATH # function(_Boost_SWAP_WITH_REALPATH _library _docstring) - if(${_library}) - get_filename_component(_boost_filepathreal ${${_library}} REALPATH) - unset(${_library} CACHE) - set(${_library} ${_boost_filepathreal} CACHE FILEPATH "${_docstring}") - endif() + if(${_library}) + get_filename_component(_boost_filepathreal ${${_library}} REALPATH) + unset(${_library} CACHE) + set(${_library} + ${_boost_filepathreal} + CACHE FILEPATH "${_docstring}") + endif() endfunction() function(_Boost_CHECK_SPELLING _var) - if(${_var}) - string(TOUPPER ${_var} _var_UC) - message(FATAL_ERROR "ERROR: ${_var} is not the correct spelling. The proper spelling is ${_var_UC}.") - endif() + if(${_var}) + string(TOUPPER ${_var} _var_UC) + message( + FATAL_ERROR + "ERROR: ${_var} is not the correct spelling. The proper spelling is ${_var_UC}." + ) + endif() endfunction() -# Guesses Boost's compiler prefix used in built library names -# Returns the guess by setting the variable pointed to by _ret +# Guesses Boost's compiler prefix used in built library names Returns the guess by setting +# the variable pointed to by _ret function(_Boost_GUESS_COMPILER_PREFIX _ret) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") - if(WIN32) - set (_boost_COMPILER "-iw") - else() - set (_boost_COMPILER "-il") - endif() - elseif (GHSMULTI) - set(_boost_COMPILER "-ghs") - elseif("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) - set(_boost_COMPILER "-vc141;-vc140") - elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) - set(_boost_COMPILER "-vc${MSVC_TOOLSET_VERSION}") - elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13.10) - set(_boost_COMPILER "-vc71") - elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13) # Good luck! - set(_boost_COMPILER "-vc7") # yes, this is correct - else() # VS 6.0 Good luck! - set(_boost_COMPILER "-vc6") # yes, this is correct - endif() - elseif (BORLAND) - set(_boost_COMPILER "-bcb") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "SunPro") - set(_boost_COMPILER "-sw") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "XL") - set(_boost_COMPILER "-xlc") - elseif (MINGW) - if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) - set(_boost_COMPILER "-mgw") # no GCC version encoding prior to 1.34 - else() - _Boost_COMPILER_DUMPVERSION(_boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR _boost_COMPILER_VERSION_MINOR) - set(_boost_COMPILER "-mgw${_boost_COMPILER_VERSION}") - endif() - elseif (UNIX) - _Boost_COMPILER_DUMPVERSION(_boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR _boost_COMPILER_VERSION_MINOR) - if(NOT Boost_VERSION VERSION_LESS 106900) - # From GCC 5 and clang 4, versioning changes and minor becomes patch. - # For those compilers, patch is exclude from compiler tag in Boost 1.69+ library naming. - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" AND _boost_COMPILER_VERSION_MAJOR VERSION_GREATER 4) - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang" AND _boost_COMPILER_VERSION_MAJOR VERSION_GREATER 3) - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") - endif() - endif() - - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") - if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) - set(_boost_COMPILER "-gcc") # no GCC version encoding prior to 1.34 - else() - # Determine which version of GCC we have. - if(APPLE) - if(Boost_MINOR_VERSION) - if(${Boost_MINOR_VERSION} GREATER 35) - # In Boost 1.36.0 and newer, the mangled compiler name used - # on macOS/Darwin is "xgcc". - set(_boost_COMPILER "-xgcc${_boost_COMPILER_VERSION}") + if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") + if(WIN32) + set(_boost_COMPILER "-iw") + else() + set(_boost_COMPILER "-il") + endif() + elseif(GHSMULTI) + set(_boost_COMPILER "-ghs") + elseif("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") + if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) + set(_boost_COMPILER "-vc141;-vc140") + elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) + set(_boost_COMPILER "-vc${MSVC_TOOLSET_VERSION}") + elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13.10) + set(_boost_COMPILER "-vc71") + elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13) # Good luck! + set(_boost_COMPILER "-vc7") # yes, this is correct + else() # VS 6.0 Good luck! + set(_boost_COMPILER "-vc6") # yes, this is correct + endif() + elseif(BORLAND) + set(_boost_COMPILER "-bcb") + elseif(CMAKE_CXX_COMPILER_ID STREQUAL "SunPro") + set(_boost_COMPILER "-sw") + elseif(CMAKE_CXX_COMPILER_ID STREQUAL "XL") + set(_boost_COMPILER "-xlc") + elseif(MINGW) + if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) + set(_boost_COMPILER "-mgw") # no GCC version encoding prior to 1.34 + else() + _boost_compiler_dumpversion( + _boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR + _boost_COMPILER_VERSION_MINOR) + set(_boost_COMPILER "-mgw${_boost_COMPILER_VERSION}") + endif() + elseif(UNIX) + _boost_compiler_dumpversion(_boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR + _boost_COMPILER_VERSION_MINOR) + if(NOT Boost_VERSION VERSION_LESS 106900) + # From GCC 5 and clang 4, versioning changes and minor becomes patch. For + # those compilers, patch is exclude from compiler tag in Boost 1.69+ library + # naming. + if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" AND _boost_COMPILER_VERSION_MAJOR + VERSION_GREATER 4) + set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") + elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang" + AND _boost_COMPILER_VERSION_MAJOR VERSION_GREATER 3) + set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") + endif() + endif() + + if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) + set(_boost_COMPILER "-gcc") # no GCC version encoding prior to 1.34 else() - # In Boost <= 1.35.0, there is no mangled compiler name for - # the macOS/Darwin version of GCC. - set(_boost_COMPILER "") + # Determine which version of GCC we have. + if(APPLE) + if(Boost_MINOR_VERSION) + if(${Boost_MINOR_VERSION} GREATER 35) + # In Boost 1.36.0 and newer, the mangled compiler name used on + # macOS/Darwin is "xgcc". + set(_boost_COMPILER "-xgcc${_boost_COMPILER_VERSION}") + else() + # In Boost <= 1.35.0, there is no mangled compiler name for + # the macOS/Darwin version of GCC. + set(_boost_COMPILER "") + endif() + else() + # We don't know the Boost version, so assume it's pre-1.36.0. + set(_boost_COMPILER "") + endif() + else() + set(_boost_COMPILER "-gcc${_boost_COMPILER_VERSION}") + endif() endif() - else() - # We don't know the Boost version, so assume it's - # pre-1.36.0. - set(_boost_COMPILER "") - endif() - else() - set(_boost_COMPILER "-gcc${_boost_COMPILER_VERSION}") + elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + # TODO: Find out any Boost version constraints vs clang support. + set(_boost_COMPILER "-clang${_boost_COMPILER_VERSION}") endif() - endif() - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang") - # TODO: Find out any Boost version constraints vs clang support. - set(_boost_COMPILER "-clang${_boost_COMPILER_VERSION}") - endif() - else() - # TODO at least Boost_DEBUG here? - set(_boost_COMPILER "") - endif() - set(${_ret} ${_boost_COMPILER} PARENT_SCOPE) + else() + # TODO at least Boost_DEBUG here? + set(_boost_COMPILER "") + endif() + set(${_ret} + ${_boost_COMPILER} + PARENT_SCOPE) endfunction() # -# Get component dependencies. Requires the dependencies to have been -# defined for the Boost release version. +# Get component dependencies. Requires the dependencies to have been defined for the +# Boost release version. # -# component - the component to check -# _ret - list of library dependencies +# component - the component to check _ret - list of library dependencies # function(_Boost_COMPONENT_DEPENDENCIES component _ret) - # Note: to add a new Boost release, run - # - # % cmake -DBOOST_DIR=/path/to/boost/source -P Utilities/Scripts/BoostScanDeps.cmake - # - # The output may be added in a new block below. If it's the same as - # the previous release, simply update the version range of the block - # for the previous release. Also check if any new components have - # been added, and add any new components to - # _Boost_COMPONENT_HEADERS. - # - # This information was originally generated by running - # BoostScanDeps.cmake against every boost release to date supported - # by FindBoost: - # - # % for version in /path/to/boost/sources/* - # do - # cmake -DBOOST_DIR=$version -P Utilities/Scripts/BoostScanDeps.cmake - # done - # - # The output was then updated by search and replace with these regexes: - # - # - Strip message(STATUS) prefix dashes - # s;^-- ;; - # - Indent - # s;^set(; set(;; - # - Add conditionals - # s;Scanning /path/to/boost/sources/boost_\(.*\)_\(.*\)_\(.*); elseif(NOT Boost_VERSION VERSION_LESS \10\20\3 AND Boost_VERSION VERSION_LESS xxxx); - # - # This results in the logic seen below, but will require the xxxx - # replacing with the following Boost release version (or the next - # minor version to be released, e.g. 1.59 was the latest at the time - # of writing, making 1.60 the next, so 106000 is the needed version - # number). Identical consecutive releases were then merged together - # by updating the end range of the first block and removing the - # following redundant blocks. - # - # Running the script against all historical releases should be - # required only if the BoostScanDeps.cmake script logic is changed. - # The addition of a new release should only require it to be run - # against the new release. - - # Handle Python version suffixes - if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") - set(component "${CMAKE_MATCH_1}") - set(component_python_version "${CMAKE_MATCH_2}") - endif() - - set(_Boost_IMPORTED_TARGETS TRUE) - if(Boost_VERSION AND Boost_VERSION VERSION_LESS 103300) - message(WARNING "Imported targets and dependency information not available for Boost version ${Boost_VERSION} (all versions older than 1.33)") - set(_Boost_IMPORTED_TARGETS FALSE) - elseif(NOT Boost_VERSION VERSION_LESS 103300 AND Boost_VERSION VERSION_LESS 103500) - set(_Boost_IOSTREAMS_DEPENDENCIES regex thread) - set(_Boost_REGEX_DEPENDENCIES thread) - set(_Boost_WAVE_DEPENDENCIES filesystem thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103500 AND Boost_VERSION VERSION_LESS 103600) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103600 AND Boost_VERSION VERSION_LESS 103800) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103800 AND Boost_VERSION VERSION_LESS 104300) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104300 AND Boost_VERSION VERSION_LESS 104400) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104400 AND Boost_VERSION VERSION_LESS 104500) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random serialization) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES serialization filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104500 AND Boost_VERSION VERSION_LESS 104700) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104700 AND Boost_VERSION VERSION_LESS 104800) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104800 AND Boost_VERSION VERSION_LESS 105000) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105000 AND Boost_VERSION VERSION_LESS 105300) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105300 AND Boost_VERSION VERSION_LESS 105400) - set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105400 AND Boost_VERSION VERSION_LESS 105500) - set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105500 AND Boost_VERSION VERSION_LESS 105600) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105600 AND Boost_VERSION VERSION_LESS 105900) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105900 AND Boost_VERSION VERSION_LESS 106000) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106000 AND Boost_VERSION VERSION_LESS 106100) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106100 AND Boost_VERSION VERSION_LESS 106200) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106300) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106300 AND Boost_VERSION VERSION_LESS 106500) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_COROUTINE2_DEPENDENCIES context fiber thread chrono system date_time) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106500 AND Boost_VERSION VERSION_LESS 106700) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106700 AND Boost_VERSION VERSION_LESS 106800) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106800 AND Boost_VERSION VERSION_LESS 106900) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106900 AND Boost_VERSION VERSION_LESS 107000) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) - set(_Boost_COROUTINE_DEPENDENCIES context) - set(_Boost_FIBER_DEPENDENCIES context) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - else() - if(NOT Boost_VERSION VERSION_LESS 107000) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) - set(_Boost_COROUTINE_DEPENDENCIES context) - set(_Boost_FIBER_DEPENDENCIES context) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - endif() - if(NOT Boost_VERSION VERSION_LESS 107100) - message(WARNING "New Boost version may have incorrect or missing dependencies and imported targets") - endif() - endif() - - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - set(_Boost_IMPORTED_TARGETS ${_Boost_IMPORTED_TARGETS} PARENT_SCOPE) - - string(REGEX REPLACE ";" " " _boost_DEPS_STRING "${_Boost_${uppercomponent}_DEPENDENCIES}") - if (NOT _boost_DEPS_STRING) - set(_boost_DEPS_STRING "(none)") - endif() - # message(STATUS "Dependencies for Boost::${component}: ${_boost_DEPS_STRING}") + # Note: to add a new Boost release, run + # + # % cmake -DBOOST_DIR=/path/to/boost/source -P Utilities/Scripts/BoostScanDeps.cmake + # + # The output may be added in a new block below. If it's the same as the previous + # release, simply update the version range of the block for the previous release. Also + # check if any new components have been added, and add any new components to + # _Boost_COMPONENT_HEADERS. + # + # This information was originally generated by running BoostScanDeps.cmake against + # every boost release to date supported by FindBoost: + # + # % for version in /path/to/boost/sources/* do cmake -DBOOST_DIR=$version -P + # Utilities/Scripts/BoostScanDeps.cmake done + # + # The output was then updated by search and replace with these regexes: + # + # - Strip message(STATUS) prefix dashes s;^-- ;; + # - Indent s;^set(; set(;; + # - Add conditionals s;Scanning /path/to/boost/sources/boost_\(.*\)_\(.*\)_\(.*); + # elseif(NOT Boost_VERSION VERSION_LESS \10\20\3 AND Boost_VERSION VERSION_LESS + # xxxx); + # + # This results in the logic seen below, but will require the xxxx replacing with the + # following Boost release version (or the next minor version to be released, e.g. 1.59 + # was the latest at the time of writing, making 1.60 the next, so 106000 is the needed + # version number). Identical consecutive releases were then merged together by + # updating the end range of the first block and removing the following redundant + # blocks. + # + # Running the script against all historical releases should be required only if the + # BoostScanDeps.cmake script logic is changed. The addition of a new release should + # only require it to be run against the new release. + + # Handle Python version suffixes + if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") + set(component "${CMAKE_MATCH_1}") + set(component_python_version "${CMAKE_MATCH_2}") + endif() + + set(_Boost_IMPORTED_TARGETS TRUE) + if(Boost_VERSION AND Boost_VERSION VERSION_LESS 103300) + message( + WARNING + "Imported targets and dependency information not available for Boost version ${Boost_VERSION} (all versions older than 1.33)" + ) + set(_Boost_IMPORTED_TARGETS FALSE) + elseif(NOT Boost_VERSION VERSION_LESS 103300 AND Boost_VERSION VERSION_LESS 103500) + set(_Boost_IOSTREAMS_DEPENDENCIES regex thread) + set(_Boost_REGEX_DEPENDENCIES thread) + set(_Boost_WAVE_DEPENDENCIES filesystem thread) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 103500 AND Boost_VERSION VERSION_LESS 103600) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_WAVE_DEPENDENCIES filesystem system thread) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 103600 AND Boost_VERSION VERSION_LESS 103800) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f + math_tr1l) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_WAVE_DEPENDENCIES filesystem system thread) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 103800 AND Boost_VERSION VERSION_LESS 104300) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f + math_tr1l) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 104300 AND Boost_VERSION VERSION_LESS 104400) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 104400 AND Boost_VERSION VERSION_LESS 104500) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + random + serialization) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_WAVE_DEPENDENCIES serialization filesystem system thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 104500 AND Boost_VERSION VERSION_LESS 104700) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 104700 AND Boost_VERSION VERSION_LESS 104800) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 104800 AND Boost_VERSION VERSION_LESS 105000) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES date_time) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105000 AND Boost_VERSION VERSION_LESS 105300) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + regex + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono + date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105300 AND Boost_VERSION VERSION_LESS 105400) + set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + regex + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono + date_time) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105400 AND Boost_VERSION VERSION_LESS 105500) + set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + log_setup + date_time + system + filesystem + thread + regex + chrono) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + regex + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105500 AND Boost_VERSION VERSION_LESS 105600) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + log_setup + date_time + system + filesystem + thread + regex + chrono) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + regex + random) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105600 AND Boost_VERSION VERSION_LESS 105900) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + log_setup + date_time + system + filesystem + thread + regex + chrono) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 105900 AND Boost_VERSION VERSION_LESS 106000) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + log_setup + date_time + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106000 AND Boost_VERSION VERSION_LESS 106100) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106100 AND Boost_VERSION VERSION_LESS 106200) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106300) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106300 AND Boost_VERSION VERSION_LESS 106500) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_COROUTINE2_DEPENDENCIES context fiber thread chrono system date_time) + set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106500 AND Boost_VERSION VERSION_LESS 106700) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106700 AND Boost_VERSION VERSION_LESS 106800) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106800 AND Boost_VERSION VERSION_LESS 106900) + set(_Boost_CHRONO_DEPENDENCIES system) + set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) + set(_Boost_CONTRACT_DEPENDENCIES thread chrono system date_time) + set(_Boost_COROUTINE_DEPENDENCIES context system) + set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) + set(_Boost_FILESYSTEM_DEPENDENCIES system) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + system + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) + set(_Boost_RANDOM_DEPENDENCIES system) + set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES + filesystem + system + serialization + thread + chrono + date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + elseif(NOT Boost_VERSION VERSION_LESS 106900 AND Boost_VERSION VERSION_LESS 107000) + set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) + set(_Boost_COROUTINE_DEPENDENCIES context) + set(_Boost_FIBER_DEPENDENCIES context) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) + set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + else() + if(NOT Boost_VERSION VERSION_LESS 107000) + set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) + set(_Boost_COROUTINE_DEPENDENCIES context) + set(_Boost_FIBER_DEPENDENCIES context) + set(_Boost_IOSTREAMS_DEPENDENCIES regex) + set(_Boost_LOG_DEPENDENCIES + date_time + log_setup + filesystem + thread + regex + chrono + atomic) + set(_Boost_MATH_DEPENDENCIES + math_c99 + math_c99f + math_c99l + math_tr1 + math_tr1f + math_tr1l + atomic) + set(_Boost_MPI_DEPENDENCIES serialization) + set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi + serialization) + set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) + set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) + set(_Boost_TIMER_DEPENDENCIES chrono system) + set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time + atomic) + set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) + endif() + if(NOT Boost_VERSION VERSION_LESS 107100) + message( + WARNING + "New Boost version may have incorrect or missing dependencies and imported targets" + ) + endif() + endif() + + string(TOUPPER ${component} uppercomponent) + set(${_ret} + ${_Boost_${uppercomponent}_DEPENDENCIES} + PARENT_SCOPE) + set(_Boost_IMPORTED_TARGETS + ${_Boost_IMPORTED_TARGETS} + PARENT_SCOPE) + + string(REGEX REPLACE ";" " " _boost_DEPS_STRING + "${_Boost_${uppercomponent}_DEPENDENCIES}") + if(NOT _boost_DEPS_STRING) + set(_boost_DEPS_STRING "(none)") + endif() + # message(STATUS "Dependencies for Boost::${component}: ${_boost_DEPS_STRING}") endfunction() # -# Get component headers. This is the primary header (or headers) for -# a given component, and is used to check that the headers are present -# as well as the library itself as an extra sanity check of the build -# environment. +# Get component headers. This is the primary header (or headers) for a given component, +# and is used to check that the headers are present as well as the library itself as an +# extra sanity check of the build environment. # -# component - the component to check -# _hdrs +# component - the component to check _hdrs # function(_Boost_COMPONENT_HEADERS component _hdrs) - # Handle Python version suffixes - if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") - set(component "${CMAKE_MATCH_1}") - set(component_python_version "${CMAKE_MATCH_2}") - endif() - - # Note: new boost components will require adding here. The header - # must be present in all versions of Boost providing a library. - set(_Boost_ATOMIC_HEADERS "boost/atomic.hpp") - set(_Boost_CHRONO_HEADERS "boost/chrono.hpp") - set(_Boost_CONTAINER_HEADERS "boost/container/container_fwd.hpp") - set(_Boost_CONTRACT_HEADERS "boost/contract.hpp") - if(Boost_VERSION VERSION_LESS 106100) - set(_Boost_CONTEXT_HEADERS "boost/context/all.hpp") - else() - set(_Boost_CONTEXT_HEADERS "boost/context/detail/fcontext.hpp") - endif() - set(_Boost_COROUTINE_HEADERS "boost/coroutine/all.hpp") - set(_Boost_DATE_TIME_HEADERS "boost/date_time/date.hpp") - set(_Boost_EXCEPTION_HEADERS "boost/exception/exception.hpp") - set(_Boost_FIBER_HEADERS "boost/fiber/all.hpp") - set(_Boost_FILESYSTEM_HEADERS "boost/filesystem/path.hpp") - set(_Boost_GRAPH_HEADERS "boost/graph/adjacency_list.hpp") - set(_Boost_GRAPH_PARALLEL_HEADERS "boost/graph/adjacency_list.hpp") - set(_Boost_IOSTREAMS_HEADERS "boost/iostreams/stream.hpp") - set(_Boost_LOCALE_HEADERS "boost/locale.hpp") - set(_Boost_LOG_HEADERS "boost/log/core.hpp") - set(_Boost_LOG_SETUP_HEADERS "boost/log/detail/setup_config.hpp") - set(_Boost_MATH_HEADERS "boost/math_fwd.hpp") - set(_Boost_MATH_C99_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_C99F_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_C99L_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1F_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1L_HEADERS "boost/math/tr1.hpp") - set(_Boost_MPI_HEADERS "boost/mpi.hpp") - set(_Boost_MPI_PYTHON_HEADERS "boost/mpi/python/config.hpp") - set(_Boost_NUMPY_HEADERS "boost/python/numpy.hpp") - set(_Boost_PRG_EXEC_MONITOR_HEADERS "boost/test/prg_exec_monitor.hpp") - set(_Boost_PROGRAM_OPTIONS_HEADERS "boost/program_options.hpp") - set(_Boost_PYTHON_HEADERS "boost/python.hpp") - set(_Boost_RANDOM_HEADERS "boost/random.hpp") - set(_Boost_REGEX_HEADERS "boost/regex.hpp") - set(_Boost_SERIALIZATION_HEADERS "boost/serialization/serialization.hpp") - set(_Boost_SIGNALS_HEADERS "boost/signals.hpp") - set(_Boost_STACKTRACE_ADDR2LINE_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_BACKTRACE_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_BASIC_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_NOOP_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_WINDBG_CACHED_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_WINDBG_HEADERS "boost/stacktrace.hpp") - set(_Boost_SYSTEM_HEADERS "boost/system/config.hpp") - set(_Boost_TEST_EXEC_MONITOR_HEADERS "boost/test/test_exec_monitor.hpp") - set(_Boost_THREAD_HEADERS "boost/thread.hpp") - set(_Boost_TIMER_HEADERS "boost/timer.hpp") - set(_Boost_TYPE_ERASURE_HEADERS "boost/type_erasure/config.hpp") - set(_Boost_UNIT_TEST_FRAMEWORK_HEADERS "boost/test/framework.hpp") - set(_Boost_WAVE_HEADERS "boost/wave.hpp") - set(_Boost_WSERIALIZATION_HEADERS "boost/archive/text_wiarchive.hpp") - if(WIN32) - set(_Boost_BZIP2_HEADERS "boost/iostreams/filter/bzip2.hpp") - set(_Boost_ZLIB_HEADERS "boost/iostreams/filter/zlib.hpp") - endif() - - string(TOUPPER ${component} uppercomponent) - set(${_hdrs} ${_Boost_${uppercomponent}_HEADERS} PARENT_SCOPE) - - string(REGEX REPLACE ";" " " _boost_HDRS_STRING "${_Boost_${uppercomponent}_HEADERS}") - if (NOT _boost_HDRS_STRING) - set(_boost_HDRS_STRING "(none)") - endif() - # message(STATUS "Headers for Boost::${component}: ${_boost_HDRS_STRING}") + # Handle Python version suffixes + if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") + set(component "${CMAKE_MATCH_1}") + set(component_python_version "${CMAKE_MATCH_2}") + endif() + + # Note: new boost components will require adding here. The header must be present in + # all versions of Boost providing a library. + set(_Boost_ATOMIC_HEADERS "boost/atomic.hpp") + set(_Boost_CHRONO_HEADERS "boost/chrono.hpp") + set(_Boost_CONTAINER_HEADERS "boost/container/container_fwd.hpp") + set(_Boost_CONTRACT_HEADERS "boost/contract.hpp") + if(Boost_VERSION VERSION_LESS 106100) + set(_Boost_CONTEXT_HEADERS "boost/context/all.hpp") + else() + set(_Boost_CONTEXT_HEADERS "boost/context/detail/fcontext.hpp") + endif() + set(_Boost_COROUTINE_HEADERS "boost/coroutine/all.hpp") + set(_Boost_DATE_TIME_HEADERS "boost/date_time/date.hpp") + set(_Boost_EXCEPTION_HEADERS "boost/exception/exception.hpp") + set(_Boost_FIBER_HEADERS "boost/fiber/all.hpp") + set(_Boost_FILESYSTEM_HEADERS "boost/filesystem/path.hpp") + set(_Boost_GRAPH_HEADERS "boost/graph/adjacency_list.hpp") + set(_Boost_GRAPH_PARALLEL_HEADERS "boost/graph/adjacency_list.hpp") + set(_Boost_IOSTREAMS_HEADERS "boost/iostreams/stream.hpp") + set(_Boost_LOCALE_HEADERS "boost/locale.hpp") + set(_Boost_LOG_HEADERS "boost/log/core.hpp") + set(_Boost_LOG_SETUP_HEADERS "boost/log/detail/setup_config.hpp") + set(_Boost_MATH_HEADERS "boost/math_fwd.hpp") + set(_Boost_MATH_C99_HEADERS "boost/math/tr1.hpp") + set(_Boost_MATH_C99F_HEADERS "boost/math/tr1.hpp") + set(_Boost_MATH_C99L_HEADERS "boost/math/tr1.hpp") + set(_Boost_MATH_TR1_HEADERS "boost/math/tr1.hpp") + set(_Boost_MATH_TR1F_HEADERS "boost/math/tr1.hpp") + set(_Boost_MATH_TR1L_HEADERS "boost/math/tr1.hpp") + set(_Boost_MPI_HEADERS "boost/mpi.hpp") + set(_Boost_MPI_PYTHON_HEADERS "boost/mpi/python/config.hpp") + set(_Boost_NUMPY_HEADERS "boost/python/numpy.hpp") + set(_Boost_PRG_EXEC_MONITOR_HEADERS "boost/test/prg_exec_monitor.hpp") + set(_Boost_PROGRAM_OPTIONS_HEADERS "boost/program_options.hpp") + set(_Boost_PYTHON_HEADERS "boost/python.hpp") + set(_Boost_RANDOM_HEADERS "boost/random.hpp") + set(_Boost_REGEX_HEADERS "boost/regex.hpp") + set(_Boost_SERIALIZATION_HEADERS "boost/serialization/serialization.hpp") + set(_Boost_SIGNALS_HEADERS "boost/signals.hpp") + set(_Boost_STACKTRACE_ADDR2LINE_HEADERS "boost/stacktrace.hpp") + set(_Boost_STACKTRACE_BACKTRACE_HEADERS "boost/stacktrace.hpp") + set(_Boost_STACKTRACE_BASIC_HEADERS "boost/stacktrace.hpp") + set(_Boost_STACKTRACE_NOOP_HEADERS "boost/stacktrace.hpp") + set(_Boost_STACKTRACE_WINDBG_CACHED_HEADERS "boost/stacktrace.hpp") + set(_Boost_STACKTRACE_WINDBG_HEADERS "boost/stacktrace.hpp") + set(_Boost_SYSTEM_HEADERS "boost/system/config.hpp") + set(_Boost_TEST_EXEC_MONITOR_HEADERS "boost/test/test_exec_monitor.hpp") + set(_Boost_THREAD_HEADERS "boost/thread.hpp") + set(_Boost_TIMER_HEADERS "boost/timer.hpp") + set(_Boost_TYPE_ERASURE_HEADERS "boost/type_erasure/config.hpp") + set(_Boost_UNIT_TEST_FRAMEWORK_HEADERS "boost/test/framework.hpp") + set(_Boost_WAVE_HEADERS "boost/wave.hpp") + set(_Boost_WSERIALIZATION_HEADERS "boost/archive/text_wiarchive.hpp") + if(WIN32) + set(_Boost_BZIP2_HEADERS "boost/iostreams/filter/bzip2.hpp") + set(_Boost_ZLIB_HEADERS "boost/iostreams/filter/zlib.hpp") + endif() + + string(TOUPPER ${component} uppercomponent) + set(${_hdrs} + ${_Boost_${uppercomponent}_HEADERS} + PARENT_SCOPE) + + string(REGEX REPLACE ";" " " _boost_HDRS_STRING "${_Boost_${uppercomponent}_HEADERS}") + if(NOT _boost_HDRS_STRING) + set(_boost_HDRS_STRING "(none)") + endif() + # message(STATUS "Headers for Boost::${component}: ${_boost_HDRS_STRING}") endfunction() # # Determine if any missing dependencies require adding to the component list. # -# Sets _Boost_${COMPONENT}_DEPENDENCIES for each required component, -# plus _Boost_IMPORTED_TARGETS (TRUE if imported targets should be -# defined; FALSE if dependency information is unavailable). -# -# componentvar - the component list variable name -# extravar - the indirect dependency list variable name +# Sets _Boost_${COMPONENT}_DEPENDENCIES for each required component, plus +# _Boost_IMPORTED_TARGETS (TRUE if imported targets should be defined; FALSE if dependency +# information is unavailable). # +# componentvar - the component list variable name extravar - the indirect dependency list +# variable name # function(_Boost_MISSING_DEPENDENCIES componentvar extravar) - # _boost_unprocessed_components - list of components requiring processing - # _boost_processed_components - components already processed (or currently being processed) - # _boost_new_components - new components discovered for future processing - # - list(APPEND _boost_unprocessed_components ${${componentvar}}) - - while(_boost_unprocessed_components) - list(APPEND _boost_processed_components ${_boost_unprocessed_components}) - foreach(component ${_boost_unprocessed_components}) - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - _Boost_COMPONENT_DEPENDENCIES("${component}" _Boost_${uppercomponent}_DEPENDENCIES) - set(_Boost_${uppercomponent}_DEPENDENCIES ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - set(_Boost_IMPORTED_TARGETS ${_Boost_IMPORTED_TARGETS} PARENT_SCOPE) - foreach(componentdep ${_Boost_${uppercomponent}_DEPENDENCIES}) - if (NOT ("${componentdep}" IN_LIST _boost_processed_components OR "${componentdep}" IN_LIST _boost_new_components)) - list(APPEND _boost_new_components ${componentdep}) - endif() - endforeach() - endforeach() - set(_boost_unprocessed_components ${_boost_new_components}) - unset(_boost_new_components) - endwhile() - set(_boost_extra_components ${_boost_processed_components}) - if(_boost_extra_components AND ${componentvar}) - list(REMOVE_ITEM _boost_extra_components ${${componentvar}}) - endif() - set(${componentvar} ${_boost_processed_components} PARENT_SCOPE) - set(${extravar} ${_boost_extra_components} PARENT_SCOPE) + # _boost_unprocessed_components - list of components requiring processing + # _boost_processed_components - components already processed (or currently being + # processed) _boost_new_components - new components discovered for future processing + # + list(APPEND _boost_unprocessed_components ${${componentvar}}) + + while(_boost_unprocessed_components) + list(APPEND _boost_processed_components ${_boost_unprocessed_components}) + foreach(component ${_boost_unprocessed_components}) + string(TOUPPER ${component} uppercomponent) + set(${_ret} + ${_Boost_${uppercomponent}_DEPENDENCIES} + PARENT_SCOPE) + _boost_component_dependencies("${component}" + _Boost_${uppercomponent}_DEPENDENCIES) + set(_Boost_${uppercomponent}_DEPENDENCIES + ${_Boost_${uppercomponent}_DEPENDENCIES} + PARENT_SCOPE) + set(_Boost_IMPORTED_TARGETS + ${_Boost_IMPORTED_TARGETS} + PARENT_SCOPE) + foreach(componentdep ${_Boost_${uppercomponent}_DEPENDENCIES}) + if(NOT ("${componentdep}" IN_LIST _boost_processed_components + OR "${componentdep}" IN_LIST _boost_new_components)) + list(APPEND _boost_new_components ${componentdep}) + endif() + endforeach() + endforeach() + set(_boost_unprocessed_components ${_boost_new_components}) + unset(_boost_new_components) + endwhile() + set(_boost_extra_components ${_boost_processed_components}) + if(_boost_extra_components AND ${componentvar}) + list(REMOVE_ITEM _boost_extra_components ${${componentvar}}) + endif() + set(${componentvar} + ${_boost_processed_components} + PARENT_SCOPE) + set(${extravar} + ${_boost_extra_components} + PARENT_SCOPE) endfunction() # -# Some boost libraries may require particular set of compler features. -# The very first one was `boost::fiber` introduced in Boost 1.62. -# One can check required compiler features of it in -# `${Boost_ROOT}/libs/fiber/build/Jamfile.v2`. +# Some boost libraries may require particular set of compler features. The very first one +# was `boost::fiber` introduced in Boost 1.62. One can check required compiler features of +# it in `${Boost_ROOT}/libs/fiber/build/Jamfile.v2`. # function(_Boost_COMPILER_FEATURES component _ret) - # Boost >= 1.62 and < 1.67 - if(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106700) - set(_Boost_FIBER_COMPILER_FEATURES - cxx_alias_templates - cxx_auto_type - cxx_constexpr - cxx_defaulted_functions - cxx_final - cxx_lambdas - cxx_noexcept - cxx_nullptr - cxx_rvalue_references - cxx_thread_local - cxx_variadic_templates - ) - endif() - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_COMPILER_FEATURES} PARENT_SCOPE) + # Boost >= 1.62 and < 1.67 + if(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106700) + set(_Boost_FIBER_COMPILER_FEATURES + cxx_alias_templates + cxx_auto_type + cxx_constexpr + cxx_defaulted_functions + cxx_final + cxx_lambdas + cxx_noexcept + cxx_nullptr + cxx_rvalue_references + cxx_thread_local + cxx_variadic_templates) + endif() + string(TOUPPER ${component} uppercomponent) + set(${_ret} + ${_Boost_${uppercomponent}_COMPILER_FEATURES} + PARENT_SCOPE) endfunction() # -# Update library search directory hint variable with paths used by prebuilt boost binaries. +# Update library search directory hint variable with paths used by prebuilt boost +# binaries. # # Prebuilt windows binaries (https://sourceforge.net/projects/boost/files/boost-binaries/) -# have library directories named using MSVC compiler version and architecture. -# This function would append corresponding directories if MSVC is a current compiler, -# so having `BOOST_ROOT` would be enough to specify to find everything. +# have library directories named using MSVC compiler version and architecture. This +# function would append corresponding directories if MSVC is a current compiler, so having +# `BOOST_ROOT` would be enough to specify to find everything. # -function(_Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS componentlibvar basedir) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(_arch_suffix 64) - else() - set(_arch_suffix 32) - endif() - if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.1) - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.0) - elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) - math(EXPR _toolset_major_version "${MSVC_TOOLSET_VERSION} / 10") - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-${_toolset_major_version}.0) +function(_Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS componentlibvar + basedir) + if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") + if(CMAKE_SIZEOF_VOID_P EQUAL 8) + set(_arch_suffix 64) + else() + set(_arch_suffix 32) + endif() + if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) + list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.1) + list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.0) + elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) + math(EXPR _toolset_major_version "${MSVC_TOOLSET_VERSION} / 10") + list(APPEND ${componentlibvar} + ${basedir}/lib${_arch_suffix}-msvc-${_toolset_major_version}.0) + endif() + set(${componentlibvar} + ${${componentlibvar}} + PARENT_SCOPE) endif() - set(${componentlibvar} ${${componentlibvar}} PARENT_SCOPE) - endif() endfunction() # # End functions/macros # -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- # main. -#------------------------------------------------------------------------------- +# ------------------------------------------------------------------------------- - -# If the user sets Boost_LIBRARY_DIR, use it as the default for both -# configurations. +# If the user sets Boost_LIBRARY_DIR, use it as the default for both configurations. if(NOT Boost_LIBRARY_DIR_RELEASE AND Boost_LIBRARY_DIR) - set(Boost_LIBRARY_DIR_RELEASE "${Boost_LIBRARY_DIR}") + set(Boost_LIBRARY_DIR_RELEASE "${Boost_LIBRARY_DIR}") endif() if(NOT Boost_LIBRARY_DIR_DEBUG AND Boost_LIBRARY_DIR) - set(Boost_LIBRARY_DIR_DEBUG "${Boost_LIBRARY_DIR}") + set(Boost_LIBRARY_DIR_DEBUG "${Boost_LIBRARY_DIR}") endif() if(NOT DEFINED Boost_USE_DEBUG_LIBS) - set(Boost_USE_DEBUG_LIBS TRUE) + set(Boost_USE_DEBUG_LIBS TRUE) endif() if(NOT DEFINED Boost_USE_RELEASE_LIBS) - set(Boost_USE_RELEASE_LIBS TRUE) + set(Boost_USE_RELEASE_LIBS TRUE) endif() if(NOT DEFINED Boost_USE_MULTITHREADED) - set(Boost_USE_MULTITHREADED TRUE) + set(Boost_USE_MULTITHREADED TRUE) endif() if(NOT DEFINED Boost_USE_DEBUG_RUNTIME) - set(Boost_USE_DEBUG_RUNTIME TRUE) + set(Boost_USE_DEBUG_RUNTIME TRUE) endif() # Check the version of Boost against the requested version. if(Boost_FIND_VERSION AND NOT Boost_FIND_VERSION_MINOR) - message(SEND_ERROR "When requesting a specific version of Boost, you must provide at least the major and minor version numbers, e.g., 1.34") + message( + SEND_ERROR + "When requesting a specific version of Boost, you must provide at least the major and minor version numbers, e.g., 1.34" + ) endif() if(Boost_FIND_VERSION_EXACT) - # The version may appear in a directory with or without the patch - # level, even when the patch level is non-zero. - set(_boost_TEST_VERSIONS - "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}.${Boost_FIND_VERSION_PATCH}" - "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") + # The version may appear in a directory with or without the patch level, even when the + # patch level is non-zero. + set(_boost_TEST_VERSIONS + "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}.${Boost_FIND_VERSION_PATCH}" + "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") else() - # The user has not requested an exact version. Among known - # versions, find those that are acceptable to the user request. - # - # Note: When adding a new Boost release, also update the dependency - # information in _Boost_COMPONENT_DEPENDENCIES and - # _Boost_COMPONENT_HEADERS. See the instructions at the top of - # _Boost_COMPONENT_DEPENDENCIES. - set(_Boost_KNOWN_VERSIONS ${Boost_ADDITIONAL_VERSIONS} - "1.70.0" "1.70" "1.69.0" "1.69" - "1.68.0" "1.68" "1.67.0" "1.67" "1.66.0" "1.66" "1.65.1" "1.65.0" "1.65" - "1.64.0" "1.64" "1.63.0" "1.63" "1.62.0" "1.62" "1.61.0" "1.61" "1.60.0" "1.60" - "1.59.0" "1.59" "1.58.0" "1.58" "1.57.0" "1.57" "1.56.0" "1.56" "1.55.0" "1.55" - "1.54.0" "1.54" "1.53.0" "1.53" "1.52.0" "1.52" "1.51.0" "1.51" - "1.50.0" "1.50" "1.49.0" "1.49" "1.48.0" "1.48" "1.47.0" "1.47" "1.46.1" - "1.46.0" "1.46" "1.45.0" "1.45" "1.44.0" "1.44" "1.43.0" "1.43" "1.42.0" "1.42" - "1.41.0" "1.41" "1.40.0" "1.40" "1.39.0" "1.39" "1.38.0" "1.38" "1.37.0" "1.37" - "1.36.1" "1.36.0" "1.36" "1.35.1" "1.35.0" "1.35" "1.34.1" "1.34.0" - "1.34" "1.33.1" "1.33.0" "1.33") - - set(_boost_TEST_VERSIONS) - if(Boost_FIND_VERSION) - set(_Boost_FIND_VERSION_SHORT "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") - # Select acceptable versions. - foreach(version ${_Boost_KNOWN_VERSIONS}) - if(NOT "${version}" VERSION_LESS "${Boost_FIND_VERSION}") - # This version is high enough. - list(APPEND _boost_TEST_VERSIONS "${version}") - elseif("${version}.99" VERSION_EQUAL "${_Boost_FIND_VERSION_SHORT}.99") - # This version is a short-form for the requested version with - # the patch level dropped. - list(APPEND _boost_TEST_VERSIONS "${version}") - endif() - endforeach() - else() - # Any version is acceptable. - set(_boost_TEST_VERSIONS "${_Boost_KNOWN_VERSIONS}") - endif() + # The user has not requested an exact version. Among known versions, find those that + # are acceptable to the user request. + # + # Note: When adding a new Boost release, also update the dependency information in + # _Boost_COMPONENT_DEPENDENCIES and _Boost_COMPONENT_HEADERS. See the instructions at + # the top of _Boost_COMPONENT_DEPENDENCIES. + set(_Boost_KNOWN_VERSIONS + ${Boost_ADDITIONAL_VERSIONS} + "1.70.0" + "1.70" + "1.69.0" + "1.69" + "1.68.0" + "1.68" + "1.67.0" + "1.67" + "1.66.0" + "1.66" + "1.65.1" + "1.65.0" + "1.65" + "1.64.0" + "1.64" + "1.63.0" + "1.63" + "1.62.0" + "1.62" + "1.61.0" + "1.61" + "1.60.0" + "1.60" + "1.59.0" + "1.59" + "1.58.0" + "1.58" + "1.57.0" + "1.57" + "1.56.0" + "1.56" + "1.55.0" + "1.55" + "1.54.0" + "1.54" + "1.53.0" + "1.53" + "1.52.0" + "1.52" + "1.51.0" + "1.51" + "1.50.0" + "1.50" + "1.49.0" + "1.49" + "1.48.0" + "1.48" + "1.47.0" + "1.47" + "1.46.1" + "1.46.0" + "1.46" + "1.45.0" + "1.45" + "1.44.0" + "1.44" + "1.43.0" + "1.43" + "1.42.0" + "1.42" + "1.41.0" + "1.41" + "1.40.0" + "1.40" + "1.39.0" + "1.39" + "1.38.0" + "1.38" + "1.37.0" + "1.37" + "1.36.1" + "1.36.0" + "1.36" + "1.35.1" + "1.35.0" + "1.35" + "1.34.1" + "1.34.0" + "1.34" + "1.33.1" + "1.33.0" + "1.33") + + set(_boost_TEST_VERSIONS) + if(Boost_FIND_VERSION) + set(_Boost_FIND_VERSION_SHORT + "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") + # Select acceptable versions. + foreach(version ${_Boost_KNOWN_VERSIONS}) + if(NOT "${version}" VERSION_LESS "${Boost_FIND_VERSION}") + # This version is high enough. + list(APPEND _boost_TEST_VERSIONS "${version}") + elseif("${version}.99" VERSION_EQUAL "${_Boost_FIND_VERSION_SHORT}.99") + # This version is a short-form for the requested version with the patch + # level dropped. + list(APPEND _boost_TEST_VERSIONS "${version}") + endif() + endforeach() + else() + # Any version is acceptable. + set(_boost_TEST_VERSIONS "${_Boost_KNOWN_VERSIONS}") + endif() endif() -# The reason that we failed to find Boost. This will be set to a -# user-friendly message when we fail to find some necessary piece of -# Boost. +# The reason that we failed to find Boost. This will be set to a user-friendly message +# when we fail to find some necessary piece of Boost. set(Boost_ERROR_REASON) if(Boost_DEBUG) - # Output some of their choices - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_MULTITHREADED = ${Boost_USE_MULTITHREADED}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_STATIC_LIBS = ${Boost_USE_STATIC_LIBS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_STATIC_RUNTIME = ${Boost_USE_STATIC_RUNTIME}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_ADDITIONAL_VERSIONS = ${Boost_ADDITIONAL_VERSIONS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_NO_SYSTEM_PATHS = ${Boost_NO_SYSTEM_PATHS}") + # Output some of their choices + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_USE_MULTITHREADED = ${Boost_USE_MULTITHREADED}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_USE_STATIC_LIBS = ${Boost_USE_STATIC_LIBS}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_USE_STATIC_RUNTIME = ${Boost_USE_STATIC_RUNTIME}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_ADDITIONAL_VERSIONS = ${Boost_ADDITIONAL_VERSIONS}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_NO_SYSTEM_PATHS = ${Boost_NO_SYSTEM_PATHS}") endif() -# Supply Boost_LIB_DIAGNOSTIC_DEFINITIONS as a convenience target. It -# will only contain any interface definitions on WIN32, but is created -# on all platforms to keep end user code free from platform dependent -# code. Also provide convenience targets to disable autolinking and -# enable dynamic linking. +# Supply Boost_LIB_DIAGNOSTIC_DEFINITIONS as a convenience target. It will only contain +# any interface definitions on WIN32, but is created on all platforms to keep end user +# code free from platform dependent code. Also provide convenience targets to disable +# autolinking and enable dynamic linking. if(NOT TARGET Boost::diagnostic_definitions) - add_library(Boost::diagnostic_definitions INTERFACE IMPORTED) - add_library(Boost::disable_autolinking INTERFACE IMPORTED) - add_library(Boost::dynamic_linking INTERFACE IMPORTED) - set_target_properties(Boost::dynamic_linking PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_ALL_DYN_LINK") + add_library(Boost::diagnostic_definitions INTERFACE IMPORTED) + add_library(Boost::disable_autolinking INTERFACE IMPORTED) + add_library(Boost::dynamic_linking INTERFACE IMPORTED) + set_target_properties(Boost::dynamic_linking PROPERTIES INTERFACE_COMPILE_DEFINITIONS + "BOOST_ALL_DYN_LINK") endif() if(WIN32) - # In windows, automatic linking is performed, so you do not have - # to specify the libraries. If you are linking to a dynamic - # runtime, then you can choose to link to either a static or a - # dynamic Boost library, the default is to do a static link. You - # can alter this for a specific library "whatever" by defining - # BOOST_WHATEVER_DYN_LINK to force Boost library "whatever" to be - # linked dynamically. Alternatively you can force all Boost - # libraries to dynamic link by defining BOOST_ALL_DYN_LINK. - - # This feature can be disabled for Boost library "whatever" by - # defining BOOST_WHATEVER_NO_LIB, or for all of Boost by defining - # BOOST_ALL_NO_LIB. - - # If you want to observe which libraries are being linked against - # then defining BOOST_LIB_DIAGNOSTIC will cause the auto-linking - # code to emit a #pragma message each time a library is selected - # for linking. - set(Boost_LIB_DIAGNOSTIC_DEFINITIONS "-DBOOST_LIB_DIAGNOSTIC") - set_target_properties(Boost::diagnostic_definitions PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_LIB_DIAGNOSTIC") - set_target_properties(Boost::disable_autolinking PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_ALL_NO_LIB") + # In windows, automatic linking is performed, so you do not have to specify the + # libraries. If you are linking to a dynamic runtime, then you can choose to link to + # either a static or a dynamic Boost library, the default is to do a static link. You + # can alter this for a specific library "whatever" by defining BOOST_WHATEVER_DYN_LINK + # to force Boost library "whatever" to be linked dynamically. Alternatively you can + # force all Boost libraries to dynamic link by defining BOOST_ALL_DYN_LINK. + + # This feature can be disabled for Boost library "whatever" by defining + # BOOST_WHATEVER_NO_LIB, or for all of Boost by defining BOOST_ALL_NO_LIB. + + # If you want to observe which libraries are being linked against then defining + # BOOST_LIB_DIAGNOSTIC will cause the auto-linking code to emit a #pragma message each + # time a library is selected for linking. + set(Boost_LIB_DIAGNOSTIC_DEFINITIONS "-DBOOST_LIB_DIAGNOSTIC") + set_target_properties(Boost::diagnostic_definitions + PROPERTIES INTERFACE_COMPILE_DEFINITIONS "BOOST_LIB_DIAGNOSTIC") + set_target_properties(Boost::disable_autolinking + PROPERTIES INTERFACE_COMPILE_DEFINITIONS "BOOST_ALL_NO_LIB") endif() -_Boost_CHECK_SPELLING(Boost_ROOT) -_Boost_CHECK_SPELLING(Boost_LIBRARYDIR) -_Boost_CHECK_SPELLING(Boost_INCLUDEDIR) +_boost_check_spelling(Boost_ROOT) +_boost_check_spelling(Boost_LIBRARYDIR) +_boost_check_spelling(Boost_INCLUDEDIR) # Collect environment variable inputs as hints. Do not consider changes. foreach(v BOOSTROOT BOOST_ROOT BOOST_INCLUDEDIR BOOST_LIBRARYDIR) - set(_env $ENV{${v}}) - if(_env) - file(TO_CMAKE_PATH "${_env}" _ENV_${v}) - else() - set(_ENV_${v} "") - endif() + set(_env $ENV{${v}}) + if(_env) + file(TO_CMAKE_PATH "${_env}" _ENV_${v}) + else() + set(_ENV_${v} "") + endif() endforeach() if(NOT _ENV_BOOST_ROOT AND _ENV_BOOSTROOT) - set(_ENV_BOOST_ROOT "${_ENV_BOOSTROOT}") + set(_ENV_BOOST_ROOT "${_ENV_BOOSTROOT}") endif() # Collect inputs and cached results. Detect changes since the last run. if(NOT BOOST_ROOT AND BOOSTROOT) - set(BOOST_ROOT "${BOOSTROOT}") + set(BOOST_ROOT "${BOOSTROOT}") endif() -set(_Boost_VARS_DIR - BOOST_ROOT - Boost_NO_SYSTEM_PATHS - ) +set(_Boost_VARS_DIR BOOST_ROOT Boost_NO_SYSTEM_PATHS) if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Declared as CMake or Environmental Variables:") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_ROOT = ${BOOST_ROOT}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_INCLUDEDIR = ${BOOST_INCLUDEDIR}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_LIBRARYDIR = ${BOOST_LIBRARYDIR}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Declared as CMake or Environmental Variables:") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " BOOST_ROOT = ${BOOST_ROOT}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " BOOST_INCLUDEDIR = ${BOOST_INCLUDEDIR}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " BOOST_LIBRARYDIR = ${BOOST_LIBRARYDIR}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") endif() # ------------------------------------------------------------------------ -# Search for Boost include DIR +# Search for Boost include DIR # ------------------------------------------------------------------------ set(_Boost_VARS_INC BOOST_INCLUDEDIR Boost_INCLUDE_DIR Boost_ADDITIONAL_VERSIONS) -_Boost_CHANGE_DETECT(_Boost_CHANGE_INCDIR ${_Boost_VARS_DIR} ${_Boost_VARS_INC}) -# Clear Boost_INCLUDE_DIR if it did not change but other input affecting the -# location did. We will find a new one based on the new inputs. +_boost_change_detect(_Boost_CHANGE_INCDIR ${_Boost_VARS_DIR} ${_Boost_VARS_INC}) +# Clear Boost_INCLUDE_DIR if it did not change but other input affecting the location did. +# We will find a new one based on the new inputs. if(_Boost_CHANGE_INCDIR AND NOT _Boost_INCLUDE_DIR_CHANGED) - unset(Boost_INCLUDE_DIR CACHE) + unset(Boost_INCLUDE_DIR CACHE) endif() if(NOT Boost_INCLUDE_DIR) - set(_boost_INCLUDE_SEARCH_DIRS "") - if(BOOST_INCLUDEDIR) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_INCLUDEDIR}) - elseif(_ENV_BOOST_INCLUDEDIR) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_INCLUDEDIR}) - endif() - - if( BOOST_ROOT ) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_ROOT}/include ${BOOST_ROOT}) - elseif( _ENV_BOOST_ROOT ) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_ROOT}/include ${_ENV_BOOST_ROOT}) - endif() - - if( Boost_NO_SYSTEM_PATHS) - list(APPEND _boost_INCLUDE_SEARCH_DIRS NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) - else() - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - foreach(ver ${_boost_TEST_VERSIONS}) - string(REPLACE "." "_" ver "${ver}") - list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS "C:/local/boost_${ver}") - endforeach() - endif() - list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS - C:/boost/include - C:/boost - /sw/local/include - ) - endif() - - # Try to find Boost by stepping backwards through the Boost versions - # we know about. - # Build a list of path suffixes for each version. - set(_boost_PATH_SUFFIXES) - foreach(_boost_VER ${_boost_TEST_VERSIONS}) - # Add in a path suffix, based on the required version, ideally - # we could read this from version.hpp, but for that to work we'd - # need to know the include dir already - set(_boost_BOOSTIFIED_VERSION) - - # Transform 1.35 => 1_35 and 1.36.0 => 1_36_0 - if(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)\\.([0-9]+)") - set(_boost_BOOSTIFIED_VERSION - "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}_${CMAKE_MATCH_3}") - elseif(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)") - set(_boost_BOOSTIFIED_VERSION - "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}") - endif() - - list(APPEND _boost_PATH_SUFFIXES - "boost-${_boost_BOOSTIFIED_VERSION}" - "boost_${_boost_BOOSTIFIED_VERSION}" - "boost/boost-${_boost_BOOSTIFIED_VERSION}" - "boost/boost_${_boost_BOOSTIFIED_VERSION}" - ) - - endforeach() - - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Include debugging info:") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " _boost_INCLUDE_SEARCH_DIRS = ${_boost_INCLUDE_SEARCH_DIRS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " _boost_PATH_SUFFIXES = ${_boost_PATH_SUFFIXES}") - endif() - - # Look for a standard boost header file. - find_path(Boost_INCLUDE_DIR - NAMES boost/config.hpp - HINTS ${_boost_INCLUDE_SEARCH_DIRS} - PATH_SUFFIXES ${_boost_PATH_SUFFIXES} - ) + set(_boost_INCLUDE_SEARCH_DIRS "") + if(BOOST_INCLUDEDIR) + list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_INCLUDEDIR}) + elseif(_ENV_BOOST_INCLUDEDIR) + list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_INCLUDEDIR}) + endif() + + if(BOOST_ROOT) + list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_ROOT}/include ${BOOST_ROOT}) + elseif(_ENV_BOOST_ROOT) + list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_ROOT}/include + ${_ENV_BOOST_ROOT}) + endif() + + if(Boost_NO_SYSTEM_PATHS) + list(APPEND _boost_INCLUDE_SEARCH_DIRS NO_CMAKE_SYSTEM_PATH + NO_SYSTEM_ENVIRONMENT_PATH) + else() + if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") + foreach(ver ${_boost_TEST_VERSIONS}) + string(REPLACE "." "_" ver "${ver}") + list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS "C:/local/boost_${ver}") + endforeach() + endif() + list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS C:/boost/include C:/boost + /sw/local/include) + endif() + + # Try to find Boost by stepping backwards through the Boost versions we know about. + # Build a list of path suffixes for each version. + set(_boost_PATH_SUFFIXES) + foreach(_boost_VER ${_boost_TEST_VERSIONS}) + # Add in a path suffix, based on the required version, ideally we could read this + # from version.hpp, but for that to work we'd need to know the include dir already + set(_boost_BOOSTIFIED_VERSION) + + # Transform 1.35 => 1_35 and 1.36.0 => 1_36_0 + if(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)\\.([0-9]+)") + set(_boost_BOOSTIFIED_VERSION + "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}_${CMAKE_MATCH_3}") + elseif(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)") + set(_boost_BOOSTIFIED_VERSION "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}") + endif() + + list( + APPEND + _boost_PATH_SUFFIXES + "boost-${_boost_BOOSTIFIED_VERSION}" + "boost_${_boost_BOOSTIFIED_VERSION}" + "boost/boost-${_boost_BOOSTIFIED_VERSION}" + "boost/boost_${_boost_BOOSTIFIED_VERSION}") + + endforeach() + + if(Boost_DEBUG) + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Include debugging info:") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " _boost_INCLUDE_SEARCH_DIRS = ${_boost_INCLUDE_SEARCH_DIRS}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + " _boost_PATH_SUFFIXES = ${_boost_PATH_SUFFIXES}") + endif() + + # Look for a standard boost header file. + find_path( + Boost_INCLUDE_DIR + NAMES boost/config.hpp + HINTS ${_boost_INCLUDE_SEARCH_DIRS} + PATH_SUFFIXES ${_boost_PATH_SUFFIXES}) endif() # ------------------------------------------------------------------------ -# Extract version information from version.hpp +# Extract version information from version.hpp # ------------------------------------------------------------------------ -# Set Boost_FOUND based only on header location and version. -# It will be updated below for component libraries. +# Set Boost_FOUND based only on header location and version. It will be updated below for +# component libraries. if(Boost_INCLUDE_DIR) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "location of version.hpp: ${Boost_INCLUDE_DIR}/boost/version.hpp") - endif() - - # Extract Boost_VERSION and Boost_LIB_VERSION from version.hpp - set(Boost_VERSION 0) - set(Boost_LIB_VERSION "") - file(STRINGS "${Boost_INCLUDE_DIR}/boost/version.hpp" _boost_VERSION_HPP_CONTENTS REGEX "#define BOOST_(LIB_)?VERSION ") - set(_Boost_VERSION_REGEX "([0-9]+)") - set(_Boost_LIB_VERSION_REGEX "\"([0-9_]+)\"") - foreach(v VERSION LIB_VERSION) - if("${_boost_VERSION_HPP_CONTENTS}" MATCHES "#define BOOST_${v} ${_Boost_${v}_REGEX}") - set(Boost_${v} "${CMAKE_MATCH_1}") - endif() - endforeach() - unset(_boost_VERSION_HPP_CONTENTS) - - math(EXPR Boost_MAJOR_VERSION "${Boost_VERSION} / 100000") - math(EXPR Boost_MINOR_VERSION "${Boost_VERSION} / 100 % 1000") - math(EXPR Boost_SUBMINOR_VERSION "${Boost_VERSION} % 100") - set(Boost_VERSION_STRING "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - - string(APPEND Boost_ERROR_REASON - "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}\nBoost include path: ${Boost_INCLUDE_DIR}") - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "version.hpp reveals boost " - "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - endif() - - if(Boost_FIND_VERSION) - # Set Boost_FOUND based on requested version. - set(_Boost_VERSION "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - if("${_Boost_VERSION}" VERSION_LESS "${Boost_FIND_VERSION}") - set(Boost_FOUND 0) - set(_Boost_VERSION_AGE "old") - elseif(Boost_FIND_VERSION_EXACT AND - NOT "${_Boost_VERSION}" VERSION_EQUAL "${Boost_FIND_VERSION}") - set(Boost_FOUND 0) - set(_Boost_VERSION_AGE "new") + if(Boost_DEBUG) + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "location of version.hpp: ${Boost_INCLUDE_DIR}/boost/version.hpp") + endif() + + # Extract Boost_VERSION and Boost_LIB_VERSION from version.hpp + set(Boost_VERSION 0) + set(Boost_LIB_VERSION "") + file(STRINGS "${Boost_INCLUDE_DIR}/boost/version.hpp" _boost_VERSION_HPP_CONTENTS + REGEX "#define BOOST_(LIB_)?VERSION ") + set(_Boost_VERSION_REGEX "([0-9]+)") + set(_Boost_LIB_VERSION_REGEX "\"([0-9_]+)\"") + foreach(v VERSION LIB_VERSION) + if("${_boost_VERSION_HPP_CONTENTS}" MATCHES + "#define BOOST_${v} ${_Boost_${v}_REGEX}") + set(Boost_${v} "${CMAKE_MATCH_1}") + endif() + endforeach() + unset(_boost_VERSION_HPP_CONTENTS) + + math(EXPR Boost_MAJOR_VERSION "${Boost_VERSION} / 100000") + math(EXPR Boost_MINOR_VERSION "${Boost_VERSION} / 100 % 1000") + math(EXPR Boost_SUBMINOR_VERSION "${Boost_VERSION} % 100") + set(Boost_VERSION_STRING + "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") + + string( + APPEND + Boost_ERROR_REASON + "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}\nBoost include path: ${Boost_INCLUDE_DIR}" + ) + if(Boost_DEBUG) + message( + STATUS + "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "version.hpp reveals boost " + "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") + endif() + + if(Boost_FIND_VERSION) + # Set Boost_FOUND based on requested version. + set(_Boost_VERSION + "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") + if("${_Boost_VERSION}" VERSION_LESS "${Boost_FIND_VERSION}") + set(Boost_FOUND 0) + set(_Boost_VERSION_AGE "old") + elseif(Boost_FIND_VERSION_EXACT AND NOT "${_Boost_VERSION}" VERSION_EQUAL + "${Boost_FIND_VERSION}") + set(Boost_FOUND 0) + set(_Boost_VERSION_AGE "new") + else() + set(Boost_FOUND 1) + endif() + if(NOT Boost_FOUND) + # State that we found a version of Boost that is too new or too old. + string( + APPEND + Boost_ERROR_REASON + "\nDetected version of Boost is too ${_Boost_VERSION_AGE}. Requested version was ${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}" + ) + if(Boost_FIND_VERSION_PATCH) + string(APPEND Boost_ERROR_REASON ".${Boost_FIND_VERSION_PATCH}") + endif() + if(NOT Boost_FIND_VERSION_EXACT) + string(APPEND Boost_ERROR_REASON " (or newer)") + endif() + string(APPEND Boost_ERROR_REASON ".") + endif() else() - set(Boost_FOUND 1) - endif() - if(NOT Boost_FOUND) - # State that we found a version of Boost that is too new or too old. - string(APPEND Boost_ERROR_REASON - "\nDetected version of Boost is too ${_Boost_VERSION_AGE}. Requested version was ${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") - if (Boost_FIND_VERSION_PATCH) - string(APPEND Boost_ERROR_REASON - ".${Boost_FIND_VERSION_PATCH}") - endif () - if (NOT Boost_FIND_VERSION_EXACT) - string(APPEND Boost_ERROR_REASON " (or newer)") - endif () - string(APPEND Boost_ERROR_REASON ".") - endif () - else() - # Caller will accept any Boost version. - set(Boost_FOUND 1) - endif() + # Caller will accept any Boost version. + set(Boost_FOUND 1) + endif() else() - set(Boost_FOUND 0) - string(APPEND Boost_ERROR_REASON - "Unable to find the Boost header files. Please set BOOST_ROOT to the root directory containing Boost or BOOST_INCLUDEDIR to the directory containing Boost's headers.") + set(Boost_FOUND 0) + string( + APPEND + Boost_ERROR_REASON + "Unable to find the Boost header files. Please set BOOST_ROOT to the root directory containing Boost or BOOST_INCLUDEDIR to the directory containing Boost's headers." + ) endif() # ------------------------------------------------------------------------ -# Prefix initialization +# Prefix initialization # ------------------------------------------------------------------------ set(Boost_LIB_PREFIX "") -if ( (GHSMULTI AND Boost_USE_STATIC_LIBS) OR - (WIN32 AND Boost_USE_STATIC_LIBS AND NOT CYGWIN) ) - set(Boost_LIB_PREFIX "lib") +if((GHSMULTI AND Boost_USE_STATIC_LIBS) + OR (WIN32 + AND Boost_USE_STATIC_LIBS + AND NOT CYGWIN)) + set(Boost_LIB_PREFIX "lib") endif() -if ( NOT Boost_NAMESPACE ) - set(Boost_NAMESPACE "boost") +if(NOT Boost_NAMESPACE) + set(Boost_NAMESPACE "boost") endif() if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_LIB_PREFIX = ${Boost_LIB_PREFIX}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_NAMESPACE = ${Boost_NAMESPACE}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_LIB_PREFIX = ${Boost_LIB_PREFIX}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Boost_NAMESPACE = ${Boost_NAMESPACE}") endif() # ------------------------------------------------------------------------ -# Suffix initialization and compiler suffix detection. +# Suffix initialization and compiler suffix detection. # ------------------------------------------------------------------------ set(_Boost_VARS_NAME - Boost_NAMESPACE - Boost_COMPILER - Boost_THREADAPI - Boost_USE_DEBUG_PYTHON - Boost_USE_MULTITHREADED - Boost_USE_STATIC_LIBS - Boost_USE_STATIC_RUNTIME - Boost_USE_STLPORT - Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS - ) -_Boost_CHANGE_DETECT(_Boost_CHANGE_LIBNAME ${_Boost_VARS_NAME}) + Boost_NAMESPACE + Boost_COMPILER + Boost_THREADAPI + Boost_USE_DEBUG_PYTHON + Boost_USE_MULTITHREADED + Boost_USE_STATIC_LIBS + Boost_USE_STATIC_RUNTIME + Boost_USE_STLPORT + Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS) +_boost_change_detect(_Boost_CHANGE_LIBNAME ${_Boost_VARS_NAME}) # Setting some more suffixes for the library -if (Boost_COMPILER) - set(_boost_COMPILER ${Boost_COMPILER}) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "using user-specified Boost_COMPILER = ${_boost_COMPILER}") - endif() +if(Boost_COMPILER) + set(_boost_COMPILER ${Boost_COMPILER}) + if(Boost_DEBUG) + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "using user-specified Boost_COMPILER = ${_boost_COMPILER}") + endif() else() - # Attempt to guess the compiler suffix - # NOTE: this is not perfect yet, if you experience any issues - # please report them and use the Boost_COMPILER variable - # to work around the problems. - _Boost_GUESS_COMPILER_PREFIX(_boost_COMPILER) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "guessed _boost_COMPILER = ${_boost_COMPILER}") - endif() + # Attempt to guess the compiler suffix NOTE: this is not perfect yet, if you + # experience any issues please report them and use the Boost_COMPILER variable to work + # around the problems. + _boost_guess_compiler_prefix(_boost_COMPILER) + if(Boost_DEBUG) + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "guessed _boost_COMPILER = ${_boost_COMPILER}") + endif() endif() -set (_boost_MULTITHREADED "-mt") -if( NOT Boost_USE_MULTITHREADED ) - set (_boost_MULTITHREADED "") +set(_boost_MULTITHREADED "-mt") +if(NOT Boost_USE_MULTITHREADED) + set(_boost_MULTITHREADED "") endif() if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_MULTITHREADED = ${_boost_MULTITHREADED}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_MULTITHREADED = ${_boost_MULTITHREADED}") endif() -#====================== +# ====================== # Systematically build up the Boost ABI tag for the 'tagged' and 'versioned' layouts # http://boost.org/doc/libs/1_66_0/more/getting_started/windows.html#library-naming # http://boost.org/doc/libs/1_66_0/boost/config/auto_link.hpp # http://boost.org/doc/libs/1_66_0/tools/build/src/tools/common.jam # http://boost.org/doc/libs/1_66_0/boostcpp.jam -set( _boost_RELEASE_ABI_TAG "-") -set( _boost_DEBUG_ABI_TAG "-") -# Key Use this library when: -# s linking statically to the C++ standard library and -# compiler runtime support libraries. +set(_boost_RELEASE_ABI_TAG "-") +set(_boost_DEBUG_ABI_TAG "-") +# Key Use this library when: s linking statically to the C++ standard library +# and compiler runtime support libraries. if(Boost_USE_STATIC_RUNTIME) - set( _boost_RELEASE_ABI_TAG "${_boost_RELEASE_ABI_TAG}s") - set( _boost_DEBUG_ABI_TAG "${_boost_DEBUG_ABI_TAG}s") + set(_boost_RELEASE_ABI_TAG "${_boost_RELEASE_ABI_TAG}s") + set(_boost_DEBUG_ABI_TAG "${_boost_DEBUG_ABI_TAG}s") endif() -# g using debug versions of the standard and runtime -# support libraries +# g using debug versions of the standard and runtime support libraries if(WIN32 AND Boost_USE_DEBUG_RUNTIME) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC" - OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xClang" - OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") - string(APPEND _boost_DEBUG_ABI_TAG "g") - endif() + if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC" + OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xClang" + OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") + string(APPEND _boost_DEBUG_ABI_TAG "g") + endif() endif() -# y using special debug build of python +# y using special debug build of python if(Boost_USE_DEBUG_PYTHON) - string(APPEND _boost_DEBUG_ABI_TAG "y") + string(APPEND _boost_DEBUG_ABI_TAG "y") endif() -# d using a debug version of your code +# d using a debug version of your code string(APPEND _boost_DEBUG_ABI_TAG "d") -# p using the STLport standard library rather than the -# default one supplied with your compiler +# p using the STLport standard library rather than the default one supplied with +# your compiler if(Boost_USE_STLPORT) - string(APPEND _boost_RELEASE_ABI_TAG "p") - string(APPEND _boost_DEBUG_ABI_TAG "p") + string(APPEND _boost_RELEASE_ABI_TAG "p") + string(APPEND _boost_DEBUG_ABI_TAG "p") endif() -# n using the STLport deprecated "native iostreams" feature -# removed from the documentation in 1.43.0 but still present in -# boost/config/auto_link.hpp +# n using the STLport deprecated "native iostreams" feature removed from the +# documentation in 1.43.0 but still present in boost/config/auto_link.hpp if(Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS) - string(APPEND _boost_RELEASE_ABI_TAG "n") - string(APPEND _boost_DEBUG_ABI_TAG "n") + string(APPEND _boost_RELEASE_ABI_TAG "n") + string(APPEND _boost_DEBUG_ABI_TAG "n") endif() -# -x86 Architecture and address model tag -# First character is the architecture, then word-size, either 32 or 64 -# Only used in 'versioned' layout, added in Boost 1.66.0 +# -x86 Architecture and address model tag First character is the architecture, then +# word-size, either 32 or 64 Only used in 'versioned' layout, added in Boost 1.66.0 if(DEFINED Boost_ARCHITECTURE) - set(_boost_ARCHITECTURE_TAG "${Boost_ARCHITECTURE}") - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "using user-specified Boost_ARCHITECTURE = ${_boost_ARCHITECTURE_TAG}") - endif() + set(_boost_ARCHITECTURE_TAG "${Boost_ARCHITECTURE}") + if(Boost_DEBUG) + message( + STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "using user-specified Boost_ARCHITECTURE = ${_boost_ARCHITECTURE_TAG}") + endif() else() - set(_boost_ARCHITECTURE_TAG "") - # {CMAKE_CXX_COMPILER_ARCHITECTURE_ID} is not currently set for all compilers - if(NOT "x${CMAKE_CXX_COMPILER_ARCHITECTURE_ID}" STREQUAL "x" AND NOT Boost_VERSION VERSION_LESS 106600) - string(APPEND _boost_ARCHITECTURE_TAG "-") - # This needs to be kept in-sync with the section of CMakePlatformId.h.in - # inside 'defined(_WIN32) && defined(_MSC_VER)' - if(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "IA64") - string(APPEND _boost_ARCHITECTURE_TAG "i") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "X86" - OR CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "x64") - string(APPEND _boost_ARCHITECTURE_TAG "x") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID MATCHES "^ARM") - string(APPEND _boost_ARCHITECTURE_TAG "a") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "MIPS") - string(APPEND _boost_ARCHITECTURE_TAG "m") - endif() - - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - string(APPEND _boost_ARCHITECTURE_TAG "64") - else() - string(APPEND _boost_ARCHITECTURE_TAG "32") + set(_boost_ARCHITECTURE_TAG "") + # {CMAKE_CXX_COMPILER_ARCHITECTURE_ID} is not currently set for all compilers + if(NOT "x${CMAKE_CXX_COMPILER_ARCHITECTURE_ID}" STREQUAL "x" AND NOT Boost_VERSION + VERSION_LESS 106600) + string(APPEND _boost_ARCHITECTURE_TAG "-") + # This needs to be kept in-sync with the section of CMakePlatformId.h.in inside + # 'defined(_WIN32) && defined(_MSC_VER)' + if(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "IA64") + string(APPEND _boost_ARCHITECTURE_TAG "i") + elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "X86" + OR CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "x64") + string(APPEND _boost_ARCHITECTURE_TAG "x") + elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID MATCHES "^ARM") + string(APPEND _boost_ARCHITECTURE_TAG "a") + elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "MIPS") + string(APPEND _boost_ARCHITECTURE_TAG "m") + endif() + + if(CMAKE_SIZEOF_VOID_P EQUAL 8) + string(APPEND _boost_ARCHITECTURE_TAG "64") + else() + string(APPEND _boost_ARCHITECTURE_TAG "32") + endif() endif() - endif() endif() if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_RELEASE_ABI_TAG = ${_boost_RELEASE_ABI_TAG}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_DEBUG_ABI_TAG = ${_boost_DEBUG_ABI_TAG}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_RELEASE_ABI_TAG = ${_boost_RELEASE_ABI_TAG}") + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_DEBUG_ABI_TAG = ${_boost_DEBUG_ABI_TAG}") endif() # ------------------------------------------------------------------------ -# Begin finding boost libraries +# Begin finding boost libraries # ------------------------------------------------------------------------ set(_Boost_VARS_LIB "") foreach(c DEBUG RELEASE) - set(_Boost_VARS_LIB_${c} BOOST_LIBRARYDIR Boost_LIBRARY_DIR_${c}) - list(APPEND _Boost_VARS_LIB ${_Boost_VARS_LIB_${c}}) - _Boost_CHANGE_DETECT(_Boost_CHANGE_LIBDIR_${c} ${_Boost_VARS_DIR} ${_Boost_VARS_LIB_${c}} Boost_INCLUDE_DIR) - # Clear Boost_LIBRARY_DIR_${c} if it did not change but other input affecting the - # location did. We will find a new one based on the new inputs. - if(_Boost_CHANGE_LIBDIR_${c} AND NOT _Boost_LIBRARY_DIR_${c}_CHANGED) - unset(Boost_LIBRARY_DIR_${c} CACHE) - endif() - - # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is set, prefer its value. - if(Boost_LIBRARY_DIR_${c}) - set(_boost_LIBRARY_SEARCH_DIRS_${c} ${Boost_LIBRARY_DIR_${c}} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) - else() - set(_boost_LIBRARY_SEARCH_DIRS_${c} "") - if(BOOST_LIBRARYDIR) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_LIBRARYDIR}) - elseif(_ENV_BOOST_LIBRARYDIR) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_LIBRARYDIR}) + set(_Boost_VARS_LIB_${c} BOOST_LIBRARYDIR Boost_LIBRARY_DIR_${c}) + list(APPEND _Boost_VARS_LIB ${_Boost_VARS_LIB_${c}}) + _boost_change_detect(_Boost_CHANGE_LIBDIR_${c} ${_Boost_VARS_DIR} + ${_Boost_VARS_LIB_${c}} Boost_INCLUDE_DIR) + # Clear Boost_LIBRARY_DIR_${c} if it did not change but other input affecting the + # location did. We will find a new one based on the new inputs. + if(_Boost_CHANGE_LIBDIR_${c} AND NOT _Boost_LIBRARY_DIR_${c}_CHANGED) + unset(Boost_LIBRARY_DIR_${c} CACHE) endif() - if(BOOST_ROOT) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_ROOT}/lib ${BOOST_ROOT}/stage/lib) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${BOOST_ROOT}") - elseif(_ENV_BOOST_ROOT) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_ROOT}/lib ${_ENV_BOOST_ROOT}/stage/lib) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${_ENV_BOOST_ROOT}") - endif() - - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} - ${Boost_INCLUDE_DIR}/lib - ${Boost_INCLUDE_DIR}/../lib - ${Boost_INCLUDE_DIR}/stage/lib - ) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}/..") - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}") - if( Boost_NO_SYSTEM_PATHS ) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) + # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is set, prefer its value. + if(Boost_LIBRARY_DIR_${c}) + set(_boost_LIBRARY_SEARCH_DIRS_${c} ${Boost_LIBRARY_DIR_${c}} NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH) else() - foreach(ver ${_boost_TEST_VERSIONS}) - string(REPLACE "." "_" ver "${ver}") - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "C:/local/boost_${ver}") - endforeach() - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "C:/boost") - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} PATHS - C:/boost/lib - C:/boost - /sw/local/lib - ) + set(_boost_LIBRARY_SEARCH_DIRS_${c} "") + if(BOOST_LIBRARYDIR) + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_LIBRARYDIR}) + elseif(_ENV_BOOST_LIBRARYDIR) + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_LIBRARYDIR}) + endif() + + if(BOOST_ROOT) + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_ROOT}/lib + ${BOOST_ROOT}/stage/lib) + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "${BOOST_ROOT}") + elseif(_ENV_BOOST_ROOT) + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_ROOT}/lib + ${_ENV_BOOST_ROOT}/stage/lib) + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "${_ENV_BOOST_ROOT}") + endif() + + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${Boost_INCLUDE_DIR}/lib + ${Boost_INCLUDE_DIR}/../lib ${Boost_INCLUDE_DIR}/stage/lib) + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}/..") + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}") + if(Boost_NO_SYSTEM_PATHS) + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} NO_CMAKE_SYSTEM_PATH + NO_SYSTEM_ENVIRONMENT_PATH) + else() + foreach(ver ${_boost_TEST_VERSIONS}) + string(REPLACE "." "_" ver "${ver}") + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "C:/local/boost_${ver}") + endforeach() + _boost_update_windows_library_search_dirs_with_prebuilt_paths( + _boost_LIBRARY_SEARCH_DIRS_${c} "C:/boost") + list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} PATHS C:/boost/lib C:/boost + /sw/local/lib) + endif() endif() - endif() endforeach() if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_LIBRARY_SEARCH_DIRS_RELEASE = ${_boost_LIBRARY_SEARCH_DIRS_RELEASE}" - "_boost_LIBRARY_SEARCH_DIRS_DEBUG = ${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") + message( + STATUS + "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "_boost_LIBRARY_SEARCH_DIRS_RELEASE = ${_boost_LIBRARY_SEARCH_DIRS_RELEASE}" + "_boost_LIBRARY_SEARCH_DIRS_DEBUG = ${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") endif() # Support preference of static libs by adjusting CMAKE_FIND_LIBRARY_SUFFIXES -if( Boost_USE_STATIC_LIBS ) - set( _boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES ${CMAKE_FIND_LIBRARY_SUFFIXES}) - if(WIN32) - list(INSERT CMAKE_FIND_LIBRARY_SUFFIXES 0 .lib .a) - else() - set(CMAKE_FIND_LIBRARY_SUFFIXES .a) - endif() +if(Boost_USE_STATIC_LIBS) + set(_boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES ${CMAKE_FIND_LIBRARY_SUFFIXES}) + if(WIN32) + list(INSERT CMAKE_FIND_LIBRARY_SUFFIXES 0 .lib .a) + else() + set(CMAKE_FIND_LIBRARY_SUFFIXES .a) + endif() endif() # We want to use the tag inline below without risking double dashes if(_boost_RELEASE_ABI_TAG) - if(${_boost_RELEASE_ABI_TAG} STREQUAL "-") - set(_boost_RELEASE_ABI_TAG "") - endif() + if(${_boost_RELEASE_ABI_TAG} STREQUAL "-") + set(_boost_RELEASE_ABI_TAG "") + endif() endif() if(_boost_DEBUG_ABI_TAG) - if(${_boost_DEBUG_ABI_TAG} STREQUAL "-") - set(_boost_DEBUG_ABI_TAG "") - endif() + if(${_boost_DEBUG_ABI_TAG} STREQUAL "-") + set(_boost_DEBUG_ABI_TAG "") + endif() endif() -# The previous behavior of FindBoost when Boost_USE_STATIC_LIBS was enabled -# on WIN32 was to: -# 1. Search for static libs compiled against a SHARED C++ standard runtime library (use if found) -# 2. Search for static libs compiled against a STATIC C++ standard runtime library (use if found) -# We maintain this behavior since changing it could break people's builds. -# To disable the ambiguous behavior, the user need only -# set Boost_USE_STATIC_RUNTIME either ON or OFF. +# The previous behavior of FindBoost when Boost_USE_STATIC_LIBS was enabled on WIN32 was +# to: 1. Search for static libs compiled against a SHARED C++ standard runtime library +# (use if found) 2. Search for static libs compiled against a STATIC C++ standard runtime +# library (use if found) We maintain this behavior since changing it could break people's +# builds. To disable the ambiguous behavior, the user need only set +# Boost_USE_STATIC_RUNTIME either ON or OFF. set(_boost_STATIC_RUNTIME_WORKAROUND false) if(WIN32 AND Boost_USE_STATIC_LIBS) - if(NOT DEFINED Boost_USE_STATIC_RUNTIME) - set(_boost_STATIC_RUNTIME_WORKAROUND TRUE) - endif() + if(NOT DEFINED Boost_USE_STATIC_RUNTIME) + set(_boost_STATIC_RUNTIME_WORKAROUND TRUE) + endif() endif() -# On versions < 1.35, remove the System library from the considered list -# since it wasn't added until 1.35. +# On versions < 1.35, remove the System library from the considered list since it wasn't +# added until 1.35. if(Boost_VERSION AND Boost_FIND_COMPONENTS) - if(Boost_VERSION LESS 103500) - list(REMOVE_ITEM Boost_FIND_COMPONENTS system) - endif() + if(Boost_VERSION LESS 103500) + list(REMOVE_ITEM Boost_FIND_COMPONENTS system) + endif() endif() -# Additional components may be required via component dependencies. -# Add any missing components to the list. -_Boost_MISSING_DEPENDENCIES(Boost_FIND_COMPONENTS _Boost_EXTRA_FIND_COMPONENTS) +# Additional components may be required via component dependencies. Add any missing +# components to the list. +_boost_missing_dependencies(Boost_FIND_COMPONENTS _Boost_EXTRA_FIND_COMPONENTS) # If thread is required, get the thread libs as a dependency if("thread" IN_LIST Boost_FIND_COMPONENTS) - if(Boost_FIND_QUIETLY) - set(_Boost_find_quiet QUIET) - else() - set(_Boost_find_quiet "") - endif() - find_package(Threads ${_Boost_find_quiet}) - unset(_Boost_find_quiet) + if(Boost_FIND_QUIETLY) + set(_Boost_find_quiet QUIET) + else() + set(_Boost_find_quiet "") + endif() + find_package(Threads ${_Boost_find_quiet}) + unset(_Boost_find_quiet) endif() # If the user changed any of our control inputs flush previous results. -if(_Boost_CHANGE_LIBDIR_DEBUG OR _Boost_CHANGE_LIBDIR_RELEASE OR _Boost_CHANGE_LIBNAME) - foreach(COMPONENT ${_Boost_COMPONENTS_SEARCHED}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - foreach(c DEBUG RELEASE) - set(_var Boost_${UPPERCOMPONENT}_LIBRARY_${c}) - unset(${_var} CACHE) - set(${_var} "${_var}-NOTFOUND") +if(_Boost_CHANGE_LIBDIR_DEBUG + OR _Boost_CHANGE_LIBDIR_RELEASE + OR _Boost_CHANGE_LIBNAME) + foreach(COMPONENT ${_Boost_COMPONENTS_SEARCHED}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + foreach(c DEBUG RELEASE) + set(_var Boost_${UPPERCOMPONENT}_LIBRARY_${c}) + unset(${_var} CACHE) + set(${_var} "${_var}-NOTFOUND") + endforeach() endforeach() - endforeach() - set(_Boost_COMPONENTS_SEARCHED "") + set(_Boost_COMPONENTS_SEARCHED "") endif() foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - - set( _boost_docstring_release "Boost ${COMPONENT} library (release)") - set( _boost_docstring_debug "Boost ${COMPONENT} library (debug)") - - # Compute component-specific hints. - set(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT "") - if(${COMPONENT} STREQUAL "mpi" OR ${COMPONENT} STREQUAL "mpi_python" OR - ${COMPONENT} STREQUAL "graph_parallel") - foreach(lib ${MPI_CXX_LIBRARIES} ${MPI_C_LIBRARIES}) - if(IS_ABSOLUTE "${lib}") - get_filename_component(libdir "${lib}" PATH) - string(REPLACE "\\" "/" libdir "${libdir}") - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT ${libdir}) - endif() - endforeach() - endif() - - # Handle Python version suffixes - unset(COMPONENT_PYTHON_VERSION_MAJOR) - unset(COMPONENT_PYTHON_VERSION_MINOR) - if(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\$") - set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") - set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") - elseif(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\\.?([0-9])\$") - set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") - set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") - set(COMPONENT_PYTHON_VERSION_MINOR "${CMAKE_MATCH_3}") - endif() - - unset(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - if (COMPONENT_PYTHON_VERSION_MINOR) - # Boost >= 1.67 - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # Debian/Ubuntu (Some versions omit the 2 and/or 3 from the suffix) - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # Gentoo - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # RPMs - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - endif() - if (COMPONENT_PYTHON_VERSION_MAJOR AND NOT COMPONENT_PYTHON_VERSION_MINOR) - # Boost < 1.67 - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}") - endif() - - # Consolidate and report component-specific hints. - if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Component-specific library search names for ${COMPONENT_NAME}: " - "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME}") + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + + set(_boost_docstring_release "Boost ${COMPONENT} library (release)") + set(_boost_docstring_debug "Boost ${COMPONENT} library (debug)") + + # Compute component-specific hints. + set(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT "") + if(${COMPONENT} STREQUAL "mpi" + OR ${COMPONENT} STREQUAL "mpi_python" + OR ${COMPONENT} STREQUAL "graph_parallel") + foreach(lib ${MPI_CXX_LIBRARIES} ${MPI_C_LIBRARIES}) + if(IS_ABSOLUTE "${lib}") + get_filename_component(libdir "${lib}" PATH) + string(REPLACE "\\" "/" libdir "${libdir}") + list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT ${libdir}) + endif() + endforeach() endif() - endif() - if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Component-specific library search paths for ${COMPONENT}: " - "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT}") - endif() - endif() - - # - # Find headers - # - _Boost_COMPONENT_HEADERS("${COMPONENT}" Boost_${UPPERCOMPONENT}_HEADER_NAME) - # Look for a standard boost header file. - if(Boost_${UPPERCOMPONENT}_HEADER_NAME) - if(EXISTS "${Boost_INCLUDE_DIR}/${Boost_${UPPERCOMPONENT}_HEADER_NAME}") - set(Boost_${UPPERCOMPONENT}_HEADER ON) + + # Handle Python version suffixes + unset(COMPONENT_PYTHON_VERSION_MAJOR) + unset(COMPONENT_PYTHON_VERSION_MINOR) + if(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\$") + set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") + set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") + elseif(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\\.?([0-9])\$") + set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") + set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") + set(COMPONENT_PYTHON_VERSION_MINOR "${CMAKE_MATCH_3}") + endif() + + unset(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) + if(COMPONENT_PYTHON_VERSION_MINOR) + # Boost >= 1.67 + list( + APPEND + _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}" + ) + # Debian/Ubuntu (Some versions omit the 2 and/or 3 from the suffix) + list( + APPEND + _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}" + ) + list( + APPEND + _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}" + ) + # Gentoo + list( + APPEND + _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}" + ) + # RPMs + list( + APPEND + _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}" + ) + endif() + if(COMPONENT_PYTHON_VERSION_MAJOR AND NOT COMPONENT_PYTHON_VERSION_MINOR) + # Boost < 1.67 + list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME + "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}") + endif() + + # Consolidate and report component-specific hints. + if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) + list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) + if(Boost_DEBUG) + message( + STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Component-specific library search names for ${COMPONENT_NAME}: " + "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME}") + endif() + endif() + if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) + list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) + if(Boost_DEBUG) + message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Component-specific library search paths for ${COMPONENT}: " + "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT}") + endif() + endif() + + # + # Find headers + # + _boost_component_headers("${COMPONENT}" Boost_${UPPERCOMPONENT}_HEADER_NAME) + # Look for a standard boost header file. + if(Boost_${UPPERCOMPONENT}_HEADER_NAME) + if(EXISTS "${Boost_INCLUDE_DIR}/${Boost_${UPPERCOMPONENT}_HEADER_NAME}") + set(Boost_${UPPERCOMPONENT}_HEADER ON) + else() + set(Boost_${UPPERCOMPONENT}_HEADER OFF) + endif() else() - set(Boost_${UPPERCOMPONENT}_HEADER OFF) - endif() - else() - set(Boost_${UPPERCOMPONENT}_HEADER ON) - message(WARNING "No header defined for ${COMPONENT}; skipping header check") - endif() - - # - # Find RELEASE libraries - # - unset(_boost_RELEASE_NAMES) - foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} ) + set(Boost_${UPPERCOMPONENT}_HEADER ON) + message(WARNING "No header defined for ${COMPONENT}; skipping header check") + endif() + + # + # Find RELEASE libraries + # + unset(_boost_RELEASE_NAMES) + foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) + foreach(compiler IN LISTS _boost_COMPILER) + list( + APPEND + _boost_RELEASE_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} + ) + endforeach() + list( + APPEND + _boost_RELEASE_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}) + if(_boost_STATIC_RUNTIME_WORKAROUND) + set(_boost_RELEASE_STATIC_ABI_TAG "-s${_boost_RELEASE_ABI_TAG}") + foreach(compiler IN LISTS _boost_COMPILER) + list( + APPEND + _boost_RELEASE_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} + ) + endforeach() + list( + APPEND + _boost_RELEASE_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} + ) + endif() endforeach() - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component} ) - if(_boost_STATIC_RUNTIME_WORKAROUND) - set(_boost_RELEASE_STATIC_ABI_TAG "-s${_boost_RELEASE_ABI_TAG}") - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} ) - endforeach() - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} ) - endif() - endforeach() - if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") - _Boost_PREPEND_LIST_WITH_THREADAPI(_boost_RELEASE_NAMES ${_boost_RELEASE_NAMES}) - endif() - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Searching for ${UPPERCOMPONENT}_LIBRARY_RELEASE: ${_boost_RELEASE_NAMES}") - endif() - - # if Boost_LIBRARY_DIR_RELEASE is not defined, - # but Boost_LIBRARY_DIR_DEBUG is, look there first for RELEASE libs - if(NOT Boost_LIBRARY_DIR_RELEASE AND Boost_LIBRARY_DIR_DEBUG) - list(INSERT _boost_LIBRARY_SEARCH_DIRS_RELEASE 0 ${Boost_LIBRARY_DIR_DEBUG}) - endif() - - # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. - string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp "${_boost_LIBRARY_SEARCH_DIRS_RELEASE}") - - if(Boost_USE_RELEASE_LIBS) - _Boost_FIND_LIBRARY(Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE RELEASE - NAMES ${_boost_RELEASE_NAMES} - HINTS ${_boost_LIBRARY_SEARCH_DIRS_tmp} - NAMES_PER_DIR - DOC "${_boost_docstring_release}" - ) - endif() - - # - # Find DEBUG libraries - # - unset(_boost_DEBUG_NAMES) - foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} ) + if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") + _boost_prepend_list_with_threadapi(_boost_RELEASE_NAMES ${_boost_RELEASE_NAMES}) + endif() + if(Boost_DEBUG) + message( + STATUS + "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + "Searching for ${UPPERCOMPONENT}_LIBRARY_RELEASE: ${_boost_RELEASE_NAMES}" + ) + endif() + + # if Boost_LIBRARY_DIR_RELEASE is not defined, but Boost_LIBRARY_DIR_DEBUG is, look + # there first for RELEASE libs + if(NOT Boost_LIBRARY_DIR_RELEASE AND Boost_LIBRARY_DIR_DEBUG) + list(INSERT _boost_LIBRARY_SEARCH_DIRS_RELEASE 0 ${Boost_LIBRARY_DIR_DEBUG}) + endif() + + # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. + string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp + "${_boost_LIBRARY_SEARCH_DIRS_RELEASE}") + + if(Boost_USE_RELEASE_LIBS) + _boost_find_library( + Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE + RELEASE + NAMES + ${_boost_RELEASE_NAMES} + HINTS + ${_boost_LIBRARY_SEARCH_DIRS_tmp} + NAMES_PER_DIR + DOC + "${_boost_docstring_release}") + endif() + + # + # Find DEBUG libraries + # + unset(_boost_DEBUG_NAMES) + foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) + foreach(compiler IN LISTS _boost_COMPILER) + list( + APPEND + _boost_DEBUG_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} + ) + endforeach() + list( + APPEND + _boost_DEBUG_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}) + if(_boost_STATIC_RUNTIME_WORKAROUND) + set(_boost_DEBUG_STATIC_ABI_TAG "-s${_boost_DEBUG_ABI_TAG}") + foreach(compiler IN LISTS _boost_COMPILER) + list( + APPEND + _boost_DEBUG_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} + ) + endforeach() + list( + APPEND + _boost_DEBUG_NAMES + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} + ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} + ) + endif() endforeach() - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component} ) - if(_boost_STATIC_RUNTIME_WORKAROUND) - set(_boost_DEBUG_STATIC_ABI_TAG "-s${_boost_DEBUG_ABI_TAG}") - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} ) - endforeach() - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} ) - endif() - endforeach() - if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") - _Boost_PREPEND_LIST_WITH_THREADAPI(_boost_DEBUG_NAMES ${_boost_DEBUG_NAMES}) - endif() - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " + if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") + _boost_prepend_list_with_threadapi(_boost_DEBUG_NAMES ${_boost_DEBUG_NAMES}) + endif() + if(Boost_DEBUG) + message( + STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " "Searching for ${UPPERCOMPONENT}_LIBRARY_DEBUG: ${_boost_DEBUG_NAMES}") - endif() - - # if Boost_LIBRARY_DIR_DEBUG is not defined, - # but Boost_LIBRARY_DIR_RELEASE is, look there first for DEBUG libs - if(NOT Boost_LIBRARY_DIR_DEBUG AND Boost_LIBRARY_DIR_RELEASE) - list(INSERT _boost_LIBRARY_SEARCH_DIRS_DEBUG 0 ${Boost_LIBRARY_DIR_RELEASE}) - endif() + endif() - # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. - string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp "${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") + # if Boost_LIBRARY_DIR_DEBUG is not defined, but Boost_LIBRARY_DIR_RELEASE is, look + # there first for DEBUG libs + if(NOT Boost_LIBRARY_DIR_DEBUG AND Boost_LIBRARY_DIR_RELEASE) + list(INSERT _boost_LIBRARY_SEARCH_DIRS_DEBUG 0 ${Boost_LIBRARY_DIR_RELEASE}) + endif() - if(Boost_USE_DEBUG_LIBS) - _Boost_FIND_LIBRARY(Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG DEBUG - NAMES ${_boost_DEBUG_NAMES} - HINTS ${_boost_LIBRARY_SEARCH_DIRS_tmp} - NAMES_PER_DIR - DOC "${_boost_docstring_debug}" - ) - endif () + # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. + string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp + "${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") + + if(Boost_USE_DEBUG_LIBS) + _boost_find_library( + Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG + DEBUG + NAMES + ${_boost_DEBUG_NAMES} + HINTS + ${_boost_LIBRARY_SEARCH_DIRS_tmp} + NAMES_PER_DIR + DOC + "${_boost_docstring_debug}") + endif() - if(Boost_REALPATH) - _Boost_SWAP_WITH_REALPATH(Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE "${_boost_docstring_release}") - _Boost_SWAP_WITH_REALPATH(Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG "${_boost_docstring_debug}" ) - endif() + if(Boost_REALPATH) + _boost_swap_with_realpath(Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE + "${_boost_docstring_release}") + _boost_swap_with_realpath(Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG + "${_boost_docstring_debug}") + endif() - _Boost_ADJUST_LIB_VARS(${UPPERCOMPONENT}) + _boost_adjust_lib_vars(${UPPERCOMPONENT}) - # Check if component requires some compiler features - _Boost_COMPILER_FEATURES(${COMPONENT} _Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) + # Check if component requires some compiler features + _boost_compiler_features(${COMPONENT} _Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) endforeach() # Restore the original find library ordering -if( Boost_USE_STATIC_LIBS ) - set(CMAKE_FIND_LIBRARY_SUFFIXES ${_boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES}) +if(Boost_USE_STATIC_LIBS) + set(CMAKE_FIND_LIBRARY_SUFFIXES ${_boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES}) endif() # ------------------------------------------------------------------------ -# End finding boost libraries +# End finding boost libraries # ------------------------------------------------------------------------ set(Boost_INCLUDE_DIRS ${Boost_INCLUDE_DIR}) set(Boost_LIBRARY_DIRS) if(Boost_LIBRARY_DIR_RELEASE) - list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_RELEASE}) + list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_RELEASE}) endif() if(Boost_LIBRARY_DIR_DEBUG) - list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_DEBUG}) + list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_DEBUG}) endif() if(Boost_LIBRARY_DIRS) - list(REMOVE_DUPLICATES Boost_LIBRARY_DIRS) + list(REMOVE_DUPLICATES Boost_LIBRARY_DIRS) endif() -# The above setting of Boost_FOUND was based only on the header files. -# Update it for the requested component libraries. +# The above setting of Boost_FOUND was based only on the header files. Update it for the +# requested component libraries. if(Boost_FOUND) - # The headers were found. Check for requested component libs. - set(_boost_CHECKED_COMPONENT FALSE) - set(_Boost_MISSING_COMPONENTS "") - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - set(_boost_CHECKED_COMPONENT TRUE) - if(NOT Boost_${UPPERCOMPONENT}_FOUND AND Boost_FIND_REQUIRED_${COMPONENT}) - list(APPEND _Boost_MISSING_COMPONENTS ${COMPONENT}) + # The headers were found. Check for requested component libs. + set(_boost_CHECKED_COMPONENT FALSE) + set(_Boost_MISSING_COMPONENTS "") + foreach(COMPONENT ${Boost_FIND_COMPONENTS}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + set(_boost_CHECKED_COMPONENT TRUE) + if(NOT Boost_${UPPERCOMPONENT}_FOUND AND Boost_FIND_REQUIRED_${COMPONENT}) + list(APPEND _Boost_MISSING_COMPONENTS ${COMPONENT}) + endif() + endforeach() + if(_Boost_MISSING_COMPONENTS AND _Boost_EXTRA_FIND_COMPONENTS) + # Optional indirect dependencies are not counted as missing. + list(REMOVE_ITEM _Boost_MISSING_COMPONENTS ${_Boost_EXTRA_FIND_COMPONENTS}) endif() - endforeach() - if(_Boost_MISSING_COMPONENTS AND _Boost_EXTRA_FIND_COMPONENTS) - # Optional indirect dependencies are not counted as missing. - list(REMOVE_ITEM _Boost_MISSING_COMPONENTS ${_Boost_EXTRA_FIND_COMPONENTS}) - endif() - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] Boost_FOUND = ${Boost_FOUND}") - endif() + if(Boost_DEBUG) + message( + STATUS + "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] Boost_FOUND = ${Boost_FOUND}" + ) + endif() - if (_Boost_MISSING_COMPONENTS) - set(Boost_FOUND 0) - # We were unable to find some libraries, so generate a sensible - # error message that lists the libraries we were unable to find. - string(APPEND Boost_ERROR_REASON - "\nCould not find the following") - if(Boost_USE_STATIC_LIBS) - string(APPEND Boost_ERROR_REASON " static") - endif() - string(APPEND Boost_ERROR_REASON - " Boost libraries:\n") - foreach(COMPONENT ${_Boost_MISSING_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - string(APPEND Boost_ERROR_REASON - " ${Boost_NAMESPACE}_${COMPONENT}${Boost_ERROR_REASON_${UPPERCOMPONENT}}\n") - endforeach() + if(_Boost_MISSING_COMPONENTS) + set(Boost_FOUND 0) + # We were unable to find some libraries, so generate a sensible error message that + # lists the libraries we were unable to find. + string(APPEND Boost_ERROR_REASON "\nCould not find the following") + if(Boost_USE_STATIC_LIBS) + string(APPEND Boost_ERROR_REASON " static") + endif() + string(APPEND Boost_ERROR_REASON " Boost libraries:\n") + foreach(COMPONENT ${_Boost_MISSING_COMPONENTS}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + string( + APPEND + Boost_ERROR_REASON + " ${Boost_NAMESPACE}_${COMPONENT}${Boost_ERROR_REASON_${UPPERCOMPONENT}}\n" + ) + endforeach() + + list(LENGTH Boost_FIND_COMPONENTS Boost_NUM_COMPONENTS_WANTED) + list(LENGTH _Boost_MISSING_COMPONENTS Boost_NUM_MISSING_COMPONENTS) + if(${Boost_NUM_COMPONENTS_WANTED} EQUAL ${Boost_NUM_MISSING_COMPONENTS}) + string( + APPEND + Boost_ERROR_REASON + "No Boost libraries were found. You may need to set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost." + ) + else() + string( + APPEND + Boost_ERROR_REASON + "Some (but not all) of the required Boost libraries were found. You may need to install these additional Boost libraries. Alternatively, set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost." + ) + endif() + endif() - list(LENGTH Boost_FIND_COMPONENTS Boost_NUM_COMPONENTS_WANTED) - list(LENGTH _Boost_MISSING_COMPONENTS Boost_NUM_MISSING_COMPONENTS) - if (${Boost_NUM_COMPONENTS_WANTED} EQUAL ${Boost_NUM_MISSING_COMPONENTS}) - string(APPEND Boost_ERROR_REASON - "No Boost libraries were found. You may need to set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost.") - else () - string(APPEND Boost_ERROR_REASON - "Some (but not all) of the required Boost libraries were found. You may need to install these additional Boost libraries. Alternatively, set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost.") - endif () - endif () + if(NOT Boost_LIBRARY_DIRS AND NOT _boost_CHECKED_COMPONENT) + # Compatibility Code for backwards compatibility with CMake 2.4's FindBoost + # module. - if( NOT Boost_LIBRARY_DIRS AND NOT _boost_CHECKED_COMPONENT ) - # Compatibility Code for backwards compatibility with CMake - # 2.4's FindBoost module. + # Look for the boost library path. Note that the user may not have installed any + # libraries so it is quite possible the Boost_LIBRARY_DIRS may not exist. + set(_boost_LIB_DIR ${Boost_INCLUDE_DIR}) - # Look for the boost library path. - # Note that the user may not have installed any libraries - # so it is quite possible the Boost_LIBRARY_DIRS may not exist. - set(_boost_LIB_DIR ${Boost_INCLUDE_DIR}) + if("${_boost_LIB_DIR}" MATCHES "boost-[0-9]+") + get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) + endif() - if("${_boost_LIB_DIR}" MATCHES "boost-[0-9]+") - get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) - endif() + if("${_boost_LIB_DIR}" MATCHES "/include$") + # Strip off the trailing "/include" in the path. + get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) + endif() - if("${_boost_LIB_DIR}" MATCHES "/include$") - # Strip off the trailing "/include" in the path. - get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) - endif() + if(EXISTS "${_boost_LIB_DIR}/lib") + string(APPEND _boost_LIB_DIR /lib) + elseif(EXISTS "${_boost_LIB_DIR}/stage/lib") + string(APPEND _boost_LIB_DIR "/stage/lib") + else() + set(_boost_LIB_DIR "") + endif() - if(EXISTS "${_boost_LIB_DIR}/lib") - string(APPEND _boost_LIB_DIR /lib) - elseif(EXISTS "${_boost_LIB_DIR}/stage/lib") - string(APPEND _boost_LIB_DIR "/stage/lib") - else() - set(_boost_LIB_DIR "") - endif() + if(_boost_LIB_DIR AND EXISTS "${_boost_LIB_DIR}") + set(Boost_LIBRARY_DIRS ${_boost_LIB_DIR}) + endif() - if(_boost_LIB_DIR AND EXISTS "${_boost_LIB_DIR}") - set(Boost_LIBRARY_DIRS ${_boost_LIB_DIR}) endif() - - endif() else() - # Boost headers were not found so no components were found. - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - set(Boost_${UPPERCOMPONENT}_FOUND 0) - endforeach() + # Boost headers were not found so no components were found. + foreach(COMPONENT ${Boost_FIND_COMPONENTS}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + set(Boost_${UPPERCOMPONENT}_FOUND 0) + endforeach() endif() # ------------------------------------------------------------------------ -# Add imported targets +# Add imported targets # ------------------------------------------------------------------------ if(Boost_FOUND) - # For header-only libraries - if(NOT TARGET Boost::boost) - add_library(Boost::boost INTERFACE IMPORTED) - if(Boost_INCLUDE_DIRS) - set_target_properties(Boost::boost PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${Boost_INCLUDE_DIRS}") - endif() - endif() - - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - if(_Boost_IMPORTED_TARGETS AND NOT TARGET Boost::${COMPONENT}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - if(Boost_${UPPERCOMPONENT}_FOUND) - if(Boost_USE_STATIC_LIBS) - add_library(Boost::${COMPONENT} STATIC IMPORTED) - else() - # Even if Boost_USE_STATIC_LIBS is OFF, we might have static - # libraries as a result. - add_library(Boost::${COMPONENT} UNKNOWN IMPORTED) - endif() + # For header-only libraries + if(NOT TARGET Boost::boost) + add_library(Boost::boost INTERFACE IMPORTED) if(Boost_INCLUDE_DIRS) - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${Boost_INCLUDE_DIRS}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY}") - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" - IMPORTED_LOCATION "${Boost_${UPPERCOMPONENT}_LIBRARY}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") - set_property(TARGET Boost::${COMPONENT} APPEND PROPERTY - IMPORTED_CONFIGURATIONS RELEASE) - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES_RELEASE "CXX" - IMPORTED_LOCATION_RELEASE "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") - set_property(TARGET Boost::${COMPONENT} APPEND PROPERTY - IMPORTED_CONFIGURATIONS DEBUG) - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES_DEBUG "CXX" - IMPORTED_LOCATION_DEBUG "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") - endif() - if(_Boost_${UPPERCOMPONENT}_DEPENDENCIES) - unset(_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES) - foreach(dep ${_Boost_${UPPERCOMPONENT}_DEPENDENCIES}) - list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES Boost::${dep}) - endforeach() - if(COMPONENT STREQUAL "thread") - list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES Threads::Threads) - endif() - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_LINK_LIBRARIES "${_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES}") + set_target_properties(Boost::boost PROPERTIES INTERFACE_INCLUDE_DIRECTORIES + "${Boost_INCLUDE_DIRS}") endif() - if(_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_COMPILE_FEATURES "${_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES}") - endif() - endif() endif() - endforeach() + + foreach(COMPONENT ${Boost_FIND_COMPONENTS}) + if(_Boost_IMPORTED_TARGETS AND NOT TARGET Boost::${COMPONENT}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + if(Boost_${UPPERCOMPONENT}_FOUND) + if(Boost_USE_STATIC_LIBS) + add_library(Boost::${COMPONENT} STATIC IMPORTED) + else() + # Even if Boost_USE_STATIC_LIBS is OFF, we might have static libraries + # as a result. + add_library(Boost::${COMPONENT} UNKNOWN IMPORTED) + endif() + if(Boost_INCLUDE_DIRS) + set_target_properties( + Boost::${COMPONENT} PROPERTIES INTERFACE_INCLUDE_DIRECTORIES + "${Boost_INCLUDE_DIRS}") + endif() + if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY}") + set_target_properties( + Boost::${COMPONENT} + PROPERTIES IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" + IMPORTED_LOCATION "${Boost_${UPPERCOMPONENT}_LIBRARY}") + endif() + if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") + set_property( + TARGET Boost::${COMPONENT} + APPEND + PROPERTY IMPORTED_CONFIGURATIONS RELEASE) + set_target_properties( + Boost::${COMPONENT} + PROPERTIES IMPORTED_LINK_INTERFACE_LANGUAGES_RELEASE "CXX" + IMPORTED_LOCATION_RELEASE + "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") + endif() + if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") + set_property( + TARGET Boost::${COMPONENT} + APPEND + PROPERTY IMPORTED_CONFIGURATIONS DEBUG) + set_target_properties( + Boost::${COMPONENT} + PROPERTIES IMPORTED_LINK_INTERFACE_LANGUAGES_DEBUG "CXX" + IMPORTED_LOCATION_DEBUG + "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") + endif() + if(_Boost_${UPPERCOMPONENT}_DEPENDENCIES) + unset(_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES) + foreach(dep ${_Boost_${UPPERCOMPONENT}_DEPENDENCIES}) + list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES + Boost::${dep}) + endforeach() + if(COMPONENT STREQUAL "thread") + list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES + Threads::Threads) + endif() + set_target_properties( + Boost::${COMPONENT} + PROPERTIES INTERFACE_LINK_LIBRARIES + "${_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES}") + endif() + if(_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) + set_target_properties( + Boost::${COMPONENT} + PROPERTIES INTERFACE_COMPILE_FEATURES + "${_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES}") + endif() + endif() + endif() + endforeach() endif() # ------------------------------------------------------------------------ -# Notification to end user about what was found +# Notification to end user about what was found # ------------------------------------------------------------------------ set(Boost_LIBRARIES "") if(Boost_FOUND) - if(NOT Boost_FIND_QUIETLY) - message(STATUS "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - if(Boost_FIND_COMPONENTS) - message(STATUS "Found the following Boost libraries:") - endif() - endif() - foreach( COMPONENT ${Boost_FIND_COMPONENTS} ) - string( TOUPPER ${COMPONENT} UPPERCOMPONENT ) - if( Boost_${UPPERCOMPONENT}_FOUND ) - if(NOT Boost_FIND_QUIETLY) - message (STATUS " ${COMPONENT}") - endif() - list(APPEND Boost_LIBRARIES ${Boost_${UPPERCOMPONENT}_LIBRARY}) - if(COMPONENT STREQUAL "thread") - list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) - endif() - endif() - endforeach() -else() - if(Boost_FIND_REQUIRED) - message(SEND_ERROR "Unable to find the requested Boost libraries.\n${Boost_ERROR_REASON}") - else() if(NOT Boost_FIND_QUIETLY) - # we opt not to automatically output Boost_ERROR_REASON here as - # it could be quite lengthy and somewhat imposing in its requests - # Since Boost is not always a required dependency we'll leave this - # up to the end-user. - if(Boost_DEBUG OR Boost_DETAILED_FAILURE_MSG) - message(STATUS "Could NOT find Boost\n${Boost_ERROR_REASON}") - else() - message(STATUS "Could NOT find Boost") - endif() - endif() - endif() + message( + STATUS + "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}" + ) + if(Boost_FIND_COMPONENTS) + message(STATUS "Found the following Boost libraries:") + endif() + endif() + foreach(COMPONENT ${Boost_FIND_COMPONENTS}) + string(TOUPPER ${COMPONENT} UPPERCOMPONENT) + if(Boost_${UPPERCOMPONENT}_FOUND) + if(NOT Boost_FIND_QUIETLY) + message(STATUS " ${COMPONENT}") + endif() + list(APPEND Boost_LIBRARIES ${Boost_${UPPERCOMPONENT}_LIBRARY}) + if(COMPONENT STREQUAL "thread") + list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) + endif() + endif() + endforeach() +else() + if(Boost_FIND_REQUIRED) + message( + SEND_ERROR + "Unable to find the requested Boost libraries.\n${Boost_ERROR_REASON}") + else() + if(NOT Boost_FIND_QUIETLY) + # we opt not to automatically output Boost_ERROR_REASON here as it could be + # quite lengthy and somewhat imposing in its requests Since Boost is not + # always a required dependency we'll leave this up to the end-user. + if(Boost_DEBUG OR Boost_DETAILED_FAILURE_MSG) + message(STATUS "Could NOT find Boost\n${Boost_ERROR_REASON}") + else() + message(STATUS "Could NOT find Boost") + endif() + endif() + endif() endif() # Configure display of cache entries in GUI. foreach(v BOOSTROOT BOOST_ROOT ${_Boost_VARS_INC} ${_Boost_VARS_LIB}) - get_property(_type CACHE ${v} PROPERTY TYPE) - if(_type) - set_property(CACHE ${v} PROPERTY ADVANCED 1) - if("x${_type}" STREQUAL "xUNINITIALIZED") - if("x${v}" STREQUAL "xBoost_ADDITIONAL_VERSIONS") - set_property(CACHE ${v} PROPERTY TYPE STRING) - else() - set_property(CACHE ${v} PROPERTY TYPE PATH) - endif() - endif() - endif() + get_property( + _type + CACHE ${v} + PROPERTY TYPE) + if(_type) + set_property(CACHE ${v} PROPERTY ADVANCED 1) + if("x${_type}" STREQUAL "xUNINITIALIZED") + if("x${v}" STREQUAL "xBoost_ADDITIONAL_VERSIONS") + set_property(CACHE ${v} PROPERTY TYPE STRING) + else() + set_property(CACHE ${v} PROPERTY TYPE PATH) + endif() + endif() + endif() endforeach() -# Record last used values of input variables so we can -# detect on the next run if the user changed them. -foreach(v - ${_Boost_VARS_INC} ${_Boost_VARS_LIB} - ${_Boost_VARS_DIR} ${_Boost_VARS_NAME} - ) - if(DEFINED ${v}) - set(_${v}_LAST "${${v}}" CACHE INTERNAL "Last used ${v} value.") - else() - unset(_${v}_LAST CACHE) - endif() +# Record last used values of input variables so we can detect on the next run if the user +# changed them. +foreach(v ${_Boost_VARS_INC} ${_Boost_VARS_LIB} ${_Boost_VARS_DIR} ${_Boost_VARS_NAME}) + if(DEFINED ${v}) + set(_${v}_LAST + "${${v}}" + CACHE INTERNAL "Last used ${v} value.") + else() + unset(_${v}_LAST CACHE) + endif() endforeach() -# Maintain a persistent list of components requested anywhere since -# the last flush. +# Maintain a persistent list of components requested anywhere since the last flush. set(_Boost_COMPONENTS_SEARCHED "${_Boost_COMPONENTS_SEARCHED}") list(APPEND _Boost_COMPONENTS_SEARCHED ${Boost_FIND_COMPONENTS}) list(REMOVE_DUPLICATES _Boost_COMPONENTS_SEARCHED) list(SORT _Boost_COMPONENTS_SEARCHED) -set(_Boost_COMPONENTS_SEARCHED "${_Boost_COMPONENTS_SEARCHED}" - CACHE INTERNAL "Components requested for this build tree.") +set(_Boost_COMPONENTS_SEARCHED + "${_Boost_COMPONENTS_SEARCHED}" + CACHE INTERNAL "Components requested for this build tree.") # Restore project's policies cmake_policy(POP) diff --git a/cmake/Modules/FindLibDebuginfod.cmake b/cmake/Modules/FindLibDebuginfod.cmake index 5ab73e2db6..fce581f4e2 100644 --- a/cmake/Modules/FindLibDebuginfod.cmake +++ b/cmake/Modules/FindLibDebuginfod.cmake @@ -28,49 +28,35 @@ find_package(PkgConfig QUIET) pkg_check_modules(PC_Debuginfod QUIET REQUIRED libdebuginfod>=${ElfUtils_MIN_VERSION}) set(LibDebuginfod_VERSION "${PC_Debuginfod_VERSION}") -find_path(LibDebuginfod_INCLUDE_DIRS - NAMES - debuginfod.h - HINTS - ${PC_Debuginfod_INCLUDEDIR} - ${PC_Debuginfod_INCLUDE_DIRS} - ${LibDebuginfod_ROOT_DIR}/include - ${LibDebuginfod_ROOT_DIR} - ${LibDebuginfod_INCLUDEDIR} - PATHS - ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES - ${_path_suffixes} - DOC - "libdebuginfod include directories") +find_path( + LibDebuginfod_INCLUDE_DIRS + NAMES debuginfod.h + HINTS ${PC_Debuginfod_INCLUDEDIR} ${PC_Debuginfod_INCLUDE_DIRS} + ${LibDebuginfod_ROOT_DIR}/include ${LibDebuginfod_ROOT_DIR} + ${LibDebuginfod_INCLUDEDIR} + PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} + PATH_SUFFIXES ${_path_suffixes} + DOC "libdebuginfod include directories") -find_library(LibDebuginfod_LIBRARIES - NAMES - libdebuginfod.so.1 libdebuginfod.so - HINTS - ${PC_Debuginfod_LIBDIR} - ${PC_Debuginfod_LIBRARY_DIRS} - ${LibDebuginfod_ROOT_DIR}/lib - ${LibDebuginfod_ROOT_DIR} - ${LibDebuginfod_LIBRARYDIR} - PATHS - ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES - ${_path_suffixes}) +find_library( + LibDebuginfod_LIBRARIES + NAMES libdebuginfod.so.1 libdebuginfod.so + HINTS ${PC_Debuginfod_LIBDIR} ${PC_Debuginfod_LIBRARY_DIRS} + ${LibDebuginfod_ROOT_DIR}/lib ${LibDebuginfod_ROOT_DIR} + ${LibDebuginfod_LIBRARYDIR} + PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} + PATH_SUFFIXES ${_path_suffixes}) include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibDebuginfod - FOUND_VAR - LibDebuginfod_FOUND - REQUIRED_VARS - LibDebuginfod_INCLUDE_DIRS - LibDebuginfod_LIBRARIES - VERSION_VAR - LibDebuginfod_VERSION) +find_package_handle_standard_args( + LibDebuginfod + FOUND_VAR LibDebuginfod_FOUND + REQUIRED_VARS LibDebuginfod_INCLUDE_DIRS LibDebuginfod_LIBRARIES + VERSION_VAR LibDebuginfod_VERSION) if(LibDebuginfod_FOUND) - set(LibDebuginfod_INCLUDE_DIRS ${LibDebuginfod_INCLUDE_DIRS}) - set(LibDebuginfod_LIBRARIES ${LibDebuginfod_LIBRARIES}) - get_filename_component(_debuginfod_dir ${LibDebuginfod_LIBRARIES} DIRECTORY) - set(LibDebuginfod_LIBRARY_DIRS ${_debuginfod_dir} "${_debuginfod_dir}/elfutils") + set(LibDebuginfod_INCLUDE_DIRS ${LibDebuginfod_INCLUDE_DIRS}) + set(LibDebuginfod_LIBRARIES ${LibDebuginfod_LIBRARIES}) + get_filename_component(_debuginfod_dir ${LibDebuginfod_LIBRARIES} DIRECTORY) + set(LibDebuginfod_LIBRARY_DIRS ${_debuginfod_dir} "${_debuginfod_dir}/elfutils") endif() diff --git a/cmake/Modules/FindLibDwarf.cmake b/cmake/Modules/FindLibDwarf.cmake index 5821b2eb9e..e30d9e4620 100644 --- a/cmake/Modules/FindLibDwarf.cmake +++ b/cmake/Modules/FindLibDwarf.cmake @@ -32,36 +32,35 @@ include(DyninstSystemPaths) # Non-standard subdirectories to search set(_path_suffixes libdw libdwarf elfutils) -find_path(LibDwarf_INCLUDE_DIR - NAMES libdw.h - HINTS ${LibDwarf_ROOT_DIR}/include ${LibDwarf_ROOT_DIR} ${LibDwarf_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "libdw include directories") +find_path( + LibDwarf_INCLUDE_DIR + NAMES libdw.h + HINTS ${LibDwarf_ROOT_DIR}/include ${LibDwarf_ROOT_DIR} ${LibDwarf_INCLUDEDIR} + PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} + PATH_SUFFIXES ${_path_suffixes} + DOC "libdw include directories") -find_library(LibDwarf_LIBRARIES - NAMES libdw.so.1 libdw.so - HINTS ${LibDwarf_ROOT_DIR}/lib ${LibDwarf_ROOT_DIR} ${LibDwarf_LIBRARYDIR} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) +find_library( + LibDwarf_LIBRARIES + NAMES libdw.so.1 libdw.so + HINTS ${LibDwarf_ROOT_DIR}/lib ${LibDwarf_ROOT_DIR} ${LibDwarf_LIBRARYDIR} + PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} + PATH_SUFFIXES ${_path_suffixes}) # Find the library with the highest version set(_max_ver 0.0) set(_max_ver_lib) foreach(l ${LibDwarf_LIBRARIES}) - get_filename_component(_dw_realpath ${LibDwarf_LIBRARIES} REALPATH) - string(REGEX MATCH - "libdw\\-(.+)\\.so\\.*$" - res - ${_dw_realpath}) + get_filename_component(_dw_realpath ${LibDwarf_LIBRARIES} REALPATH) + string(REGEX MATCH "libdw\\-(.+)\\.so\\.*$" res ${_dw_realpath}) - # The library version number is stored in CMAKE_MATCH_1 - set(_cur_ver ${CMAKE_MATCH_1}) + # The library version number is stored in CMAKE_MATCH_1 + set(_cur_ver ${CMAKE_MATCH_1}) - if(${_cur_ver} VERSION_GREATER ${_max_ver}) - set(_max_ver ${_cur_ver}) - set(_max_ver_lib ${l}) - endif() + if(${_cur_ver} VERSION_GREATER ${_max_ver}) + set(_max_ver ${_cur_ver}) + set(_max_ver_lib ${l}) + endif() endforeach() # Set the exported variables to the best match @@ -69,22 +68,19 @@ set(LibDwarf_LIBRARIES ${_max_ver_lib}) set(LibDwarf_VERSION ${_max_ver}) include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibDwarf - FOUND_VAR - LibDwarf_FOUND - REQUIRED_VARS - LibDwarf_LIBRARIES - LibDwarf_INCLUDE_DIR - VERSION_VAR - LibDwarf_VERSION) +find_package_handle_standard_args( + LibDwarf + FOUND_VAR LibDwarf_FOUND + REQUIRED_VARS LibDwarf_LIBRARIES LibDwarf_INCLUDE_DIR + VERSION_VAR LibDwarf_VERSION) # Export cache variables if(LibDwarf_FOUND) - set(LibDwarf_INCLUDE_DIRS ${LibDwarf_INCLUDE_DIR}) - set(LibDwarf_LIBRARIES ${LibDwarf_LIBRARIES}) + set(LibDwarf_INCLUDE_DIRS ${LibDwarf_INCLUDE_DIR}) + set(LibDwarf_LIBRARIES ${LibDwarf_LIBRARIES}) - # Because we only report the library with the largest version, we are - # guaranteed there is only one file in LibDwarf_LIBRARIES - get_filename_component(_dw_dir ${LibDwarf_LIBRARIES} DIRECTORY) - set(LibDwarf_LIBRARY_DIRS ${_dw_dir}) + # Because we only report the library with the largest version, we are guaranteed there + # is only one file in LibDwarf_LIBRARIES + get_filename_component(_dw_dir ${LibDwarf_LIBRARIES} DIRECTORY) + set(LibDwarf_LIBRARY_DIRS ${_dw_dir}) endif() diff --git a/cmake/Modules/FindLibElf.cmake b/cmake/Modules/FindLibElf.cmake index f76ead7158..f2bfcf1705 100644 --- a/cmake/Modules/FindLibElf.cmake +++ b/cmake/Modules/FindLibElf.cmake @@ -35,36 +35,35 @@ include(DyninstSystemPaths) # Non-standard subdirectories to search set(_path_suffixes libelf libelfls elfutils) -find_path(LibElf_INCLUDE_DIR - NAMES libelf.h - HINTS ${LibElf_ROOT_DIR}/include ${LibElf_ROOT_DIR} ${LibElf_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "libelf include directories") +find_path( + LibElf_INCLUDE_DIR + NAMES libelf.h + HINTS ${LibElf_ROOT_DIR}/include ${LibElf_ROOT_DIR} ${LibElf_INCLUDEDIR} + PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} + PATH_SUFFIXES ${_path_suffixes} + DOC "libelf include directories") -find_library(LibElf_LIBRARIES - NAMES libelf.so.1 libelf.so - HINTS ${LibElf_ROOT_DIR}/lib ${LibElf_ROOT_DIR} ${LibElf_LIBRARYDIR} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) +find_library( + LibElf_LIBRARIES + NAMES libelf.so.1 libelf.so + HINTS ${LibElf_ROOT_DIR}/lib ${LibElf_ROOT_DIR} ${LibElf_LIBRARYDIR} + PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} + PATH_SUFFIXES ${_path_suffixes}) # Find the library with the highest version set(_max_ver 0.0) set(_max_ver_lib) foreach(l ${LibElf_LIBRARIES}) - get_filename_component(_elf_realpath ${LibElf_LIBRARIES} REALPATH) - string(REGEX MATCH - "libelf\\-(.+)\\.so\\.*$" - res - ${_elf_realpath}) + get_filename_component(_elf_realpath ${LibElf_LIBRARIES} REALPATH) + string(REGEX MATCH "libelf\\-(.+)\\.so\\.*$" res ${_elf_realpath}) - # The library version number is stored in CMAKE_MATCH_1 - set(_cur_ver ${CMAKE_MATCH_1}) + # The library version number is stored in CMAKE_MATCH_1 + set(_cur_ver ${CMAKE_MATCH_1}) - if(${_cur_ver} VERSION_GREATER ${_max_ver}) - set(_max_ver ${_cur_ver}) - set(_max_ver_lib ${l}) - endif() + if(${_cur_ver} VERSION_GREATER ${_max_ver}) + set(_max_ver ${_cur_ver}) + set(_max_ver_lib ${l}) + endif() endforeach() # Set the exported variables to the best match @@ -72,22 +71,19 @@ set(LibElf_LIBRARIES ${_max_ver_lib}) set(LibElf_VERSION ${_max_ver}) include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibElf - FOUND_VAR - LibElf_FOUND - REQUIRED_VARS - LibElf_LIBRARIES - LibElf_INCLUDE_DIR - VERSION_VAR - LibElf_VERSION) +find_package_handle_standard_args( + LibElf + FOUND_VAR LibElf_FOUND + REQUIRED_VARS LibElf_LIBRARIES LibElf_INCLUDE_DIR + VERSION_VAR LibElf_VERSION) # Export cache variables if(LibElf_FOUND) - set(LibElf_INCLUDE_DIRS ${LibElf_INCLUDE_DIR}) - set(LibElf_LIBRARIES ${LibElf_LIBRARIES}) + set(LibElf_INCLUDE_DIRS ${LibElf_INCLUDE_DIR}) + set(LibElf_LIBRARIES ${LibElf_LIBRARIES}) - # Because we only report the library with the largest version, we are - # guaranteed there is only one file in LibElf_LIBRARIES - get_filename_component(_elf_dir ${LibElf_LIBRARIES} DIRECTORY) - set(LibElf_LIBRARY_DIRS ${_elf_dir} "${_elf_dir}/elfutils") + # Because we only report the library with the largest version, we are guaranteed there + # is only one file in LibElf_LIBRARIES + get_filename_component(_elf_dir ${LibElf_LIBRARIES} DIRECTORY) + set(LibElf_LIBRARY_DIRS ${_elf_dir} "${_elf_dir}/elfutils") endif() diff --git a/cmake/Modules/FindLibIberty.cmake b/cmake/Modules/FindLibIberty.cmake index 88b60d1150..8d560e33c5 100644 --- a/cmake/Modules/FindLibIberty.cmake +++ b/cmake/Modules/FindLibIberty.cmake @@ -30,13 +30,13 @@ #======================================================================================== if(LibIberty_FOUND) - return() + return() endif() -# Keep the semantics of IBERTY_LIBRARIES for backward compatibility -# NB: If both are specified, LibIberty_LIBRARIES is ignored +# Keep the semantics of IBERTY_LIBRARIES for backward compatibility NB: If both are +# specified, LibIberty_LIBRARIES is ignored if(NOT "${IBERTY_LIBRARIES}" STREQUAL "") - set(LibIberty_LIBRARIES ${IBERTY_LIBRARIES}) + set(LibIberty_LIBRARIES ${IBERTY_LIBRARIES}) endif() include(DyninstSystemPaths) @@ -44,38 +44,37 @@ include(DyninstSystemPaths) # Non-standard subdirectories to search set(_path_suffixes libiberty iberty) -find_path(LibIberty_INCLUDE_DIRS - NAMES libiberty.h - HINTS ${LibIberty_ROOT_DIR} ${LibIberty_ROOT_DIR}/include ${LibIberty_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "LibIberty include directories") +find_path( + LibIberty_INCLUDE_DIRS + NAMES libiberty.h + HINTS ${LibIberty_ROOT_DIR} ${LibIberty_ROOT_DIR}/include ${LibIberty_INCLUDEDIR} + PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} + PATH_SUFFIXES ${_path_suffixes} + DOC "LibIberty include directories") # iberty_pic is for Debian <= wheezy -find_library(LibIberty_LIBRARIES - NAMES iberty_pic iberty - HINTS ${LibIberty_ROOT_DIR} - ${LibIberty_LIBRARYDIR} - ${IBERTY_LIBRARIES} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) +find_library( + LibIberty_LIBRARIES + NAMES iberty_pic iberty + HINTS ${LibIberty_ROOT_DIR} ${LibIberty_LIBRARYDIR} ${IBERTY_LIBRARIES} + PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} + PATH_SUFFIXES ${_path_suffixes}) include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibIberty - FOUND_VAR - LibIberty_FOUND - REQUIRED_VARS - LibIberty_LIBRARIES) +find_package_handle_standard_args( + LibIberty + FOUND_VAR LibIberty_FOUND + REQUIRED_VARS LibIberty_LIBRARIES) # For backwards compatibility only set(IBERTY_FOUND ${LibIberty_FOUND}) if(LibIberty_FOUND) - foreach(l ${LibIberty_LIBRARIES}) - get_filename_component(_dir ${l} DIRECTORY) - list(APPEND LibIberty_LIBRARY_DIRS ${_dir}) - endforeach() - - # For backwards compatibility only - set(IBERTY_LIBRARIES ${LibIberty_LIBRARIES}) + foreach(l ${LibIberty_LIBRARIES}) + get_filename_component(_dir ${l} DIRECTORY) + list(APPEND LibIberty_LIBRARY_DIRS ${_dir}) + endforeach() + + # For backwards compatibility only + set(IBERTY_LIBRARIES ${LibIberty_LIBRARIES}) endif() diff --git a/cmake/Modules/FindTBB.cmake b/cmake/Modules/FindTBB.cmake index 93a9b8c662..cc62ffe166 100644 --- a/cmake/Modules/FindTBB.cmake +++ b/cmake/Modules/FindTBB.cmake @@ -59,7 +59,7 @@ #====================================================================================================== if(TBB_FOUND) - return() + return() endif() include(FindPackageHandleStandardArgs) @@ -68,15 +68,15 @@ include(FindPackageHandleStandardArgs) # Check the build type # if(NOT DEFINED TBB_USE_DEBUG_BUILD) - if(CMAKE_BUILD_TYPE MATCHES "(Debug|DEBUG|debug)") - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() + if(CMAKE_BUILD_TYPE MATCHES "(Debug|DEBUG|debug)") + set(TBB_BUILD_TYPE DEBUG) + else() + set(TBB_BUILD_TYPE RELEASE) + endif() elseif(TBB_USE_DEBUG_BUILD) - set(TBB_BUILD_TYPE DEBUG) + set(TBB_BUILD_TYPE DEBUG) else() - set(TBB_BUILD_TYPE RELEASE) + set(TBB_BUILD_TYPE RELEASE) endif() # @@ -88,167 +88,160 @@ set(TBB_SEARCH_DIR ${TBB_ROOT_DIR} $ENV{TBB_INSTALL_DIR} $ENV{TBBROOT}) # Define the search directories based on the current platform if(CMAKE_SYSTEM_NAME STREQUAL "Windows") - set(TBB_DEFAULT_SEARCH_DIR "C:/Program Files/Intel/TBB" - "C:/Program Files (x86)/Intel/TBB") + set(TBB_DEFAULT_SEARCH_DIR "C:/Program Files/Intel/TBB" + "C:/Program Files (x86)/Intel/TBB") - # Set the target architecture - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(TBB_ARCHITECTURE "intel64") - else() - set(TBB_ARCHITECTURE "ia32") - endif() + # Set the target architecture + if(CMAKE_SIZEOF_VOID_P EQUAL 8) + set(TBB_ARCHITECTURE "intel64") + else() + set(TBB_ARCHITECTURE "ia32") + endif() - # Set the TBB search library path search suffix based on the version of VC - if(WINDOWS_STORE) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11_ui") - elseif(MSVC14) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc14") - elseif(MSVC12) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc12") - elseif(MSVC11) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11") - elseif(MSVC10) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc10") - endif() + # Set the TBB search library path search suffix based on the version of VC + if(WINDOWS_STORE) + set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11_ui") + elseif(MSVC14) + set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc14") + elseif(MSVC12) + set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc12") + elseif(MSVC11) + set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11") + elseif(MSVC10) + set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc10") + endif() - # Add the library path search suffix for the VC independent version of TBB - list(APPEND TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc_mt") + # Add the library path search suffix for the VC independent version of TBB + list(APPEND TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc_mt") elseif(CMAKE_SYSTEM_NAME STREQUAL "Darwin") - # OS X - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") + # OS X + set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - # TODO: Check to see which C++ library is being used by the compiler. - if(NOT ${CMAKE_SYSTEM_VERSION} VERSION_LESS 13.0) - # The default C++ library on OS X 10.9 and later is libc++ - set(TBB_LIB_PATH_SUFFIX "lib/libc++" "lib") - else() - set(TBB_LIB_PATH_SUFFIX "lib") - endif() + # TODO: Check to see which C++ library is being used by the compiler. + if(NOT ${CMAKE_SYSTEM_VERSION} VERSION_LESS 13.0) + # The default C++ library on OS X 10.9 and later is libc++ + set(TBB_LIB_PATH_SUFFIX "lib/libc++" "lib") + else() + set(TBB_LIB_PATH_SUFFIX "lib") + endif() elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux") - # Linux - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") + # Linux + set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - # TODO: Check compiler version to see the suffix should be /gcc4.1 or - # /gcc4.1. For now, assume that the compiler is more recent than gcc - # 4.4.x or later. - if(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64") - set(TBB_LIB_PATH_SUFFIX "lib/intel64/gcc4.4") - elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^i.86$") - set(TBB_LIB_PATH_SUFFIX "lib/ia32/gcc4.4") - endif() + # TODO: Check compiler version to see the suffix should be /gcc4.1 or + # /gcc4.1. For now, assume that the compiler is more recent than gcc 4.4.x or + # later. + if(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64") + set(TBB_LIB_PATH_SUFFIX "lib/intel64/gcc4.4") + elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^i.86$") + set(TBB_LIB_PATH_SUFFIX "lib/ia32/gcc4.4") + endif() endif() # # Find the TBB include dir # -find_path(TBB_INCLUDE_DIRS tbb/tbb.h - HINTS ${TBB_INCLUDE_DIRS} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} - PATH_SUFFIXES include) +find_path( + TBB_INCLUDE_DIRS tbb/tbb.h + HINTS ${TBB_INCLUDE_DIRS} ${TBB_SEARCH_DIR} + PATHS ${TBB_DEFAULT_SEARCH_DIR} + PATH_SUFFIXES include) # # Set version strings # if(TBB_INCLUDE_DIRS) - # Starting in 2020.1.1, tbb_stddef.h is replaced by version.h - set(_version_files - "${TBB_INCLUDE_DIRS}/tbb/tbb_stddef.h" - "${TBB_INCLUDE_DIRS}/tbb/version.h" - ) - foreach(f IN ITEMS ${_version_files}) - if(EXISTS ${f}) - set(_version_file ${f}) - endif() - endforeach() - unset(_version_files) - - file(READ ${_version_file} _tbb_version_file) - string(REGEX - REPLACE ".*#define TBB_VERSION_MAJOR ([0-9]+).*" - "\\1" - TBB_VERSION_MAJOR - "${_tbb_version_file}") - string(REGEX - REPLACE ".*#define TBB_VERSION_MINOR ([0-9]+).*" - "\\1" - TBB_VERSION_MINOR - "${_tbb_version_file}") - string(REGEX - REPLACE ".*#define TBB_INTERFACE_VERSION ([0-9]+).*" - "\\1" - TBB_INTERFACE_VERSION - "${_tbb_version_file}") + # Starting in 2020.1.1, tbb_stddef.h is replaced by version.h + set(_version_files "${TBB_INCLUDE_DIRS}/tbb/tbb_stddef.h" + "${TBB_INCLUDE_DIRS}/tbb/version.h") + foreach(f IN ITEMS ${_version_files}) + if(EXISTS ${f}) + set(_version_file ${f}) + endif() + endforeach() + unset(_version_files) + + file(READ ${_version_file} _tbb_version_file) + string(REGEX REPLACE ".*#define TBB_VERSION_MAJOR ([0-9]+).*" "\\1" TBB_VERSION_MAJOR + "${_tbb_version_file}") + string(REGEX REPLACE ".*#define TBB_VERSION_MINOR ([0-9]+).*" "\\1" TBB_VERSION_MINOR + "${_tbb_version_file}") + string(REGEX REPLACE ".*#define TBB_INTERFACE_VERSION ([0-9]+).*" "\\1" + TBB_INTERFACE_VERSION "${_tbb_version_file}") - # The TBB_VERSION_MINOR isn't necessarily changed for minor releases - # Hence, we need to read the engineering versioning in TBB_INTERFACE_VERSION - # to get the minor version correct - if("${TBB_VERSION_MINOR}" STREQUAL "0") - math(EXPR _tbb_iface_major_ver "${TBB_INTERFACE_VERSION} / 100") - math(EXPR TBB_VERSION_MINOR "${TBB_INTERFACE_VERSION} - ${_tbb_iface_major_ver} * 100") - endif() - set(TBB_VERSION "${TBB_VERSION_MAJOR}.${TBB_VERSION_MINOR}") + # The TBB_VERSION_MINOR isn't necessarily changed for minor releases Hence, we need to + # read the engineering versioning in TBB_INTERFACE_VERSION to get the minor version + # correct + if("${TBB_VERSION_MINOR}" STREQUAL "0") + math(EXPR _tbb_iface_major_ver "${TBB_INTERFACE_VERSION} / 100") + math(EXPR TBB_VERSION_MINOR + "${TBB_INTERFACE_VERSION} - ${_tbb_iface_major_ver} * 100") + endif() + set(TBB_VERSION "${TBB_VERSION_MAJOR}.${TBB_VERSION_MINOR}") endif() # # Find TBB components # if(TBB_VERSION VERSION_LESS 4.3) - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc tbb) + set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc tbb) else() - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc_proxy tbbmalloc tbb) + set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc_proxy tbbmalloc tbb) endif() set(TBB_LIBRARY_DIRS) # Find each component foreach(_comp ${TBB_SEARCH_COMPOMPONENTS}) - message(STATUS "Searching for ${_comp}...") - message(STATUS "Hints: ${TBB_LIBRARY} ${TBB_SEARCH_DIR}") - if(";${TBB_FIND_COMPONENTS};tbb;" MATCHES ";${_comp};") + message(STATUS "Searching for ${_comp}...") + message(STATUS "Hints: ${TBB_LIBRARY} ${TBB_SEARCH_DIR}") + if(";${TBB_FIND_COMPONENTS};tbb;" MATCHES ";${_comp};") - # Search for the libraries - find_library(TBB_${_comp}_LIBRARY_RELEASE ${_comp} - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_release) + # Search for the libraries + find_library( + TBB_${_comp}_LIBRARY_RELEASE ${_comp} + HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} + PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH + PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_release) - find_library(TBB_${_comp}_LIBRARY_DEBUG ${_comp}_debug - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_debug) + find_library( + TBB_${_comp}_LIBRARY_DEBUG ${_comp}_debug + HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} + PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH + PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_debug) - if(TBB_${_comp}_LIBRARY_DEBUG) - list(APPEND TBB_LIBRARIES_DEBUG "${TBB_${_comp}_LIBRARY_DEBUG}") - message(STATUS "Found ${TBB_${_comp}_LIBRARY_DEBUG}") - endif() - if(TBB_${_comp}_LIBRARY_RELEASE) - list(APPEND TBB_LIBRARIES_RELEASE "${TBB_${_comp}_LIBRARY_RELEASE}") - message(STATUS "Found ${TBB_${_comp}_LIBRARY_RELEASE}") - endif() - if(TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE} AND NOT TBB_${_comp}_LIBRARY) - set(TBB_${_comp}_LIBRARY "${TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE}}") - endif() + if(TBB_${_comp}_LIBRARY_DEBUG) + list(APPEND TBB_LIBRARIES_DEBUG "${TBB_${_comp}_LIBRARY_DEBUG}") + message(STATUS "Found ${TBB_${_comp}_LIBRARY_DEBUG}") + endif() + if(TBB_${_comp}_LIBRARY_RELEASE) + list(APPEND TBB_LIBRARIES_RELEASE "${TBB_${_comp}_LIBRARY_RELEASE}") + message(STATUS "Found ${TBB_${_comp}_LIBRARY_RELEASE}") + endif() + if(TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE} AND NOT TBB_${_comp}_LIBRARY) + set(TBB_${_comp}_LIBRARY "${TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE}}") + endif() - if(TBB_${_comp}_LIBRARY AND EXISTS "${TBB_${_comp}_LIBRARY}") - set(TBB_${_comp}_FOUND TRUE) - else() - set(TBB_${_comp}_FOUND FALSE) - endif() + if(TBB_${_comp}_LIBRARY AND EXISTS "${TBB_${_comp}_LIBRARY}") + set(TBB_${_comp}_FOUND TRUE) + else() + set(TBB_${_comp}_FOUND FALSE) + endif() - # Mark internal variables as advanced - mark_as_advanced(TBB_${_comp}_LIBRARY_RELEASE) - mark_as_advanced(TBB_${_comp}_LIBRARY_DEBUG) - mark_as_advanced(TBB_${_comp}_LIBRARY) + # Mark internal variables as advanced + mark_as_advanced(TBB_${_comp}_LIBRARY_RELEASE) + mark_as_advanced(TBB_${_comp}_LIBRARY_DEBUG) + mark_as_advanced(TBB_${_comp}_LIBRARY) - # Save the directory names for each library component - if(TBB_USE_DEBUG_BUILD) - get_filename_component(_dir ${TBB_${_comp}_LIBRARY_DEBUG} DIRECTORY) - else() - get_filename_component(_dir ${TBB_${_comp}_LIBRARY_RELEASE} DIRECTORY) + # Save the directory names for each library component + if(TBB_USE_DEBUG_BUILD) + get_filename_component(_dir ${TBB_${_comp}_LIBRARY_DEBUG} DIRECTORY) + else() + get_filename_component(_dir ${TBB_${_comp}_LIBRARY_RELEASE} DIRECTORY) + endif() + list(APPEND TBB_LIBRARY_DIRS ${_dir}) endif() - list(APPEND TBB_LIBRARY_DIRS ${_dir}) - endif() endforeach() # @@ -258,53 +251,42 @@ set(TBB_DEFINITIONS_RELEASE "") set(TBB_DEFINITIONS_DEBUG "-DTBB_USE_DEBUG=1") if(TBB_LIBRARIES_${TBB_BUILD_TYPE}) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_${TBB_BUILD_TYPE}}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_${TBB_BUILD_TYPE}}") + set(TBB_DEFINITIONS "${TBB_DEFINITIONS_${TBB_BUILD_TYPE}}") + set(TBB_LIBRARIES "${TBB_LIBRARIES_${TBB_BUILD_TYPE}}") elseif(TBB_LIBRARIES_RELEASE) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_RELEASE}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_RELEASE}") + set(TBB_DEFINITIONS "${TBB_DEFINITIONS_RELEASE}") + set(TBB_LIBRARIES "${TBB_LIBRARIES_RELEASE}") elseif(TBB_LIBRARIES_DEBUG) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_DEBUG}") + set(TBB_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}") + set(TBB_LIBRARIES "${TBB_LIBRARIES_DEBUG}") endif() -find_package_handle_standard_args(TBB - REQUIRED_VARS - TBB_INCLUDE_DIRS - TBB_LIBRARIES - HANDLE_COMPONENTS - VERSION_VAR - TBB_VERSION) +find_package_handle_standard_args( + TBB + REQUIRED_VARS TBB_INCLUDE_DIRS TBB_LIBRARIES + HANDLE_COMPONENTS + VERSION_VAR TBB_VERSION) # # Create targets # if(NOT CMAKE_VERSION VERSION_LESS 3.0 AND TBB_FOUND) - add_library(TBB SHARED IMPORTED) - set_target_properties(TBB - PROPERTIES INTERFACE_INCLUDE_DIRECTORIES - ${TBB_INCLUDE_DIRS} - IMPORTED_LOCATION - ${TBB_LIBRARIES}) - if(TBB_LIBRARIES_RELEASE AND TBB_LIBRARIES_DEBUG) - set_target_properties(TBB - PROPERTIES INTERFACE_COMPILE_DEFINITIONS - "$<$:TBB_USE_DEBUG=1>" - IMPORTED_LOCATION_DEBUG - ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELWITHDEBINFO - ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELEASE - ${TBB_LIBRARIES_RELEASE} - IMPORTED_LOCATION_MINSIZEREL - ${TBB_LIBRARIES_RELEASE}) - elseif(TBB_LIBRARIES_RELEASE) - set_target_properties(TBB - PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_RELEASE}) - else() - set_target_properties(TBB - PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_DEBUG}) - endif() + add_library(TBB SHARED IMPORTED) + set_target_properties(TBB PROPERTIES INTERFACE_INCLUDE_DIRECTORIES ${TBB_INCLUDE_DIRS} + IMPORTED_LOCATION ${TBB_LIBRARIES}) + if(TBB_LIBRARIES_RELEASE AND TBB_LIBRARIES_DEBUG) + set_target_properties( + TBB + PROPERTIES INTERFACE_COMPILE_DEFINITIONS "$<$:TBB_USE_DEBUG=1>" + IMPORTED_LOCATION_DEBUG ${TBB_LIBRARIES_DEBUG} + IMPORTED_LOCATION_RELWITHDEBINFO ${TBB_LIBRARIES_DEBUG} + IMPORTED_LOCATION_RELEASE ${TBB_LIBRARIES_RELEASE} + IMPORTED_LOCATION_MINSIZEREL ${TBB_LIBRARIES_RELEASE}) + elseif(TBB_LIBRARIES_RELEASE) + set_target_properties(TBB PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_RELEASE}) + else() + set_target_properties(TBB PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_DEBUG}) + endif() endif() mark_as_advanced(TBB_INCLUDE_DIRS TBB_LIBRARIES TBB_LIBRARY_DIRS) diff --git a/cmake/Modules/FindThreadDB.cmake b/cmake/Modules/FindThreadDB.cmake index 35bd118d04..333063e478 100644 --- a/cmake/Modules/FindThreadDB.cmake +++ b/cmake/Modules/FindThreadDB.cmake @@ -7,46 +7,43 @@ # THREAD_DB_DEFINITIONS - Compiler switches required for using thread_db # -if (THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) - set (Thread_Db_FIND_QUIETLY TRUE) -endif (THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) +if(THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) + set(Thread_Db_FIND_QUIETLY TRUE) +endif(THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) -find_path (THREAD_DB_INCLUDE_DIR - NAMES - thread_db.h - HINTS - ${THREAD_DB_INCLUDE_DIRS} - PATHS - /usr/include - /usr/include/thread_db - /usr/local/include - /opt/local/include - /sw/include - ENV CPATH) # PATH and INCLUDE will also work +find_path( + THREAD_DB_INCLUDE_DIR + NAMES thread_db.h + HINTS ${THREAD_DB_INCLUDE_DIRS} + PATHS /usr/include + /usr/include/thread_db + /usr/local/include + /opt/local/include + /sw/include + ENV + CPATH) # PATH and INCLUDE will also work -find_library (THREAD_DB_LIBRARIES - NAMES - thread_db - HINTS - ${THREAD_DB_LIBRARIES} - PATHS - /usr/lib - /usr/lib64 - /usr/local/lib - /usr/local/lib64 - /opt/local/lib - /opt/local/lib64 - /sw/lib - ENV LIBRARY_PATH # PATH and LIB will also work - ENV LD_LIBRARY_PATH) -include (FindPackageHandleStandardArgs) - - -# handle the QUIETLY and REQUIRED arguments and set THREAD_DB_FOUND to TRUE -# if all listed variables are TRUE -FIND_PACKAGE_HANDLE_STANDARD_ARGS(Thread_Db DEFAULT_MSG +find_library( THREAD_DB_LIBRARIES - THREAD_DB_INCLUDE_DIR) + NAMES thread_db + HINTS ${THREAD_DB_LIBRARIES} + PATHS /usr/lib + /usr/lib64 + /usr/local/lib + /usr/local/lib64 + /opt/local/lib + /opt/local/lib64 + /sw/lib + ENV + LIBRARY_PATH # PATH and LIB will also work + ENV + LD_LIBRARY_PATH) +include(FindPackageHandleStandardArgs) + +# handle the QUIETLY and REQUIRED arguments and set THREAD_DB_FOUND to TRUE if all listed +# variables are TRUE +find_package_handle_standard_args(Thread_Db DEFAULT_MSG THREAD_DB_LIBRARIES + THREAD_DB_INCLUDE_DIR) -#mark_as_advanced(LIBDW_INCLUDE_DIR DWARF_INCLUDE_DIR) -#mark_as_advanced(THREAD_DB_INCLUDE_DIRS THREAD_DB_LIBRARIES) +# mark_as_advanced(LIBDW_INCLUDE_DIR DWARF_INCLUDE_DIR) +# mark_as_advanced(THREAD_DB_INCLUDE_DIRS THREAD_DB_LIBRARIES) diff --git a/cmake/Modules/FindValgrind.cmake b/cmake/Modules/FindValgrind.cmake index e286e671d1..6bd5aa0f6d 100644 --- a/cmake/Modules/FindValgrind.cmake +++ b/cmake/Modules/FindValgrind.cmake @@ -25,21 +25,21 @@ include(DyninstSystemPaths) -find_path(Valgrind_INCLUDE_DIR - NAMES valgrind.h - HINTS ${Valgrind_ROOT_DIR}/include ${Valgrind_ROOT_DIR} ${Valgrind_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES valgrind - DOC "Valgrind include directory") +find_path( + Valgrind_INCLUDE_DIR + NAMES valgrind.h + HINTS ${Valgrind_ROOT_DIR}/include ${Valgrind_ROOT_DIR} ${Valgrind_INCLUDEDIR} + PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} + PATH_SUFFIXES valgrind + DOC "Valgrind include directory") include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(Valgrind - FOUND_VAR - Valgrind_FOUND - REQUIRED_VARS - Valgrind_INCLUDE_DIR) +find_package_handle_standard_args( + Valgrind + FOUND_VAR Valgrind_FOUND + REQUIRED_VARS Valgrind_INCLUDE_DIR) # Export cache variables if(Valgrind_FOUND) - set(Valgrind_INCLUDE_DIRS ${Valgrind_INCLUDE_DIR}) + set(Valgrind_INCLUDE_DIRS ${Valgrind_INCLUDE_DIR}) endif() diff --git a/cmake/ThreadingBuildingBlocks.cmake b/cmake/ThreadingBuildingBlocks.cmake index 551f83156c..4e61dcf5c8 100644 --- a/cmake/ThreadingBuildingBlocks.cmake +++ b/cmake/ThreadingBuildingBlocks.cmake @@ -38,139 +38,162 @@ #===================================================================================== if(TBB_FOUND) - return() + return() endif() # -------------- RUNTIME CONFIGURATION ---------------------------------------- # Use debug versions of TBB libraries -set(TBB_USE_DEBUG_BUILD OFF CACHE BOOL "Use debug versions of TBB libraries") +set(TBB_USE_DEBUG_BUILD + OFF + CACHE BOOL "Use debug versions of TBB libraries") # Minimum version of TBB (assumes a dotted-decimal format: YYYY.XX) if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") - set(_tbb_min_version 2019.7) + set(_tbb_min_version 2019.7) else() - set(_tbb_min_version 2018.6) + set(_tbb_min_version 2018.6) endif() -set(TBB_MIN_VERSION ${_tbb_min_version} CACHE STRING "Minimum version of TBB (assumes a dotted-decimal format: YYYY.XX)") +set(TBB_MIN_VERSION + ${_tbb_min_version} + CACHE STRING "Minimum version of TBB (assumes a dotted-decimal format: YYYY.XX)") if(${TBB_MIN_VERSION} VERSION_LESS ${_tbb_min_version}) - message( - FATAL_ERROR - "Requested TBB version ${TBB_MIN_VERSION} is less than minimum supported version ${_tbb_min_version}" - ) + message( + FATAL_ERROR + "Requested TBB version ${TBB_MIN_VERSION} is less than minimum supported version ${_tbb_min_version}" + ) endif() # -------------- PATHS -------------------------------------------------------- # TBB root directory -set(TBB_ROOT_DIR "/usr" CACHE PATH "TBB root directory") +set(TBB_ROOT_DIR + "/usr" + CACHE PATH "TBB root directory") # TBB include directory hint -set(TBB_INCLUDEDIR "${TBB_ROOT_DIR}/include" CACHE PATH "TBB include directory") +set(TBB_INCLUDEDIR + "${TBB_ROOT_DIR}/include" + CACHE PATH "TBB include directory") # TBB library directory hint -set(TBB_LIBRARYDIR "${TBB_ROOT_DIR}/lib" CACHE PATH "TBB library directory") +set(TBB_LIBRARYDIR + "${TBB_ROOT_DIR}/lib" + CACHE PATH "TBB library directory") # Translate to FindTBB names set(TBB_LIBRARY ${TBB_LIBRARYDIR}) set(TBB_INCLUDE_DIR ${TBB_INCLUDEDIR}) -# The specific TBB libraries we need -# NB: This should _NOT_ be a cache variable +# The specific TBB libraries we need NB: This should _NOT_ be a cache variable set(_tbb_components tbb tbbmalloc tbbmalloc_proxy) find_package(TBB ${TBB_MIN_VERSION} COMPONENTS ${_tbb_components}) # -------------- SOURCE BUILD ------------------------------------------------- if(TBB_FOUND) - # Force the cache entries to be updated - # Normally, these would not be exported. However, we need them in the Testsuite - set(TBB_INCLUDE_DIRS ${TBB_INCLUDE_DIRS} CACHE PATH "TBB include directory" FORCE) - set(TBB_LIBRARY_DIRS ${TBB_LIBRARY_DIRS} CACHE PATH "TBB library directory" FORCE) - set(TBB_DEFINITIONS ${TBB_DEFINITIONS} CACHE STRING "TBB compiler definitions" FORCE) - set(TBB_LIBRARIES ${TBB_LIBRARIES} CACHE FILEPATH "TBB library files" FORCE) - - if(NOT TARGET TBB) - add_library(TBB SHARED IMPORTED) - endif() + # Force the cache entries to be updated Normally, these would not be exported. + # However, we need them in the Testsuite + set(TBB_INCLUDE_DIRS + ${TBB_INCLUDE_DIRS} + CACHE PATH "TBB include directory" FORCE) + set(TBB_LIBRARY_DIRS + ${TBB_LIBRARY_DIRS} + CACHE PATH "TBB library directory" FORCE) + set(TBB_DEFINITIONS + ${TBB_DEFINITIONS} + CACHE STRING "TBB compiler definitions" FORCE) + set(TBB_LIBRARIES + ${TBB_LIBRARIES} + CACHE FILEPATH "TBB library files" FORCE) + + if(NOT TARGET TBB) + add_library(TBB SHARED IMPORTED) + endif() elseif(NOT TBB_FOUND AND STERILE_BUILD) - message(FATAL_ERROR "TBB not found and cannot be downloaded because build is sterile.") + message( + FATAL_ERROR "TBB not found and cannot be downloaded because build is sterile.") else() - # If we didn't find a suitable version on the system, then download one from the web - message(STATUS "${ThreadingBuildingBlocks_ERROR_REASON}") - message(STATUS "Attempting to build TBB(${TBB_MIN_VERSION}) as external project") - - if(NOT UNIX) - message(FATAL_ERROR "Building TBB from source is not supported on this platform") - endif() - - # Forcibly update the cache variables - set(TBB_ROOT_DIR ${CMAKE_INSTALL_PREFIX} CACHE PATH "TBB root directory" FORCE) - set(TBB_INCLUDE_DIRS ${TBB_ROOT_DIR}/include CACHE PATH "TBB include directory" FORCE) - set(TBB_LIBRARY_DIRS ${TBB_ROOT_DIR}/lib CACHE PATH "TBB library directory" FORCE) - set(TBB_DEFINITIONS "" CACHE STRING "TBB compiler definitions" FORCE) - - set(_tbb_libraries) - set(_tbb_components_cfg) - - foreach(c ${_tbb_components}) - # Generate make target names - if(${c} STREQUAL tbbmalloc_proxy) - # tbbmalloc_proxy is spelled tbbproxy in their Makefiles - list(APPEND _tbb_components_cfg tbbproxy_release) - else() - list(APPEND _tbb_components_cfg ${c}_release) - endif() - - # Generate library filenames - list(APPEND _tbb_libraries "${TBB_LIBRARY_DIRS}/lib${c}.so") - - foreach(t RELEASE DEBUG) - set(TBB_${c}_LIBRARY_${t} "${TBB_LIBRARY_DIRS}/lib${c}.so" CACHE FILEPATH "" FORCE) + # If we didn't find a suitable version on the system, then download one from the web + message(STATUS "${ThreadingBuildingBlocks_ERROR_REASON}") + message(STATUS "Attempting to build TBB(${TBB_MIN_VERSION}) as external project") + + if(NOT UNIX) + message(FATAL_ERROR "Building TBB from source is not supported on this platform") + endif() + + # Forcibly update the cache variables + set(TBB_ROOT_DIR + ${CMAKE_INSTALL_PREFIX} + CACHE PATH "TBB root directory" FORCE) + set(TBB_INCLUDE_DIRS + ${TBB_ROOT_DIR}/include + CACHE PATH "TBB include directory" FORCE) + set(TBB_LIBRARY_DIRS + ${TBB_ROOT_DIR}/lib + CACHE PATH "TBB library directory" FORCE) + set(TBB_DEFINITIONS + "" + CACHE STRING "TBB compiler definitions" FORCE) + + set(_tbb_libraries) + set(_tbb_components_cfg) + + foreach(c ${_tbb_components}) + # Generate make target names + if(${c} STREQUAL tbbmalloc_proxy) + # tbbmalloc_proxy is spelled tbbproxy in their Makefiles + list(APPEND _tbb_components_cfg tbbproxy_release) + else() + list(APPEND _tbb_components_cfg ${c}_release) + endif() + + # Generate library filenames + list(APPEND _tbb_libraries "${TBB_LIBRARY_DIRS}/lib${c}.so") + + foreach(t RELEASE DEBUG) + set(TBB_${c}_LIBRARY_${t} + "${TBB_LIBRARY_DIRS}/lib${c}.so" + CACHE FILEPATH "" FORCE) + endforeach() endforeach() - endforeach() - - set(TBB_LIBRARIES ${_tbb_libraries} CACHE FILEPATH "TBB library files" FORCE) - - # Split the dotted decimal version into major/minor parts - string(REGEX REPLACE "\\." ";" _tbb_download_name ${TBB_MIN_VERSION}) - list(GET _tbb_download_name 0 _tbb_ver_major) - list(GET _tbb_download_name 1 _tbb_ver_minor) - - include(ExternalProject) - set(_tbb_prefix_dir ${CMAKE_BINARY_DIR}/tbb) - - # Set the compiler for TBB - # It assumes gcc and tests for Intel, so clang is the only - # one that needs special treatment. - if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") - set(_tbb_compiler "compiler=clang") - endif() - - ExternalProject_Add( - TBB - PREFIX ${_tbb_prefix_dir} - URL https://github.com/01org/tbb/archive/${_tbb_ver_major}_U${_tbb_ver_minor}.tar.gz - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND "" - BUILD_COMMAND - CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} - $(MAKE) -C src - ${_tbb_components_cfg} - tbb_build_dir=${_tbb_prefix_dir}/src - tbb_build_prefix=tbb - ${_tbb_compiler} - INSTALL_COMMAND - ${CMAKE_COMMAND} - -DLIBDIR=${TBB_LIBRARY_DIRS} - -DINCDIR=${TBB_INCLUDE_DIRS} - -DPREFIX=${_tbb_prefix_dir} - -P ${CMAKE_CURRENT_LIST_DIR}/ThreadingBuildingBlocks.install.cmake - ) + + set(TBB_LIBRARIES + ${_tbb_libraries} + CACHE FILEPATH "TBB library files" FORCE) + + # Split the dotted decimal version into major/minor parts + string(REGEX REPLACE "\\." ";" _tbb_download_name ${TBB_MIN_VERSION}) + list(GET _tbb_download_name 0 _tbb_ver_major) + list(GET _tbb_download_name 1 _tbb_ver_minor) + + include(ExternalProject) + set(_tbb_prefix_dir ${CMAKE_BINARY_DIR}/tbb) + + # Set the compiler for TBB It assumes gcc and tests for Intel, so clang is the only + # one that needs special treatment. + if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") + set(_tbb_compiler "compiler=clang") + endif() + + externalproject_add( + TBB + PREFIX ${_tbb_prefix_dir} + URL https://github.com/01org/tbb/archive/${_tbb_ver_major}_U${_tbb_ver_minor}.tar.gz + BUILD_IN_SOURCE 1 + CONFIGURE_COMMAND "" + BUILD_COMMAND + CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} $(MAKE) -C src + ${_tbb_components_cfg} tbb_build_dir=${_tbb_prefix_dir}/src + tbb_build_prefix=tbb ${_tbb_compiler} + INSTALL_COMMAND + ${CMAKE_COMMAND} -DLIBDIR=${TBB_LIBRARY_DIRS} -DINCDIR=${TBB_INCLUDE_DIRS} + -DPREFIX=${_tbb_prefix_dir} -P + ${CMAKE_CURRENT_LIST_DIR}/ThreadingBuildingBlocks.install.cmake) endif() - + include_directories(SYSTEM ${TBB_INCLUDE_DIRS}) link_directories(${TBB_LIBRARY_DIRS}) diff --git a/cmake/ThreadingBuildingBlocks.install.cmake b/cmake/ThreadingBuildingBlocks.install.cmake index c1043c389e..e1f60c770b 100644 --- a/cmake/ThreadingBuildingBlocks.install.cmake +++ b/cmake/ThreadingBuildingBlocks.install.cmake @@ -11,14 +11,16 @@ ################################################################# file(MAKE_DIRECTORY ${LIBDIR} ${INCDIR}) -file(COPY ${PREFIX}/src/tbb_release/ DESTINATION ${LIBDIR} FILES_MATCHING PATTERN "*.so.*") +file( + COPY ${PREFIX}/src/tbb_release/ + DESTINATION ${LIBDIR} + FILES_MATCHING + PATTERN "*.so.*") file(COPY ${PREFIX}/src/TBB/include/tbb DESTINATION ${INCDIR}) file(GLOB _tbb_libs ${LIBDIR}/libtbb*.so.*) foreach(l ${_tbb_libs}) - string(REGEX REPLACE "\\.2$" "" _l_short ${l}) - execute_process( - COMMAND ${CMAKE_COMMAND} -E create_symlink ${l} ${_l_short} - ) + string(REGEX REPLACE "\\.2$" "" _l_short ${l}) + execute_process(COMMAND ${CMAKE_COMMAND} -E create_symlink ${l} ${_l_short}) endforeach() diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake index 91fa984f55..b36281b905 100644 --- a/cmake/cap_arch_def.cmake +++ b/cmake/cap_arch_def.cmake @@ -4,121 +4,97 @@ # cap_32_64 - This host 64-bit platform supports modifying 32-bit binaries # -set (CAP_DEFINES - -Dcap_dynamic_heap - -Dcap_liveness - -Dcap_threads -) - -if (PLATFORM MATCHES i386) -set (ARCH_DEFINES -Darch_x86) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_fixpoint_gen - -Dcap_noaddr_gen - -Dcap_stripped_binaries - -Dcap_tramp_liveness - -Dcap_virtual_registers - -Dcap_stack_mods - ) - -elseif (PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) -set (ARCH_DEFINES -Darch_x86_64 -Darch_64bit) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_32_64 - -Dcap_fixpoint_gen - -Dcap_noaddr_gen - -Dcap_registers - -Dcap_stripped_binaries - -Dcap_tramp_liveness - -Dcap_stack_mods - ) - -elseif (PLATFORM MATCHES ppc64) - set (ARCH_DEFINES -Darch_power -Darch_64bit) - set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -m64") - set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -m64") - set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_32_64 - -Dcap_registers - -Dcap_toc_64 - ) -elseif (PLATFORM MATCHES aarch64) - #set (ARCH_DEFINES -Daarch_64 -Darch_64bit) - set (ARCH_DEFINES -Darch_aarch64 -Darch_64bit) - set (CAP_DEFINES ${CAP_DEFINES} -Dcap_registers) -endif (PLATFORM MATCHES i386) - -if (PLATFORM MATCHES linux) -set (OS_DEFINES -Dos_linux) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_async_events - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - -Dcap_ptrace - ) -set (BUG_DEFINES -Dbug_syscall_changepc_rewind -Dbug_force_terminate_failure) - -elseif (PLATFORM MATCHES freebsd) -set (OS_DEFINES -Dos_freebsd) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - ) -set (BUG_DEFINES -Dbug_freebsd_missing_sigstop - -Dbug_freebsd_mt_suspend - -Dbug_freebsd_change_pc - -Dbug_phdrs_first_page - -Dbug_syscall_changepc_rewind - ) - -elseif (PLATFORM STREQUAL i386-unknown-nt4.0) -set (OS_DEFINES -Dos_windows) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_mutatee_traps - ) -endif (PLATFORM MATCHES linux) - - -if (PLATFORM STREQUAL i386-unknown-linux2.4) -set (OLD_DEFINES -Di386_unknown_linux2_0) - -elseif (PLATFORM STREQUAL x86_64-unknown-linux2.4) -set (OLD_DEFINES -Dx86_64_unknown_linux2_4) - -elseif (PLATFORM STREQUAL ppc64_linux) -set (OLD_DEFINES -Dppc64_linux) -set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) - -elseif (PLATFORM STREQUAL i386-unknown-freebsd7.2) -set (OLD_DEFINES -Di386_unknown_freebsd7_0) - -elseif (PLATFORM STREQUAL amd64-unknown-freebsd7.2) -set (OLD_DEFINES -Damd64_unknown_freebsd7_0) - -elseif (PLATFORM STREQUAL i386-unknown-nt4.0) -set (OLD_DEFINES -Di386_unknown_nt4_0) -elseif (PLATFORM STREQUAL aarch64-unknown-linux) - set (OLD_DEFINES -Daarch64_unknown_linux) -else (PLATFORM STREQUAL i386-unknown-linux2.4) - message (FATAL_ERROR "Unknown platform: ${PLATFORM}") -endif (PLATFORM STREQUAL i386-unknown-linux2.4) - -if (THREAD_DB_FOUND) -message (STATUS "-- Enabling ThreadDB support") -set (CAP_DEFINES ${CAP_DEFINES} -Dcap_thread_db) -endif (THREAD_DB_FOUND) - -set (UNIFIED_DEFINES ${CAP_DEFINES} ${BUG_DEFINES} ${ARCH_DEFINES} ${OS_DEFINES} ${OLD_DEFINES}) - -foreach (def ${UNIFIED_DEFINES}) - add_definitions (${def}) +set(CAP_DEFINES -Dcap_dynamic_heap -Dcap_liveness -Dcap_threads) + +if(PLATFORM MATCHES i386) + set(ARCH_DEFINES -Darch_x86) + set(CAP_DEFINES + ${CAP_DEFINES} + -Dcap_fixpoint_gen + -Dcap_noaddr_gen + -Dcap_stripped_binaries + -Dcap_tramp_liveness + -Dcap_virtual_registers + -Dcap_stack_mods) + +elseif(PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) + set(ARCH_DEFINES -Darch_x86_64 -Darch_64bit) + set(CAP_DEFINES + ${CAP_DEFINES} + -Dcap_32_64 + -Dcap_fixpoint_gen + -Dcap_noaddr_gen + -Dcap_registers + -Dcap_stripped_binaries + -Dcap_tramp_liveness + -Dcap_stack_mods) + +elseif(PLATFORM MATCHES ppc64) + set(ARCH_DEFINES -Darch_power -Darch_64bit) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -m64") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -m64") + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_32_64 -Dcap_registers -Dcap_toc_64) +elseif(PLATFORM MATCHES aarch64) + # set (ARCH_DEFINES -Daarch_64 -Darch_64bit) + set(ARCH_DEFINES -Darch_aarch64 -Darch_64bit) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_registers) +endif(PLATFORM MATCHES i386) + +if(PLATFORM MATCHES linux) + set(OS_DEFINES -Dos_linux) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_async_events -Dcap_binary_rewriter -Dcap_dwarf + -Dcap_mutatee_traps -Dcap_ptrace) + set(BUG_DEFINES -Dbug_syscall_changepc_rewind -Dbug_force_terminate_failure) + +elseif(PLATFORM MATCHES freebsd) + set(OS_DEFINES -Dos_freebsd) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_binary_rewriter -Dcap_dwarf -Dcap_mutatee_traps) + set(BUG_DEFINES + -Dbug_freebsd_missing_sigstop -Dbug_freebsd_mt_suspend -Dbug_freebsd_change_pc + -Dbug_phdrs_first_page -Dbug_syscall_changepc_rewind) + +elseif(PLATFORM STREQUAL i386-unknown-nt4.0) + set(OS_DEFINES -Dos_windows) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_mutatee_traps) +endif(PLATFORM MATCHES linux) + +if(PLATFORM STREQUAL i386-unknown-linux2.4) + set(OLD_DEFINES -Di386_unknown_linux2_0) + +elseif(PLATFORM STREQUAL x86_64-unknown-linux2.4) + set(OLD_DEFINES -Dx86_64_unknown_linux2_4) + +elseif(PLATFORM STREQUAL ppc64_linux) + set(OLD_DEFINES -Dppc64_linux) + set(BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) + +elseif(PLATFORM STREQUAL i386-unknown-freebsd7.2) + set(OLD_DEFINES -Di386_unknown_freebsd7_0) + +elseif(PLATFORM STREQUAL amd64-unknown-freebsd7.2) + set(OLD_DEFINES -Damd64_unknown_freebsd7_0) + +elseif(PLATFORM STREQUAL i386-unknown-nt4.0) + set(OLD_DEFINES -Di386_unknown_nt4_0) +elseif(PLATFORM STREQUAL aarch64-unknown-linux) + set(OLD_DEFINES -Daarch64_unknown_linux) +else(PLATFORM STREQUAL i386-unknown-linux2.4) + message(FATAL_ERROR "Unknown platform: ${PLATFORM}") +endif(PLATFORM STREQUAL i386-unknown-linux2.4) + +if(THREAD_DB_FOUND) + message(STATUS "-- Enabling ThreadDB support") + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_thread_db) +endif(THREAD_DB_FOUND) + +set(UNIFIED_DEFINES ${CAP_DEFINES} ${BUG_DEFINES} ${ARCH_DEFINES} ${OS_DEFINES} + ${OLD_DEFINES}) + +foreach(def ${UNIFIED_DEFINES}) + add_definitions(${def}) endforeach() - -set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${UNIFIED_DEF_STRING}") -set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${UNIFIED_DEF_STRING}") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${UNIFIED_DEF_STRING}") +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${UNIFIED_DEF_STRING}") message(STATUS "Set arch and platform based definitions") - diff --git a/cmake/endian.cmake b/cmake/endian.cmake index c0be21b772..b24c512dee 100644 --- a/cmake/endian.cmake +++ b/cmake/endian.cmake @@ -1,8 +1,8 @@ -INCLUDE(TestBigEndian) +include(TestBigEndian) -TEST_BIG_ENDIAN(BIGENDIAN) +test_big_endian(BIGENDIAN) if(${BIGENDIAN}) - ADD_DEFINITIONS(-DDYNINST_BIG_ENDIAN) + add_definitions(-DDYNINST_BIG_ENDIAN) else() - ADD_DEFINITIONS(-DDYNINST_LITTLE_ENDIAN) + add_definitions(-DDYNINST_LITTLE_ENDIAN) endif(${BIGENDIAN}) diff --git a/cmake/optimization.cmake b/cmake/optimization.cmake index a06912707e..d887c1f049 100644 --- a/cmake/optimization.cmake +++ b/cmake/optimization.cmake @@ -1,56 +1,56 @@ -if (CMAKE_COMPILER_IS_GNUCXX - OR ${CMAKE_C_COMPILER_ID} MATCHES Clang - OR ${CMAKE_C_COMPILER_ID} MATCHES GNU - OR ${CMAKE_C_COMPILER_ID} MATCHES Intel) -if(ENABLE_LTO) - set(LTO_FLAGS "-flto") - set(LTO_LINK_FLAGS "-fuse-ld=bfd") -else() - set(LTO_FLAGS "") - set(LTO_LINK_FLAGS "") -endif() -set (CMAKE_C_FLAGS_DEBUG "-Og -g3") -set (CMAKE_CXX_FLAGS_DEBUG "-Og -g3") - -set (CMAKE_C_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") - -set (FORCE_FRAME_POINTER "-fno-omit-frame-pointer") -# Ensure each library is fully linked -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined") - -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -else (MSVC) -if(ENABLE_LTO) - set(LTO_FLAGS "/GL") - set(LTO_LINK_FLAGS "/LTCG") -else() - set(LTO_FLAGS "") - set(LTO_LINK_FLAGS "") -endif() -set (CMAKE_C_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") -set (CMAKE_CXX_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") - -set (CMAKE_C_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") - -set (FORCE_FRAME_POINTER "/Oy-") - -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_STATIC_LINKER_FLAGS "${CMAKE_STATIC_LINKER_FLAGS} ${LTO_LINK_FLAGS}") +if(CMAKE_COMPILER_IS_GNUCXX + OR ${CMAKE_C_COMPILER_ID} MATCHES Clang + OR ${CMAKE_C_COMPILER_ID} MATCHES GNU + OR ${CMAKE_C_COMPILER_ID} MATCHES Intel) + if(ENABLE_LTO) + set(LTO_FLAGS "-flto") + set(LTO_LINK_FLAGS "-fuse-ld=bfd") + else() + set(LTO_FLAGS "") + set(LTO_LINK_FLAGS "") + endif() + set(CMAKE_C_FLAGS_DEBUG "-Og -g3") + set(CMAKE_CXX_FLAGS_DEBUG "-Og -g3") + + set(CMAKE_C_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") + + set(CMAKE_C_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") + + set(CMAKE_C_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_MINSIZEREL "-Os ${LTO_FLAGS}") + + set(FORCE_FRAME_POINTER "-fno-omit-frame-pointer") + # Ensure each library is fully linked + set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined") + + set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") + set(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") +else(MSVC) + if(ENABLE_LTO) + set(LTO_FLAGS "/GL") + set(LTO_LINK_FLAGS "/LTCG") + else() + set(LTO_FLAGS "") + set(LTO_LINK_FLAGS "") + endif() + set(CMAKE_C_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") + set(CMAKE_CXX_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") + + set(CMAKE_C_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_RELEASE "/MP /O2 /MD ${LTO_FLAGS}") + + set(CMAKE_C_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD ${LTO_FLAGS}") + + set(CMAKE_C_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") + set(CMAKE_CXX_FLAGS_MINSIZEREL "/MP /O1 /MD ${LTO_FLAGS}") + + set(FORCE_FRAME_POINTER "/Oy-") + + set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") + set(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") + set(CMAKE_STATIC_LINKER_FLAGS "${CMAKE_STATIC_LINKER_FLAGS} ${LTO_LINK_FLAGS}") endif() message(STATUS "Set optimization flags") diff --git a/cmake/options.cmake b/cmake/options.cmake index 35ec0779e0..7cbe66bcb2 100644 --- a/cmake/options.cmake +++ b/cmake/options.cmake @@ -1,27 +1,30 @@ # Use OpenMP? -option (USE_OpenMP "Use OpenMP for parallel parsing" ON) +option(USE_OpenMP "Use OpenMP for parallel parsing" ON) # Use SymtabAPI or SymLite? -option (LIGHTWEIGHT_SYMTAB "Use lightweight symtab interface for ParseAPI, ProcControl, and Stackwalker; disables DyninstAPI build" OFF) +option( + LIGHTWEIGHT_SYMTAB + "Use lightweight symtab interface for ParseAPI, ProcControl, and Stackwalker; disables DyninstAPI build" + OFF) # Use ParseAPI analysis in Stackwalker? -option (SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" ON) +option(SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" ON) -option (BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) +option(BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) -option (ENABLE_LTO "Enable Link-Time Optimization" OFF) +option(ENABLE_LTO "Enable Link-Time Optimization" OFF) option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) # Some global on/off switches -if (LIGHTWEIGHT_SYMTAB) -add_definitions (-DWITHOUT_SYMTAB_API -DWITH_SYMLITE) +if(LIGHTWEIGHT_SYMTAB) + add_definitions(-DWITHOUT_SYMTAB_API -DWITH_SYMLITE) else() -add_definitions (-DWITH_SYMTAB_API -DWITHOUT_SYMLITE) + add_definitions(-DWITH_SYMTAB_API -DWITHOUT_SYMLITE) endif() -if (SW_ANALYSIS_STEPPER) -add_definitions (-DUSE_PARSE_API) +if(SW_ANALYSIS_STEPPER) + add_definitions(-DUSE_PARSE_API) endif() message(STATUS "Options set") diff --git a/cmake/platform.cmake b/cmake/platform.cmake index 02627009dc..5976700510 100644 --- a/cmake/platform.cmake +++ b/cmake/platform.cmake @@ -1,5 +1,5 @@ -if (UNIX) -include (${DYNINST_ROOT}/cmake/platform_unix.cmake) -else () -include (${DYNINST_ROOT}/cmake/platform_windows.cmake) +if(UNIX) + include(${DYNINST_ROOT}/cmake/platform_unix.cmake) +else() + include(${DYNINST_ROOT}/cmake/platform_windows.cmake) endif() diff --git a/cmake/platform_unix.cmake b/cmake/platform_unix.cmake index 7b1bea840c..4709fe8eb2 100644 --- a/cmake/platform_unix.cmake +++ b/cmake/platform_unix.cmake @@ -1,39 +1,34 @@ -set (PLATFORM $ENV{PLATFORM}) +set(PLATFORM $ENV{PLATFORM}) message(STATUS "-- Input platform: ${PLATFORM}") -set (VALID_PLATFORMS - amd64-unknown-freebsd7.2 - i386-unknown-freebsd7.2 - i386-unknown-linux2.4 - ppc64_linux - x86_64-unknown-linux2.4 - aarch64-unknown-linux - ) +set(VALID_PLATFORMS + amd64-unknown-freebsd7.2 i386-unknown-freebsd7.2 i386-unknown-linux2.4 ppc64_linux + x86_64-unknown-linux2.4 aarch64-unknown-linux) -if (NOT PLATFORM) -set (INVALID_PLATFORM true) +if(NOT PLATFORM) + set(INVALID_PLATFORM true) else() -list (FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) - if (PLATFORM_FOUND EQUAL -1) - set (INVALID_PLATFORM true) - endif() + list(FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) + if(PLATFORM_FOUND EQUAL -1) + set(INVALID_PLATFORM true) + endif() endif() - -execute_process (COMMAND ${DYNINST_ROOT}/scripts/sysname OUTPUT_VARIABLE SYSNAME_OUT) +execute_process(COMMAND ${DYNINST_ROOT}/scripts/sysname OUTPUT_VARIABLE SYSNAME_OUT) string(REPLACE "\n" "" SYSPLATFORM ${SYSNAME_OUT}) -if (INVALID_PLATFORM) -# Try to set it automatically -execute_process (COMMAND ${DYNINST_ROOT}/scripts/dynsysname ${SYSNAME_OUT} - OUTPUT_VARIABLE DYNSYSNAME_OUT - ) -string (REPLACE "\n" "" PLATFORM ${DYNSYSNAME_OUT}) -message (STATUS "-- Attempting to automatically identify platform: ${PLATFORM}") +if(INVALID_PLATFORM) + # Try to set it automatically + execute_process(COMMAND ${DYNINST_ROOT}/scripts/dynsysname ${SYSNAME_OUT} + OUTPUT_VARIABLE DYNSYSNAME_OUT) + string(REPLACE "\n" "" PLATFORM ${DYNSYSNAME_OUT}) + message(STATUS "-- Attempting to automatically identify platform: ${PLATFORM}") endif() -list (FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) +list(FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) -if (PLATFORM_FOUND EQUAL -1) -message (FATAL_ERROR "Error: unknown platform ${PLATFORM}; please set the PLATFORM environment variable to one of the following options: ${VALID_PLATFORMS}") +if(PLATFORM_FOUND EQUAL -1) + message( + FATAL_ERROR + "Error: unknown platform ${PLATFORM}; please set the PLATFORM environment variable to one of the following options: ${VALID_PLATFORMS}" + ) endif() - diff --git a/cmake/platform_windows.cmake b/cmake/platform_windows.cmake index dd03b4ebbb..6fa44dd691 100644 --- a/cmake/platform_windows.cmake +++ b/cmake/platform_windows.cmake @@ -1 +1 @@ -set (PLATFORM i386-unknown-nt4.0) +set(PLATFORM i386-unknown-nt4.0) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index a95a9d4ba5..5c9a39355a 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,131 +1,162 @@ -set (DYNINST_MAJOR_VERSION 12) -set (DYNINST_MINOR_VERSION 1) -set (DYNINST_PATCH_VERSION 0) +set(DYNINST_MAJOR_VERSION 12) +set(DYNINST_MINOR_VERSION 1) +set(DYNINST_PATCH_VERSION 0) -set (SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") -set (LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") -set (DYNINST_VERSION "${LIBVERSION}") +set(SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") +set(LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") +set(DYNINST_VERSION "${LIBVERSION}") if(CMAKE_CONFIGURATION_TYPES) - set(CMAKE_CONFIGURATION_TYPES Debug Release) - set(CMAKE_CONFIGURATION_TYPES "${CMAKE_CONFIGURATION_TYPES}" CACHE STRING - "Reset the available configurations to exclude MinSizeRel and RelWithDebugInfo" FORCE) + set(CMAKE_CONFIGURATION_TYPES Debug Release) + set(CMAKE_CONFIGURATION_TYPES + "${CMAKE_CONFIGURATION_TYPES}" + CACHE + STRING + "Reset the available configurations to exclude MinSizeRel and RelWithDebugInfo" + FORCE) endif() -if (LIGHTWEIGHT_SYMTAB) - set(SYMREADER symLite) +if(LIGHTWEIGHT_SYMTAB) + set(SYMREADER symLite) else() - set(SYMREADER symtabAPI) + set(SYMREADER symtabAPI) endif() # Link libraries privately when possible -function (target_link_private_libraries target) - if(${CMAKE_VERSION} VERSION_LESS "2.8.7") - target_link_libraries (${target} ${ARGN}) - else() - target_link_libraries (${target} LINK_PRIVATE ${ARGN}) - endif() -endfunction () - -set(ALL_DYNINST_TARGETS "" CACHE INTERNAL "") - -function (dyninst_library target) - add_library (${target} ${SRC_LIST}) - # add boost as a universal dependencies for all sub libraries - if(TARGET boost) - add_dependencies (${target} boost) - endif() - target_link_private_libraries (${target} ${ARGN}) - FILE (GLOB headers "h/*.h" "${CMAKE_CURRENT_BINARY_DIR}/h/*.h") - set (ACTUAL_TARGETS ${target}) - set (ALL_TARGETS "${ARGN};${target}") - if(${ENABLE_STATIC_LIBS}) - set (ACTUAL_TARGETS ${ACTUAL_TARGETS} ${target}_static) - add_library (${target}_static STATIC ${SRC_LIST}) - endif() - message(STATUS "Building ${ACTUAL_TARGETS}...") - set_target_properties (${ACTUAL_TARGETS} PROPERTIES PUBLIC_HEADER "${headers}") - set_target_properties (${ACTUAL_TARGETS} PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) - set_target_properties (${target} PROPERTIES SOVERSION ${SOVERSION} VERSION ${LIBVERSION} CLEAN_DIRECT_OUTPUT 1) - set (INSTALL_TARGETS ${ACTUAL_TARGETS}) - foreach (dep ${ARGN}) - message(STATUS "Processing dependent target ${dep}...") - if(TARGET ${dep}) - get_target_property(dep_dir ${dep} LIBRARY_OUTPUT_DIRECTORY) - if(EXISTS ${dep_dir} AND IS_DIRECTORY ${dep_dir}) - message(STATUS "Found dependency location ${dep_dir}") - install(SCRIPT ${dep_dir}/cmake_install.cmake) - endif() +function(target_link_private_libraries target) + if(${CMAKE_VERSION} VERSION_LESS "2.8.7") + target_link_libraries(${target} ${ARGN}) + else() + target_link_libraries(${target} LINK_PRIVATE ${ARGN}) endif() - endforeach() - install (TARGETS ${INSTALL_TARGETS} - EXPORT ${target}Targets - COMPONENT ${target} - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) - add_custom_target(${target}-install - DEPENDS ${target} - COMMAND "${CMAKE_COMMAND}" -P "${CMAKE_CURRENT_BINARY_DIR}/cmake_install.cmake" - ) - set(ALL_DYNINST_TARGETS "${ALL_DYNINST_TARGETS};${target}" CACHE INTERNAL "") - install (EXPORT ${target}Targets - DESTINATION "${INSTALL_CMAKE_DIR}") - configure_file("${DYNINST_ROOT}/cmake/${PROJECT_NAME}Config.cmake.in" "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" @ONLY) - configure_file("${DYNINST_ROOT}/cmake/${PROJECT_NAME}ConfigVersion.cmake.in" "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" @ONLY) - install (FILES - "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" - "${PROJECT_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" - DESTINATION "${INSTALL_CMAKE_DIR}") endfunction() +set(ALL_DYNINST_TARGETS + "" + CACHE INTERNAL "") -include (${DYNINST_ROOT}/cmake/platform.cmake) -include (${DYNINST_ROOT}/cmake/cap_arch_def.cmake) -include (${DYNINST_ROOT}/cmake/visibility.cmake) -include (${DYNINST_ROOT}/cmake/warnings.cmake) -include (${DYNINST_ROOT}/cmake/options.cmake) -include (${DYNINST_ROOT}/cmake/optimization.cmake) -include (${DYNINST_ROOT}/cmake/endian.cmake) - -set (BUILD_SHARED_LIBS ON) +function(dyninst_library target) + add_library(${target} ${SRC_LIST}) + # add boost as a universal dependencies for all sub libraries + if(TARGET boost) + add_dependencies(${target} boost) + endif() + target_link_private_libraries(${target} ${ARGN}) + file(GLOB headers "h/*.h" "${CMAKE_CURRENT_BINARY_DIR}/h/*.h") + set(ACTUAL_TARGETS ${target}) + set(ALL_TARGETS "${ARGN};${target}") + if(${ENABLE_STATIC_LIBS}) + set(ACTUAL_TARGETS ${ACTUAL_TARGETS} ${target}_static) + add_library(${target}_static STATIC ${SRC_LIST}) + endif() + message(STATUS "Building ${ACTUAL_TARGETS}...") + set_target_properties(${ACTUAL_TARGETS} PROPERTIES PUBLIC_HEADER "${headers}") + set_target_properties(${ACTUAL_TARGETS} PROPERTIES LIBRARY_OUTPUT_DIRECTORY + ${CMAKE_CURRENT_BINARY_DIR}) + set_target_properties( + ${target} + PROPERTIES SOVERSION ${SOVERSION} + VERSION ${LIBVERSION} + CLEAN_DIRECT_OUTPUT 1) + set(INSTALL_TARGETS ${ACTUAL_TARGETS}) + foreach(dep ${ARGN}) + message(STATUS "Processing dependent target ${dep}...") + if(TARGET ${dep}) + get_target_property(dep_dir ${dep} LIBRARY_OUTPUT_DIRECTORY) + if(EXISTS ${dep_dir} AND IS_DIRECTORY ${dep_dir}) + message(STATUS "Found dependency location ${dep_dir}") + install(SCRIPT ${dep_dir}/cmake_install.cmake) + endif() + endif() + endforeach() + install( + TARGETS ${INSTALL_TARGETS} + EXPORT ${target}Targets + COMPONENT ${target} + RUNTIME DESTINATION ${INSTALL_LIB_DIR} + LIBRARY DESTINATION ${INSTALL_LIB_DIR} + ARCHIVE DESTINATION ${INSTALL_LIB_DIR} + PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) + add_custom_target( + ${target}-install + DEPENDS ${target} + COMMAND "${CMAKE_COMMAND}" -P "${CMAKE_CURRENT_BINARY_DIR}/cmake_install.cmake") + set(ALL_DYNINST_TARGETS + "${ALL_DYNINST_TARGETS};${target}" + CACHE INTERNAL "") + install(EXPORT ${target}Targets DESTINATION "${INSTALL_CMAKE_DIR}") + configure_file( + "${DYNINST_ROOT}/cmake/${PROJECT_NAME}Config.cmake.in" + "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" + @ONLY) + configure_file( + "${DYNINST_ROOT}/cmake/${PROJECT_NAME}ConfigVersion.cmake.in" + "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" + @ONLY) + install( + FILES + "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" + "${PROJECT_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" + DESTINATION "${INSTALL_CMAKE_DIR}") +endfunction() -set (INSTALL_BIN_DIR bin CACHE PATH "Installation directory for executables") -set (INSTALL_LIB_DIR lib CACHE PATH "Installation directory for libraries") -set (INSTALL_INCLUDE_DIR include CACHE PATH "Installation directory for header files") -set (INSTALL_CMAKE_DIR lib/cmake/${PROJECT_NAME} CACHE PATH "Installation directory for CMake files") -set (INSTALL_DOC_DIR share/doc CACHE PATH "Installation directory for manuals") +include(${DYNINST_ROOT}/cmake/platform.cmake) +include(${DYNINST_ROOT}/cmake/cap_arch_def.cmake) +include(${DYNINST_ROOT}/cmake/visibility.cmake) +include(${DYNINST_ROOT}/cmake/warnings.cmake) +include(${DYNINST_ROOT}/cmake/options.cmake) +include(${DYNINST_ROOT}/cmake/optimization.cmake) +include(${DYNINST_ROOT}/cmake/endian.cmake) + +set(BUILD_SHARED_LIBS ON) + +set(INSTALL_BIN_DIR + bin + CACHE PATH "Installation directory for executables") +set(INSTALL_LIB_DIR + lib + CACHE PATH "Installation directory for libraries") +set(INSTALL_INCLUDE_DIR + include + CACHE PATH "Installation directory for header files") +set(INSTALL_CMAKE_DIR + lib/cmake/${PROJECT_NAME} + CACHE PATH "Installation directory for CMake files") +set(INSTALL_DOC_DIR + share/doc + CACHE PATH "Installation directory for manuals") # Make the above absolute paths if necessary -foreach (p BIN LIB INCLUDE CMAKE) - set (var INSTALL_${p}_DIR) - if (NOT IS_ABSOLUTE "${${var}}") - set (${var} "${CMAKE_INSTALL_PREFIX}/${${var}}") - endif() +foreach(p BIN LIB INCLUDE CMAKE) + set(var INSTALL_${p}_DIR) + if(NOT IS_ABSOLUTE "${${var}}") + set(${var} "${CMAKE_INSTALL_PREFIX}/${${var}}") + endif() endforeach() if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - add_definitions(-DWIN32_LEAN_AND_MEAN) - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER 19) - add_definitions(-D_SILENCE_STDEXT_HASH_DEPRECATION_WARNINGS=1) - else() - add_definitions(-Dsnprintf=_snprintf) - endif() + add_definitions(-DWIN32_LEAN_AND_MEAN) + if(CMAKE_C_COMPILER_VERSION VERSION_GREATER 19) + add_definitions(-D_SILENCE_STDEXT_HASH_DEPRECATION_WARNINGS=1) + else() + add_definitions(-Dsnprintf=_snprintf) + endif() endif() # # DyninstConfig.cmake -file (RELATIVE_PATH REL_INCLUDE_DIR "${INSTALL_CMAKE_DIR}" "${INSTALL_INCLUDE_DIR}") +file(RELATIVE_PATH REL_INCLUDE_DIR "${INSTALL_CMAKE_DIR}" "${INSTALL_INCLUDE_DIR}") # For the install tree -set (CONF_INCLUDE_DIRS "\${DYNINST_CMAKE_DIR}/${REL_INCLUDE_DIR}") +set(CONF_INCLUDE_DIRS "\${DYNINST_CMAKE_DIR}/${REL_INCLUDE_DIR}") # set default configuration type -if (NOT CMAKE_BUILD_TYPE) - set (CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING - "Choose the build type (None, Debug, Release, RelWithDebInfo, MinSizeRel)" FORCE) +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE + RelWithDebInfo + CACHE STRING + "Choose the build type (None, Debug, Release, RelWithDebInfo, MinSizeRel)" + FORCE) endif() - diff --git a/cmake/visibility.cmake b/cmake/visibility.cmake index e9935e0041..035598fca0 100644 --- a/cmake/visibility.cmake +++ b/cmake/visibility.cmake @@ -1,5 +1,6 @@ -if(CMAKE_COMPILER_IS_GNUCXX OR ${CMAKE_C_COMPILER_ID} MATCHES Clang) - set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fvisibility=hidden") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fvisibility=hidden -fvisibility-inlines-hidden") +if(CMAKE_COMPILER_IS_GNUCXX OR ${CMAKE_C_COMPILER_ID} MATCHES Clang) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fvisibility=hidden") + set(CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} -fvisibility=hidden -fvisibility-inlines-hidden") message(STATUS "Found g++, enabling -fvisibility=hidden") endif() diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index f9f5c7f827..1b55898ff9 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -2,174 +2,184 @@ # cmake warning options # -option(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS "Disable all warning suppressions and frame size overrides." OFF) - -set(DYNINST_EXTRA_WARNINGS "" CACHE STRING "Additional warning options to enable if available. ;-separated without leading '-' (Wopt1[;Wopt2]...).") +option(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS + "Disable all warning suppressions and frame size overrides." OFF) + +set(DYNINST_EXTRA_WARNINGS + "" + CACHE + STRING + "Additional warning options to enable if available. ;-separated without leading '-' (Wopt1[;Wopt2]...)." + ) option(DYNINST_WARNINGS_AS_ERRORS "Treat compilation warnings as errors" OFF) - -if (DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) - add_definitions(-DDYNINST_DIAGNOSTIC_NO_SUPPRESSIONS) - message(STATUS "DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS set: disabling all dyninst warning suppressions and frame size overrides") +if(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + add_definitions(-DDYNINST_DIAGNOSTIC_NO_SUPPRESSIONS) + message( + STATUS + "DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS set: disabling all dyninst warning suppressions and frame size overrides" + ) endif() - -# Frame sizes are larger for debug build, so adjust based on build type -# files with functions containing large frames are adjust below -# (the value could be made significantly maller if more files are adjusted). +# Frame sizes are larger for debug build, so adjust based on build type files with +# functions containing large frames are adjust below (the value could be made +# significantly maller if more files are adjusted). # set(defaultDebugMaxFrameSize 24576) set(defaultNonDebugMaxFrameSize 20480) - -# REQUESTED_WARNING_FLAGS is a list of warning flags for C and C++ programs -# to enable if supported by the compiler. The values do not include the -# the initial '-' - -list(APPEND REQUESTED_WARNING_FLAGS - Wall - Wextra - Wpedantic - - Walloca - Wcast-align - Wcast-qual - Wcomma-subscript - Wctor-dtor-privacy - Wdeprecated-copy-dtor - Wdouble-promotion - Wduplicated-branches - Wduplicated-cond - Wenum-conversion - Wextra-semi - Wfloat-equal - Wformat-overflow=2 - Wformat-signedness - Wformat=2 - Wframe-larger-than=${defaultNonDebugMaxFrameSize} - Wjump-misses-init - Wlogical-op - Wmismatched-tags - Wmissing-braces - Wmultichar - Wnoexcept - Wnon-virtual-dtor - Woverloaded-virtual - Wpointer-arith - Wrange-loop-construct - Wrestrict - Wshadow - Wstrict-null-sentinel - Wsuggest-attribute=format - Wsuggest-attribute=malloc - Wuninitialized - Wvla - Wvolatile - Wwrite-strings - ) - -#list(APPEND REQUESTED_WARNING_FLAGS Werror) - -#list(APPEND REQUESTED_WARNING_FLAGS Wredundant-tags) -#list(APPEND REQUESTED_WARNING_FLAGS Wnull-dereference) -#list(APPEND REQUESTED_WARNING_FLAGS Wconversion) -#list(APPEND REQUESTED_WARNING_FLAGS Wzero-as-null-pointer-constant) -#list(APPEND REQUESTED_WARNING_FLAGS Wuseless-cast) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-override) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-types) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-methods) -#list(APPEND REQUESTED_WARNING_FLAGS Wsign-promo) -#list(APPEND REQUESTED_WARNING_FLAGS Wold-style-cast) -#list(APPEND REQUESTED_WARNING_FLAGS Walloc-zero) - -if (DYNINST_EXTRA_WARNINGS) +# REQUESTED_WARNING_FLAGS is a list of warning flags for C and C++ programs to enable if +# supported by the compiler. The values do not include the the initial '-' + +list( + APPEND + REQUESTED_WARNING_FLAGS + Wall + Wextra + Wpedantic + Walloca + Wcast-align + Wcast-qual + Wcomma-subscript + Wctor-dtor-privacy + Wdeprecated-copy-dtor + Wdouble-promotion + Wduplicated-branches + Wduplicated-cond + Wenum-conversion + Wextra-semi + Wfloat-equal + Wformat-overflow=2 + Wformat-signedness + Wformat=2 + Wframe-larger-than=${defaultNonDebugMaxFrameSize} + Wjump-misses-init + Wlogical-op + Wmismatched-tags + Wmissing-braces + Wmultichar + Wnoexcept + Wnon-virtual-dtor + Woverloaded-virtual + Wpointer-arith + Wrange-loop-construct + Wrestrict + Wshadow + Wstrict-null-sentinel + Wsuggest-attribute=format + Wsuggest-attribute=malloc + Wuninitialized + Wvla + Wvolatile + Wwrite-strings) + +# list(APPEND REQUESTED_WARNING_FLAGS Werror) + +# list(APPEND REQUESTED_WARNING_FLAGS Wredundant-tags) list(APPEND REQUESTED_WARNING_FLAGS +# Wnull-dereference) list(APPEND REQUESTED_WARNING_FLAGS Wconversion) list(APPEND +# REQUESTED_WARNING_FLAGS Wzero-as-null-pointer-constant) list(APPEND +# REQUESTED_WARNING_FLAGS Wuseless-cast) list(APPEND REQUESTED_WARNING_FLAGS +# Wsuggest-override) list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-types) list(APPEND +# REQUESTED_WARNING_FLAGS Wsuggest-final-methods) list(APPEND REQUESTED_WARNING_FLAGS +# Wsign-promo) list(APPEND REQUESTED_WARNING_FLAGS Wold-style-cast) list(APPEND +# REQUESTED_WARNING_FLAGS Walloc-zero) + +if(DYNINST_EXTRA_WARNINGS) list(APPEND REQUESTED_WARNING_FLAGS ${DYNINST_EXTRA_WARNINGS}) - message(STATUS "DYNINST_EXTRA_WARNINGS set, adding extra warnings: ${DYNINST_EXTRA_WARNINGS}") + message( + STATUS + "DYNINST_EXTRA_WARNINGS set, adding extra warnings: ${DYNINST_EXTRA_WARNINGS}" + ) endif() -if (DYNINST_WARNINGS_AS_ERRORS) +if(DYNINST_WARNINGS_AS_ERRORS) list(APPEND REQUESTED_WARNING_FLAGS "Werror") message(STATUS "DYNINST_WARNINGS_AS_ERRORS set: treating warnings as errors") endif() -if (CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") - include(CheckCCompilerFlag) - foreach (f IN LISTS REQUESTED_WARNING_FLAGS) - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${f}") - set(CMAKE_REQUIRED_FLAGS "-${f}") - check_c_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX "warning: *command[- ]line option|-Wunknown-warning-option") - # Previous two lines are equivalent to below, but also catches - # a 0 exit status with a warning message output: - # check_c_compiler_flag("-${f}" "${v}") - if (${v}) - string(APPEND SUPPORTED_C_WARNING_FLAGS " -${f}") - if (f MATCHES "^(.*)=[0-9]+$") - # set generic variable if warning is parameterized with a number - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${CMAKE_MATCH_1}") - set("${v}" 1) +if(CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") + include(CheckCCompilerFlag) + foreach(f IN LISTS REQUESTED_WARNING_FLAGS) + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${f}") + set(CMAKE_REQUIRED_FLAGS "-${f}") + check_c_source_compiles( + "int main(){return 0;}" "${v}" FAIL_REGEX + "warning: *command[- ]line option|-Wunknown-warning-option") + # Previous two lines are equivalent to below, but also catches a 0 exit status + # with a warning message output: check_c_compiler_flag("-${f}" "${v}") + if(${v}) + string(APPEND SUPPORTED_C_WARNING_FLAGS " -${f}") + if(f MATCHES "^(.*)=[0-9]+$") + # set generic variable if warning is parameterized with a number + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${CMAKE_MATCH_1}") + set("${v}" 1) + endif() endif() - endif() - endforeach() + endforeach() endif() -if (CMAKE_CXX_COMPILER_ID MATCHES "^(GNU|Clang)$") - include(CheckCXXCompilerFlag) - foreach (f IN LISTS REQUESTED_WARNING_FLAGS) - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${f}") - set(CMAKE_REQUIRED_FLAGS "-${f}") - check_cxx_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX "warning: *command[- ]line option|-Wunknown-warning-option") - if (${v}) - string(APPEND SUPPORTED_CXX_WARNING_FLAGS " -${f}") - if (f MATCHES "^(.*)=[0-9]+$") - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${CMAKE_MATCH_1}") - set("${v}" 1) +if(CMAKE_CXX_COMPILER_ID MATCHES "^(GNU|Clang)$") + include(CheckCXXCompilerFlag) + foreach(f IN LISTS REQUESTED_WARNING_FLAGS) + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${f}") + set(CMAKE_REQUIRED_FLAGS "-${f}") + check_cxx_source_compiles( + "int main(){return 0;}" "${v}" FAIL_REGEX + "warning: *command[- ]line option|-Wunknown-warning-option") + if(${v}) + string(APPEND SUPPORTED_CXX_WARNING_FLAGS " -${f}") + if(f MATCHES "^(.*)=[0-9]+$") + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${CMAKE_MATCH_1}") + set("${v}" 1) + endif() endif() - endif() - endforeach() + endforeach() endif() -# If -Wframe-larger-than is available adjust the value to allow for larger -# frames based on compiler version and build type for the following 3 files: +# If -Wframe-larger-than is available adjust the value to allow for larger frames based on +# compiler version and build type for the following 3 files: # -# instructionAPI/src/InstructionDecoder-power.C -# (includes instructionAPI/src/power-opcode-table.C) -# instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C -# (includes instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C) -# common/src/MachSyscall.C -# (includes common/src/SyscallInformation.C) +# instructionAPI/src/InstructionDecoder-power.C (includes +# instructionAPI/src/power-opcode-table.C) +# instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C (includes +# instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C) common/src/MachSyscall.C (includes +# common/src/SyscallInformation.C) # -if (HAS_CPP_FLAG_Wframe_larger_than AND NOT DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) - # Override the default frame size maximum for DEBUG (-O0) build types - # as there stack frames are larger: +if(HAS_CPP_FLAG_Wframe_larger_than AND NOT DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + # Override the default frame size maximum for DEBUG (-O0) build types as there stack + # frames are larger: # - add_compile_options($<$:-Wframe-larger-than=${defaultDebugMaxFrameSize}>) + add_compile_options( + $<$:-Wframe-larger-than=${defaultDebugMaxFrameSize}>) - # Use worst-case values discovered so far. For most gcc versions - # SyscallInformation.C stack frame size is less than than the default and - # InstructionDecoder-power.C is less than 76800, but for some environments - # and compiler configurations the following are needed: + # Use worst-case values discovered so far. For most gcc versions SyscallInformation.C + # stack frame size is less than than the default and InstructionDecoder-power.C is + # less than 76800, but for some environments and compiler configurations the following + # are needed: # set(debugMaxFrameSizeOverrideSyscallInformation 81920) set(debugMaxFrameSizeOverridePowerOpcodeTable 358400) - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[7](\.|$)") - set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38912) + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[7](\.|$)") + set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38912) endif() # most gcc's are under the default using -Og, but rhel's requires 30000 set(debugMaxFrameSizeOverrideFinalizeOperands 30000) - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[6](\.|$)") - set(nonDebugMaxFrameSizeOverrideFinalizeOperands 30000) + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[6](\.|$)") + set(nonDebugMaxFrameSizeOverrideFinalizeOperands 30000) endif() endif() unset(CMAKE_REQUIRED_FLAGS) -if (MSVC) - message(STATUS "TODO: Set up custom warning flags for MSVC") +if(MSVC) + message(STATUS "TODO: Set up custom warning flags for MSVC") endif() message(STATUS "Using C warning flags: ${SUPPORTED_C_WARNING_FLAGS}") message(STATUS "Using CXX warning flags: ${SUPPORTED_CXX_WARNING_FLAGS}") -message(STATUS "Extra CXX DEBUG warning flags: -Wframe-larger-than=${defaultDebugMaxFrameSize}") +message( + STATUS + "Extra CXX DEBUG warning flags: -Wframe-larger-than=${defaultDebugMaxFrameSize}") set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${SUPPORTED_C_WARNING_FLAGS}") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${SUPPORTED_CXX_WARNING_FLAGS}") diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 91e0ea258a..0a9ff1cee2 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -1,145 +1,132 @@ # CMake configuration for common directory if(NOT WIN32) -include_directories ( - ${PROJECT_SOURCE_DIR}/common/h - ${PROJECT_SOURCE_DIR}/common/src - ) + include_directories(${PROJECT_SOURCE_DIR}/common/h ${PROJECT_SOURCE_DIR}/common/src) else() -include_directories ( - ${PROJECT_SOURCE_DIR}/common/h # don't include common/src; anything from there can still collide with default includes. - # stupid Windows case-insensitive naming. - ) + include_directories( + ${PROJECT_SOURCE_DIR}/common/h # don't include common/src; anything from there can + # still collide with default includes. + # stupid Windows case-insensitive naming. + ) endif() - -set (SRC_LIST +set(SRC_LIST src/pfq-rwlock.C src/concurrent.C - src/Timer.C - src/Types.C + src/Timer.C + src/Types.C src/lprintf.C - src/pathName.C - src/stats.C - src/Annotatable.C - src/MappedFile.C - src/sha1.C + src/pathName.C + src/stats.C + src/Annotatable.C + src/MappedFile.C + src/sha1.C src/util.C - src/Node.C - src/Graph.C - src/Edge.C - src/DOT.C - src/dyn_regs.C - src/AST.C - src/addrtranslate.C - src/arch-x86.C - src/arch-power.C - src/arch-aarch64.C - src/debug_common.C - src/VariableLocation.C + src/Node.C + src/Graph.C + src/Edge.C + src/DOT.C + src/dyn_regs.C + src/AST.C + src/addrtranslate.C + src/arch-x86.C + src/arch-power.C + src/arch-aarch64.C + src/debug_common.C + src/VariableLocation.C src/Buffer.C - src/MachSyscall.C - ) - -set (C_SRC_LIST -) - -if (PLATFORM MATCHES freebsd) - set (SRC_LIST ${SRC_LIST} - src/freebsdKludges.C - src/addrtranslate-sysv.C - src/addrtranslate-freebsd.C - src/symbolDemangleWithCache.C - ) - set (C_SRC_LIST ${C_SRC_LIST} - src/symbolDemangle.c - ) + src/MachSyscall.C) + +set(C_SRC_LIST) + +if(PLATFORM MATCHES freebsd) + set(SRC_LIST ${SRC_LIST} src/freebsdKludges.C src/addrtranslate-sysv.C + src/addrtranslate-freebsd.C src/symbolDemangleWithCache.C) + set(C_SRC_LIST ${C_SRC_LIST} src/symbolDemangle.c) +endif() + +if(PLATFORM MATCHES linux) + set(SRC_LIST + ${SRC_LIST} + src/linuxKludges.C + src/parseauxv.C + src/addrtranslate-sysv.C + src/addrtranslate-auxv.C + src/addrtranslate-linux.C + src/symbolDemangleWithCache.C) + set(C_SRC_LIST ${C_SRC_LIST} src/symbolDemangle.c) endif() -if (PLATFORM MATCHES linux) - set (SRC_LIST ${SRC_LIST} - src/linuxKludges.C - src/parseauxv.C - src/addrtranslate-sysv.C - src/addrtranslate-auxv.C - src/addrtranslate-linux.C - src/symbolDemangleWithCache.C - ) - set (C_SRC_LIST ${C_SRC_LIST} - src/symbolDemangle.c - ) +if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) + set(SRC_LIST + ${SRC_LIST} src/ntKludges.C + # src/dthread-win.C src/dthread.C + src/addrtranslate-win.C) + add_definitions(-DWIN32 -D_WIN32_WINNT=0x500) endif() -if (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - set (SRC_LIST ${SRC_LIST} - src/ntKludges.C -# src/dthread-win.C -# src/dthread.C - src/addrtranslate-win.C - ) - add_definitions(-DWIN32 -D_WIN32_WINNT=0x500) -endif() - - -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) -SET_SOURCE_FILES_PROPERTIES(${C_SRC_LIST} PROPERTIES LANGUAGE C) -set (SRC_LIST ${SRC_LIST} - ${C_SRC_LIST} -) - -if (${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[789](\.|$)") - # Disable var-tracking-assignments for arch-x86.C for gcc 7, 8, & 9. - # The default max size for these compilers is too small so it fails, - # adjusting it using - # - # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=600000000" - # - # succeeds, but just disable it. - SET_SOURCE_FILES_PROPERTIES(src/arch-x86.C - PROPERTIES COMPILE_FLAGS "-fno-var-tracking-assignments") +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set_source_files_properties(${C_SRC_LIST} PROPERTIES LANGUAGE C) +set(SRC_LIST ${SRC_LIST} ${C_SRC_LIST}) + +if(${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[789](\.|$)") + # Disable var-tracking-assignments for arch-x86.C for gcc 7, 8, & 9. The default + # max size for these compilers is too small so it fails, adjusting it using + # + # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=600000000" + # + # succeeds, but just disable it. + set_source_files_properties( + src/arch-x86.C PROPERTIES COMPILE_FLAGS "-fno-var-tracking-assignments") endif() endif() # adjust warning threshold if set in cmake/warnings.cmake -if (debugMaxFrameSizeOverrideSyscallInformation) - SET_SOURCE_FILES_PROPERTIES(src/MachSyscall.C PROPERTIES COMPILE_FLAGS - $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideSyscallInformation}>) +if(debugMaxFrameSizeOverrideSyscallInformation) + set_source_files_properties( + src/MachSyscall.C + PROPERTIES + COMPILE_FLAGS + $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideSyscallInformation}> + ) endif() -if (nonDebugMaxFrameSizeOverrideSyscallInformation) - SET_SOURCE_FILES_PROPERTIES(src/MachSyscall.C PROPERTIES COMPILE_FLAGS - $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideSyscallInformation}>) +if(nonDebugMaxFrameSizeOverrideSyscallInformation) + set_source_files_properties( + src/MachSyscall.C + PROPERTIES + COMPILE_FLAGS + $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideSyscallInformation}> + ) endif() -ADD_DEFINITIONS(-DCOMMON_LIB) +add_definitions(-DCOMMON_LIB) dyninst_library(common) if(TARGET LibIberty) - add_dependencies(common LibIberty) - target_link_libraries(common PRIVATE LibIberty) + add_dependencies(common LibIberty) + target_link_libraries(common PRIVATE LibIberty) - if(${ENABLE_STATIC_LIBS}) - target_link_libraries(common_static PRIVATE LibIberty) - endif() + if(${ENABLE_STATIC_LIBS}) + target_link_libraries(common_static PRIVATE LibIberty) + endif() endif() if(TARGET TBB) add_dependencies(common TBB) endif() if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - target_link_private_libraries(common Psapi WS2_32 dbghelp) + target_link_private_libraries(common Psapi WS2_32 dbghelp) endif() target_link_private_libraries(common ${Boost_LIBRARIES}) target_link_libraries(common PUBLIC ${TBB_LIBRARIES}) if(USE_OpenMP) - set_target_properties(common PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) + set_target_properties(common PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} + LINK_FLAGS ${OpenMP_CXX_FLAGS}) endif() # Install AMDGPU headers under subdirectory of common/h/AMDGPU -set(AMDGPU_HEADER - ${DYNINST_ROOT}/common/h/AMDGPU -) +set(AMDGPU_HEADER ${DYNINST_ROOT}/common/h/AMDGPU) install(DIRECTORY ${AMDGPU_HEADER} DESTINATION ${INSTALL_INCLUDE_DIR}) - diff --git a/dwarf/CMakeLists.txt b/dwarf/CMakeLists.txt index e959351b20..e4ef428141 100644 --- a/dwarf/CMakeLists.txt +++ b/dwarf/CMakeLists.txt @@ -1,24 +1,14 @@ # CMake configuration for dynDwarf (dwarf) directory -if (NOT UNIX) - return() +if(NOT UNIX) + return() endif() -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/elf/h - ${PROJECT_SOURCE_DIR}/common/src - ) +include_directories(src h ${PROJECT_SOURCE_DIR}/elf/h ${PROJECT_SOURCE_DIR}/common/src) add_definitions(-DDYNDWARF_LIB) -set (SRC_LIST - src/dwarfResult.C - src/dwarfExprParser.C - src/dwarfFrameParser.C - src/dwarfHandle.C - ) - +set(SRC_LIST src/dwarfResult.C src/dwarfExprParser.C src/dwarfFrameParser.C + src/dwarfHandle.C) dyninst_library(dynDwarf dynElf common ${LibDwarf_LIBRARIES}) add_dependencies(dynDwarf ElfUtils) diff --git a/dynC_API/CMakeLists.txt b/dynC_API/CMakeLists.txt index 9c0d49605e..0dc95115dc 100644 --- a/dynC_API/CMakeLists.txt +++ b/dynC_API/CMakeLists.txt @@ -1,16 +1,12 @@ - file(GLOB SRC_LIST "src/*.C") -include_directories(h - src - ${PROJECT_SOURCE_DIR}/dyninstAPI/src - ${PROJECT_SOURCE_DIR}/proccontrol/h -) +include_directories(h src ${PROJECT_SOURCE_DIR}/dyninstAPI/src + ${PROJECT_SOURCE_DIR}/proccontrol/h) set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) add_definitions(-DDYNC_EXPORTS) if(WIN32) -add_definitions(-DYY_NO_UNISTD_H) + add_definitions(-DYY_NO_UNISTD_H) endif() dyninst_library(dynC_API dyninstAPI) diff --git a/dyninstAPI/CMakeLists.txt b/dyninstAPI/CMakeLists.txt index 518e6aacc9..e9ee10cd87 100644 --- a/dyninstAPI/CMakeLists.txt +++ b/dyninstAPI/CMakeLists.txt @@ -1,219 +1,213 @@ # CMake configuration for dyninstAPI directory -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/proccontrol/h - ) +include_directories(src h ${PROJECT_SOURCE_DIR}/proccontrol/h) -set (SRC_LIST - src/BPatch.C - src/BPatch_image.C - src/BPatch_function.C - src/BPatch_snippet.C - src/BPatch_thread.C - src/BPatch_process.C - src/BPatch_type.C - src/BPatch_module.C - src/BPatch_object.C - src/BPatch_point.C - src/BPatch_collections.C - src/BPatch_sourceBlock.C - src/BPatch_basicBlock.C - src/BPatch_basicBlockLoop.C - src/BPatch_edge.C - src/BPatch_loopTreeNode.C - src/BPatch_flowGraph.C - src/BPatch_frame.C - src/BPatch_parRegion.C - src/BPatch_statement.C - src/BPatch_addressSpace.C - src/BPatch_binaryEdit.C - src/BPatch_memoryAccess.C - src/debug.C - src/ast.C - src/registerSpace.C - src/codegen.C - src/inst.C - src/instPoint.C - src/baseTramp.C - src/addressSpace.C - src/binaryEdit.C - src/infHeap.C - src/frame.C - src/codeRange.C - src/image.C - src/parse-cfg.C - src/mapped_object.C - src/mapped_module.C - src/function.C - src/block.C - src/edge.C - src/variable.C - src/util.C - src/BPatch_instruction.C - src/parRegion.C - src/Parsing.C - src/Parsing-arch.C - src/hybridInstrumentation.C - src/hybridOverwrites.C - src/hybridCallbacks.C - src/dynProcess.C - src/dynThread.C - src/pcEventHandler.C - src/pcEventMuxer.C - src/Relocation/CodeMover.C - src/Relocation/CFG/RelocGraph.C - src/Relocation/CFG/RelocBlock.C - src/Relocation/CFG/RelocEdge.C - src/Relocation/CFG/RelocTarget.C - src/Relocation/Springboard.C - src/Relocation/Widgets/ASTWidget.C - src/Relocation/Widgets/CFWidget.C - src/Relocation/Widgets/CallbackWidget.C - src/Relocation/Widgets/InsnWidget.C - src/Relocation/Widgets/InstWidget.C - src/Relocation/Widgets/PCWidget.C - src/Relocation/Widgets/RelDataWidget.C - src/Relocation/Widgets/StackModWidget.C - src/Relocation/Transformers/Transformer.C - src/Relocation/Transformers/Instrumenter.C - src/Relocation/Transformers/Modification.C - src/Relocation/Transformers/Movement-adhoc.C - src/Relocation/Transformers/Movement-analysis.C - src/Relocation/CodeTracker.C - src/Relocation/CodeBuffer.C - src/Relocation/patchapi_debug.C - src/Relocation/DynObject.C - src/Relocation/DynAddrSpace.C - src/Relocation/DynPointMaker.C - src/Relocation/DynCFGMaker.C - src/Relocation/DynInstrumenter.C - src/Patching.C - src/frameChecker.C - src/BPatch_memoryAccessAdapter.C -) +set(SRC_LIST + src/BPatch.C + src/BPatch_image.C + src/BPatch_function.C + src/BPatch_snippet.C + src/BPatch_thread.C + src/BPatch_process.C + src/BPatch_type.C + src/BPatch_module.C + src/BPatch_object.C + src/BPatch_point.C + src/BPatch_collections.C + src/BPatch_sourceBlock.C + src/BPatch_basicBlock.C + src/BPatch_basicBlockLoop.C + src/BPatch_edge.C + src/BPatch_loopTreeNode.C + src/BPatch_flowGraph.C + src/BPatch_frame.C + src/BPatch_parRegion.C + src/BPatch_statement.C + src/BPatch_addressSpace.C + src/BPatch_binaryEdit.C + src/BPatch_memoryAccess.C + src/debug.C + src/ast.C + src/registerSpace.C + src/codegen.C + src/inst.C + src/instPoint.C + src/baseTramp.C + src/addressSpace.C + src/binaryEdit.C + src/infHeap.C + src/frame.C + src/codeRange.C + src/image.C + src/parse-cfg.C + src/mapped_object.C + src/mapped_module.C + src/function.C + src/block.C + src/edge.C + src/variable.C + src/util.C + src/BPatch_instruction.C + src/parRegion.C + src/Parsing.C + src/Parsing-arch.C + src/hybridInstrumentation.C + src/hybridOverwrites.C + src/hybridCallbacks.C + src/dynProcess.C + src/dynThread.C + src/pcEventHandler.C + src/pcEventMuxer.C + src/Relocation/CodeMover.C + src/Relocation/CFG/RelocGraph.C + src/Relocation/CFG/RelocBlock.C + src/Relocation/CFG/RelocEdge.C + src/Relocation/CFG/RelocTarget.C + src/Relocation/Springboard.C + src/Relocation/Widgets/ASTWidget.C + src/Relocation/Widgets/CFWidget.C + src/Relocation/Widgets/CallbackWidget.C + src/Relocation/Widgets/InsnWidget.C + src/Relocation/Widgets/InstWidget.C + src/Relocation/Widgets/PCWidget.C + src/Relocation/Widgets/RelDataWidget.C + src/Relocation/Widgets/StackModWidget.C + src/Relocation/Transformers/Transformer.C + src/Relocation/Transformers/Instrumenter.C + src/Relocation/Transformers/Modification.C + src/Relocation/Transformers/Movement-adhoc.C + src/Relocation/Transformers/Movement-analysis.C + src/Relocation/CodeTracker.C + src/Relocation/CodeBuffer.C + src/Relocation/patchapi_debug.C + src/Relocation/DynObject.C + src/Relocation/DynAddrSpace.C + src/Relocation/DynPointMaker.C + src/Relocation/DynCFGMaker.C + src/Relocation/DynInstrumenter.C + src/Patching.C + src/frameChecker.C + src/BPatch_memoryAccessAdapter.C) # This is just .. messy. Sorry. get_directory_property(local_comp_defs COMPILE_DEFINITIONS) -list (FIND local_comp_defs cap_stack_mods cap_stack_mods_found) -if (cap_stack_mods_found GREATER -1) -set (SRC_LIST ${SRC_LIST} - src/StackMod/OffsetVector.C - src/StackMod/StackAccess.C - src/StackMod/StackLocation.C - src/StackMod/StackMod.C - src/StackMod/StackModExpr.C - src/StackMod/StackModChecker.C - src/StackMod/TMap.C -) -endif () +list(FIND local_comp_defs cap_stack_mods cap_stack_mods_found) +if(cap_stack_mods_found GREATER -1) + set(SRC_LIST + ${SRC_LIST} + src/StackMod/OffsetVector.C + src/StackMod/StackAccess.C + src/StackMod/StackLocation.C + src/StackMod/StackMod.C + src/StackMod/StackModExpr.C + src/StackMod/StackModChecker.C + src/StackMod/TMap.C) +endif() -if (PLATFORM MATCHES i386 OR PLATFORM MATCHES amd64 OR PLATFORM MATCHES x86_64) -set (SRC_LIST ${SRC_LIST} - src/RegisterConversion-x86.C - src/Relocation/Widgets/CFWidget-x86.C - src/Relocation/Widgets/PCWidget-x86.C - src/inst-x86.C - src/emit-x86.C - src/codegen-x86.C - src/stackwalk-x86.C - src/dynProcess-x86.C - src/parse-x86.C - src/IAPI_to_AST.C -) -elseif (PLATFORM MATCHES ppc) -set (SRC_LIST ${SRC_LIST} - src/inst-power.C - src/codegen-power.C - src/parse-power.C - src/RegisterConversion-ppc.C - src/stackwalk-ppc.C - src/Relocation/Widgets/CFWidget-ppc.C - src/Relocation/Widgets/PCWidget-ppc.C -) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} - src/inst-aarch64.C - src/emit-aarch64.C - src/codegen-aarch64.C - src/parse-aarch64.C - src/RegisterConversion-aarch64.C - src/stackwalk-aarch64.C - src/Relocation/Widgets/CFWidget-aarch64.C - src/Relocation/Widgets/PCWidget-aarch64.C -) -endif () +if(PLATFORM MATCHES i386 + OR PLATFORM MATCHES amd64 + OR PLATFORM MATCHES x86_64) + set(SRC_LIST + ${SRC_LIST} + src/RegisterConversion-x86.C + src/Relocation/Widgets/CFWidget-x86.C + src/Relocation/Widgets/PCWidget-x86.C + src/inst-x86.C + src/emit-x86.C + src/codegen-x86.C + src/stackwalk-x86.C + src/dynProcess-x86.C + src/parse-x86.C + src/IAPI_to_AST.C) +elseif(PLATFORM MATCHES ppc) + set(SRC_LIST + ${SRC_LIST} + src/inst-power.C + src/codegen-power.C + src/parse-power.C + src/RegisterConversion-ppc.C + src/stackwalk-ppc.C + src/Relocation/Widgets/CFWidget-ppc.C + src/Relocation/Widgets/PCWidget-ppc.C) +elseif(PLATFORM MATCHES aarch64) + set(SRC_LIST + ${SRC_LIST} + src/inst-aarch64.C + src/emit-aarch64.C + src/codegen-aarch64.C + src/parse-aarch64.C + src/RegisterConversion-aarch64.C + src/stackwalk-aarch64.C + src/Relocation/Widgets/CFWidget-aarch64.C + src/Relocation/Widgets/PCWidget-aarch64.C) +endif() -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd.C - src/unix.C - src/freebsd-x86.C - src/syscallNotification.C - src/syscall-freebsd.C -) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/inst-linux.C - src/unix.C - src/syscallNotification.C - src/syscall-linux.C -) - if (PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) - set (SRC_LIST ${SRC_LIST} src/linux-x86.C) - elseif (PLATFORM MATCHES ppc) - set (SRC_LIST ${SRC_LIST} src/linux-power.C) - elseif (PLATFORM MATCHES aarch64) - set (SRC_LIST ${SRC_LIST} src/linux-aarch64.C) - endif() +if(PLATFORM MATCHES freebsd) + set(SRC_LIST ${SRC_LIST} src/freebsd.C src/unix.C src/freebsd-x86.C + src/syscallNotification.C src/syscall-freebsd.C) +elseif(PLATFORM MATCHES linux) + set(SRC_LIST ${SRC_LIST} src/linux.C src/inst-linux.C src/unix.C + src/syscallNotification.C src/syscall-linux.C) + if(PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) + set(SRC_LIST ${SRC_LIST} src/linux-x86.C) + elseif(PLATFORM MATCHES ppc) + set(SRC_LIST ${SRC_LIST} src/linux-power.C) + elseif(PLATFORM MATCHES aarch64) + set(SRC_LIST ${SRC_LIST} src/linux-aarch64.C) + endif() elseif(PLATFORM MATCHES windows OR PLATFORM MATCHES nt) - set (SRC_LIST ${SRC_LIST} - src/hybridCallbacks.C - src/hybridInstrumentation.C - src/hybridOverwrites.C + set(SRC_LIST + ${SRC_LIST} + src/hybridCallbacks.C + src/hybridInstrumentation.C + src/hybridOverwrites.C src/inst-winnt.C src/pdwinnt.C src/syscall-nt.C - src/Relocation/DynAddrSpace.C - src/Relocation/DynCFGMaker.C - src/Relocation/DynInstrumenter.C - src/Relocation/DynObject.C - src/Relocation/DynPointMaker.C - ) + src/Relocation/DynAddrSpace.C + src/Relocation/DynCFGMaker.C + src/Relocation/DynInstrumenter.C + src/Relocation/DynObject.C + src/Relocation/DynPointMaker.C) endif() set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) add_definitions(-DBPATCH_DLL_BUILD) -if (PLATFORM MATCHES i386 AND UNIX) -set (SRC_LIST ${SRC_LIST} src/cpuid-x86.S) -set_source_files_properties(src/cpuid-x86.S PROPERTIES LANGUAGE C) -endif () +if(PLATFORM MATCHES i386 AND UNIX) + set(SRC_LIST ${SRC_LIST} src/cpuid-x86.S) + set_source_files_properties(src/cpuid-x86.S PROPERTIES LANGUAGE C) +endif() -dyninst_library(dyninstAPI common instructionAPI stackwalk pcontrol patchAPI parseAPI symtabAPI) +dyninst_library( + dyninstAPI + common + instructionAPI + stackwalk + pcontrol + patchAPI + parseAPI + symtabAPI) target_link_private_libraries(dyninstAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES}) -if (UNIX) - # Boost auto-links on Windows; don't double-link - target_link_private_libraries (dyninstAPI pthread) +if(UNIX) + # Boost auto-links on Windows; don't double-link + target_link_private_libraries(dyninstAPI pthread) else() - target_link_private_libraries(dyninstAPI dbghelp WS2_32 imagehlp) + target_link_private_libraries(dyninstAPI dbghelp WS2_32 imagehlp) endif() if(UNIX) - # gcc/clang search directories - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" OR CMAKE_CXX_COMPILER_ID STREQUAL "Clang") - execute_process( - COMMAND ${CMAKE_CXX_COMPILER} -print-search-dirs - OUTPUT_VARIABLE SEARCH_DIRS - ) - if(SEARCH_DIRS MATCHES "libraries:[ ]?[=]?(.+)\n") - set(DYNINST_COMPILER_SEARCH_DIRS ${CMAKE_MATCH_1}) - endif() - endif() - target_compile_definitions(dyninstAPI PRIVATE DYNINST_COMPILER_SEARCH_DIRS=${DYNINST_COMPILER_SEARCH_DIRS}) + # gcc/clang search directories + if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" OR CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + execute_process(COMMAND ${CMAKE_CXX_COMPILER} -print-search-dirs + OUTPUT_VARIABLE SEARCH_DIRS) + if(SEARCH_DIRS MATCHES "libraries:[ ]?[=]?(.+)\n") + set(DYNINST_COMPILER_SEARCH_DIRS ${CMAKE_MATCH_1}) + endif() + endif() + target_compile_definitions( + dyninstAPI PRIVATE DYNINST_COMPILER_SEARCH_DIRS=${DYNINST_COMPILER_SEARCH_DIRS}) endif() install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index b454688d79..0922804f27 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -1,247 +1,230 @@ # CMake configuration for dyninstAPI_RT directory -cmake_minimum_required (VERSION 2.6.4) -project (DyninstRT C) - -set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}/..) - -include (${DYNINST_ROOT}/cmake/LanguageStandards.cmake) -include (${DYNINST_ROOT}/cmake/shared.cmake) - -include_directories ( - ${DYNINST_ROOT}/dyninstAPI_RT/src - ${DYNINST_ROOT}/dyninstAPI_RT/h - ${DYNINST_ROOT} - ) - -set (SRC_LIST - src/RTcommon.c -) - -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/RTposix.c - src/RTfreebsd.c - src/RTheap.c - src/RTheap-freebsd.c - src/RTthread.c - src/RTspace.S - src/RTsignal.c -) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/RTposix.c - src/RTlinux.c - src/RTheap.c - src/RTheap-linux.c - src/RTthread.c - src/RTspace.S - src/RTsignal.c -) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} - src/RTstatic_ctors_dtors_begin.c - src/RTstatic_ctors_dtors_end.c -) -elseif (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) -set (SRC_LIST ${SRC_LIST} - src/RTheap.c - src/RTheap-win.c - src/RTwinnt.c - src/RTthread.c - src/RTthread-x86.c -) -endif () - -set (SRC_LIST_i386 - src/RTthread-x86.c - src/RTtlsgetaddr-x86.S -) -set (RT_STATIC_ONLY_SRC_LIST_i386 - src/RTstatic_ctors_dtors-x86.c -) -set (SRC_LIST_x86_64 - src/RTthread-x86-64.c - src/RTtlsgetaddr-x86.S -) -set (RT_STATIC_ONLY_SRC_LIST_x86_64 - src/RTstatic_ctors_dtors-x86.c -) -set (SRC_LIST_ppc64 - src/RTthread-powerpc.c - src/RTthread-powerpc-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_ppc64 - src/RTstatic_ctors_dtors-ppc64.c -) -set (SRC_LIST_aarch64 - src/RTthread-aarch64.c - #src/RTthread-aarch64-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_aarch64 - src/RTstatic_ctors_dtors-aarch64.c -) - - -# We use gcc to compile the various assembly files, but -# cmake doesn't default to knowing that gcc can -# handle .S. -ENABLE_LANGUAGE(ASM) -file (GLOB SRC_ASSEMBLY "src/*.S") +cmake_minimum_required(VERSION 2.6.4) +project(DyninstRT C) + +set(DYNINST_ROOT ${PROJECT_SOURCE_DIR}/..) + +include(${DYNINST_ROOT}/cmake/LanguageStandards.cmake) +include(${DYNINST_ROOT}/cmake/shared.cmake) + +include_directories(${DYNINST_ROOT}/dyninstAPI_RT/src ${DYNINST_ROOT}/dyninstAPI_RT/h + ${DYNINST_ROOT}) + +set(SRC_LIST src/RTcommon.c) + +if(PLATFORM MATCHES freebsd) + set(SRC_LIST + ${SRC_LIST} + src/RTposix.c + src/RTfreebsd.c + src/RTheap.c + src/RTheap-freebsd.c + src/RTthread.c + src/RTspace.S + src/RTsignal.c) +elseif(PLATFORM MATCHES linux) + set(SRC_LIST + ${SRC_LIST} + src/RTposix.c + src/RTlinux.c + src/RTheap.c + src/RTheap-linux.c + src/RTthread.c + src/RTspace.S + src/RTsignal.c) + set(RT_STATIC_ONLY_SRC_LIST + ${RT_STATIC_ONLY_SRC_LIST} src/RTstatic_ctors_dtors_begin.c + src/RTstatic_ctors_dtors_end.c) +elseif(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) + set(SRC_LIST ${SRC_LIST} src/RTheap.c src/RTheap-win.c src/RTwinnt.c src/RTthread.c + src/RTthread-x86.c) +endif() + +set(SRC_LIST_i386 src/RTthread-x86.c src/RTtlsgetaddr-x86.S) +set(RT_STATIC_ONLY_SRC_LIST_i386 src/RTstatic_ctors_dtors-x86.c) +set(SRC_LIST_x86_64 src/RTthread-x86-64.c src/RTtlsgetaddr-x86.S) +set(RT_STATIC_ONLY_SRC_LIST_x86_64 src/RTstatic_ctors_dtors-x86.c) +set(SRC_LIST_ppc64 src/RTthread-powerpc.c src/RTthread-powerpc-asm.S) +set(RT_STATIC_ONLY_SRC_LIST_ppc64 src/RTstatic_ctors_dtors-ppc64.c) +set(SRC_LIST_aarch64 src/RTthread-aarch64.c + # src/RTthread-aarch64-asm.S + ) +set(RT_STATIC_ONLY_SRC_LIST_aarch64 src/RTstatic_ctors_dtors-aarch64.c) + +# We use gcc to compile the various assembly files, but cmake doesn't default to knowing +# that gcc can handle .S. +enable_language(ASM) +file(GLOB SRC_ASSEMBLY "src/*.S") if(NEED_NATIVE_ASSEMBER MATCHES YES) -set_source_files_properties(${SRC_ASSEMBLY} - PROPERTIES - LANGUAGE ASM) + set_source_files_properties(${SRC_ASSEMBLY} PROPERTIES LANGUAGE ASM) else() -set_source_files_properties(${SRC_ASSEMBLY} - PROPERTIES - LANGUAGE C) + set_source_files_properties(${SRC_ASSEMBLY} PROPERTIES LANGUAGE C) endif() # The arch-specific files other than RTthread-x86 are Unix-only. if(UNIX) -if (PLATFORM MATCHES amd64 OR PLATFORM MATCHES x86_64) -set (SRC_LIST_mabi ${SRC_LIST} ${SRC_LIST_i386}) -set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_i386}) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_x86_64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_x86_64}) -elseif (PLATFORM MATCHES ppc64) -set (SRC_LIST_mabi ${SRC_LIST}) -set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST}) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc64}) -elseif (PLATFORM MATCHES i386) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_i386}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_i386}) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_aarch64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_aarch64}) -endif() + if(PLATFORM MATCHES amd64 OR PLATFORM MATCHES x86_64) + set(SRC_LIST_mabi ${SRC_LIST} ${SRC_LIST_i386}) + set(RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} + ${RT_STATIC_ONLY_SRC_LIST_i386}) + set(SRC_LIST ${SRC_LIST} ${SRC_LIST_x86_64}) + set(RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} + ${RT_STATIC_ONLY_SRC_LIST_x86_64}) + elseif(PLATFORM MATCHES ppc64) + set(SRC_LIST_mabi ${SRC_LIST}) + set(RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST}) + set(SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc64}) + set(RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} + ${RT_STATIC_ONLY_SRC_LIST_ppc64}) + elseif(PLATFORM MATCHES i386) + set(SRC_LIST ${SRC_LIST} ${SRC_LIST_i386}) + set(RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} + ${RT_STATIC_ONLY_SRC_LIST_i386}) + elseif(PLATFORM MATCHES aarch64) + set(SRC_LIST ${SRC_LIST} ${SRC_LIST_aarch64}) + set(RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} + ${RT_STATIC_ONLY_SRC_LIST_aarch64}) + endif() endif() -add_library (dyninstAPI_RT SHARED ${SRC_LIST}) +add_library(dyninstAPI_RT SHARED ${SRC_LIST}) if(TARGET TBB) add_dependencies(dyninstAPI_RT TBB) endif() -if (NOT PLATFORM MATCHES nt AND NOT PLATFORM MATCHES windows) - target_link_libraries (dyninstAPI_RT ${CMAKE_DL_LIBS}) +if(NOT PLATFORM MATCHES nt AND NOT PLATFORM MATCHES windows) + target_link_libraries(dyninstAPI_RT ${CMAKE_DL_LIBS}) else() # windows - target_link_libraries (dyninstAPI_RT ws2_32 dbghelp psapi) + target_link_libraries(dyninstAPI_RT ws2_32 dbghelp psapi) endif() -add_library (dyninstAPI_RT_static STATIC ${SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST}) +add_library(dyninstAPI_RT_static STATIC ${SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST}) if(TARGET TBB) add_dependencies(dyninstAPI_RT_static TBB) endif() # this should carry over from CMakeLists.txt -set_target_properties (dyninstAPI_RT - PROPERTIES - OUTPUT_NAME dyninstAPI_RT - SOVERSION ${SOVERSION} - VERSION ${LIBVERSION}) +set_target_properties( + dyninstAPI_RT + PROPERTIES OUTPUT_NAME dyninstAPI_RT + SOVERSION ${SOVERSION} + VERSION ${LIBVERSION}) # this will not -set_target_properties (dyninstAPI_RT_static - PROPERTIES - OUTPUT_NAME dyninstAPI_RT - COMPILE_DEFINITIONS DYNINST_RT_STATIC_LIB) - -set_target_properties (dyninstAPI_RT PROPERTIES CLEAN_DIRECT_OUTPUT 1) -set_target_properties (dyninstAPI_RT_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) +set_target_properties( + dyninstAPI_RT_static PROPERTIES OUTPUT_NAME dyninstAPI_RT COMPILE_DEFINITIONS + DYNINST_RT_STATIC_LIB) +set_target_properties(dyninstAPI_RT PROPERTIES CLEAN_DIRECT_OUTPUT 1) +set_target_properties(dyninstAPI_RT_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) message(STATUS "dyninstAPI RT library SOVERSION: ${SOVERSION}") message(STATUS "dyninstAPI RT library LIBVERSION: ${LIBVERSION}") -FILE (GLOB headers "h/*.h") +file(GLOB headers "h/*.h") # append, you fool! -set_target_properties (dyninstAPI_RT dyninstAPI_RT_static PROPERTIES PUBLIC_HEADER "${headers}") +set_target_properties(dyninstAPI_RT dyninstAPI_RT_static PROPERTIES PUBLIC_HEADER + "${headers}") -INSTALL (TARGETS dyninstAPI_RT dyninstAPI_RT_static - EXPORT DyninstTargets - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) +install( + TARGETS dyninstAPI_RT dyninstAPI_RT_static + EXPORT DyninstTargets + RUNTIME DESTINATION ${INSTALL_LIB_DIR} + LIBRARY DESTINATION ${INSTALL_LIB_DIR} + ARCHIVE DESTINATION ${INSTALL_LIB_DIR} + PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) # Test to see if we want the 32-bit library -if (SRC_LIST_mabi) - -# The following code is from CheckCCompilerFlag.cmake. It uses a -# simple program that can be compiled even if 32-bit includes are -# missing; we need to extend it somewhat - -INCLUDE(CheckCSourceCompiles) - -MACRO (CHECK_C_COMPILER_FLAG_EXTENDED _FLAG _RESULT) - SET(SAFE_CMAKE_C_FLAGS "${CMAKE_C_FLAGS}") - SET(CMAKE_C_FLAGS "${_FLAG}") - -# Addition here: use signal.h - CHECK_C_SOURCE_COMPILES("#include - int main(void) { return 0; }" - ${_RESULT} -# End addition - # Some compilers do not fail with a bad flag - FAIL_REGEX "warning: command line option .* is valid for .* but not for C" - # Apple gcc - FAIL_REGEX "unrecognized .*option" # GNU - FAIL_REGEX "unknown .*option" # Clang - FAIL_REGEX "ignoring unknown option" # MSVC - FAIL_REGEX "warning D9002" # MSVC, any lang - FAIL_REGEX "[Uu]nknown option" # HP - FAIL_REGEX "[Ww]arning: [Oo]ption" # SunPro - FAIL_REGEX "command option .* is not recognized" # XL - ) - SET(CMAKE_C_FLAGS "${SAFE_CMAKE_C_FLAGS}") -ENDMACRO (CHECK_C_COMPILER_FLAG_EXTENDED) - - -message (STATUS "Checking for 32-bit runtime library...") - -CHECK_C_COMPILER_FLAG_EXTENDED ("-m32" CHECK_RT_LIB_32) -if (CHECK_RT_LIB_32 AND NOT ${BUILD_RTLIB_32} MATCHES "OFF") -message (STATUS "Enabling 32-bit runtime library; change BUILD_RTLIB_32 to OFF to disable") -SET (BUILD_RTLIB_32 ON) -ELSE () -message (STATUS "Disabling 32-bit runtime library; change BUILD_RTLIB_32 to ON and install 32-bit build environment to enable") -SET (BUILD_RTLIB_32 OFF) -ENDIF() - -if (BUILD_RTLIB_32 MATCHES "ON") - -add_library (dyninstAPI_RT_m32 SHARED ${SRC_LIST_mabi}) -target_link_libraries (dyninstAPI_RT_m32 ${CMAKE_DL_LIBS}) -add_library (dyninstAPI_RT_m32_static STATIC ${SRC_LIST_mabi} ${RT_STATIC_ONLY_SRC_LIST_mabi}) - -set_target_properties (dyninstAPI_RT_m32 - PROPERTIES - COMPILE_FLAGS "-DMUTATEE_32 -m32" - LINK_FLAGS "-m32" - OUTPUT_NAME dyninstAPI_RT_m32 - SOVERSION ${SOVERSION} - VERSION ${LIBVERSION}) - -set_target_properties (dyninstAPI_RT_m32_static - PROPERTIES - OUTPUT_NAME dyninstAPI_RT_m32 - COMPILE_FLAGS "-DMUTATEE_32 -m32" - LINK_FLAGS "-m32" - COMPILE_DEFINITIONS DYNINST_RT_STATIC_LIB) - -set_target_properties (dyninstAPI_RT_m32 PROPERTIES CLEAN_DIRECT_OUTPUT 1) -set_target_properties (dyninstAPI_RT_m32_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) - -INSTALL (TARGETS dyninstAPI_RT_m32 dyninstAPI_RT_m32_static - EXPORT DyninstTargets - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) - -install (EXPORT DyninstTargets - DESTINATION "${INSTALL_CMAKE_DIR}") - -endif() +if(SRC_LIST_mabi) + + # The following code is from CheckCCompilerFlag.cmake. It uses a simple program that + # can be compiled even if 32-bit includes are missing; we need to extend it somewhat + + include(CheckCSourceCompiles) + + macro(CHECK_C_COMPILER_FLAG_EXTENDED _FLAG _RESULT) + set(SAFE_CMAKE_C_FLAGS "${CMAKE_C_FLAGS}") + set(CMAKE_C_FLAGS "${_FLAG}") + + # Addition here: use signal.h + check_c_source_compiles( + "#include + int main(void) { return 0; }" + ${_RESULT} + # End addition Some compilers do not fail with a bad flag + FAIL_REGEX + "warning: command line option .* is valid for .* but not for C" + # Apple gcc + FAIL_REGEX + "unrecognized .*option" # GNU + FAIL_REGEX + "unknown .*option" # Clang + FAIL_REGEX + "ignoring unknown option" # MSVC + FAIL_REGEX + "warning D9002" # MSVC, any lang + FAIL_REGEX + "[Uu]nknown option" # HP + FAIL_REGEX + "[Ww]arning: [Oo]ption" # SunPro + FAIL_REGEX + "command option .* is not recognized" # XL + ) + set(CMAKE_C_FLAGS "${SAFE_CMAKE_C_FLAGS}") + endmacro(CHECK_C_COMPILER_FLAG_EXTENDED) + + message(STATUS "Checking for 32-bit runtime library...") + + check_c_compiler_flag_extended("-m32" CHECK_RT_LIB_32) + if(CHECK_RT_LIB_32 AND NOT ${BUILD_RTLIB_32} MATCHES "OFF") + message( + STATUS + "Enabling 32-bit runtime library; change BUILD_RTLIB_32 to OFF to disable" + ) + set(BUILD_RTLIB_32 ON) + else() + message( + STATUS + "Disabling 32-bit runtime library; change BUILD_RTLIB_32 to ON and install 32-bit build environment to enable" + ) + set(BUILD_RTLIB_32 OFF) + endif() + + if(BUILD_RTLIB_32 MATCHES "ON") + + add_library(dyninstAPI_RT_m32 SHARED ${SRC_LIST_mabi}) + target_link_libraries(dyninstAPI_RT_m32 ${CMAKE_DL_LIBS}) + add_library(dyninstAPI_RT_m32_static STATIC ${SRC_LIST_mabi} + ${RT_STATIC_ONLY_SRC_LIST_mabi}) + + set_target_properties( + dyninstAPI_RT_m32 + PROPERTIES COMPILE_FLAGS "-DMUTATEE_32 -m32" + LINK_FLAGS "-m32" + OUTPUT_NAME dyninstAPI_RT_m32 + SOVERSION ${SOVERSION} + VERSION ${LIBVERSION}) + + set_target_properties( + dyninstAPI_RT_m32_static + PROPERTIES OUTPUT_NAME dyninstAPI_RT_m32 + COMPILE_FLAGS "-DMUTATEE_32 -m32" + LINK_FLAGS "-m32" + COMPILE_DEFINITIONS DYNINST_RT_STATIC_LIB) + + set_target_properties(dyninstAPI_RT_m32 PROPERTIES CLEAN_DIRECT_OUTPUT 1) + set_target_properties(dyninstAPI_RT_m32_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) + + install( + TARGETS dyninstAPI_RT_m32 dyninstAPI_RT_m32_static + EXPORT DyninstTargets + RUNTIME DESTINATION ${INSTALL_LIB_DIR} + LIBRARY DESTINATION ${INSTALL_LIB_DIR} + ARCHIVE DESTINATION ${INSTALL_LIB_DIR} + PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) + + install(EXPORT DyninstTargets DESTINATION "${INSTALL_CMAKE_DIR}") + + endif() endif() diff --git a/elf/CMakeLists.txt b/elf/CMakeLists.txt index 4f80f46170..94f6f77fb7 100644 --- a/elf/CMakeLists.txt +++ b/elf/CMakeLists.txt @@ -1,17 +1,12 @@ # CMake configuration for dynElf (elf) directory -if (NOT UNIX) - return() +if(NOT UNIX) + return() endif() -include_directories ( - src - h - ) +include_directories(src h) -set (SRC_LIST - src/Elf_X.C - ) +set(SRC_LIST src/Elf_X.C) dyninst_library(dynElf ${LibElf_LIBRARIES}) if(TARGET TBB) @@ -20,8 +15,8 @@ endif() add_dependencies(dynElf ElfUtils) target_link_private_libraries(dynElf ${ElfUtils_LIBRARIES}) -if (ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) - add_definitions(-DDEBUGINFOD_LIB) +if(ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) + add_definitions(-DDEBUGINFOD_LIB) endif() add_definitions(-DDYNELF_LIB) diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index f780902f1f..3d81cec4e5 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -1,42 +1,39 @@ # CMake configuration for instructionAPI directory -include_directories ( +include_directories( ${PROJECT_SOURCE_DIR}/instructionAPI/src ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/cdna2 - ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/vega - ) + ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/vega) - -set (SRC_LIST - src/Instruction.C - src/InstructionAST.C - src/Operation.C - src/Operand.C - src/Register.C - src/Ternary.C - src/Expression.C - src/BinaryFunction.C - src/InstructionCategories.C - src/ArchSpecificFormatters.C - src/Immediate.C - src/InstructionDecoder.C - src/InstructionDecoder-x86.C - src/InstructionDecoder-power.C - src/InstructionDecoder-aarch64.C - src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C - src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C - src/InstructionDecoderImpl.C - ) -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set(SRC_LIST + src/Instruction.C + src/InstructionAST.C + src/Operation.C + src/Operand.C + src/Register.C + src/Ternary.C + src/Expression.C + src/BinaryFunction.C + src/InstructionCategories.C + src/ArchSpecificFormatters.C + src/Immediate.C + src/InstructionDecoder.C + src/InstructionDecoder-x86.C + src/InstructionDecoder-power.C + src/InstructionDecoder-aarch64.C + src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C + src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C + src/InstructionDecoderImpl.C) +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) set(instructionDecoderPowerExtraFlags "") -if (${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^([1-9]|1[01])(\.|$)") - # Disable var-tracking-assignments for InstructionDecoder-power.C for - # all known versions of gcc.. The default max size is too small so it - # fails, and adjusting it using +if(${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^([1-9]|1[01])(\.|$)") + # Disable var-tracking-assignments for InstructionDecoder-power.C for all known + # versions of gcc.. The default max size is too small so it fails, and adjusting + # it using # - # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=900000000" + # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=900000000" # # succeeds, but the object file produced is >1GB, so disable it. string(APPEND instructionDecoderPowerExtraFlags "-fno-var-tracking-assignments") @@ -44,37 +41,51 @@ if (${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") endif() # adjust warning threshold if set in cmake/warnings.cmake -if (debugMaxFrameSizeOverridePowerOpcodeTable) - string(APPEND instructionDecoderPowerExtraFlags - " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverridePowerOpcodeTable}>") +if(debugMaxFrameSizeOverridePowerOpcodeTable) + string( + APPEND + instructionDecoderPowerExtraFlags + " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverridePowerOpcodeTable}>" + ) endif() -if (nonDebugMaxFrameSizeOverridePowerOpcodeTable) - string(APPEND instructionDecoderPowerExtraFlags - " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverridePowerOpcodeTable}>") +if(nonDebugMaxFrameSizeOverridePowerOpcodeTable) + string( + APPEND + instructionDecoderPowerExtraFlags + " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverridePowerOpcodeTable}>" + ) endif() -if (NOT instructionDecoderPowerExtraFlags STREQUAL "") - SET_SOURCE_FILES_PROPERTIES(src/InstructionDecoder-power.C - PROPERTIES COMPILE_FLAGS "${instructionDecoderPowerExtraFlags}") +if(NOT instructionDecoderPowerExtraFlags STREQUAL "") + set_source_files_properties( + src/InstructionDecoder-power.C PROPERTIES COMPILE_FLAGS + "${instructionDecoderPowerExtraFlags}") endif() set(finalizeOperandsExtraFlags "") -if (debugMaxFrameSizeOverrideFinalizeOperands) - string(APPEND finalizeOperandsExtraFlags - " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideFinalizeOperands}>") +if(debugMaxFrameSizeOverrideFinalizeOperands) + string( + APPEND + finalizeOperandsExtraFlags + " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideFinalizeOperands}>" + ) endif() -if (nonDebugMaxFrameSizeOverrideFinalizeOperands) - string(APPEND finalizeOperandsExtraFlags - " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideFinalizeOperands}>") +if(nonDebugMaxFrameSizeOverrideFinalizeOperands) + string( + APPEND + finalizeOperandsExtraFlags + " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideFinalizeOperands}>" + ) endif() -if (NOT finalizeOperandsExtraFlags STREQUAL "") - SET_SOURCE_FILES_PROPERTIES(src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C - PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") +if(NOT finalizeOperandsExtraFlags STREQUAL "") + set_source_files_properties(src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") endif() -ADD_DEFINITIONS(-DINSTRUCTION_LIB) +add_definitions(-DINSTRUCTION_LIB) dyninst_library(instructionAPI common) -target_link_private_libraries(instructionAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} tbbmalloc) +target_link_private_libraries(instructionAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} + tbbmalloc) diff --git a/parseAPI/CMakeLists.txt b/parseAPI/CMakeLists.txt index 41245da9af..8faa83141e 100644 --- a/parseAPI/CMakeLists.txt +++ b/parseAPI/CMakeLists.txt @@ -1,139 +1,129 @@ # CMake configuration for parseAPI directory -include_directories ( - ${PROJECT_SOURCE_DIR}/parseAPI/src - ) +include_directories(${PROJECT_SOURCE_DIR}/parseAPI/src) -set (SRC_LIST - src/ParserDetails.C - src/Parser.C - src/CFGFactory.C - src/Function.C - src/Block.C - src/CodeObject.C - src/debug_parse.C - src/CodeSource.C - src/ParseData.C - src/InstructionAdapter.C - src/Parser-speculative.C - src/ParseCallback.C - src/IA_IAPI.C - src/IA_x86.C - src/IA_power.C - src/IA_aarch64.C +set(SRC_LIST + src/ParserDetails.C + src/Parser.C + src/CFGFactory.C + src/Function.C + src/Block.C + src/CodeObject.C + src/debug_parse.C + src/CodeSource.C + src/ParseData.C + src/InstructionAdapter.C + src/Parser-speculative.C + src/ParseCallback.C + src/IA_IAPI.C + src/IA_x86.C + src/IA_power.C + src/IA_aarch64.C src/IA_amdgpu.C - src/CFGModifier.C - src/StackTamperVisitor.C - src/JumpTableFormatPred.C - src/JumpTableIndexPred.C - src/IndirectAnalyzer.C - src/IndirectASTVisitor.C - src/SymbolicExpression.C - src/BoundFactCalculator.C - src/BoundFactData.C - src/ThunkData.C - ../dataflowAPI/src/ABI.C - src/dominator.C - src/LoopAnalyzer.C - src/Loop.C - src/LoopTreeNode.C - src/IdiomModelDesc.C - src/ProbabilisticParser.C - ) + src/CFGModifier.C + src/StackTamperVisitor.C + src/JumpTableFormatPred.C + src/JumpTableIndexPred.C + src/IndirectAnalyzer.C + src/IndirectASTVisitor.C + src/SymbolicExpression.C + src/BoundFactCalculator.C + src/BoundFactData.C + src/ThunkData.C + ../dataflowAPI/src/ABI.C + src/dominator.C + src/LoopAnalyzer.C + src/Loop.C + src/LoopTreeNode.C + src/IdiomModelDesc.C + src/ProbabilisticParser.C) set(ROSE_SRC - ../dataflowAPI/src/ABI.C - ../dataflowAPI/src/Absloc.C - ../dataflowAPI/src/AbslocInterface.C - ../dataflowAPI/src/convertOpcodes.C - ../dataflowAPI/src/debug_dataflow.C - ../dataflowAPI/src/ExpressionConversionVisitor.C - ../dataflowAPI/src/InstructionCache.C - ../dataflowAPI/src/liveness.C - ../dataflowAPI/src/RegisterMap.C - ../dataflowAPI/src/RoseImpl.C - ../dataflowAPI/src/RoseInsnFactory.C - ../dataflowAPI/src/slicing.C - ../dataflowAPI/src/stackanalysis.C - ../dataflowAPI/src/SymbolicExpansion.C - ../dataflowAPI/src/SymEval.C - ../dataflowAPI/src/SymEvalPolicy.C - ../dataflowAPI/src/templates.C - ../dataflowAPI/src/Visitors.C - ../dataflowAPI/rose/ExtentMap.C - ../dataflowAPI/rose/rangemap.C - ../dataflowAPI/rose/util/Assert.C - ../dataflowAPI/rose/util/Message.C - ../dataflowAPI/rose/util/Sawyer.C - ../dataflowAPI/rose/util/Synchronization.C - ../dataflowAPI/rose/util/rose_getline.C - ../dataflowAPI/rose/util/SmallObject.C - ../dataflowAPI/rose/util/Stopwatch.C - ../dataflowAPI/rose/util/StringUtility.C - ../dataflowAPI/rose/util/Attribute.C - ../dataflowAPI/rose/util/Combinatorics.C - ../dataflowAPI/rose/util/LinearCongruentialGenerator.C - ../dataflowAPI/rose/semantics/BaseSemantics2.C - ../dataflowAPI/rose/semantics/DispatcherARM64.C - ../dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C - ../dataflowAPI/rose/semantics/DispatcherPowerpc.C - ../dataflowAPI/rose/semantics/RegisterParts.C - ../dataflowAPI/rose/semantics/Registers.C - ../dataflowAPI/rose/semantics/BinarySymbolicExpr.C - ../dataflowAPI/rose/semantics/RegisterStateGeneric.C - ../dataflowAPI/rose/semantics/SymEvalSemantics.C -) + ../dataflowAPI/src/ABI.C + ../dataflowAPI/src/Absloc.C + ../dataflowAPI/src/AbslocInterface.C + ../dataflowAPI/src/convertOpcodes.C + ../dataflowAPI/src/debug_dataflow.C + ../dataflowAPI/src/ExpressionConversionVisitor.C + ../dataflowAPI/src/InstructionCache.C + ../dataflowAPI/src/liveness.C + ../dataflowAPI/src/RegisterMap.C + ../dataflowAPI/src/RoseImpl.C + ../dataflowAPI/src/RoseInsnFactory.C + ../dataflowAPI/src/slicing.C + ../dataflowAPI/src/stackanalysis.C + ../dataflowAPI/src/SymbolicExpansion.C + ../dataflowAPI/src/SymEval.C + ../dataflowAPI/src/SymEvalPolicy.C + ../dataflowAPI/src/templates.C + ../dataflowAPI/src/Visitors.C + ../dataflowAPI/rose/ExtentMap.C + ../dataflowAPI/rose/rangemap.C + ../dataflowAPI/rose/util/Assert.C + ../dataflowAPI/rose/util/Message.C + ../dataflowAPI/rose/util/Sawyer.C + ../dataflowAPI/rose/util/Synchronization.C + ../dataflowAPI/rose/util/rose_getline.C + ../dataflowAPI/rose/util/SmallObject.C + ../dataflowAPI/rose/util/Stopwatch.C + ../dataflowAPI/rose/util/StringUtility.C + ../dataflowAPI/rose/util/Attribute.C + ../dataflowAPI/rose/util/Combinatorics.C + ../dataflowAPI/rose/util/LinearCongruentialGenerator.C + ../dataflowAPI/rose/semantics/BaseSemantics2.C + ../dataflowAPI/rose/semantics/DispatcherARM64.C + ../dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C + ../dataflowAPI/rose/semantics/DispatcherPowerpc.C + ../dataflowAPI/rose/semantics/RegisterParts.C + ../dataflowAPI/rose/semantics/Registers.C + ../dataflowAPI/rose/semantics/BinarySymbolicExpr.C + ../dataflowAPI/rose/semantics/RegisterStateGeneric.C + ../dataflowAPI/rose/semantics/SymEvalSemantics.C) # FIXME: Rose needs a bunch of warning cleanup -SET_SOURCE_FILES_PROPERTIES(${ROSE_SRC} PROPERTIES LANGUAGE CXX COMPILE_FLAGS -w) -set (SRC_LIST ${SRC_LIST} - ${ROSE_SRC} -) +set_source_files_properties(${ROSE_SRC} PROPERTIES LANGUAGE CXX COMPILE_FLAGS -w) +set(SRC_LIST ${SRC_LIST} ${ROSE_SRC}) -if (LIGHTWEIGHT_SYMTAB) -set (SRC_LIST ${SRC_LIST} - src/SymLiteCodeSource.C -) +if(LIGHTWEIGHT_SYMTAB) + set(SRC_LIST ${SRC_LIST} src/SymLiteCodeSource.C) else() -set (SRC_LIST ${SRC_LIST} - src/SymtabCodeSource.C -) + set(SRC_LIST ${SRC_LIST} src/SymtabCodeSource.C) endif() -if (ENABLE_PARSE_API_GRAPHS) -set (SRC_LIST ${SRC_LIST} - src/GraphAdapter.C - ) +if(ENABLE_PARSE_API_GRAPHS) + set(SRC_LIST ${SRC_LIST} src/GraphAdapter.C) endif() - -ADD_DEFINITIONS(-DPARSER_LIB) -ADD_DEFINITIONS(-DDATAFLOW_LIB) +add_definitions(-DPARSER_LIB) +add_definitions(-DDATAFLOW_LIB) if(WIN32) -ADD_DEFINITIONS(-DROSE_UTIL_EXPORTS) -ADD_DEFINITIONS(-DNOMINMAX) + add_definitions(-DROSE_UTIL_EXPORTS) + add_definitions(-DNOMINMAX) endif() dyninst_library(parseAPI common instructionAPI ${SYMREADER}) target_link_private_libraries(parseAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} tbbmalloc) -if (WIN32) -target_link_private_libraries(parseAPI shlwapi) +if(WIN32) + target_link_private_libraries(parseAPI shlwapi) endif() message(STATUS "Architecture is: ${CMAKE_LIBRARY_ARCHITECTURE}") -FILE (GLOB headers "h/*.h") -FILE (GLOB dataflowheaders "../dataflowAPI/h/*.h") -set_target_properties (parseAPI PROPERTIES PUBLIC_HEADER "${headers};${dataflowheaders}") +file(GLOB headers "h/*.h") +file(GLOB dataflowheaders "../dataflowAPI/h/*.h") +set_target_properties(parseAPI PROPERTIES PUBLIC_HEADER "${headers};${dataflowheaders}") -if (USE_OpenMP) -set_target_properties (parseAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) +if(USE_OpenMP) + set_target_properties(parseAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} + LINK_FLAGS ${OpenMP_CXX_FLAGS}) endif() if(${ENABLE_STATIC_LIBS}) - set_target_properties (parseAPI_static PROPERTIES PUBLIC_HEADER "${headers};${dataflowheaders}") + set_target_properties(parseAPI_static PROPERTIES PUBLIC_HEADER + "${headers};${dataflowheaders}") endif() -install (TARGETS parseAPI +install( + TARGETS parseAPI RUNTIME DESTINATION ${INSTALL_LIB_DIR} LIBRARY DESTINATION ${INSTALL_LIB_DIR} ARCHIVE DESTINATION ${INSTALL_LIB_DIR} diff --git a/parseThat/CMakeLists.txt b/parseThat/CMakeLists.txt index 96121b3b9b..bdbe14fd7d 100644 --- a/parseThat/CMakeLists.txt +++ b/parseThat/CMakeLists.txt @@ -1,9 +1,35 @@ -add_executable(parseThat src/parseThat.C src/config.C src/ipc.C src/record.C src/strlist.C src/reglist.C src/log.C src/utils.C src/sha1.C src/dyninstCore.C src/dyninstCompat.v5.C) +add_executable( + parseThat + src/parseThat.C + src/config.C + src/ipc.C + src/record.C + src/strlist.C + src/reglist.C + src/log.C + src/utils.C + src/sha1.C + src/dyninstCore.C + src/dyninstCompat.v5.C) add_definitions(-DHAVE_BPATCH_PROCESS_H) -if (USE_OpenMP) -set_target_properties (parseThat PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) +if(USE_OpenMP) + set_target_properties(parseThat PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} + LINK_FLAGS ${OpenMP_CXX_FLAGS}) endif() -target_link_private_libraries(parseThat dyninstAPI patchAPI parseAPI instructionAPI stackwalk symtabAPI common pcontrol dynDwarf dynElf ${Boost_LIBRARIES} ${ElfUtils_LIBRARIES}) +target_link_private_libraries( + parseThat + dyninstAPI + patchAPI + parseAPI + instructionAPI + stackwalk + symtabAPI + common + pcontrol + dynDwarf + dynElf + ${Boost_LIBRARIES} + ${ElfUtils_LIBRARIES}) install(TARGETS parseThat RUNTIME DESTINATION bin) diff --git a/patchAPI/CMakeLists.txt b/patchAPI/CMakeLists.txt index 237e870f06..3ba62c7bc0 100644 --- a/patchAPI/CMakeLists.txt +++ b/patchAPI/CMakeLists.txt @@ -1,31 +1,28 @@ # CMake configuration for patchAPI directory -include_directories ( - ${PROJECT_SOURCE_DIR}/patchAPI/src - ) +include_directories(${PROJECT_SOURCE_DIR}/patchAPI/src) -set (SRC_LIST - src/AddrSpace.C - src/Instrumenter.C - src/PatchObject.C - src/PatchBlock.C - src/PatchEdge.C - src/PatchFunction.C - src/PatchMgr.C - src/Point.C - src/CFGMaker.C - src/PointMaker.C - src/Command.C - src/PatchCallback.C - src/ParseCallback.C - src/PatchModifier.C - src/PatchLoop.C - src/PatchLoopTreeNode.C - ) +set(SRC_LIST + src/AddrSpace.C + src/Instrumenter.C + src/PatchObject.C + src/PatchBlock.C + src/PatchEdge.C + src/PatchFunction.C + src/PatchMgr.C + src/Point.C + src/CFGMaker.C + src/PointMaker.C + src/Command.C + src/PatchCallback.C + src/ParseCallback.C + src/PatchModifier.C + src/PatchLoop.C + src/PatchLoopTreeNode.C) -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -ADD_DEFINITIONS(-DPATCHAPI_LIB) +add_definitions(-DPATCHAPI_LIB) dyninst_library(patchAPI common instructionAPI parseAPI) target_link_private_libraries(patchAPI ${Boost_LIBRARIES}) diff --git a/proccontrol/CMakeLists.txt b/proccontrol/CMakeLists.txt index d0b6ed3e04..c39cb3514f 100644 --- a/proccontrol/CMakeLists.txt +++ b/proccontrol/CMakeLists.txt @@ -1,86 +1,77 @@ # CMake configuration for proccontrol directory -include_directories ( - src - h - ) +include_directories(src h) -set (SRC_LIST - src/event.C - src/generator.C - src/handler.C - src/mailbox.C - src/process.C - src/pcerrors.C - src/procpool.C - src/irpc.C - src/response.C - src/resp.C - src/memcache.C - src/procset.C - src/processplat.C - src/loadLibrary/injector.C - src/loadLibrary/codegen.C - src/loadLibrary/codegen-x86.C - src/loadLibrary/codegen-ppc.C - src/loadLibrary/codegen-aarch64.C - src/x86_process.C - src/ppc_process.C - src/arm_process.C - src/pcmachsyscall.C - ) +set(SRC_LIST + src/event.C + src/generator.C + src/handler.C + src/mailbox.C + src/process.C + src/pcerrors.C + src/procpool.C + src/irpc.C + src/response.C + src/resp.C + src/memcache.C + src/procset.C + src/processplat.C + src/loadLibrary/injector.C + src/loadLibrary/codegen.C + src/loadLibrary/codegen-x86.C + src/loadLibrary/codegen-ppc.C + src/loadLibrary/codegen-aarch64.C + src/x86_process.C + src/ppc_process.C + src/arm_process.C + src/pcmachsyscall.C) if(UNIX) -set (SRC_LIST ${SRC_LIST} - src/sysv.C - src/int_thread_db.C - src/mmapalloc.C -) + set(SRC_LIST ${SRC_LIST} src/sysv.C src/int_thread_db.C src/mmapalloc.C) elseif(WIN32) -set (SRC_LIST ${SRC_LIST} - src/GeneratorWindows.C - src/DecoderWindows.C - src/windows_handler.C - src/windows_process.C - src/windows_thread.C - src/loadLibrary/codegen-win.C - ../common/src/dthread-win.C - ../common/src/dthread.C -) + set(SRC_LIST + ${SRC_LIST} + src/GeneratorWindows.C + src/DecoderWindows.C + src/windows_handler.C + src/windows_process.C + src/windows_thread.C + src/loadLibrary/codegen-win.C + ../common/src/dthread-win.C + ../common/src/dthread.C) endif() -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-freebsd.C - ) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-linux.C - ) +if(PLATFORM MATCHES freebsd) + set(SRC_LIST + ${SRC_LIST} + src/freebsd.C + src/unix.C + src/notify_pipe.C + ../common/src/dthread-unix.C + ../common/src/dthread.C + src/loadLibrary/codegen-freebsd.C) +elseif(PLATFORM MATCHES linux) + set(SRC_LIST + ${SRC_LIST} + src/linux.C + src/unix.C + src/notify_pipe.C + ../common/src/dthread-unix.C + ../common/src/dthread.C + src/loadLibrary/codegen-linux.C) endif() -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -ADD_DEFINITIONS(-DPROCCONTROL_EXPORTS) +add_definitions(-DPROCCONTROL_EXPORTS) -set (DEPS common ${SYMREADER}) +set(DEPS common ${SYMREADER}) dyninst_library(pcontrol ${DEPS}) target_link_private_libraries(pcontrol ${CMAKE_DL_LIBS}) target_link_private_libraries(pcontrol ${Boost_LIBRARIES}) -if (UNIX) -# Boost auto-links on Windows; don't double-link -target_link_private_libraries(pcontrol pthread) +if(UNIX) + # Boost auto-links on Windows; don't double-link + target_link_private_libraries(pcontrol pthread) endif() - diff --git a/stackwalk/CMakeLists.txt b/stackwalk/CMakeLists.txt index 106717e693..c9374818f2 100644 --- a/stackwalk/CMakeLists.txt +++ b/stackwalk/CMakeLists.txt @@ -1,103 +1,72 @@ # CMake configuration for proccontrol directory -include_directories ( - ${PROJECT_SOURCE_DIR}/proccontrol/h - ${PROJECT_SOURCE_DIR}/elf/h - ${PROJECT_SOURCE_DIR}/dwarf/h - src - h - ) +include_directories(${PROJECT_SOURCE_DIR}/proccontrol/h ${PROJECT_SOURCE_DIR}/elf/h + ${PROJECT_SOURCE_DIR}/dwarf/h src h) -set (SRC_LIST - src/frame.C - src/framestepper.C - src/swk_errors.C - src/symlookup.C - src/walker.C - src/procstate.C - src/steppergroup.C - src/libstate.C - src/sw_pcontrol.C -) +set(SRC_LIST + src/frame.C + src/framestepper.C + src/swk_errors.C + src/symlookup.C + src/walker.C + src/procstate.C + src/steppergroup.C + src/libstate.C + src/sw_pcontrol.C) -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd-swk.C - src/x86-swk.C - src/symtab-swk.C - src/dbginfo-stepper.C - src/x86-wanderer.C - src/linuxbsd-swk.C - src/linuxbsd-x86-swk.C - src/freebsd-x86-swk.C -) -elseif (PLATFORM MATCHES linux OR PLATFORM MATCHES freebsd) - set (SRC_LIST ${SRC_LIST} - src/symtab-swk.C - src/linuxbsd-swk.C - src/linux-swk.C - ) - if (PLATFORM MATCHES ppc) - set (SRC_LIST ${SRC_LIST} - src/linux-ppc-swk.C - src/ppc-swk.C - ) +if(PLATFORM MATCHES freebsd) + set(SRC_LIST + ${SRC_LIST} + src/freebsd-swk.C + src/x86-swk.C + src/symtab-swk.C + src/dbginfo-stepper.C + src/x86-wanderer.C + src/linuxbsd-swk.C + src/linuxbsd-x86-swk.C + src/freebsd-x86-swk.C) +elseif(PLATFORM MATCHES linux OR PLATFORM MATCHES freebsd) + set(SRC_LIST ${SRC_LIST} src/symtab-swk.C src/linuxbsd-swk.C src/linux-swk.C) + if(PLATFORM MATCHES ppc) + set(SRC_LIST ${SRC_LIST} src/linux-ppc-swk.C src/ppc-swk.C) - elseif (PLATFORM MATCHES aarch64) - set (SRC_LIST ${SRC_LIST} - src/linux-aarch64-swk.C - src/aarch64-swk.C - src/dbginfo-stepper.C - ) + elseif(PLATFORM MATCHES aarch64) + set(SRC_LIST ${SRC_LIST} src/linux-aarch64-swk.C src/aarch64-swk.C + src/dbginfo-stepper.C) - elseif (PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) - set (SRC_LIST ${SRC_LIST} - src/dbginfo-stepper.C - src/linux-x86-swk.C - src/x86-wanderer.C - src/linuxbsd-x86-swk.C - src/x86-swk.C - ) + elseif(PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) + set(SRC_LIST ${SRC_LIST} src/dbginfo-stepper.C src/linux-x86-swk.C + src/x86-wanderer.C src/linuxbsd-x86-swk.C src/x86-swk.C) endif() endif() -if (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - set (SRC_LIST ${SRC_LIST} - src/x86-wanderer.C - src/x86-swk.C - src/win-x86-swk.C - src/symtab-swk.C - ) +if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) + set(SRC_LIST ${SRC_LIST} src/x86-wanderer.C src/x86-swk.C src/win-x86-swk.C + src/symtab-swk.C) endif() -if (SW_ANALYSIS_STEPPER) - set (SRC_LIST ${SRC_LIST} - src/analysis_stepper.C - src/callchecker-IAPI.C - ) -else () - set (SRC_LIST ${SRC_LIST} - src/callchecker.C - ) +if(SW_ANALYSIS_STEPPER) + set(SRC_LIST ${SRC_LIST} src/analysis_stepper.C src/callchecker-IAPI.C) +else() + set(SRC_LIST ${SRC_LIST} src/callchecker.C) endif() -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -ADD_DEFINITIONS(-DSTACKWALKER_EXPORTS) +add_definitions(-DSTACKWALKER_EXPORTS) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${FORCE_FRAME_POINTER}") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${FORCE_FRAME_POINTER}") set(DEPS common instructionAPI pcontrol) -if (UNIX) -set (DEPS ${DEPS} dynDwarf dynElf) +if(UNIX) + set(DEPS ${DEPS} dynDwarf dynElf) endif() -set (DEPS ${DEPS} ${SYMREADER}) +set(DEPS ${DEPS} ${SYMREADER}) -if (SW_ANALYSIS_STEPPER) -set (DEPS ${DEPS} parseAPI) +if(SW_ANALYSIS_STEPPER) + set(DEPS ${DEPS} parseAPI) endif() - dyninst_library(stackwalk ${DEPS}) target_link_private_libraries(stackwalk ${Boost_LIBRARIES}) diff --git a/symlite/CMakeLists.txt b/symlite/CMakeLists.txt index 343ae92f86..7bac328fed 100644 --- a/symlite/CMakeLists.txt +++ b/symlite/CMakeLists.txt @@ -1,31 +1,22 @@ # CMake configuration for symlite directory -if (NOT UNIX) - return() +if(NOT UNIX) + return() endif() -include_directories ( - src - ${PROJECT_SOURCE_DIR}/elf/h - ) +include_directories(src ${PROJECT_SOURCE_DIR}/elf/h) -set (SRC_LIST - src/SymLite-elf.C - ) +set(SRC_LIST src/SymLite-elf.C) add_definitions(-DSYMLITE_LIB) -#add_library (symLite ${SRC_LIST}) -#add_library (symLite_static STATIC ${SRC_LIST}) -#FILE (GLOB headers "h/*.h") -#set_target_properties (symLite symLite_static PROPERTIES PUBLIC_HEADER "${headers}") +# add_library (symLite ${SRC_LIST}) add_library (symLite_static STATIC ${SRC_LIST}) FILE +# (GLOB headers "h/*.h") set_target_properties (symLite symLite_static PROPERTIES +# PUBLIC_HEADER "${headers}") -#target_link_private_libraries (symLite common) -#target_link_private_libraries (symLite dynElf) +# target_link_private_libraries (symLite common) target_link_private_libraries (symLite +# dynElf) -#INSTALL (TARGETS symLite symLite_static -# EXPORT DyninstTargets -# RUNTIME DESTINATION ${INSTALL_LIB_DIR} -# LIBRARY DESTINATION ${INSTALL_LIB_DIR} -# ARCHIVE DESTINATION ${INSTALL_LIB_DIR} -# PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) +# INSTALL (TARGETS symLite symLite_static EXPORT DyninstTargets RUNTIME DESTINATION +# ${INSTALL_LIB_DIR} LIBRARY DESTINATION ${INSTALL_LIB_DIR} ARCHIVE DESTINATION +# ${INSTALL_LIB_DIR} PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) dyninst_library(symLite common dynElf) diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 4ca6896f83..bdfdf49359 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -1,113 +1,83 @@ # CMake configuration for symtabAPI directory -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/dwarf/h - ${PROJECT_SOURCE_DIR}/elf/h - ) +include_directories(src h ${PROJECT_SOURCE_DIR}/dwarf/h ${PROJECT_SOURCE_DIR}/elf/h) if(NOT WIN32) - include_directories(${PROJECT_SOURCE_DIR}/common/src) + include_directories(${PROJECT_SOURCE_DIR}/common/src) endif() - - -set (SRC_LIST - src/Object.C - src/Aggregate.C - src/Function.C - src/Variable.C - src/Symbol.C - src/LineInformation.C - src/Symtab.C - src/Symtab-edit.C - src/Symtab-lookup.C - src/Module.C - src/Region.C - src/Collections.C - src/Type.C - src/AddrLookup.C - src/annotations.C - src/debug.C - src/SymtabReader.C - ) - -if (PLATFORM MATCHES freebsd OR - PLATFORM MATCHES linux) - -set (SRC_LIST ${SRC_LIST} - src/Object-elf.C - src/Archive.C - src/Archive-elf.C - src/parseDwarf.C +set(SRC_LIST + src/Object.C + src/Aggregate.C + src/Function.C + src/Variable.C + src/Symbol.C + src/LineInformation.C + src/Symtab.C + src/Symtab-edit.C + src/Symtab-lookup.C + src/Module.C + src/Region.C + src/Collections.C + src/Type.C + src/AddrLookup.C + src/annotations.C + src/debug.C + src/SymtabReader.C) + +if(PLATFORM MATCHES freebsd OR PLATFORM MATCHES linux) + + set(SRC_LIST + ${SRC_LIST} + src/Object-elf.C + src/Archive.C + src/Archive-elf.C + src/parseDwarf.C src/LinkMap.C src/emitElf.C - src/emitElfStatic.C - src/dwarfWalker.C -) - -if (PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-x86.C - src/relocationEntry-elf-x86.C - ) -elseif (PLATFORM MATCHES i386) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-x86.C - src/relocationEntry-elf-x86.C - ) -elseif (PLATFORM MATCHES ppc64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-ppc64.C - src/relocationEntry-elf-ppc64.C - ) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-aarch64.C - src/relocationEntry-elf-aarch64.C - ) -else (TRUE) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-stub.C - src/relocationEntry-stub.C - ) -endif() + src/emitElfStatic.C + src/dwarfWalker.C) + + if(PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) + set(SRC_LIST ${SRC_LIST} src/emitElfStatic-x86.C src/relocationEntry-elf-x86.C) + elseif(PLATFORM MATCHES i386) + set(SRC_LIST ${SRC_LIST} src/emitElfStatic-x86.C src/relocationEntry-elf-x86.C) + elseif(PLATFORM MATCHES ppc64) + set(SRC_LIST ${SRC_LIST} src/emitElfStatic-ppc64.C + src/relocationEntry-elf-ppc64.C) + elseif(PLATFORM MATCHES aarch64) + set(SRC_LIST ${SRC_LIST} src/emitElfStatic-aarch64.C + src/relocationEntry-elf-aarch64.C) + else(TRUE) + set(SRC_LIST ${SRC_LIST} src/emitElfStatic-stub.C src/relocationEntry-stub.C) + endif() endif() - -if (PLATFORM MATCHES nt) -set (SRC_LIST ${SRC_LIST} - src/Object-nt.C - src/emitWin.C - src/relocationEntry-stub.C -) +if(PLATFORM MATCHES nt) + set(SRC_LIST ${SRC_LIST} src/Object-nt.C src/emitWin.C src/relocationEntry-stub.C) endif() -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -ADD_DEFINITIONS(-DSYMTAB_LIB) +add_definitions(-DSYMTAB_LIB) -set (DEPS common) +set(DEPS common) if(UNIX) - list (APPEND DEPS - dynElf - dynDwarf - ${ElfUtils_LIBRARIES} - ) + list(APPEND DEPS dynElf dynDwarf ${ElfUtils_LIBRARIES}) else() - list (APPEND DEPS dbghelp) + list(APPEND DEPS dbghelp) endif() dyninst_library(symtabAPI ${DEPS}) if(TARGET ElfUtils) - add_dependencies(symtabAPI ElfUtils) + add_dependencies(symtabAPI ElfUtils) endif() target_link_private_libraries(symtabAPI ${Boost_LIBRARIES}) if(USE_OpenMP) - set_target_properties(symtabAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) + set_target_properties(symtabAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} + LINK_FLAGS ${OpenMP_CXX_FLAGS}) endif() From 231dd173f44912e318a4a3e294b2fc7aaa83ecad Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 6 May 2022 15:52:11 -0500 Subject: [PATCH 120/505] Remove endian CMake check (#1270) The usage of the macros was removed by d233ae759 in 2020. --- cmake/endian.cmake | 8 -------- cmake/shared.cmake | 1 - 2 files changed, 9 deletions(-) delete mode 100644 cmake/endian.cmake diff --git a/cmake/endian.cmake b/cmake/endian.cmake deleted file mode 100644 index b24c512dee..0000000000 --- a/cmake/endian.cmake +++ /dev/null @@ -1,8 +0,0 @@ -include(TestBigEndian) - -test_big_endian(BIGENDIAN) -if(${BIGENDIAN}) - add_definitions(-DDYNINST_BIG_ENDIAN) -else() - add_definitions(-DDYNINST_LITTLE_ENDIAN) -endif(${BIGENDIAN}) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 5c9a39355a..6d27929bbc 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -106,7 +106,6 @@ include(${DYNINST_ROOT}/cmake/visibility.cmake) include(${DYNINST_ROOT}/cmake/warnings.cmake) include(${DYNINST_ROOT}/cmake/options.cmake) include(${DYNINST_ROOT}/cmake/optimization.cmake) -include(${DYNINST_ROOT}/cmake/endian.cmake) set(BUILD_SHARED_LIBS ON) From 5e601431484bba3623697c37078ba794998c404c Mon Sep 17 00:00:00 2001 From: "Jonathan R. Madsen" Date: Wed, 11 May 2022 13:23:34 -0500 Subject: [PATCH 121/505] Docker: make build.sh verbose, fix file copy bug in Dockerfile.test (#1273) - remove old code before copying code into testing container - build with verbosity in build.sh (this helps when build errors occur) --- docker/Dockerfile.test | 3 +++ docker/build.sh | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/docker/Dockerfile.test b/docker/Dockerfile.test index 3ebb608b0c..f08a5bbde9 100644 --- a/docker/Dockerfile.test +++ b/docker/Dockerfile.test @@ -3,6 +3,9 @@ FROM ${dyninst_base} # docker build --build-arg dyninst_base=ghcr.io/dyninst/dyninst-ubuntu-20.04:latest -f Dockerfile.test -t dyninst-test ../ +# Remove old code +RUN rm -rf /code + # Add updated Dyninst code COPY . /code diff --git a/docker/build.sh b/docker/build.sh index 804aa60215..435d2b0061 100644 --- a/docker/build.sh +++ b/docker/build.sh @@ -17,7 +17,7 @@ mkdir -p $DYNINST_INSTALL_DIR CMAKE_WERROR_FLAGS='-DCMAKE_C_FLAGS="-Werror" -DCMAKE_CXX_FLAGS="-Werror"' cmake -S /code -B $DYNINST_BUILD_DIR -DCMAKE_INSTALL_PREFIX=$DYNINST_INSTALL_DIR $CMAKE_WERROR_FLAGS -cmake --build $DYNINST_BUILD_DIR -- -j2 +cmake --build $DYNINST_BUILD_DIR --target all --parallel 2 -- VERBOSE=1 cmake --install $DYNINST_BUILD_DIR echo "::endgroup::" From 35c289a2d38bd5b3c20c07cbe1c1f3c31ccc34a1 Mon Sep 17 00:00:00 2001 From: John Mellor-Crummey Date: Mon, 11 Jul 2022 19:07:00 -0500 Subject: [PATCH 122/505] fix races with parallel analysis of cubins (#1284) --- symtabAPI/src/LineInformation.C | 11 +++++++++-- symtabAPI/src/Object-elf.C | 12 +++++++++--- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/symtabAPI/src/LineInformation.C b/symtabAPI/src/LineInformation.C index 56c3ad6169..2f44a357c6 100644 --- a/symtabAPI/src/LineInformation.C +++ b/symtabAPI/src/LineInformation.C @@ -60,8 +60,12 @@ bool LineInformation::addLine( unsigned int lineSource, lowInclusiveAddr, highExclusiveAddr); Statement::Ptr insert_me(the_stmt); insert_me->setStrings_(strings_); - return insert( insert_me).second; - + bool result; +#pragma omp critical (addLine) +{ + result = insert( insert_me).second; +} + return result; } /* end setLineToAddressRangeMapping() */ bool LineInformation::addLine( std::string lineSource, unsigned int lineNo, @@ -78,8 +82,11 @@ void LineInformation::addLineInfo(LineInformation *lineInfo) { if(!lineInfo) return; +#pragma omp critical (addLine) +{ insert(lineInfo->begin(), lineInfo->end()); } +} bool LineInformation::addAddressRange( Offset lowInclusiveAddr, Offset highExclusiveAddr, diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index d70477d7d5..896095f9cf 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3646,9 +3646,15 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) int status; - while ((status = dwarf_next_lines(dbg, off = next_off, &next_off, &cu, - &files, &fileCount, &lineBuffer, &lineCount)) == 0) - { + while (1) { + +#pragma omp critical (next_lines) +{ + status = dwarf_next_lines(dbg, off = next_off, &next_off, &cu, + &files, &fileCount, &lineBuffer, &lineCount); +} + if (status != 0) break; + boost::unique_lock l(strings->lock); size_t offset = strings->size(); From 3dd22166bc74eae637ceec1bc9846dc008259dc3 Mon Sep 17 00:00:00 2001 From: "James A. Kupsch" Date: Sun, 10 Jul 2022 23:37:37 -0500 Subject: [PATCH 123/505] Add exec entry point to parse hints is missing Always include an an executable's entry point as a parsing hint, otherwise for stripped binaries no functions are parsed. --- parseAPI/src/SymtabCodeSource.C | 42 +++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/parseAPI/src/SymtabCodeSource.C b/parseAPI/src/SymtabCodeSource.C index 6d098cfdbe..f44b8835ef 100644 --- a/parseAPI/src/SymtabCodeSource.C +++ b/parseAPI/src/SymtabCodeSource.C @@ -29,6 +29,7 @@ */ #include #include +#include #include @@ -482,6 +483,9 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) parsing_printf("[%s:%d] processing %lu symtab hints\n",FILE__,__LINE__, fsyms.size()); + atomic_bool foundEntrySymbol{}; + Address entryOffset = _symtab->getEntryOffset(); + #pragma omp parallel for schedule(auto) for (unsigned int i = 0; i < fsyms.size(); i++) { SymtabAPI::Function *f = fsyms[i]; @@ -542,6 +546,10 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) sr->getMemOffset(), sr->getMemOffset()+sr->getDiskSize()); } else { + if (entryOffset == offset) { + foundEntrySymbol = true; + } + _hints.push_back(Hint(f->getOffset(), f->getSymbolSize(), cr, fname_s)); parsing_printf("\t<%lx,%s,[%lx,%lx)>\n", f->getOffset(), @@ -550,6 +558,40 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) cr->offset()+cr->length()); } } + + if (!foundEntrySymbol && _symtab->isExecutable()) { + // add entry point as this object is an executable + // and no symbol referenced the entry point + parsing_printf("Adding exectable entry point at %lx\n", entryOffset); + SymtabAPI::Region *sr = _symtab->findEnclosingRegion(entryOffset); + if (sr) { + CodeRegion *cr = NULL; + { + RegionMap::const_accessor a; + bool found = rmap.find(a, sr); + if (found) { + cr = a->second; + } + } + + if (cr) { + const char startFuncName[] = "_start"; + // use 0 for function length as length is unknown and value unused + _hints.push_back(Hint(entryOffset, 0, cr, startFuncName)); + parsing_printf("\t<%lx,%s,[%lx,%lx)>\n", + entryOffset, + startFuncName, + cr->offset(), + cr->offset() + cr->length()); + } else { + parsing_printf("[%s:%d] unrecognized Region %lx entry point function %lx\n", + FILE__, __LINE__, sr->getMemOffset(), entryOffset); + } + } else { + parsing_printf("[%s:%d] Symtab Region for entry point function %lx not found\n", + FILE__, __LINE__, entryOffset); + } + } } void From 02c20e9169a9e6ca9da7a486df4e9160143063cb Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 28 Jul 2022 16:18:46 -0500 Subject: [PATCH 124/505] Updates for v12.2.0 release (#1289) * Update CHANGELOG * Update SO version * Update docs --- CHANGELOG.md | 42 ++++++++++++++++++++++++++ cmake/shared.cmake | 2 +- common/doc/manual_frontpage.tex | 4 +-- dataflowAPI/doc/dataflowAPI.pdf | Bin 349841 -> 349833 bytes dynC_API/doc/dynC_API.pdf | Bin 298532 -> 298530 bytes dyninstAPI/doc/dyninstAPI.docx | Bin 151289 -> 151289 bytes dyninstAPI/doc/dyninstAPI.pdf | Bin 422213 -> 422302 bytes instructionAPI/doc/instructionAPI.pdf | Bin 563447 -> 563449 bytes parseAPI/doc/parseAPI.pdf | Bin 404163 -> 404155 bytes patchAPI/doc/patchAPI.pdf | Bin 614110 -> 614205 bytes proccontrol/doc/proccontrol.docx | Bin 107962 -> 108244 bytes proccontrol/doc/proccontrol.pdf | Bin 370176 -> 370687 bytes stackwalk/doc/stackwalk.pdf | Bin 318611 -> 318608 bytes symtabAPI/doc/symtabAPI.pdf | Bin 457106 -> 457099 bytes 14 files changed, 45 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 53a9fc29b5..ecc33820c9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,47 @@ # Change Log +## [12.2.0](https://github.com/dyninst/dyninst/tree/v12.2.0) (2022-07-28) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.1.0...v12.2.0) + +- Add exec entry point to parse hints is missing +- fix races with parallel analysis of cubins ([1284](https://github.com/dyninst/dyninst/issues/1284)) +- Docker: make build.sh verbose, fix file copy bug in Dockerfile.test ([1273](https://github.com/dyninst/dyninst/issues/1273)) +- Remove endian CMake check ([1270](https://github.com/dyninst/dyninst/issues/1270)) +- Update and enforce formatting of CMake files ([1267](https://github.com/dyninst/dyninst/issues/1267)) +- Fix bug in processing library paths in FindLibIberty.cmake ([1266](https://github.com/dyninst/dyninst/issues/1266)) +- Fix decoding of DWARF expressions into machine registers for Intel GPUs ([1262](https://github.com/dyninst/dyninst/issues/1262)) +- Docker: don't use autamus cache ([1259](https://github.com/dyninst/dyninst/issues/1259)) +- Remove unused build options ([1253](https://github.com/dyninst/dyninst/issues/1253)) +- Fix dyninstAPI_RT files to build with older glibc ([1252](https://github.com/dyninst/dyninst/issues/1252)) +- Redo finalization to get correct function boundiaries when ([1249](https://github.com/dyninst/dyninst/issues/1249)) +- Fix format string errors in stackwalk/callchecker.C ([1250](https://github.com/dyninst/dyninst/issues/1250)) +- Make dyninstAPI_RT files build with standard C ([1246](https://github.com/dyninst/dyninst/issues/1246)) +- Add cmake options for C/C++ language standards ([1246](https://github.com/dyninst/dyninst/issues/1246)) +- Use bfd linker for LTO ([1248](https://github.com/dyninst/dyninst/issues/1248)) +- Cleanup (remove) ancient linux kernel support ([1241](https://github.com/dyninst/dyninst/issues/1241)) +- remove unused files containing pragmas ([1240](https://github.com/dyninst/dyninst/issues/1240)) +- Remove unneeded #pragma's ([1240](https://github.com/dyninst/dyninst/issues/1240)) +- Add compiler warning related cmake options ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Add cmake option to disable diagnostic suppressions ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Fix frame-larger-than warning ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Remove MSC compiler warning suppressions ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Improve compiler diagnostic suppression handling ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Remove unused git files ([1244](https://github.com/dyninst/dyninst/issues/1244)) +- Docker: make compile warnings fatal ([1242](https://github.com/dyninst/dyninst/issues/1242)) +- Docker: use external-tests instead of testsuite in base image ([1209](https://github.com/dyninst/dyninst/issues/1209)) +- Docker: don't build Dyninst through spack for the environment ([1222](https://github.com/dyninst/dyninst/issues/1222)) +- Docker: use more OS packages for dependencies ([1221](https://github.com/dyninst/dyninst/issues/1221)) +- Remove void pointer arithmetic when using Valgrind annotations ([1236](https://github.com/dyninst/dyninst/issues/1236)) +- Add parsing of names for inlined functions in DWARF ([1237](https://github.com/dyninst/dyninst/issues/1237)) +- Remove BUILD_RT option ([1238](https://github.com/dyninst/dyninst/issues/1238)) +- Fix warnings with cmake's MINSIZEREL build type ([1235](https://github.com/dyninst/dyninst/issues/1235)) +- Correctly propagate pc ranges for blocks and local variables ([1226](https://github.com/dyninst/dyninst/issues/1226)) +- Docker: testing workflow to run libabigail ([1220](https://github.com/dyninst/dyninst/issues/1220)) +- Remove usage of DW_AT_MIPS_linkage_name ([1223](https://github.com/dyninst/dyninst/issues/1223)) +- Docker: adding a workflow for release ([1219](https://github.com/dyninst/dyninst/issues/1219)) +- Merge pull request #1217 from dyninst/thaines/docker_base_container_defaults +- Update dependency versions in base container config + ## [12.1.0](https://github.com/dyninst/dyninst/tree/v12.1.0) (2022-03-09) [Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.1...v12.1.0) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 6d27929bbc..fe9de4db5b 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,5 +1,5 @@ set(DYNINST_MAJOR_VERSION 12) -set(DYNINST_MINOR_VERSION 1) +set(DYNINST_MINOR_VERSION 2) set(DYNINST_PATCH_VERSION 0) set(SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") diff --git a/common/doc/manual_frontpage.tex b/common/doc/manual_frontpage.tex index 9690a3de53..160610633d 100644 --- a/common/doc/manual_frontpage.tex +++ b/common/doc/manual_frontpage.tex @@ -42,9 +42,9 @@ % }; \node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$) - {\fontsize{24}{32}\selectfont 12.1 Release}; + {\fontsize{24}{32}\selectfont 12.2 Release}; \node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$) - {\fontsize{24}{32}\selectfont March 2022}; + {\fontsize{24}{32}\selectfont July 2022}; % Contact information % \matrix (UWaddress) [% diff --git a/dataflowAPI/doc/dataflowAPI.pdf b/dataflowAPI/doc/dataflowAPI.pdf index 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90f6098f47d5582fa483ea2d2d1ad923d612de87 Mon Sep 17 00:00:00 2001 From: "Weixiao.zhan" <45820168+weixiao-zhan@users.noreply.github.com> Date: Wed, 17 Aug 2022 11:53:56 -0500 Subject: [PATCH 125/505] Docker - use ppa for gcc11 (#1291) --- docker/Dockerfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 63a6c50e57..8f88f1df9a 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -64,7 +64,7 @@ RUN python3 -m pip install --upgrade pip && \ # Update gcc to 11.1.1 (otherwise we'd have 9.3.0) RUN apt-get install -y software-properties-common && \ - add-apt-repository 'deb http://mirrors.kernel.org/ubuntu hirsute main universe' && \ + add-apt-repository -y ppa:ubuntu-toolchain-r/test && \ apt-get update && \ apt-get install -y gcc-11 g++-11 && \ update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-9 70 --slave /usr/bin/g++ g++ /usr/bin/g++-9 --slave /usr/bin/gcov gcov /usr/bin/gcov-9 --slave /usr/bin/gcc-ar gcc-ar /usr/bin/gcc-ar-9 --slave /usr/bin/gcc-ranlib gcc-ranlib /usr/bin/gcc-ranlib-9 && \ @@ -80,7 +80,7 @@ ENV PATH=/opt/spack/bin:$PATH RUN python3 -m pip install botocore boto3 # Find packages already installed on system, e.g. autoconf -RUN spack external find --not-buildable gcc@11.0.1 autoconf bzip2 git tar xz perl cmake m4 ncurses && \ +RUN spack external find --not-buildable gcc autoconf bzip2 git tar xz perl cmake m4 ncurses && \ spack config add 'packages:all:target:[x86_64]' # 'spack external find' doesn't work on libraries From 9d1a3d8655958749556fcd55225485a96d27562d Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 5 Oct 2022 09:28:50 -0500 Subject: [PATCH 126/505] fix location list PC range values (#1297) - in some instances the valid PC range for the variable was being offset twice by the base address of the shared object; the value returned by libdw already adds this offset and then dyninst adds it again in some instances --- symtabAPI/src/dwarfWalker.C | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 6459910a46..3f4dc9c7ff 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -2647,9 +2647,10 @@ bool DwarfWalker::decodeLocationListForStaticOffsetOrAddress( } } else { - dwarf_printf("(0x%lx) Using lexical range, shifted by module low\n", id()); - loc.lowPC = location->ld_lopc + base; - loc.hiPC = location->ld_hipc + base; + dwarf_printf("(0x%lx) Using lexical range\n", id()); + + loc.lowPC = location->ld_lopc; + loc.hiPC = location->ld_hipc; dwarf_printf("(0x%lx) valid over range 0x%lx to 0x%lx\n", id(), loc.lowPC, loc.hiPC); From ef13561a38a6b3c0ea8bcebab2572fc85e20ea96 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 5 Oct 2022 10:06:01 -0500 Subject: [PATCH 127/505] Fix public header deletes (#1301) * Undelete stackwalk/h/local_var.h This was incorrectly removed by d42b65910. * Undelete parseAPI/h/GraphAdapter.h This was incorrectly removed by d42b65910. It is still needed if ENABLE_PARSE_API_GRAPHS is set. --- parseAPI/h/GraphAdapter.h | 93 ++++++++++++ stackwalk/h/local_var.h | 289 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 parseAPI/h/GraphAdapter.h create mode 100644 stackwalk/h/local_var.h diff --git a/parseAPI/h/GraphAdapter.h b/parseAPI/h/GraphAdapter.h new file mode 100644 index 0000000000..384740f09f --- /dev/null +++ b/parseAPI/h/GraphAdapter.h @@ -0,0 +1,93 @@ + + +#include "CFG.h" +#include +#include + +using namespace Dyninst; +using namespace ParseAPI; +using namespace std; + +namespace boost +{ + template<> + struct graph_traits + { + // Boost graph typedefs + struct function_tags : public virtual boost::vertex_list_graph_tag, + public virtual boost::bidirectional_graph_tag + { + }; + + + typedef function_tags traversal_category; + typedef Function::blocklist::const_iterator vertex_iterator; + typedef size_t vertices_size_type; + typedef Block* vertex_descriptor; + typedef Edge* edge_descriptor; + typedef boost::directed_tag directed_category; + typedef boost::allow_parallel_edge_tag edge_parallel_category; + static vertex_descriptor null_vertex() + { + return NULL; + } + typedef Block::edgelist::const_iterator out_edge_iterator; + typedef Block::edgelist::const_iterator in_edge_iterator; + typedef void edge_iterator; + typedef void adjacency_iterator; + typedef size_t degree_size_type; + typedef size_t edges_size_type; + }; + template<> + struct vertex_property_type + { + typedef property type; + }; + + + + + std::pair::vertex_iterator, + boost::graph_traits::vertex_iterator> vertices(const Dyninst::ParseAPI::Function& g) + { + return std::make_pair(g.blocks().begin(), g.blocks().end()); + } +} + +boost::graph_traits::vertices_size_type num_vertices(const Function& g) +{ + return g.blocks().size(); +} +boost::graph_traits::vertex_descriptor source(boost::graph_traits::edge_descriptor e, const Function& g) +{ + return e->src(); +} +boost::graph_traits::vertex_descriptor target(boost::graph_traits::edge_descriptor e, const Function& g) +{ + return e->trg(); +} +std::pair::out_edge_iterator, boost::graph_traits::out_edge_iterator> + out_edges(boost::graph_traits::vertex_descriptor v, const Function& g) +{ + return std::make_pair(v->targets().begin(), v->targets().end()); +} +boost::graph_traits::degree_size_type out_degree(boost::graph_traits::vertex_descriptor v, const Function& g) +{ + return v->targets().size(); +} +std::pair::in_edge_iterator, boost::graph_traits::in_edge_iterator> + in_edges(boost::graph_traits::vertex_descriptor v, const Function& g) +{ + return std::make_pair(v->sources().begin(), v->sources().end()); +} +boost::graph_traits::degree_size_type in_degree(boost::graph_traits::vertex_descriptor v, const Function& g) +{ + return v->sources().size(); +} +boost::graph_traits::degree_size_type degree(boost::graph_traits::vertex_descriptor v, const Function& g) +{ + return in_degree(v,g)+out_degree(v,g); + +} +PARSER_EXPORT bool dominates(Function& f, Address a, Address b); +PARSER_EXPORT bool dominates(Function& f, Block* a, Block* b); diff --git a/stackwalk/h/local_var.h b/stackwalk/h/local_var.h new file mode 100644 index 0000000000..63e2692e3f --- /dev/null +++ b/stackwalk/h/local_var.h @@ -0,0 +1,289 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#if !defined (local_var_h_) +#define local_var_h_ + +#include +#include "Symbol.h" +#include "Symtab.h" +#include "Type.h" +#include "Function.h" + +#include "frame.h" +#include "procstate.h" +#include "walker.h" + +#include +#include + +using namespace Dyninst; +using namespace SymtabAPI; +using namespace Stackwalker; + +static Symtab *getSymtabForName(std::string name) +{ + static std::map symtabs; + std::map::iterator i; + + i = symtabs.find(name); + if (i != symtabs.end()) { + return i->second; + } + + Symtab *obj = NULL; + Symtab::openFile(obj, name); + symtabs[name] = obj; + return obj; +} + +class LVReader : public MemRegReader +{ + private: + ProcessState *proc; + int current_depth; + std::vector *swalk; + Dyninst::THR_ID thrd; + + bool isFrameRegister(MachRegister reg) + { + return reg.isFramePointer(); + } + + bool isStackRegister(MachRegister reg) + { + return reg.isStackPointer(); + } + public: + + LVReader(ProcessState *p, int f, std::vector *s, Dyninst::THR_ID t) : + proc(p), + current_depth(f), + swalk(s), + thrd(t) + { + } + + virtual bool ReadMem(Address addr, void *buffer, unsigned size) + { + return proc->readMem(buffer, addr, size); + } + + + virtual bool GetReg(MachRegister reg, MachRegisterVal &val) + { + Frame &f = (*swalk)[current_depth]; + if (isFrameRegister(reg)) { + val = static_cast(f.getFP()); + return true; + } + if (isStackRegister(reg)) { + val = static_cast(f.getSP()); + return true; + } + if (reg.isPC() || reg == Dyninst::ReturnAddr) { + val = static_cast(f.getRA()); + return true; + } + + if (!current_depth) { + return proc->getRegValue(reg, thrd, val); + } + + current_depth--; + Frame &g = (*swalk)[current_depth]; + Offset offset; + void *symtab_v; + std::string lib; + g.getLibOffset(lib, offset, symtab_v); + Symtab *symtab = getSymtabForName(lib); + if (!symtab) + return false; + + bool result = symtab->getRegValueAtFrame(offset, reg, val, this); + current_depth++; + return result; + } + + virtual bool start() { + return true; + } + virtual bool done() { + return true; + } + virtual ~LVReader() {} +}; + +/** + * Given a StackwalkerAPI frame, return the SymtabAPI function + * that created the frame. + **/ +static Dyninst::SymtabAPI::Function *getFunctionForFrame(Frame f) +{ + Offset offset; + void *symtab_v; + std::string lib_name; + bool result = f.getLibOffset(lib_name, offset, symtab_v); + if (!result) + return NULL; + Symtab *symtab = NULL; + if (symtab_v) { + symtab = (Symtab *) symtab_v; + } + else { + symtab = getSymtabForName(lib_name); + } + Function *func; + result = symtab->getContainingFunction(offset, func); + if (!result) + return NULL; + return func; +} + +/** + * Given a frame in a stackwalk, and a local variable, get the value + * of that local variable in the frame. + * + * 'localVar' is the variable that we're getting the value of. + * 'swalk' is a stackwalk from StackwalkerAPI + * 'frame' is an index into swalk and notes the frame that we'll be reading + * the variable from. localVar should be part of the frame defined by + * swalk[frame] + * 'out_buffer' is a buffer where we will write the value of the local variable. + * out_buffer_size should be the size of out_buffer, used to prevent buffer overflows + * + * getLocalVariableValue will return one of the following on success or error + **/ +static int glvv_Success = 0; +static int glvv_EParam = -1; +static int glvv_EOutOfScope = -2; +static int glvv_EBufferSize = -3; +static int glvv_EUnknown = -4; + +static int getLocalVariableValue(localVar *var, + std::vector &swalk, unsigned frame, + void *out_buffer, unsigned out_buffer_size) +{ + bool result; + + if (!var || frame < 0 || frame >= swalk.size() || !out_buffer) { + return glvv_EParam; + } + + /** + * Find the SymtabAPI object for this frame + * Find the offset for this frame's RA() + **/ + std::string lib_name; + Offset offset; + void *symtab_v; + swalk[frame].getLibOffset(lib_name, offset, symtab_v); + THR_ID thrd = swalk[frame].getThread(); + ProcessState *proc = swalk[frame].getWalker()->getProcessState(); + + /** + * Find the variable location that is valid at this point. + **/ + bool deref; + std::vector &locs = var->getLocationLists(); + std::vector::iterator i; + for (i = locs.begin(); i != locs.end(); i++) { + if (i->lowPC <= offset && offset < i->hiPC) { + break; + } + } + if (i == locs.end()) { + return glvv_EOutOfScope; + } + VariableLocation &loc = *i; + + /** + * Interpret the variable location + **/ + Address var_addr = 0; + deref = (loc.refClass == storageRef); + switch (loc.stClass) { + case storageAddr: + var_addr = loc.frameOffset; + break; + case storageReg: + case storageRegOffset: { + MachRegisterVal reg_value; + MachRegister reg = loc.mr_reg; + if (loc.stClass == storageRegOffset && reg == -1) { + reg = MachRegister::getFramePointer(proc->getAddressWidth() == 4 ? Arch_x86 : Arch_x86_64); + } + + LVReader r(proc, frame, &swalk, thrd); + result = r.GetReg(reg, reg_value); + + if (loc.stClass == storageReg) { + var_addr = reg_value; + } + else { + deref = true; + var_addr = reg_value + loc.frameOffset; + } + break; + } + } + + /** + * Get the size of the variable + **/ + unsigned size = out_buffer_size; + Type *var_type = var->getType(); + if (var_type) { + size = var_type->getSize(); + } + if (size > out_buffer_size) { + return glvv_EBufferSize; + } + + /** + * Read the resulting value + **/ + if (deref) { + result = proc->readMem(out_buffer, var_addr, size); + if (!result) { + return glvv_EUnknown; + } + return glvv_Success; + } + + if (size > sizeof(var_addr)) { + //Value stored in register, but larger than a register? + return glvv_EBufferSize; + } + memcpy(out_buffer, &var_addr, size); + + return glvv_Success; +} + +#endif From c6f38ae5ac04d7e78e9341ea9cfe393424e6fb2b Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 21 Oct 2022 14:12:00 -0500 Subject: [PATCH 128/505] Search 'elfutils' subdirectory for libdebuginfod/includedir (#1307) * Search 'elfutils' subdirectory for libdebuginfod/includedir Debian distributions put the elfutils includes under /include/elfutils. This just adds the /elfutils subdirectory to the search where is returned from pkg-config. --- cmake/Modules/FindLibDebuginfod.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/Modules/FindLibDebuginfod.cmake b/cmake/Modules/FindLibDebuginfod.cmake index fce581f4e2..b3d3691d8b 100644 --- a/cmake/Modules/FindLibDebuginfod.cmake +++ b/cmake/Modules/FindLibDebuginfod.cmake @@ -33,7 +33,7 @@ find_path( NAMES debuginfod.h HINTS ${PC_Debuginfod_INCLUDEDIR} ${PC_Debuginfod_INCLUDE_DIRS} ${LibDebuginfod_ROOT_DIR}/include ${LibDebuginfod_ROOT_DIR} - ${LibDebuginfod_INCLUDEDIR} + ${LibDebuginfod_INCLUDEDIR} ${PC_Debuginfod_INCLUDEDIR}/elfutils PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} PATH_SUFFIXES ${_path_suffixes} DOC "libdebuginfod include directories") From 91967d13e1fa63a25ed0925980df58f673085b79 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 21 Oct 2022 16:31:22 -0500 Subject: [PATCH 129/505] Fix possible null pointer access in BPatch_module::findFunctionByAddress (#1308) * Fix null pointer access in BPatch_module::findFunctionByAddress 'isValid' checks that 'mod' is not null. The code here only runs if mod _is_ null. --- dyninstAPI/src/BPatch_module.C | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/dyninstAPI/src/BPatch_module.C b/dyninstAPI/src/BPatch_module.C index cb22428225..fad283bcb8 100644 --- a/dyninstAPI/src/BPatch_module.C +++ b/dyninstAPI/src/BPatch_module.C @@ -527,9 +527,7 @@ BPatch_module::findFunctionByAddress(void *addr, BPatch_VectorfileName()); - BPatch_reportError(BPatchSerious, 100, msg.c_str()); + BPatch_reportError(BPatchSerious, 100, "Module is not valid"); } return NULL; } From eea540a94564371d3170d01ab16c62ccbc8f9b9d Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 24 Oct 2022 09:55:44 -0500 Subject: [PATCH 130/505] Do not build dyninstAPI_RT as separate CMake project (#1309) * Move dyninstAPI_RT project into Dyninst * Always treat .S files as C files This should have been removed by fc790218e in 2016. --- CMakeLists.txt | 60 ++---------------------------------- dyninstAPI/CMakeLists.txt | 2 -- dyninstAPI_RT/CMakeLists.txt | 21 +------------ 3 files changed, 3 insertions(+), 80 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 72cab2e837..feb490a70c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -23,9 +23,6 @@ if("${isSystemDir}" STREQUAL "-1") set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") endif() -set(RT_SOURCE_DIR ${DYNINST_ROOT}/dyninstAPI_RT) -set(RT_BINARY_DIR ${PROJECT_BINARY_DIR}/dyninstAPI_RT) - set(CMAKE_MODULE_PATH "${DYNINST_ROOT}/cmake" "${DYNINST_ROOT}/cmake/Modules" ${CMAKE_MODULE_PATH}) @@ -101,64 +98,11 @@ if(${SYMREADER} MATCHES symtabAPI) add_subdirectory(parseThat) endif() -# Build the RT library as a separate project so we can change compilers -message(STATUS "Configuring DyninstAPI_RT in ${RT_BINARY_DIR}") -file(REMOVE_RECURSE ${RT_BINARY_DIR}/CMakeCache.txt ${RT_BINARY_DIR}/CMakeFiles - ${RT_BINARY_DIR}/Makefile) -file(MAKE_DIRECTORY ${RT_BINARY_DIR}) -set(RT_C_COMPILER - ${CMAKE_C_COMPILER} - CACHE STRING "Compiler for runtime library") +add_subdirectory(dyninstAPI_RT) + set(ENABLE_STATIC_LIBS NO CACHE STRING "Build static libraries as well?") -message(STATUS "Configuring RT library") - -execute_process( - WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMAND - ${CMAKE_COMMAND} "-DCMAKE_C_COMPILER=${RT_C_COMPILER}" - "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}" - "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}" - "-DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH}" "-DINSTALL_LIB_DIR=${INSTALL_LIB_DIR}" - "-DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR}" "-DCMAKE_C_FLAGS=${CMAKE_C_FLAGS}" - "-DBUILD_RTLIB_32=${BUILD_RTLIB_32}" "-DPLATFORM=${PLATFORM}" - "-DDYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS=${DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS}" - "-DDYNINST_EXTRA_WARNINGS=${DYNINST_EXTRA_WARNINGS}" - "-DDYNINST_WARNINGS_AS_ERRORS=${DYNINST_WARNINGS_AS_ERRORS}" - "-DDYNINST_CXX_LANGUAGE_STANDARD=${DYNINST_CXX_LANGUAGE_STANDARD}" - "-DDYNINST_C_LANGUAGE_STANDARD=${DYNINST_C_LANGUAGE_STANDARD}" -G - "${CMAKE_GENERATOR}" -B "${RT_BINARY_DIR}" -S "${RT_SOURCE_DIR}") -find_file( - ${RT_MAKEFILE} Makefile - PATHS ${RT_BINARY_DIR} - NO_DEFAULT_PATH) -message(STATUS "RTlib Makefile: ${RT_MAKEFILE}") -if(MSVC) - include_external_msproject(DyninstAPI_RT dyninstAPI_RT/dyninstAPI_RT.vcxproj) - include_external_msproject(DyninstAPI_RT_static - dyninstAPI_RT/dyninstAPI_RT_static.vcxproj) -else() - add_custom_target( - DyninstRT ALL - $(MAKE) - WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMENT "Building DyninstRT") - if(TARGET TBB) - add_dependencies(DyninstRT TBB) - endif() - if(TARGET dyninstAPI) - add_dependencies(dyninstAPI DyninstRT) - endif() - if(TARGET dyninstAPI-static) - add_dependencies(dyninstAPI-static DyninstRT) - endif() - if(TARGET boost) - add_dependencies(DyninstRT boost) - endif() -endif() - -install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") set(VERSION_STRING "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") diff --git a/dyninstAPI/CMakeLists.txt b/dyninstAPI/CMakeLists.txt index e9ee10cd87..788216df19 100644 --- a/dyninstAPI/CMakeLists.txt +++ b/dyninstAPI/CMakeLists.txt @@ -209,5 +209,3 @@ if(UNIX) target_compile_definitions( dyninstAPI PRIVATE DYNINST_COMPILER_SEARCH_DIRS=${DYNINST_COMPILER_SEARCH_DIRS}) endif() - -install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index 0922804f27..c1f587f41f 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -1,12 +1,3 @@ -# CMake configuration for dyninstAPI_RT directory -cmake_minimum_required(VERSION 2.6.4) -project(DyninstRT C) - -set(DYNINST_ROOT ${PROJECT_SOURCE_DIR}/..) - -include(${DYNINST_ROOT}/cmake/LanguageStandards.cmake) -include(${DYNINST_ROOT}/cmake/shared.cmake) - include_directories(${DYNINST_ROOT}/dyninstAPI_RT/src ${DYNINST_ROOT}/dyninstAPI_RT/h ${DYNINST_ROOT}) @@ -55,11 +46,7 @@ set(RT_STATIC_ONLY_SRC_LIST_aarch64 src/RTstatic_ctors_dtors-aarch64.c) # that gcc can handle .S. enable_language(ASM) file(GLOB SRC_ASSEMBLY "src/*.S") -if(NEED_NATIVE_ASSEMBER MATCHES YES) - set_source_files_properties(${SRC_ASSEMBLY} PROPERTIES LANGUAGE ASM) -else() - set_source_files_properties(${SRC_ASSEMBLY} PROPERTIES LANGUAGE C) -endif() +set_source_files_properties(${SRC_ASSEMBLY} PROPERTIES LANGUAGE C) # The arch-specific files other than RTthread-x86 are Unix-only. if(UNIX) @@ -88,9 +75,6 @@ if(UNIX) endif() add_library(dyninstAPI_RT SHARED ${SRC_LIST}) -if(TARGET TBB) - add_dependencies(dyninstAPI_RT TBB) -endif() if(NOT PLATFORM MATCHES nt AND NOT PLATFORM MATCHES windows) target_link_libraries(dyninstAPI_RT ${CMAKE_DL_LIBS}) @@ -99,9 +83,6 @@ else() # windows endif() add_library(dyninstAPI_RT_static STATIC ${SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST}) -if(TARGET TBB) - add_dependencies(dyninstAPI_RT_static TBB) -endif() # this should carry over from CMakeLists.txt set_target_properties( From bedbd67402a188bd1e9046fc147fec4831d53235 Mon Sep 17 00:00:00 2001 From: bbiiggppiigg Date: Wed, 26 Oct 2022 13:57:13 +0000 Subject: [PATCH 131/505] Fix incorrect format string in Result.h for u48 / s48 / u64 / s64 (#1311) --- instructionAPI/h/Result.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/instructionAPI/h/Result.h b/instructionAPI/h/Result.h index b6f0421388..a8e27b67dd 100644 --- a/instructionAPI/h/Result.h +++ b/instructionAPI/h/Result.h @@ -473,9 +473,10 @@ namespace Dyninst snprintf(hex, 20, "%x", (unsigned int)val.s32val); break; case u64: - return std::to_string(val.u64val); + snprintf(hex, 20, "%lx", val.u64val); + break; case s64: - return std::to_string(val.s64val); + snprintf(hex, 20, "%lx", (uint64_t) val.s64val); break; case sp_float: snprintf(hex, 20, "%f", (double)val.floatval); @@ -487,10 +488,10 @@ namespace Dyninst snprintf(hex, 20, "%x", (unsigned int)val.bitval); break; case u48: - return std::to_string(val.s48val); + snprintf(hex, 20, "%lx", val.u48val); break; case s48: - return std::to_string(val.s48val); + snprintf(hex, 20, "%lx", (uint64_t ) val.s48val); break; case m512: snprintf(hex, 20, "%p", val.m512val); From 5f0b86ebb263467f1d36915f0f8c396e484ffe6f Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 9 Nov 2022 09:44:57 -0600 Subject: [PATCH 132/505] Allow assignment conversion without framepointer (#1314) * When performing assignment conversion of an instruction and with stack frame analysis, the call would assert if the frame pointer (or stack pointer) was TOP. Change to treat this as unknown (just as a bottom value is). --- dataflowAPI/src/AbslocInterface.C | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/dataflowAPI/src/AbslocInterface.C b/dataflowAPI/src/AbslocInterface.C index 8dfa1c3ebd..9d7ad000c2 100644 --- a/dataflowAPI/src/AbslocInterface.C +++ b/dataflowAPI/src/AbslocInterface.C @@ -428,10 +428,8 @@ bool AbsRegionConverter::getCurrentStackHeight(ParseAPI::Function *func, StackAnalysis::Height heightSA = sA.findSP(block, addr); - // Ensure that analysis has been performed. - assert(!heightSA.isTop()); - - if (heightSA.isBottom()) { + // return false if height unknown + if (heightSA.isBottom() || heightSA.isTop()) { return false; } @@ -449,10 +447,8 @@ bool AbsRegionConverter::getCurrentFrameHeight(ParseAPI::Function *func, StackAnalysis::Height heightSA = sA.find(block, addr, MachRegister::getFramePointer(func->isrc()->getArch()));; - // Ensure that analysis has been performed. - assert(!heightSA.isTop()); - - if (heightSA.isBottom()) { + // return false if height unknown + if (heightSA.isBottom() || heightSA.isTop()) { return false; } From 1e379019f8676d2759c16de3a76ed609028a014e Mon Sep 17 00:00:00 2001 From: bbiiggppiigg Date: Wed, 9 Nov 2022 15:45:22 +0000 Subject: [PATCH 133/505] Manually add hex prefix when formatting an Operand (#1313) --- instructionAPI/src/Operand.C | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/instructionAPI/src/Operand.C b/instructionAPI/src/Operand.C index ddab6629a7..849e2a3144 100644 --- a/instructionAPI/src/Operand.C +++ b/instructionAPI/src/Operand.C @@ -134,7 +134,7 @@ namespace Dyninst Result res = op_value->eval(); if (res.defined) { char hex[20]; - snprintf(hex, 20, "%lux", res.convert()); + snprintf(hex, 20, "0x%lx", res.convert()); return string(hex); } } From 14a148c50d767af14eecbf4ed13bb2edb59ff061 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 9 Nov 2022 12:37:23 -0600 Subject: [PATCH 134/505] Directly link to common in dynC_API (#1319) --- dynC_API/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dynC_API/CMakeLists.txt b/dynC_API/CMakeLists.txt index 0dc95115dc..71df36a009 100644 --- a/dynC_API/CMakeLists.txt +++ b/dynC_API/CMakeLists.txt @@ -10,4 +10,4 @@ if(WIN32) endif() dyninst_library(dynC_API dyninstAPI) -target_link_private_libraries(dynC_API ${Boost_LIBRARIES}) +target_link_libraries(dynC_API PRIVATE common) From 44e8e658a1ca78a0320c1a8afc136ca09d37780c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 9 Nov 2022 12:37:44 -0600 Subject: [PATCH 135/505] Use dyn_c_hash_map in DwarfWalker (#1318) --- symtabAPI/src/dwarfWalker.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index f8e54493eb..8573fc13f3 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -218,7 +218,7 @@ class DwarfWalker : public DwarfParseActions { } Error; - using ParsedFuncs = tbb::concurrent_hash_map; + using ParsedFuncs = Dyninst::dyn_c_hash_map; DwarfWalker(Symtab *symtab, Dwarf* dbg, std::shared_ptr pf = nullptr); From 66a9a3d95bf72e5a92602b961f4b34fdaf256c2a Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 9 Nov 2022 12:38:05 -0600 Subject: [PATCH 136/505] Remove unused TBB from parseAPI (#1317) ParseAPI doesn't use TBB directly. This only compiled because of incidental inclusion of TBB via the global CMake config. --- parseAPI/CMakeLists.txt | 2 +- parseAPI/src/Parser.C | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/parseAPI/CMakeLists.txt b/parseAPI/CMakeLists.txt index 8faa83141e..8fac79a62e 100644 --- a/parseAPI/CMakeLists.txt +++ b/parseAPI/CMakeLists.txt @@ -102,7 +102,7 @@ if(WIN32) endif() dyninst_library(parseAPI common instructionAPI ${SYMREADER}) -target_link_private_libraries(parseAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} tbbmalloc) +target_link_private_libraries(parseAPI ${Boost_LIBRARIES}) if(WIN32) target_link_private_libraries(parseAPI shlwapi) diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index 047164b4bc..8095d05796 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -53,8 +53,6 @@ #include #include -#include "tbb/concurrent_vector.h" - using namespace std; using namespace Dyninst; using namespace Dyninst::ParseAPI; From 55848b7719271e1a784d75ccbbca5a31f1616d5f Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 11 Nov 2022 14:04:20 -0600 Subject: [PATCH 137/505] Support hash_compare concept from TBB >= 2021.1 (#1316) * Make keys const for dyn_c_hashmap allocator This is to match the updated allocator definition in TBB from OneAPI * Make a custom hasher --- common/h/concurrent.h | 49 ++++++++++++++++++++++++++++++++++--- symtabAPI/src/dwarfWalker.h | 46 +++++++++++++++++----------------- 2 files changed, 68 insertions(+), 27 deletions(-) diff --git a/common/h/concurrent.h b/common/h/concurrent.h index 17982aad24..2caa02f63e 100644 --- a/common/h/concurrent.h +++ b/common/h/concurrent.h @@ -40,6 +40,7 @@ #include #include #include +#include namespace Dyninst { @@ -52,12 +53,54 @@ namespace dyn_c_annotations { void COMMON_EXPORT runlock(void*); } +namespace concurrent { + template + struct hasher { + size_t operator()(K const& k) const { + return boost::hash{}(k); + } + }; + + namespace detail { + template + struct hash_compare; + + // New style tbb_hash_compare concept (TBB_VERSION_MAJOR >= 2021) + template + class hash_compare { + hasher my_hasher; + public: + size_t hash(Key const& k) const { + return my_hasher(k); + } + bool equal(Key const& k1, Key const& k2) const { + return k1 == k2; + } + }; + + // Old style tbb_hash_compare concept + template + class hash_compare { + public: + static size_t hash(Key const& k) { + return hasher{}(k); + } + static bool equal(Key const& k1, Key const& k2) { + return k1 == k2; + } + }; + } +} + template class dyn_c_hash_map : protected tbb::concurrent_hash_map, std::allocator>> { + concurrent::detail::hash_compare= 2021, K>, + std::allocator>> { + + using base = tbb::concurrent_hash_map= 2021, K>, + std::allocator>>; - typedef tbb::concurrent_hash_map, std::allocator>> base; public: using typename base::value_type; using typename base::mapped_type; diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 8573fc13f3..9bd29ee74d 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -26,30 +26,28 @@ #include namespace Dyninst { -namespace SymtabAPI { - typedef struct { - Dwarf_Off off; - bool file; - Module * m; - } type_key; -} -} - -namespace tbb { - using namespace Dyninst::SymtabAPI; - template<> - struct tbb_hash_compare { - static size_t hash(const type_key& k) { - size_t seed = 0; - boost::hash_combine(seed, k.off); - boost::hash_combine(seed, k.file); - boost::hash_combine(seed, static_cast(k.m)); - return seed; - } - static bool equal(const type_key& k1, const type_key& k2) { - return (k1.off==k2.off && k1.file==k2.file && k1.m==k2.m); - } - }; + namespace SymtabAPI { + typedef struct { + Dwarf_Off off; + bool file; + Module * m; + } type_key; + inline bool operator==(type_key const& k1, type_key const& k2) { + return k1.off==k2.off && k1.file==k2.file && k1.m==k2.m; + } + } + namespace concurrent { + template<> + struct hasher { + size_t operator()(const SymtabAPI::type_key& k) const { + size_t seed = 0; + boost::hash_combine(seed, k.off); + boost::hash_combine(seed, k.file); + boost::hash_combine(seed, static_cast(k.m)); + return seed; + } + }; + } } namespace Dyninst { From bf14405ca0652eadf410a7530dea49618a49a1e8 Mon Sep 17 00:00:00 2001 From: John Mellor-Crummey Date: Fri, 11 Nov 2022 16:58:31 -0600 Subject: [PATCH 138/505] ParseAPI: improve tail call recognition (#1315) Don't consider a branch that is a self-loop as a potential tail call. --- parseAPI/src/Parser.C | 2 ++ 1 file changed, 2 insertions(+) diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index 8095d05796..14fdb2b823 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -918,9 +918,11 @@ Parser::finalize(Function *f) b->copy_targets(targets); for (auto e : targets) { if (!e->interproc() && (e->type() == INDIRECT || e->type() == DIRECT)) { + if (b->last() != e->trg()->start()) { // if not an instruction that branches to itself e->_type._interproc = true; parsing_printf("from %lx to %lx, marked as tail call (jump at entry), re-finalize\n", b->last(), e->trg()->start()); return false; + } } } } From eba4854fc95b4fd394f7b1de8fd5f0c90036a4cf Mon Sep 17 00:00:00 2001 From: kupsch Date: Mon, 14 Nov 2022 21:53:17 -0600 Subject: [PATCH 139/505] fix Instruction class to allow valid assignment (#1323) * Allow the Instruction class to allow correct assignment semantics by changing a member from a reference to a pointer * The formatter member is a reference (to a singleton) that can not be changed after it is initialized. Assignment to this member wrongly assigns to the previously bound referent singleton and wrongly slices the rhs to the ArchSpecificFormatter base class. The base class has no data members, and since the assignment does not change the type of the object (its vtable), it appears to have no effect. Also a default constructed Instuction object sets the formatter to the x86 formatter even if the host was not x86. * Change Instruction::format to return an error string if the arch is set to Arch_none (default constructed, to prevent nullptr dereference) --- instructionAPI/h/Instruction.h | 3 ++- instructionAPI/src/Instruction.C | 14 ++++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/instructionAPI/h/Instruction.h b/instructionAPI/h/Instruction.h index 2782c9f1fa..e9298c82d1 100644 --- a/instructionAPI/h/Instruction.h +++ b/instructionAPI/h/Instruction.h @@ -317,7 +317,8 @@ namespace Dyninst Architecture arch_decoded_from; mutable std::list m_Successors; static int numInsnsAllocated; - ArchSpecificFormatter& formatter; + // formatter is a non-owning pointer to a singleton object + ArchSpecificFormatter* formatter; }; } } diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index a22ff3f109..bcc16621bf 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -85,7 +85,7 @@ namespace Dyninst size_t size, const unsigned char* raw, Dyninst::Architecture arch) : m_InsnOp(what), m_Valid(true), arch_decoded_from(arch), - formatter(ArchSpecificFormatter::getFormatter(arch)) + formatter(&ArchSpecificFormatter::getFormatter(arch)) { copyRaw(size, raw); @@ -130,7 +130,7 @@ namespace Dyninst } INSTRUCTION_EXPORT Instruction::Instruction() : - m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(ArchSpecificFormatter::getFormatter(Arch_x86_64)) + m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(nullptr) { #if defined(DEBUG_INSN_ALLOCATIONS) numInsnsAllocated++; @@ -451,11 +451,17 @@ namespace Dyninst } INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const { - return formatter; + return *formatter; } INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const { + // if Arch_none, this is an error and the formatter is nullptr, + // so return an error string (could also abort or except) + if (arch_decoded_from == Arch_none) { + return "ERROR_NO_ARCH_SET_FOR_INSTRUCTION"; + } + DECODE_OPERANDS(); //remove this once ArchSpecificFormatter is extended for all architectures @@ -518,7 +524,7 @@ namespace Dyninst cout << endl; #endif // defined(DEBUG_READ_WRITE) - return opstr + formatter.getInstructionString(formattedOperands); + return opstr + formatter->getInstructionString(formattedOperands); } INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const From 5d24b5030044261c91f00cbda5bc046790b22701 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 15 Nov 2022 16:05:57 -0600 Subject: [PATCH 140/505] Ignore unknown pragma warnings when building without OpenMP (#1324) Oddly, these also show up when ENABLE_STATIC_LIBS=OFF and USE_OpenMP=ON. --- cmake/warnings.cmake | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index 1b55898ff9..d1d8479c39 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -96,6 +96,11 @@ endif() if(DYNINST_WARNINGS_AS_ERRORS) list(APPEND REQUESTED_WARNING_FLAGS "Werror") message(STATUS "DYNINST_WARNINGS_AS_ERRORS set: treating warnings as errors") + + # If not building with OpenMP or if static libs are enabled, ignore OpenMP pragma warnings + if(NOT USE_OpenMP OR ENABLE_STATIC_LIBS) + list(APPEND REQUESTED_WARNING_FLAGS "Wno-unknown-pragmas") + endif() endif() if(CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") From 3af05b774b15f98b4de334e686c58ed5992b2b37 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 16 Nov 2022 22:38:58 -0600 Subject: [PATCH 141/505] Fix shadowing of 'filename' member in Elf_X::findDebugFile (#1325) This is an error when DYNINST_WARNINGS_AS_ERRORS=ON and ENABLE_DEBUGINFOD=ON. --- elf/src/Elf_X.C | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/elf/src/Elf_X.C b/elf/src/Elf_X.C index 25a2bb0bda..6a750dac4b 100644 --- a/elf/src/Elf_X.C +++ b/elf/src/Elf_X.C @@ -1763,15 +1763,15 @@ bool Elf_X::findDebugFile(std::string origfilename, string &output_name, char* & if (client == NULL) return false; - char *filename; + char *path; int fd = debuginfod_find_debuginfo(client, (const unsigned char *)buildid.c_str(), - 0, &filename); + 0, &path); debuginfod_end(client); if (fd >= 0) { - string fname = string(filename); - free(filename); + string fname = string(path); + free(path); close(fd); bool result = loadDebugFileFromDisk(fname, From def4204359d2051958d99e8f3c515dbc9ff3edf0 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 21 Nov 2022 13:46:38 -0600 Subject: [PATCH 142/505] Documentation updates for v12.2.1 patch release (#1328) * Doc updates for v12.2.1 release * Update formatting for cmake/warnings.cmake --- CHANGELOG.md | 21 +++++++++++++++++++++ cmake/shared.cmake | 2 +- cmake/warnings.cmake | 7 ++++--- 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ecc33820c9..3d13d7b7d0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,26 @@ # Change Log +## [12.2.1](https://github.com/dyninst/dyninst/tree/v12.2.1) (2022-11-21) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.2.0...v12.2.1) + +- Fix shadowing of 'filename' member in Elf_X::findDebugFile ([1325](https://github.com/dyninst/dyninst/issues/1325)) +- Ignore unknown pragma warnings when building without OpenMP ([1324](https://github.com/dyninst/dyninst/issues/1324)) +- fix Instruction class to allow valid assignment ([1323](https://github.com/dyninst/dyninst/issues/1323)) +- ParseAPI: improve tail call recognition ([1315](https://github.com/dyninst/dyninst/issues/1315)) +- Support hash_compare concept from TBB >= 2021.1 ([1316](https://github.com/dyninst/dyninst/issues/1316)) +- Remove unused TBB from parseAPI ([1317](https://github.com/dyninst/dyninst/issues/1317)) +- Use dyn_c_hash_map in DwarfWalker ([1318](https://github.com/dyninst/dyninst/issues/1318)) +- Directly link to common in dynC_API ([1319](https://github.com/dyninst/dyninst/issues/1319)) +- Manually add hex prefix when formatting an Operand ([1313](https://github.com/dyninst/dyninst/issues/1313)) +- Allow assignment conversion without framepointer ([1314](https://github.com/dyninst/dyninst/issues/1314)) +- Fix incorrect format string in Result.h for u48 / s48 / u64 / s64 ([1311](https://github.com/dyninst/dyninst/issues/1311)) +- Do not build dyninstAPI_RT as separate CMake project ([1309](https://github.com/dyninst/dyninst/issues/1309)) +- Fix possible null pointer access in BPatch_module::findFunctionByAddress ([1308](https://github.com/dyninst/dyninst/issues/1308)) +- Search 'elfutils' subdirectory for libdebuginfod/includedir ([1307](https://github.com/dyninst/dyninst/issues/1307)) +- Fix public header deletes ([1301](https://github.com/dyninst/dyninst/issues/1301)) +- fix location list PC range values ([1297](https://github.com/dyninst/dyninst/issues/1297)) +- Docker - use ppa for gcc11 ([1291](https://github.com/dyninst/dyninst/issues/1291)) + ## [12.2.0](https://github.com/dyninst/dyninst/tree/v12.2.0) (2022-07-28) [Full Changelog](https://github.com/dyninst/dyninst/compare/v12.1.0...v12.2.0) diff --git a/cmake/shared.cmake b/cmake/shared.cmake index fe9de4db5b..15045380fe 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,6 +1,6 @@ set(DYNINST_MAJOR_VERSION 12) set(DYNINST_MINOR_VERSION 2) -set(DYNINST_PATCH_VERSION 0) +set(DYNINST_PATCH_VERSION 1) set(SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") set(LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake index d1d8479c39..a104c222d7 100644 --- a/cmake/warnings.cmake +++ b/cmake/warnings.cmake @@ -96,10 +96,11 @@ endif() if(DYNINST_WARNINGS_AS_ERRORS) list(APPEND REQUESTED_WARNING_FLAGS "Werror") message(STATUS "DYNINST_WARNINGS_AS_ERRORS set: treating warnings as errors") - - # If not building with OpenMP or if static libs are enabled, ignore OpenMP pragma warnings + + # If not building with OpenMP or if static libs are enabled, ignore OpenMP pragma + # warnings if(NOT USE_OpenMP OR ENABLE_STATIC_LIBS) - list(APPEND REQUESTED_WARNING_FLAGS "Wno-unknown-pragmas") + list(APPEND REQUESTED_WARNING_FLAGS "Wno-unknown-pragmas") endif() endif() From 3937542bdc773b6f10740e0746e9c4fb7f8e02d6 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 30 Nov 2022 10:10:35 -0600 Subject: [PATCH 143/505] Remove outdated Boost version checks (#1329) * Remove check of BOOST_THREAD_PROVIDES_ONCE_CXX11 This is internally by Boost for all versions we support. * Remove version check in parseAPI/GraphAdapter.C We require at least version 1.70.0 now * Remove version check in proccontrol/PCProcess.h We require at least version 1.70.0 now --- dwarf/src/dwarfFrameParser.C | 2 -- parseAPI/src/GraphAdapter.C | 5 ----- proccontrol/h/PCProcess.h | 4 ---- 3 files changed, 11 deletions(-) diff --git a/dwarf/src/dwarfFrameParser.C b/dwarf/src/dwarfFrameParser.C index afcc32222c..fd75706fac 100644 --- a/dwarf/src/dwarfFrameParser.C +++ b/dwarf/src/dwarfFrameParser.C @@ -70,9 +70,7 @@ DwarfFrameParser::DwarfFrameParser(Dwarf * dbg_, Elf * eh_frame, Architecture ar dbg(dbg_), dbg_eh_frame(eh_frame), arch(arch_), -#ifndef BOOST_THREAD_PROVIDES_ONCE_CXX11 fde_dwarf_once(BOOST_ONCE_INIT), -#endif fde_dwarf_status(dwarf_status_uninitialized) { } diff --git a/parseAPI/src/GraphAdapter.C b/parseAPI/src/GraphAdapter.C index 68d7acb230..69ffe2d9c9 100644 --- a/parseAPI/src/GraphAdapter.C +++ b/parseAPI/src/GraphAdapter.C @@ -4,12 +4,7 @@ #include #include -#if BOOST_VERSION > 104000 #include -#else -#include -#endif - #include #include diff --git a/proccontrol/h/PCProcess.h b/proccontrol/h/PCProcess.h index 3fe43e2e88..be7b3aa7fd 100644 --- a/proccontrol/h/PCProcess.h +++ b/proccontrol/h/PCProcess.h @@ -48,11 +48,7 @@ #include "boost/enable_shared_from_this.hpp" #include "boost/version.hpp" -#if BOOST_VERSION >= 107000 #define CHECKED_DELETE_NOEXCEPT BOOST_NOEXCEPT -#else -#define CHECKED_DELETE_NOEXCEPT -#endif From 42612b456e1958e4823bdb8f3022273804a49fc3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A9sz=C3=A1ros=20Gergely?= Date: Thu, 15 Dec 2022 17:12:59 +0100 Subject: [PATCH 144/505] Lookup functions in the binding table directly (#1337) instead of making multiple redundant copies of it. Copying and making a map out of the table incurs a significant overhead. --- dyninstAPI/src/unix.C | 32 ++++---------------------------- symtabAPI/h/Symtab.h | 1 + symtabAPI/src/Symtab.C | 24 ++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 28 deletions(-) diff --git a/dyninstAPI/src/unix.C b/dyninstAPI/src/unix.C index 868204d9ad..2dac684c64 100644 --- a/dyninstAPI/src/unix.C +++ b/dyninstAPI/src/unix.C @@ -743,45 +743,21 @@ func_instance *block_instance::callee() { // get the relocation information for this image Symtab *sym = obj()->parse_img()->getObject(); - std::vector fbt; - if (!sym->getFuncBindingTable(fbt)) { - return NULL; - } - - - /** - * Object files and static binaries will not have a function binding table - * because the function binding table holds relocations used by the dynamic - * linker - */ - if (!fbt.size() && !sym->isStaticBinary() && - sym->getObjectType() != obj_RelocatableFile ) - { - fprintf(stderr, "%s[%d]: WARN: zero func bindings\n", FILE__, __LINE__); - } - - std::map pltFuncs; - obj()->parse_img()->getPltFuncs(pltFuncs); - // find the target address in the list of relocationEntries - if (pltFuncs.find(target_addr) != pltFuncs.end()) { + relocationEntry function_binding; + if(sym->findPltEntryByTarget(target_addr, function_binding)) { Address base_addr = obj()->codeBase(); - for (u_int i=0; i < fbt.size(); i++) { - if (fbt[i].target_addr() == target_addr) - { // check to see if this function has been bound yet...if the // PLT entry for this function has been modified by the runtime // linker func_instance *target_pdf = 0; - if (proc()->hasBeenBound(fbt[i], target_pdf, base_addr)) { + if (proc()->hasBeenBound(function_binding, target_pdf, base_addr)) { updateCallTarget(target_pdf); obj()->setCalleeName(this, target_pdf->symTabName()); obj()->setCallee(this, target_pdf); return target_pdf; } - } - } - return callee(pltFuncs[target_addr]); + return callee(function_binding.name()); } else { /* * Sometimes, the PLT address and the CFG target aren't the same diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 4a06cadad8..4b5d4c88e5 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -219,6 +219,7 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, // Relocation entries bool getFuncBindingTable(std::vector &fbt) const; + bool findPltEntryByTarget(Address target_address, relocationEntry &result) const; bool updateFuncBindingTable(Offset stub_addr, Offset plt_addr); /************************************** diff --git a/symtabAPI/src/Symtab.C b/symtabAPI/src/Symtab.C index 2308b5276e..2222394aeb 100644 --- a/symtabAPI/src/Symtab.C +++ b/symtabAPI/src/Symtab.C @@ -1548,6 +1548,30 @@ SYMTAB_EXPORT bool Symtab::getFuncBindingTable(std::vector &fbt return true; } +SYMTAB_EXPORT bool Symtab::findPltEntryByTarget(const Address target_address, relocationEntry &result) const +{ + /** + * Object files and static binaries will not have a function binding table + * because the function binding table holds relocations used by the dynamic + * linker + */ + if(relocation_table_.empty() && !isStaticBinary() && + getObjectType() != obj_RelocatableFile) + { + fprintf(stderr, "%s[%d]: WARN: zero func bindings\n", FILE__, __LINE__); + } + + auto it = std::find_if(relocation_table_.cbegin(), relocation_table_.cend(), + [=](const relocationEntry& entry) { + return entry.target_addr() == target_address; + }); + if(it == relocation_table_.cend()) + return false; + + result = *it; + return true; +} + SYMTAB_EXPORT bool Symtab::updateFuncBindingTable(Offset stub_addr, Offset plt_addr) { int stub_idx = -1, plt_idx = -1; From c98df5b73ef51aa690c90373965861c9e791e75c Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Mon, 19 Dec 2022 17:16:38 -0600 Subject: [PATCH 145/505] Remove dead implementation of IA_power::isLinkerStub (#1342) Disabled by a382e03ff in 2012. --- parseAPI/src/IA_power.C | 382 ---------------------------------------- 1 file changed, 382 deletions(-) diff --git a/parseAPI/src/IA_power.C b/parseAPI/src/IA_power.C index db3eed06a3..5979ab6371 100644 --- a/parseAPI/src/IA_power.C +++ b/parseAPI/src/IA_power.C @@ -437,394 +437,12 @@ bool IA_power::isIATcall(std::string &) const return false; } -typedef enum { - STUB_UNKNOWN, - STUB_LONG_BRANCH, - STUB_TOC_BRANCH, - STUB_PLT_CALL -} linker_stub_t; - -linker_stub_t checkLinkerStub(void *insn_buf, Offset &off) -{ -#if defined(ppc64_linux) - const unsigned int B_UNCOND = 0x48000000; - const unsigned int ADDIS_R12_R12 = 0x3d8c0000; - const unsigned int ADDIS_R12_R2 = 0x3d820000; - const unsigned int ADDIS_R2_R2 = 0x3c420000; - const unsigned int ADDI_R12_R12 = 0x398c0000; - const unsigned int ADDI_R2_R2 = 0x38420000; - const unsigned int STD_R2_40R1 = 0xf8410028; - const unsigned int LD_R2_40R1 = 0xe8410028; - const unsigned int LD_R2_0R12 = 0xe84c0000; - const unsigned int LD_R11_0R12 = 0xe96c0000; - const unsigned int LD_R11_0R2 = 0xe9620000; - const unsigned int MTCTR_R11 = 0x7d6903a6; - const unsigned int BCTR = 0x4e800420; - - /* - * Linker stubs seen from GNU's binutils. - * (see the following functions in binutils' bfd/elf64-ppc.c: - * ppc_build_one_stub() - * build_plt_stub() - * build_tls_get_addr_stub() - * - * We could be clever and create some sort of state machine that will - * determine the correct signature by only reading each instruction - * once. However, I assume this will also make the code harder to - * maintain, and so I've gone the dumb route. We can re-code this - * section if it's determined to be a performance bottleneck. - * - * Add stub signatures as we see more. - */ - - // ---------------------------------------------- - // ppc_stub_plt_call: - // - - // binutils >= 2.18 PLT stub signatures look like this: - // if (PPC_HA (off) != 0) - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 - // LD_R11_0R12 | PPC_LO (off) - // ADDI_R12_R12 | PPC_LO (off) if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R2_0R12 | PPC_LO (off + 8) - // LD_R11_0R12 | PPC_LO (off + 16) - // BCTR - // else - // STD_R2_40R1 - // LD_R11_0R2 | PPC_LO (off) - // ADDI_R2_R2 | PPC_LO (off) - // MTCTR_R11 - // LD_R11_0R2 | PPC_LO (off + 16) - // LD_R2_0R2 | PPC_LO (off + 8) - // BCTR - // endif - // - // This results in three possible stubs: - - instruction *insn = static_cast(insn_buf); - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[2].asInt() & 0xffff0000) == ADDI_R12_R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[6].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_PLT_CALL; - } - - // binutils from 1.15 -> 2.18 PLT stub signatures look like this: - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 - // LD_R11_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 8) != PPC_HA (off)) - // LD_R2_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R11_0R12 | PPC_LO (off) - // BCTR - // - // This results in three possible stubs: - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == (ADDIS_R12_R12 | 1) - && insn[5].asInt() == MTCTR_R11 - && (insn[6].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[7].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[3].asInt() == (ADDIS_R12_R12 | 1) - && (insn[4].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[5].asInt() == (ADDIS_R12_R12 | 1) - && insn[6].asInt() == MTCTR_R11 - && (insn[7].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[8].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - // binutils < 1.15 PLT stub signatures look like this: - // LD_R2_40R1 if (glink) - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 if (!glink) - // LD_R11_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 8) != PPC_HA (off)) - // LD_R2_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R11_0R12 | PPC_LO (off) - // BCTR - // - // The non-glink case is identical to the cases above, so we need only - // handle the three glink cases: - - /* Ugg. The toc register is pulled off the stack for these cases. - This is most likely the toc for the callee, but we don't know - who the callee is yet. - */ - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == (ADDIS_R12_R12 | 1) - && insn[5].asInt() == MTCTR_R11 - && (insn[6].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[7].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[3].asInt() == (ADDIS_R12_R12 | 1) - && (insn[4].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[5].asInt() == (ADDIS_R12_R12 | 1) - && insn[6].asInt() == MTCTR_R11 - && (insn[7].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[8].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - // ---------------------------------------------- - // ppc_stub_long_branch: - // ppc_stub_long_branch_r2off: - if ( (insn[0].asInt() & 0xfc000000) == B_UNCOND) - { - off = IFORM_LI(insn[0]) << 2; - return STUB_LONG_BRANCH; - } - - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && (insn[3].asInt() & 0xfc000003) == B_UNCOND) - { - off = (3 * 4) + (IFORM_LI(insn[3]) << 2); - return STUB_LONG_BRANCH; - } - - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDI_R2_R2 - && (insn[2].asInt() & 0xfc000003) == B_UNCOND) - { - off = (2 * 4) + (IFORM_LI(insn[2]) << 2); - return STUB_LONG_BRANCH; - } - - // ---------------------------------------------- - // ppc_stub_plt_branch: - // - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[2].asInt() == MTCTR_R11 - && insn[3].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } - - if ( (insn[0].asInt() & 0xffff0000) == LD_R11_0R2 - && insn[1].asInt() == MTCTR_R11 - && insn[2].asInt() == BCTR) - { - off = DFORM_SI(insn[0]); - return STUB_TOC_BRANCH; - } - - // ---------------------------------------------- - // ppc_stub_plt_branch_r2off: - // - - // With offset > 16 bits && r2offset > 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[4].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[5].asInt() == MTCTR_R11 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[1]) << 16) + DFORM_SI(insn[2]); - return STUB_TOC_BRANCH; - } - - // With offset > 16 bits && r2offset <= 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && insn[5].asInt() == BCTR) - { - off = (DFORM_SI(insn[1]) << 16) + DFORM_SI(insn[2]); - return STUB_TOC_BRANCH; - } - - // With offset <= 16 bits && r2offset > 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[3].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && insn[5].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } - - // With offset <= 16 bits && r2offset <= 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[3].asInt() == MTCTR_R11 - && insn[4].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } -#else - (void)insn_buf; -#endif - - off = 0; - return STUB_UNKNOWN; -} - bool IA_power::isLinkerStub() const { // Disabling this code because it ends with an // incorrect CFG. return false; - - if (validLinkerStubState) - return cachedLinkerStubState; - - if (!validCFT) - return false; - - if (!isCall()) { - cachedLinkerStubState = false; - validLinkerStubState = true; - return cachedLinkerStubState; - } - - if (!cachedCFT.first) return false; - - void *insn_buf = _isrc->getPtrToInstruction(cachedCFT.second); - if (!insn_buf) - return false; - - Offset off; - linker_stub_t stub_type = checkLinkerStub(insn_buf, off); - - switch (stub_type) { - case STUB_UNKNOWN: - // It's not a linker stub (that we know of). Allow processing to - // continue unmodified, probably leading to the eventual creation - // of a targXXXXX function. - break; - - case STUB_LONG_BRANCH: - cachedCFT.second += off; - break; - - case STUB_TOC_BRANCH: - cachedCFT.second += off; - assert(0 && "STUB_TOC_BRANCH not implemented yet."); - - // Although tempting, we cannot just read the word directly from the - // mutatee, and find the symbol that matches. There may be no - // child process to read from. - // - // In theory, we can use the relocations to determine the final - // address/symbol. But, I can't get binutils to actually generate - // this kind of stub. Let's deal with this once we find a binary - // that uses it. - break; - - case STUB_PLT_CALL: - cachedCFT.second = _obj->cs()->getTOC(current) + off; - break; - } - - cachedLinkerStubState = (stub_type != STUB_UNKNOWN); - validLinkerStubState = true; - - return cachedLinkerStubState; } AST::Ptr PPC_BLR_Visitor::visit(AST *a) { From 2e3bf92eedf575c780e4381ae810a050ee404f03 Mon Sep 17 00:00:00 2001 From: kupsch Date: Thu, 5 Jan 2023 13:13:14 -0600 Subject: [PATCH 146/505] add missing include file (#1344) - add missing #include On more platforms and library combinations is included via some other header, but there is combination where this is not true --- dataflowAPI/src/AbslocInterface.C | 1 + 1 file changed, 1 insertion(+) diff --git a/dataflowAPI/src/AbslocInterface.C b/dataflowAPI/src/AbslocInterface.C index 9d7ad000c2..582e640049 100644 --- a/dataflowAPI/src/AbslocInterface.C +++ b/dataflowAPI/src/AbslocInterface.C @@ -29,6 +29,7 @@ */ +#include #include "Absloc.h" #include "AbslocInterface.h" From 3ac13c33c804a9afa4bf57d561bbbc7a4c96ae5a Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 10 Jan 2023 16:20:09 -0600 Subject: [PATCH 147/505] Refactor common/src/Types.h (#1351) * Remove double128_t It's never used * Replace custom limit macros with the ones from stdint * Remove custom fixed-width types and limit macros We require C++11, so just use the [c]stdint headers. * Use correct signedness for Address comparison --- common/src/Types.h | 94 ++----------------------------------------- common/src/arch-x86.h | 4 +- 2 files changed, 5 insertions(+), 93 deletions(-) diff --git a/common/src/Types.h b/common/src/Types.h index 20dbe90d72..5b51c5da6b 100644 --- a/common/src/Types.h +++ b/common/src/Types.h @@ -36,98 +36,10 @@ #if !defined(_Types_h_) #define _Types_h_ -/* Sets up 64 and 32 bit - types: - int64_t uint64_t int32_t uint32_t - constant macros: - I64_C(x) UI64_C(x) - limits: - I64_MAX I64_MIN UI64_MAX - I32_MAX I32_MIN UI32_MAX - - note: needs to be included before anything that includes inttypes.h - (eg. stdio on some systems) -*/ - -/* Set up the 32 AND 64 BIT TYPES ===================================== */ -/* - --- inttypes.h --- - int32_t uint32_t int64_t uint64_t 32B lmts 64Blmts 64BlitMacros# -Linux yes yes yes yes yes yes yes -FreeBSD yes yes yes yes yes yes yes -WindowsNT nonexistant - - # we rename all of the 64 bit literal macros to our shortened name -*/ - -#if defined(os_windows) - typedef signed __int64 int64_t; - typedef signed __int32 int32_t; - typedef signed __int16 int16_t; - typedef signed __int8 int8_t; - typedef unsigned __int64 uint64_t; - typedef unsigned __int32 uint32_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int8 uint8_t; - -#elif defined(os_linux) -#if !defined(__STDC_CONSTANT_MACROS) -#define __STDC_CONSTANT_MACROS -#endif -#if !defined(__STDC_LIMIT_MACROS) -#define __STDC_LIMIT_MACROS -#endif -#include -#if defined(arch_x86_64) || defined(arch_64bit) -#define TYPE64BIT -#endif -typedef long double double128_t; - -#elif defined(os_freebsd) -#if !defined(__STDC_CONSTANT_MACROS) -#define __STDC_CONSTANT_MACROS -#endif -#if !defined(__STDC_LIMIT_MACROS) -#define __STDC_LIMIT_MACROS -#endif -#include -typedef long double double128_t; - -/* FreeBSD doesn't define this */ -typedef int64_t off64_t; - +#if defined __cplusplus +# include #else -#error Unknown architecture -#endif - - -/* Set up the 64 BIT LITERAL MACROS =================================== */ -#if defined(os_windows) - /* nt ----------------------------- */ -#define I64_C(x) (x##i64) -#define UI64_C(x) (x##ui64) -#else /* linux, freebsd ----------------- */ -#define I64_C(x) INT64_C(x) -#define UI64_C(x) UINT64_C(x) -#endif - -/* Set up the 32 and 64 BIT LIMITS for those not already set up ======= */ -#if defined(os_windows) - /* nt ----------------------------- */ -#include -#define I64_MAX _I64_MAX -#define UI64_MAX _UI64_MAX -#define I64_MIN _I64_MIN -#define I32_MAX _I32_MAX -#define I32_MIN _I32_MIN -#define UI32_MAX _UI32_MAX -#else /* linux, freebsd ----------------- */ -#define I64_MAX INT64_MAX -#define UI64_MAX UINT64_MAX -#define I64_MIN INT64_MIN -#define I32_MAX INT32_MAX -#define I32_MIN INT32_MIN -#define UI32_MAX UINT32_MAX +# include #endif /* diff --git a/common/src/arch-x86.h b/common/src/arch-x86.h index e78f0844aa..cf58611ad6 100644 --- a/common/src/arch-x86.h +++ b/common/src/arch-x86.h @@ -1159,13 +1159,13 @@ inline bool is_disp16(long disp) { } inline bool is_disp32(long disp) { - return (disp <= I32_MAX && disp >= I32_MIN); + return (disp <= INT32_MAX && disp >= INT32_MIN); } inline bool is_disp32(Address a1, Address a2) { return is_disp32(a2 - (a1 + JUMP_REL32_SZ)); } inline bool is_addr32(Address addr) { - return (addr < UI32_MAX); + return (addr < UINT32_MAX); } COMMON_EXPORT void decode_SIB(unsigned sib, unsigned& scale, From 51a78a436b5494ffa11be1dc73d89792c313577d Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 25 Jan 2023 16:12:58 -0600 Subject: [PATCH 148/505] Remove special global ctor/dtor search in ppc for static binaries (#1353) Neither of the other platforms searches through .init to try to find a global constructor. Moreover, the gmon_start function has been removed in the latest glibc's. --- dyninstAPI/src/parse-power.C | 204 +---------------------------------- 1 file changed, 2 insertions(+), 202 deletions(-) diff --git a/dyninstAPI/src/parse-power.C b/dyninstAPI/src/parse-power.C index 96f7a64bfc..27f57bfa3e 100644 --- a/dyninstAPI/src/parse-power.C +++ b/dyninstAPI/src/parse-power.C @@ -407,110 +407,7 @@ func_instance *mapped_object::findGlobalConstructorFunc(const std::string &ctorH return ctorFuncs->at(0); } - /* If the symbol isn't found, try looking for it in a call instruction in - * the .init section - * - * On Linux, the instruction sequence is: - * ... - * some instructions - * ... - * call call_gmon_start - * call frame_dummy - * call ctor_handler - * - * On FreeBSD, the instruction sequence is: - * ... - * some instructions - * ... - * call frame_dummy - * call ctor_handler - */ - Symtab *linkedFile = parse_img()->getObject(); - Region *initRegion = NULL; - if( !linkedFile->findRegion(initRegion, ".init") ) { - vector symFuncs; - if( linkedFile->findFunctionsByName(symFuncs, "_init") ) { - initRegion = symFuncs[0]->getRegion(); - }else{ - logLine("failed to locate .init Region or _init function\n"); - return NULL; - } - } - - if( initRegion == NULL ) { - logLine("failed to locate .init Region or _init function\n"); - return NULL; - } - - // Search for last of a fixed number of calls -#if defined(os_freebsd) - const unsigned CTOR_NUM_CALLS = 2; -#else - const unsigned CTOR_NUM_CALLS = 3; -#endif - - Address ctorAddress = 0; - unsigned bytesSeen = 0; - unsigned numCalls = 0; - const unsigned char *p = reinterpret_cast(initRegion->getPtrToRawData()); - - InstructionDecoder decoder(p, initRegion->getDiskSize(), - parse_img()->codeObject()->cs()->getArch()); - - Instruction curInsn = decoder.decode(); - while(numCalls < CTOR_NUM_CALLS && curInsn.isValid() && - bytesSeen < initRegion->getDiskSize()) - { - InsnCategory category = curInsn.getCategory(); - if( category == c_CallInsn ) { - numCalls++; - } - if( numCalls < CTOR_NUM_CALLS ) { - bytesSeen += curInsn.size(); - curInsn = decoder.decode(); - } - } - - if( numCalls != CTOR_NUM_CALLS ) { - logLine("heuristic for finding global constructor function failed\n"); - return NULL; - } - - Address callAddress = initRegion->getMemOffset() + bytesSeen; - - RegisterAST thePC = RegisterAST( - Dyninst::MachRegister::getPC(parse_img()->codeObject()->cs()->getArch())); - - Expression::Ptr callTarget = curInsn.getControlFlowTarget(); - if( !callTarget.get() ) { - logLine("failed to find global constructor function\n"); - return NULL; - } - callTarget->bind(&thePC, Result(s64, callAddress)); - - Result actualTarget = callTarget->eval(); - if( actualTarget.defined ) { - ctorAddress = actualTarget.convert

    (); - }else{ - logLine("failed to find global constructor function\n"); - return NULL; - } - - if( !ctorAddress || !parse_img()->codeObject()->cs()->isValidAddress(ctorAddress) ) { - logLine("invalid address for global constructor function\n"); - return NULL; - } - - func_instance *ret; - if( (ret = findFuncByEntry(ctorAddress)) == NULL ) { - logLine("unable to create representation for global constructor function\n"); - return NULL; - } - - inst_printf("%s[%d]: set global constructor address to 0x%lx\n", FILE__, __LINE__, - ctorAddress); - - return ret; + return NULL; } func_instance *mapped_object::findGlobalDestructorFunc(const std::string &dtorHandler) { @@ -520,103 +417,6 @@ func_instance *mapped_object::findGlobalDestructorFunc(const std::string &dtorHa if( ctorFuncs != NULL ) { return ctorFuncs->at(0); } - - /* - * If the symbol isn't found, try looking for it in a call in the - * .fini section. It is the last call in .fini. - * - * The pattern is: - * - * _fini: - * - * ... some code ... - * - * call dtor_handler - * - * ... prologue ... - */ - Symtab *linkedFile = parse_img()->getObject(); - Region *finiRegion = NULL; - if( !linkedFile->findRegion(finiRegion, ".fini") ) { - vector symFuncs; - if( linkedFile->findFunctionsByName(symFuncs, "_fini") ) { - finiRegion = symFuncs[0]->getRegion(); - }else{ - logLine("failed to locate .fini Region or _fini function\n"); - return NULL; - } - } - - if( finiRegion == NULL ) { - logLine("failed to locate .fini Region or _fini function\n"); - return NULL; - } - - // Search for last call in the function - Address dtorAddress = 0; - unsigned bytesSeen = 0; - const unsigned char *p = reinterpret_cast(finiRegion->getPtrToRawData()); - - InstructionDecoder decoder(p, finiRegion->getDiskSize(), - parse_img()->codeObject()->cs()->getArch()); - - Instruction lastCall; - Instruction curInsn = decoder.decode(); - bool find = false; - - while(curInsn.isValid() && - bytesSeen < finiRegion->getDiskSize()) - { - InsnCategory category = curInsn.getCategory(); - if( category == c_CallInsn ) { - find = true; - lastCall = curInsn; - break; - } - - bytesSeen += curInsn.size(); - curInsn = decoder.decode(); - } - - if( !find || !lastCall.isValid() ) { - logLine("heuristic for finding global destructor function failed\n"); - return NULL; - } - - Address callAddress = finiRegion->getMemOffset() + bytesSeen; - - RegisterAST thePC = RegisterAST( - Dyninst::MachRegister::getPC(parse_img()->codeObject()->cs()->getArch())); - - Expression::Ptr callTarget = lastCall.getControlFlowTarget(); - if( !callTarget.get() ) { - logLine("failed to find global destructor function\n"); - return NULL; - } - callTarget->bind(&thePC, Result(s64, callAddress)); - - Result actualTarget = callTarget->eval(); - if( actualTarget.defined ) { - dtorAddress = actualTarget.convert
    (); - }else{ - logLine("failed to find global destructor function\n"); - return NULL; - } - - if( !dtorAddress || !parse_img()->codeObject()->cs()->isValidAddress(dtorAddress) ) { - logLine("invalid address for global destructor function\n"); - return NULL; - } - - // A targ stub should have been created at the address - func_instance *ret = NULL; - if( (ret = findFuncByEntry(dtorAddress)) == NULL ) { - logLine("unable to find global destructor function\n"); - return NULL; - } - inst_printf("%s[%d]: set global destructor address to 0x%lx\n", FILE__, __LINE__, - dtorAddress); - - return ret; + return NULL; } From 0232fb63b9b7850022adbd104ff7e89d9e6535e2 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Fri, 27 Jan 2023 12:46:21 -0600 Subject: [PATCH 149/505] Use instrumentation logging in baseTramp::guarded (#1354) --- dyninstAPI/src/baseTramp.C | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/dyninstAPI/src/baseTramp.C b/dyninstAPI/src/baseTramp.C index 805c1bff0c..1fac9f195f 100644 --- a/dyninstAPI/src/baseTramp.C +++ b/dyninstAPI/src/baseTramp.C @@ -526,8 +526,9 @@ bool baseTramp::guarded() const { } if (recursive && guarded) { - cerr << "Warning: mix of recursive and guarded snippets @ " << point_ - << ", picking guarded" << endl; + inst_printf( + "Warning: mix of recursive and guarded snippets @ %p, picking guarded \n", + static_cast(point_)); return true; } if (guarded) return true; From 56805be361aaaed82d53cd9e5c795e09cc2467da Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 31 Jan 2023 13:10:36 -0600 Subject: [PATCH 150/505] BPatch_snippet::generateArrayRef - fix possible null pointer access (#1356) --- dyninstAPI/src/BPatch_snippet.C | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/dyninstAPI/src/BPatch_snippet.C b/dyninstAPI/src/BPatch_snippet.C index dac9e4675e..adce127fdb 100644 --- a/dyninstAPI/src/BPatch_snippet.C +++ b/dyninstAPI/src/BPatch_snippet.C @@ -183,25 +183,25 @@ AstNodePtr generateArrayRef(const BPatch_snippet &lOperand, // We have to be a little forgiving of the - typeArray *arrayType = lOperand.ast_wrapper->getType()->getSymtabType(Type::share)->getArrayType(); - if (!arrayType) + if (lOperand.ast_wrapper->getType() == NULL) { - if (lOperand.ast_wrapper->getType() == NULL) - { - BPatch_reportError(BPatchSerious, 109, - "array reference has no type information"); - } - else - { - fprintf(stderr, "%s[%d]: error here: type is %s\n", FILE__, __LINE__, - lOperand.ast_wrapper->getType()->getName()); - BPatch_reportError(BPatchSerious, 109, - "array reference has array reference to non-array type"); - } + BPatch_reportError(BPatchSerious, 109, + "array reference has no type information"); assert(0); return AstNodePtr(); } + typeArray *arrayType = lOperand.ast_wrapper->getType()->getSymtabType(Type::share)->getArrayType(); + if (!arrayType) + { + fprintf(stderr, "%s[%d]: error here: type is %s\n", FILE__, __LINE__, + lOperand.ast_wrapper->getType()->getName()); + BPatch_reportError(BPatchSerious, 109, + "array reference has array reference to non-array type"); + assert(0); + return AstNodePtr(); + } + auto elementType = arrayType->getBaseType(Type::share); assert(elementType); long int elementSize = elementType->getSize(); From d7c9f9fa593bd62ce9a7971b24ccd4fd54aa5def Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Tue, 31 Jan 2023 14:05:25 -0600 Subject: [PATCH 151/505] Remove AObject::pickLanguage (#1358) This was only used by the STABs parsing code. It should have been removed by 5e142eff. Language detection is handled by `void Object::getModuleLanguageInfo` and requires DWARF (it does nothing on non-ELF binaries). --- symtabAPI/src/Object.C | 56 ------------------------------------------ symtabAPI/src/Object.h | 3 --- 2 files changed, 59 deletions(-) diff --git a/symtabAPI/src/Object.C b/symtabAPI/src/Object.C index 7fb064ce2c..ee8171d306 100644 --- a/symtabAPI/src/Object.C +++ b/symtabAPI/src/Object.C @@ -393,62 +393,6 @@ SYMTAB_EXPORT AObject::AObject(MappedFile *mf_, void (*err_func)(const char *), { } -// a helper routine that selects a language based on information from the symtab -supportedLanguages AObject::pickLanguage(string &working_module, char *working_options, - supportedLanguages working_lang) -{ - supportedLanguages lang = lang_Unknown; - - // (2) -- check suffixes -- try to keep most common suffixes near the top of the checklist - string::size_type len = working_module.length(); - if((len>2) && (working_module.substr(len-2,2) == string(".c"))) lang = lang_C; - else if ((len>2) && (working_module.substr(len-2,2) == string(".C"))) lang = lang_CPlusPlus; - else if ((len>4) && (working_module.substr(len-4,4) == string(".cpp"))) lang = lang_CPlusPlus; - else if ((len>2) && (working_module.substr(len-2,2) == string(".F"))) lang = lang_Fortran; - else if ((len>2) && (working_module.substr(len-2,2) == string(".f"))) lang = lang_Fortran; - else if ((len>3) && (working_module.substr(len-3,3) == string(".cc"))) lang = lang_C; - else if ((len>2) && (working_module.substr(len-2,2) == string(".a"))) lang = lang_Assembly; // is this right? - else if ((len>2) && (working_module.substr(len-2,2) == string(".S"))) lang = lang_Assembly; - else if ((len>2) && (working_module.substr(len-2,2) == string(".s"))) lang = lang_Assembly; - else - { - //(3) -- try to use options string -- if we have 'em - if (working_options) - { - // NOTE: a binary is labeled "gcc2_compiled" even if compiled w/g77 -- thus this is - // quite inaccurate to make such assumptions - if (strstr(working_options, "gcc")) - lang = lang_C; - else if (strstr(working_options, "g++")) - lang = lang_CPlusPlus; - } - } - // This next section tries to determine the version of the debug info generator for a - // Sun fortran compiler. Some leave the underscores on names in the debug info, and some - // have the "pretty" names, we need to detect this in order to properly read the debug. - if (working_lang == lang_Fortran) - { - if (working_options) - { - char *dbg_gen = NULL; - //cerr << FILE__ << __LINE__ << ": OPT: " << working_options << endl; - if (NULL != (dbg_gen = strstr(working_options, "DBG_GEN="))) - { - //cerr << __FILE__ << __LINE__ << ": OPT: " << dbg_gen << endl; - // Sun fortran compiler (probably), need to examine version - char *dbg_gen_ver_maj = dbg_gen + strlen("DBG_GEN="); - //cerr << __FILE__ << __LINE__ << ": OPT: " << dbg_gen_ver_maj << endl; - char *next_dot = strchr(dbg_gen_ver_maj, '.'); - if (NULL != next_dot) - { - *next_dot = '\0'; //terminate major version number string - } - } - } - } - return lang; -} - SymbolIter::SymbolIter( Object & obj ) : symbols(obj.getAllSymbols()), currentPositionInVector(0) { diff --git a/symtabAPI/src/Object.h b/symtabAPI/src/Object.h index 1c14da69ba..c81b677ee6 100644 --- a/symtabAPI/src/Object.h +++ b/symtabAPI/src/Object.h @@ -98,9 +98,6 @@ class AObject { SYMTAB_EXPORT bool getAllExceptions(std::vector&excpBlocks) const; SYMTAB_EXPORT std::vector getAllRegions() const; - SYMTAB_EXPORT supportedLanguages pickLanguage(std::string &working_module, char *working_options, - supportedLanguages working_lang); - SYMTAB_EXPORT Offset loader_off() const; SYMTAB_EXPORT unsigned loader_len() const; SYMTAB_EXPORT int getAddressWidth() const; From a5632893defd9abbaeb3a1005698bcd9bfda3b79 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 1 Feb 2023 10:35:57 -0600 Subject: [PATCH 152/505] Update detection of DWARF languages (#1357) * Remove macro checks for C and C++ These values are present in elfutils for the versions we now require (>=0.186 right now). * Add c++ 14 * Add Fortran 03,08 --- symtabAPI/src/Object-elf.C | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 896095f9cf..9eb7a1dc89 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -3239,23 +3239,20 @@ void Object::getModuleLanguageInfo(dyn_hash_map *mod case DW_LANG_C: case DW_LANG_C89: case DW_LANG_C99: -#ifdef DW_LANG_C11 case DW_LANG_C11: -#endif (*mod_langs)[working_module] = lang_C; break; case DW_LANG_C_plus_plus: -#ifdef DW_LANG_C_plus_plus_03 case DW_LANG_C_plus_plus_03: -#endif -#ifdef DW_LANG_C_plus_plus_11 case DW_LANG_C_plus_plus_11: -#endif + case DW_LANG_C_plus_plus_14: (*mod_langs)[working_module] = lang_CPlusPlus; break; case DW_LANG_Fortran77: case DW_LANG_Fortran90: case DW_LANG_Fortran95: + case DW_LANG_Fortran03: + case DW_LANG_Fortran08: (*mod_langs)[working_module] = lang_Fortran; break; default: From ac658dea96f755e21b6256f74007157be54e745e Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Thu, 9 Feb 2023 10:05:11 -0600 Subject: [PATCH 153/505] Replace DwarfWalker::findString with DwarfWalker::find_call_file (#1360) The original function was only ever used to find DW_AT_call_file. During the transition to libdw, the added check for that attribute made the rest of the string processing useless. Moreover, the code update also introduced a bug in checking the return value of dwarf_whatform which rendered the function completely useless as a generic stringform parser. --- symtabAPI/src/dwarfWalker.C | 79 ++++++++----------------------------- symtabAPI/src/dwarfWalker.h | 2 +- 2 files changed, 18 insertions(+), 63 deletions(-) diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index 3f4dc9c7ff..b662c92e1c 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -529,13 +529,13 @@ bool DwarfWalker::parseCallsite() if (!has_line) return true; - std::string inline_file; - bool result = findString(DW_AT_call_file, inline_file); - if (!result) + using opt_string = boost::optional; + opt_string inline_file = find_call_file(); + if (!inline_file) return false; Dyninst::Offset inline_line; - result = findConstant(DW_AT_call_line, inline_line, &e, dbg()); + bool result = findConstant(DW_AT_call_line, inline_line, &e, dbg()); if (!result) return false; @@ -543,7 +543,7 @@ bool DwarfWalker::parseCallsite() // cout << "Found inline call site in func (0x" << hex << id() << ") " // << curFunc()->getName() << " at " << curFunc()->getOffset() << dec // << ", file " << inline_file << ": " << inline_line << endl; - ifunc->setFile(inline_file); + ifunc->setFile(inline_file.get()); ifunc->callsite_line = inline_line; return true; } @@ -2023,65 +2023,20 @@ bool DwarfWalker::checkForConstantOrExpr(Dwarf_Half /*attr*/, return true; } -bool DwarfWalker::findString(Dwarf_Half attr, - string &str) -{ - Dwarf_Half form; - Dwarf_Attribute strattr; - +boost::optional DwarfWalker::find_call_file() { Dwarf_Die e = entry(); - if (attr == DW_AT_call_file || attr == DW_AT_decl_file) { - unsigned long line_index; - bool result = findConstant(attr, line_index, &e, dbg()); - if (!result) - return false; - StringTablePtr strs = mod()->getStrings(); - boost::unique_lock l(strs->lock); - if (line_index >= strs->size()) { - dwarf_printf("Dwarf error reading line index %lu from srcFiles(%p) of size %lu\n", - line_index, (void*)strs.get(), strs->size()); - return false; - } - // cout << "findString found " << (*srcFiles())[line_index].str << " at srcFiles[" << line_index << "] for " << mod()->fileName() << endl; - str = (*srcFiles())[line_index].str; - return true; - } - auto ret_p = dwarf_attr(&e, attr, &strattr); - if(!ret_p) return false; - form = dwarf_whatform(&strattr); - if (form != 0) { - return false; - } - - bool result; - switch (form) { - case DW_FORM_string: - { - const char *s = dwarf_formstring(&strattr); - if(!s) return false; - // cout << "findString found " << s << " in DW_FORM_string" << endl; - str = s; - result = true; - break; - } - case DW_FORM_block: - case DW_FORM_block1: - case DW_FORM_block2: - case DW_FORM_block4: - { - Dwarf_Block *block = NULL; - DWARF_FAIL_RET(dwarf_formblock(&strattr, block)); - str = (char *) block->data; - // cout << "findString found " << str << " in DW_FORM_block" << endl; - result = !str.empty(); - break; - } - default: - dwarf_printf("(0x%lx) Warning: string form not used 0x%x\n", id(), (int) form); - result = false; - break; + unsigned long line_index; + bool result = findConstant(DW_AT_call_file, line_index, &e, dbg()); + if (!result) + return {}; + StringTablePtr strs = mod()->getStrings(); + boost::unique_lock l(strs->lock); + if (line_index >= strs->size()) { + dwarf_printf("Dwarf error reading line index %lu from srcFiles(%p) of size %lu\n", + line_index, (void*)strs.get(), strs->size()); + return {}; } - return result; + return (*srcFiles())[line_index].str; } bool DwarfWalker::findConstant(Dwarf_Half attr, Address &value, Dwarf_Die *entry, Dwarf * /*dbg*/) { diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 9bd29ee74d..90c81e2ffa 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -358,7 +358,7 @@ class DwarfWalker : public DwarfParseActions { bool &constant, bool &expr, Dwarf_Half &form); - bool findString(Dwarf_Half attr, std::string &str); + boost::optional find_call_file(); public: static bool findConstant(Dwarf_Half attr, Address &value, Dwarf_Die *entry, Dwarf *dbg); static bool findConstantWithForm(Dwarf_Attribute &attr, Dwarf_Half form, From dca907291e7cfb0f7f2fd49852ffc9489de48e46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A9sz=C3=A1ros=20Gergely?= Date: Thu, 9 Feb 2023 20:01:06 +0100 Subject: [PATCH 154/505] Fix sema type for vex2 encoded vpand (#1364) The vex encoded form of VPAND takes three operands dest,src1,src2. --- common/src/arch-x86.C | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C index d955d4d0ba..de886b026b 100644 --- a/common/src/arch-x86.C +++ b/common/src/arch-x86.C @@ -6790,7 +6790,7 @@ ia32_entry sseMapMult[][3] = { e_vpminub, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, { e_vpminub, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, }, { /* SSEDB_66 */ - { e_vpand, t_done, 0, true, { Vps, Hps, Wps }, 0, s1RW2R, 0 }, + { e_vpand, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, { e_No_Entry, t_vexw, VEXW91, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_vexw, VEXW64, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSEDC_66 */ From 89e2782a1ffa784b9a022f7eefb8ad3e4bba87b6 Mon Sep 17 00:00:00 2001 From: "Jonathan R. Madsen" Date: Thu, 9 Feb 2023 13:54:47 -0600 Subject: [PATCH 155/505] Fixed nullptr issues in dyninstAPI/src/mapped_object.C (#1361) - checking whether std::string::c_str() == 0 is pointless because std::string cannot be constructed from a nullptr. use std::string::empty() - add nullptr checks in find*Vector* functions --- dyninstAPI/src/mapped_object.C | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/dyninstAPI/src/mapped_object.C b/dyninstAPI/src/mapped_object.C index ad6acf2529..a4c12f2508 100644 --- a/dyninstAPI/src/mapped_object.C +++ b/dyninstAPI/src/mapped_object.C @@ -425,7 +425,7 @@ void mapped_object::set_short_name() { const std::vector *mapped_object::findFuncVectorByPretty(const std::string &funcname) { - if (funcname.c_str() == 0) return NULL; + if (funcname.empty()) return NULL; // First, check the underlying image. const std::vector *img_funcs = parse_img()->findFuncVectorByPretty(funcname); if (img_funcs == NULL) { @@ -435,7 +435,7 @@ const std::vector *mapped_object::findFuncVectorByPretty(const assert(img_funcs->size()); // Fast path: auto iter = allFunctionsByPrettyName.find(funcname); - if (iter != allFunctionsByPrettyName.end()) { + if (iter != allFunctionsByPrettyName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the functions before (this can happen as a // side effect of adding functions). But did we get them all? std::vector *map_funcs = iter->second; @@ -460,7 +460,7 @@ const std::vector *mapped_object::findFuncVectorByPretty(const const std::vector *mapped_object::findFuncVectorByMangled(const std::string &funcname) { - if (funcname.c_str() == 0) return NULL; + if (funcname.empty()) return NULL; // First, check the underlying image. const std::vector *img_funcs = parse_img()->findFuncVectorByMangled(funcname); @@ -471,7 +471,7 @@ const std::vector *mapped_object::findFuncVectorByMangled(cons assert(img_funcs->size()); // Fast path: auto iter = allFunctionsByMangledName.find(funcname); - if (iter != allFunctionsByMangledName.end()) { + if (iter != allFunctionsByMangledName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the functions before (this can happen as a // side effect of adding functions). But did we get them all? std::vector *map_funcs = iter->second; @@ -497,7 +497,7 @@ const std::vector *mapped_object::findFuncVectorByMangled(cons const std::vector *mapped_object::findVarVectorByPretty(const std::string &varname) { - if (varname.c_str() == 0) return NULL; + if (varname.empty()) return NULL; // First, check the underlying image. const std::vector *img_vars = parse_img()->findVarVectorByPretty(varname); @@ -506,7 +506,7 @@ const std::vector *mapped_object::findVarVectorByPretty(const st assert(img_vars->size()); // Fast path: auto iter = allVarsByPrettyName.find(varname); - if (iter != allVarsByPrettyName.end()) { + if (iter != allVarsByPrettyName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the variabletions before (this can happen as a // side effect of adding variabletions). But did we get them all? std::vector *map_variables = iter->second; @@ -531,7 +531,7 @@ const std::vector *mapped_object::findVarVectorByPretty(const st const std::vector *mapped_object::findVarVectorByMangled(const std::string &varname) { - if (varname.c_str() == 0) return NULL; + if (varname.empty()) return NULL; // First, check the underlying image. const std::vector *img_vars = parse_img()->findVarVectorByMangled(varname); @@ -541,7 +541,7 @@ const std::vector *mapped_object::findVarVectorByMangled(const // Fast path: auto iter = allVarsByMangledName.find(varname); - if (iter != allVarsByMangledName.end()) { + if (iter != allVarsByMangledName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the variabletions before (this can happen as a // side effect of adding variables). But did we get them all? std::vector *map_variables = iter->second; From fd9cb3f69172b2b227a26f6f0f73d03561c5ea64 Mon Sep 17 00:00:00 2001 From: Weixiao Zhan Date: Tue, 14 Feb 2023 12:00:29 -0600 Subject: [PATCH 156/505] handle ENDBR64 --- common/h/entryIDs.h | 2 ++ common/src/arch-x86.C | 2 ++ instructionAPI/src/InstructionDecoder-x86.C | 23 +++++++++++++++++---- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index fcbc935355..df44c39b71 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -202,6 +202,8 @@ enum entryID : unsigned int { e_vdppd, // SSE 4.1 e_dpps, // SSE 4.1 e_emms, + e_endbr32, + e_endbr64, e_enter, e_enterq, e_extractps, // SSE 4.1 diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C index de886b026b..30c939600f 100644 --- a/common/src/arch-x86.C +++ b/common/src/arch-x86.C @@ -978,6 +978,8 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vdppd, "vdppd") (e_dpps, "dpps") (e_emms, "emms") + (e_endbr32, "endbr32") + (e_endbr64, "endbr64") (e_enter, "enter") (e_extractps, "extractps") (e_extrq, "extrq") diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C index 769fa4775b..3cb5723b78 100644 --- a/instructionAPI/src/InstructionDecoder-x86.C +++ b/instructionAPI/src/InstructionDecoder-x86.C @@ -1797,7 +1797,17 @@ namespace Dyninst decodedInstruction->getPrefix(), locs, m_Arch); return; } - } + } else if (decodedInstruction->getPrefix()->getPrefix(0) == PREFIX_REP && + *(b.start+1) == (unsigned char)(0x0F) && *(b.start+2) == (unsigned char)(0x1E)) { + // handling ENDBR family + if (*(b.start+3) == (unsigned char)(0xFB)) { + m_Operation = Operation(e_endbr32, entryNames_IAPI[e_endbr32], m_Arch); + return; + } else if (*(b.start+3) == (unsigned char)(0xFA)) { + m_Operation = Operation(e_endbr64, entryNames_IAPI[e_endbr64], m_Arch); + return; + } + } m_Operation = Operation(decodedInstruction->getEntry(), decodedInstruction->getPrefix(), locs, m_Arch); @@ -1831,10 +1841,15 @@ namespace Dyninst if (decodedInstruction->getEntry()->getID() == e_ret_near || decodedInstruction->getEntry()->getID() == e_ret_far) { - Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(is64BitMode ? x86_64::rsp : x86::esp), + Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(is64BitMode ? x86_64::rsp : x86::esp), is64BitMode ? u64 : u32); - insn_to_complete->addSuccessor(ret_addr, false, true, false, false); - } + insn_to_complete->addSuccessor(ret_addr, false, true, false, false); + } + if (insn_to_complete->getOperation().getID() == e_endbr32 || + insn_to_complete->getOperation().getID() == e_endbr64) { + insn_to_complete->m_Operands.clear(); + return true; + } for(int i = 0; i < 3; i++) { From fb5fdc34210c52b4bc23b3eca791bef8a0670998 Mon Sep 17 00:00:00 2001 From: Weixiao Zhan Date: Tue, 14 Feb 2023 16:17:21 -0600 Subject: [PATCH 157/505] revise space --- instructionAPI/src/InstructionDecoder-x86.C | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C index 3cb5723b78..8fec700cfb 100644 --- a/instructionAPI/src/InstructionDecoder-x86.C +++ b/instructionAPI/src/InstructionDecoder-x86.C @@ -1841,9 +1841,9 @@ namespace Dyninst if (decodedInstruction->getEntry()->getID() == e_ret_near || decodedInstruction->getEntry()->getID() == e_ret_far) { - Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(is64BitMode ? x86_64::rsp : x86::esp), + Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(is64BitMode ? x86_64::rsp : x86::esp), is64BitMode ? u64 : u32); - insn_to_complete->addSuccessor(ret_addr, false, true, false, false); + insn_to_complete->addSuccessor(ret_addr, false, true, false, false); } if (insn_to_complete->getOperation().getID() == e_endbr32 || insn_to_complete->getOperation().getID() == e_endbr64) { From 17b82b78f43169fff197c3b30020446c9b5701c5 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Wed, 15 Feb 2023 17:34:13 -0600 Subject: [PATCH 158/505] Remove use of couts in the AMDGPU instruction decoders --- .../cdna2/InstructionDecoder-amdgpu-cdna2.C | 11 +---------- .../vega/InstructionDecoder-amdgpu-vega.C | 17 +---------------- 2 files changed, 2 insertions(+), 26 deletions(-) diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C index 27b70c7eae..c17c20e6b9 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -205,8 +205,6 @@ namespace Dyninst { insn = insn_high = insn_long = 0; useImm = false; isCall = false; - if (!getenv("DEBUG_DECODE")) - cout.setstate(ios_base::badbit); } // here we assemble the first 64 bit (if available) as an instruction @@ -220,7 +218,6 @@ namespace Dyninst { imm_at_64 = get32bit(b,8); insn_long = ( ((uint64_t) insn_high) << 32) | insn; - cout << " setup insn_long = " << std::hex << insn_long << endl; } void InstructionDecoder_amdgpu_cdna2::decodeOpcode(InstructionDecoder::buffer &b) { @@ -230,9 +227,7 @@ namespace Dyninst { } void InstructionDecoder_amdgpu_cdna2::debug_instr(){ - cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family - << " length = " << insn_in_progress->size()<< endl << endl; - + // cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family << " length = " << insn_in_progress->size()<< endl << endl; } Instruction InstructionDecoder_amdgpu_cdna2::decode(InstructionDecoder::buffer &b) { @@ -242,8 +237,6 @@ namespace Dyninst { //cout << "Is Branch Instruction !! , name = " << insn_in_progress -> getOperation().mnemonic << endl; //std::mem_fun(decode_lookup_table[instr_family])(this); } - debug_instr(); - cout.clear(); b.start += insn_in_progress->size(); return *insn_in_progress; } @@ -253,8 +246,6 @@ namespace Dyninst { InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); setupInsnWord(b); mainDecode(); - debug_instr(); - cout.clear(); Instruction* iptr = const_cast(insn_to_complete); *iptr = *(insn_in_progress.get()); } diff --git a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C index 1666eb7387..449255ae00 100644 --- a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C +++ b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C @@ -389,7 +389,6 @@ namespace Dyninst { void InstructionDecoder_amdgpu_vega::finalizeVOP1Operands(){ layout_vop1 & layout = insn_layout.vop1; - //cout << " finalizing vop1 operands , vdst = " << std::dec << layout.vdst << " src0 = " << layout.src0 <appendOperand(decodeVDST(layout.vdst),false,true); insn_in_progress->appendOperand(decodeSSRC(layout.src0),true,false); @@ -408,11 +407,9 @@ namespace Dyninst { makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.ssrc0,2) ); - // TODO : addSuccessors commented out to avoid jump table analysis aborts if(insn_in_progress->getOperation().operationID == amdgpu_op_s_setpc_b64){ //RegisterAST::Ptr tmpqq = boost::dynamic_pointer_cast(new_pc_ast); - //std::cout << "setting pc to offset " << std::hex <getID()<< std::endl; // non fall through branches are added as Successor //insn_in_progress->appendOperand(new_pc_ast,true,false); insn_in_progress->addSuccessor(new_pc_ast, false, false, false, false); @@ -452,7 +449,6 @@ namespace Dyninst { if(isBranch){ if(!isModifyPC){ - //cout << "calling make branch target "<< endl; makeBranchTarget(isCall,isConditional,layout.simm16); } @@ -466,7 +462,6 @@ namespace Dyninst { if(isBranch){ if(!isModifyPC){ - //cout << "calling make branch target "<< endl; makeBranchTarget(isCall,isConditional,layout.simm16); } @@ -516,9 +511,7 @@ namespace Dyninst { offset_expr = layout.soe ? decodeSGPRorM0(layout.soffset) : Immediate::makeImmediate(Result(u64,0)); } - // cout << "layout.sbase = " << std::hex << layout.sbase << endl; //MachRegister mr = makeAmdgpuRegID(amdgpu_vega::sgpr0,4,2); - // cout << " shouldn't it be " << amdgpu_vega::sgpr_vec2_0 << " " << mr << endl; Expression::Ptr sbase_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.sbase << 1,2)); if(isScratch) offset_expr = makeMultiplyExpression(offset_expr, @@ -698,8 +691,6 @@ namespace Dyninst { insn = insn_high = insn_long = 0; useImm = false; isCall = false; - if (!getenv("DEBUG_DECODE")) - cout.setstate(ios_base::badbit); } // here we assemble the first 64 bit (if available) as an instruction @@ -721,9 +712,7 @@ namespace Dyninst { } void InstructionDecoder_amdgpu_vega::debug_instr(){ - cout << "\ndecoded instruction " << insn_in_progress->getOperation().mnemonic - << " length = " << insn_in_progress->size()<< endl; - + //cout << "\ndecoded instruction " << insn_in_progress->getOperation().mnemonic << " length = " << insn_in_progress->size()<< endl; } @@ -733,8 +722,6 @@ namespace Dyninst { if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){ std::mem_fun(decode_lookup_table[instr_family])(this); } - debug_instr(); - cout.clear(); b.start += insn_in_progress->size(); return *insn_in_progress; } @@ -743,8 +730,6 @@ namespace Dyninst { InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); setupInsnWord(b); mainDecode(b); - //debug_instr(); - cout.clear(); Instruction* iptr = const_cast(insn_to_complete); *iptr = *(insn_in_progress.get()); b.start += insn_in_progress->size(); From 54320d4d3016c654985f375bd5ea87e73c6315e6 Mon Sep 17 00:00:00 2001 From: "Weixiao.zhan" <45820168+weixiao-zhan@users.noreply.github.com> Date: Thu, 16 Feb 2023 16:41:34 -0600 Subject: [PATCH 159/505] update spack.yaml for spack v0.19.1 (#1367) --- docker/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docker/Dockerfile b/docker/Dockerfile index 8f88f1df9a..dcf34aa65d 100644 --- a/docker/Dockerfile +++ b/docker/Dockerfile @@ -110,7 +110,7 @@ COPY . /code WORKDIR /opt/dyninst-env RUN . /opt/spack/share/spack/setup-env.sh && \ spack env create -d . && \ - echo " concretization: together" >> spack.yaml && \ + echo " concretizer:\n unify: true" >> spack.yaml && \ spack env activate . && \ spack add cmake@${CMAKE_VERSION} && \ spack add perl@${PERL_VERSION} && \ From 72bc4c6de1baa151ca3941d0f63fb0a7b0925c70 Mon Sep 17 00:00:00 2001 From: Bolo -- Josef Burger Date: Fri, 17 Feb 2023 13:57:37 -0600 Subject: [PATCH 160/505] x86 8-bit immediate values were interpreted incorrectly cross-platform. (#1373) Correct interpretation of Intel instructions requires sign extension. On intel it works because chars are signed on that platform. On other platforms (arm64, powerpc64) intel code was not correctly analyzed because incorrect values were generated from 8 bit immediate constants; which were interpreted as unsigned on those systems. These changes ensure intel code will be correctly interpreted on any system, regardless of the signedness of chars. A n-way validation was used to validate this change, to ensure that correct code interpretation of (intel, arm, power) code happens on all three platforms. No other issues of this nature were located -- at this time. Jim Kupsch contributed additional correctness changes to common/src/arch-x86.C that were added to this branch/PR to fix yet more problems of this ilk. --- common/src/arch-x86.C | 10 +++++----- common/src/arch-x86.h | 3 ++- instructionAPI/h/Result.h | 5 +++-- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C index 30c939600f..e8484f52e8 100644 --- a/common/src/arch-x86.C +++ b/common/src/arch-x86.C @@ -10492,7 +10492,7 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig addr++; /* Get displacements we're going to use */ - const char* disp8 = (const char*)addr; + const signed char* disp8 = (const signed char*)addr; const short* disp16 = (const short*)addr; const int* disp32 = (const int*)addr; @@ -10677,7 +10677,7 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig } /* Update displacement pointers */ - disp8 = (const char*)addr; + disp8 = (const signed char*)addr; disp16 = (const short*)addr; disp32 = (const int*)addr; @@ -10955,7 +10955,7 @@ unsigned int ia32_decode_operands (const ia32_prefixes& pref, nib += wordSzB * addrSzAttr; if(mac) { - int offset = 0; + long offset = 0; switch(addrSzAttr) { case 1: // 16-bit offset @@ -11746,7 +11746,7 @@ int displacement(const unsigned char *instr, unsigned type) { disp = *(const int *)(instr+2); } else if (type & IS_JUMP) { if (type & REL_B) { - disp = *(const char *)(instr+1); + disp = *(const signed char *)(instr+1); } else if (type & REL_W) { disp = *(const short *)(instr+1); // skip opcode } else if (type & REL_D) { @@ -11754,7 +11754,7 @@ int displacement(const unsigned char *instr, unsigned type) { } } else if (type & IS_JCC) { if (type & REL_B) { - disp = *(const char *)(instr+1); + disp = *(const signed char *)(instr+1); } else if (type & REL_W) { disp = *(const short *)(instr+2); // skip two byte opcode } else if (type & REL_D) { diff --git a/common/src/arch-x86.h b/common/src/arch-x86.h index cf58611ad6..e6be9336e1 100644 --- a/common/src/arch-x86.h +++ b/common/src/arch-x86.h @@ -48,7 +48,8 @@ namespace NS_x86 { /* operand types */ -typedef char byte_t; /* a byte operand */ +/* signed char required for correct immediate value interpretation */ +typedef signed char byte_t; /* a byte operand */ typedef short word_t; /* a word (16-bit) operand */ typedef int dword_t; /* a double word (32-bit) operand */ diff --git a/instructionAPI/h/Result.h b/instructionAPI/h/Result.h index a8e27b67dd..19549232d3 100644 --- a/instructionAPI/h/Result.h +++ b/instructionAPI/h/Result.h @@ -56,7 +56,8 @@ namespace Dyninst { unsigned char bitval : 1; unsigned char u8val; - char s8val; + /* char can be signed or unsigned, must be signed for s8val */ + signed char s8val; uint16_t u16val; int16_t s16val; uint32_t u24val:24; @@ -132,7 +133,7 @@ namespace Dyninst }; template < > struct Result_type2type { - typedef char type; + typedef signed char type; }; template < > struct Result_type2type { From 5ad79439de5468982f9ba878e916403f2c8671ec Mon Sep 17 00:00:00 2001 From: Bolo Date: Mon, 20 Feb 2023 13:58:46 -0600 Subject: [PATCH 161/505] Prevent fallthrough analysis of amdgpu swap/set pc instructions. Both amdgpu setpc and swappc instructions are _not_ fallthrough branch instructions. We need to stop analysis at that instruction. The CDNA2 (MI200) instructions of swappc and ssetpc were missing. They have been added for similar fallthrough prevention on that architecture. --- instructionAPI/src/Instruction.C | 3 +++ 1 file changed, 3 insertions(+) diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index bcc16621bf..6f244d508b 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -540,7 +540,10 @@ namespace Dyninst case e_sysexit: case e_call: case e_syscall: + case amdgpu_op_s_setpc_b64: case amdgpu_op_s_swappc_b64: + case amdgpu_cdna2_op_S_SETPC_B64: + case amdgpu_cdna2_op_S_SWAPPC_B64: return false; case e_jnb: case e_jb: From f1987aa94789d4d2318a6db2a9edab9b303af560 Mon Sep 17 00:00:00 2001 From: Bolo Date: Tue, 21 Feb 2023 10:28:53 -0600 Subject: [PATCH 162/505] Allow CFG analysis based on instructionAPI alone w/out semantics. Dyninst can generate a CFG just based on instructions and decoding. However, up to this point if a semantics package was not available for an architecture, a non-semantics architecture would result in a panic. With this change, a warning message, similar to the crash message, is output once to allow users to know that they aren't using semantic info, and only instructionAPI itself. --- dataflowAPI/src/SymEval.C | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/dataflowAPI/src/SymEval.C b/dataflowAPI/src/SymEval.C index 89e1eea2df..68eeabcb9b 100644 --- a/dataflowAPI/src/SymEval.C +++ b/dataflowAPI/src/SymEval.C @@ -57,6 +57,9 @@ #include "boost/tuple/tuple.hpp" +/* once flag for the warning of unimplemented symbolic expansion */ +#include + using namespace std; using namespace Dyninst; using namespace InstructionAPI; @@ -536,8 +539,14 @@ bool SymEval::expandInsn(const Instruction &insn, break; } default: - assert(0 && "Unimplemented symbolic expansion architecture"); - break; + /* once per arch would be better, but ... */ + static std::once_flag arch_warning_flag; + std::call_once(arch_warning_flag, [&]{ + cerr << "Unimplemented symbolic expansion architecture: " << insn.getArch() << endl; + } + ); + return false; + break; } return true; From 6c21cc1da566466dc99d007a5ad1d1ca83cbae36 Mon Sep 17 00:00:00 2001 From: Hsuan-Heng Wu Date: Tue, 5 Jul 2022 20:24:04 -0500 Subject: [PATCH 163/505] Added support for gfx908 based on the XML-ISA-DROP for MI100 Fixed a bug in the instruction decoder that returns incorrect value on the last instruction. --- .../h/AMDGPU/gfx908/amdgpu_gfx908_op_table.h | 1216 ++ .../h/AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h | 617 + common/h/dyn_regs.h | 203 + common/h/entryIDs.h | 1 + common/src/dyn_regs.C | 81 +- dwarf/src/dwarfHandle.C | 5 +- elf/src/Elf_X.C | 4 +- instructionAPI/CMakeLists.txt | 6 +- instructionAPI/h/Instruction.h | 2 +- instructionAPI/h/Operation_impl.h | 2 +- .../cdna2/InstructionDecoder-amdgpu-cdna2.C | 3 +- .../src/AMDGPU/cdna2/finalizeOperands.C | 24 + .../gfx908/InstructionDecoder-amdgpu-gfx908.C | 261 + .../gfx908/InstructionDecoder-amdgpu-gfx908.h | 317 + .../gfx908/amdgpu_gfx908_decoder_impl.C | 2387 ++++ .../gfx908/amdgpu_gfx908_decoder_impl.h | 401 + .../AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h | 32 + .../gfx908/amdgpu_gfx908_opcode_tables.C | 2982 ++++ .../src/AMDGPU/gfx908/decodeOperands.C | 5884 ++++++++ .../src/AMDGPU/gfx908/decodeOperands.h | 41 + .../src/AMDGPU/gfx908/finalizeOperands.C | 11469 ++++++++++++++++ instructionAPI/src/Instruction.C | 2 +- instructionAPI/src/InstructionCategories.C | 1 + instructionAPI/src/InstructionDecoderImpl.C | 3 + instructionAPI/src/Register.C | 12 +- instructionAPI/src/amdgpu_branchinsn_table.h | 16 + instructionAPI/src/debug_decode.C | 77 + instructionAPI/src/debug_decode.h | 52 + parseAPI/src/IA_IAPI.C | 6 +- parseAPI/src/IA_amdgpu.C | 2 +- parseAPI/src/Parser.C | 7 + parseAPI/src/SymbolicExpression.C | 1 + proccontrol/src/process.C | 1 + 33 files changed, 26097 insertions(+), 21 deletions(-) create mode 100644 common/h/AMDGPU/gfx908/amdgpu_gfx908_op_table.h create mode 100644 common/h/AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h create mode 100644 instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C create mode 100644 instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h create mode 100644 instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C create mode 100644 instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.h create mode 100644 instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h create mode 100644 instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_opcode_tables.C create mode 100644 instructionAPI/src/AMDGPU/gfx908/decodeOperands.C create mode 100644 instructionAPI/src/AMDGPU/gfx908/decodeOperands.h create mode 100644 instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C create mode 100644 instructionAPI/src/debug_decode.C create mode 100644 instructionAPI/src/debug_decode.h diff --git a/common/h/AMDGPU/gfx908/amdgpu_gfx908_op_table.h b/common/h/AMDGPU/gfx908/amdgpu_gfx908_op_table.h new file mode 100644 index 0000000000..2c54592110 --- /dev/null +++ b/common/h/AMDGPU/gfx908/amdgpu_gfx908_op_table.h @@ -0,0 +1,1216 @@ +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD, +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_AND, +amdgpu_gfx908_op_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_DEC, +amdgpu_gfx908_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_INC, +amdgpu_gfx908_op_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_OR, +amdgpu_gfx908_op_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SUB, +amdgpu_gfx908_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP, +amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_XOR, +amdgpu_gfx908_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx908_op_BUFFER_LOAD_DWORD, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX2, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX3, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX4, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16, +amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_SSHORT, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_USHORT, +amdgpu_gfx908_op_BUFFER_STORE_BYTE, +amdgpu_gfx908_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_STORE_DWORD, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX2, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX3, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX4, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XY, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx908_op_BUFFER_STORE_LDS_DWORD, +amdgpu_gfx908_op_BUFFER_STORE_SHORT, +amdgpu_gfx908_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_BUFFER_WBINVL1, +amdgpu_gfx908_op_BUFFER_WBINVL1_VOL, +amdgpu_gfx908_op_DS_ADD_F32, +amdgpu_gfx908_op_DS_ADD_RTN_F32, +amdgpu_gfx908_op_DS_ADD_RTN_U32, +amdgpu_gfx908_op_DS_ADD_RTN_U64, +amdgpu_gfx908_op_DS_ADD_SRC2_F32, +amdgpu_gfx908_op_DS_ADD_SRC2_U32, +amdgpu_gfx908_op_DS_ADD_SRC2_U64, +amdgpu_gfx908_op_DS_ADD_U32, +amdgpu_gfx908_op_DS_ADD_U64, +amdgpu_gfx908_op_DS_AND_B32, +amdgpu_gfx908_op_DS_AND_B64, +amdgpu_gfx908_op_DS_AND_RTN_B32, +amdgpu_gfx908_op_DS_AND_RTN_B64, +amdgpu_gfx908_op_DS_AND_SRC2_B32, +amdgpu_gfx908_op_DS_AND_SRC2_B64, +amdgpu_gfx908_op_DS_APPEND, +amdgpu_gfx908_op_DS_BPERMUTE_B32, +amdgpu_gfx908_op_DS_CMPST_B32, +amdgpu_gfx908_op_DS_CMPST_B64, +amdgpu_gfx908_op_DS_CMPST_F32, +amdgpu_gfx908_op_DS_CMPST_F64, +amdgpu_gfx908_op_DS_CMPST_RTN_B32, +amdgpu_gfx908_op_DS_CMPST_RTN_B64, +amdgpu_gfx908_op_DS_CMPST_RTN_F32, +amdgpu_gfx908_op_DS_CMPST_RTN_F64, +amdgpu_gfx908_op_DS_CONDXCHG32_RTN_B64, +amdgpu_gfx908_op_DS_CONSUME, +amdgpu_gfx908_op_DS_DEC_RTN_U32, +amdgpu_gfx908_op_DS_DEC_RTN_U64, +amdgpu_gfx908_op_DS_DEC_SRC2_U32, +amdgpu_gfx908_op_DS_DEC_SRC2_U64, +amdgpu_gfx908_op_DS_DEC_U32, +amdgpu_gfx908_op_DS_DEC_U64, +amdgpu_gfx908_op_DS_GWS_BARRIER, +amdgpu_gfx908_op_DS_GWS_INIT, +amdgpu_gfx908_op_DS_GWS_SEMA_BR, +amdgpu_gfx908_op_DS_GWS_SEMA_P, +amdgpu_gfx908_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_gfx908_op_DS_GWS_SEMA_V, +amdgpu_gfx908_op_DS_INC_RTN_U32, +amdgpu_gfx908_op_DS_INC_RTN_U64, +amdgpu_gfx908_op_DS_INC_SRC2_U32, +amdgpu_gfx908_op_DS_INC_SRC2_U64, +amdgpu_gfx908_op_DS_INC_U32, +amdgpu_gfx908_op_DS_INC_U64, +amdgpu_gfx908_op_DS_MAX_F32, +amdgpu_gfx908_op_DS_MAX_F64, +amdgpu_gfx908_op_DS_MAX_I32, +amdgpu_gfx908_op_DS_MAX_I64, +amdgpu_gfx908_op_DS_MAX_RTN_F32, +amdgpu_gfx908_op_DS_MAX_RTN_F64, +amdgpu_gfx908_op_DS_MAX_RTN_I32, +amdgpu_gfx908_op_DS_MAX_RTN_I64, +amdgpu_gfx908_op_DS_MAX_RTN_U32, +amdgpu_gfx908_op_DS_MAX_RTN_U64, +amdgpu_gfx908_op_DS_MAX_SRC2_F32, +amdgpu_gfx908_op_DS_MAX_SRC2_F64, +amdgpu_gfx908_op_DS_MAX_SRC2_I32, +amdgpu_gfx908_op_DS_MAX_SRC2_I64, +amdgpu_gfx908_op_DS_MAX_SRC2_U32, +amdgpu_gfx908_op_DS_MAX_SRC2_U64, +amdgpu_gfx908_op_DS_MAX_U32, +amdgpu_gfx908_op_DS_MAX_U64, +amdgpu_gfx908_op_DS_MIN_F32, +amdgpu_gfx908_op_DS_MIN_F64, +amdgpu_gfx908_op_DS_MIN_I32, +amdgpu_gfx908_op_DS_MIN_I64, +amdgpu_gfx908_op_DS_MIN_RTN_F32, +amdgpu_gfx908_op_DS_MIN_RTN_F64, +amdgpu_gfx908_op_DS_MIN_RTN_I32, +amdgpu_gfx908_op_DS_MIN_RTN_I64, +amdgpu_gfx908_op_DS_MIN_RTN_U32, +amdgpu_gfx908_op_DS_MIN_RTN_U64, +amdgpu_gfx908_op_DS_MIN_SRC2_F32, +amdgpu_gfx908_op_DS_MIN_SRC2_F64, +amdgpu_gfx908_op_DS_MIN_SRC2_I32, +amdgpu_gfx908_op_DS_MIN_SRC2_I64, +amdgpu_gfx908_op_DS_MIN_SRC2_U32, +amdgpu_gfx908_op_DS_MIN_SRC2_U64, +amdgpu_gfx908_op_DS_MIN_U32, +amdgpu_gfx908_op_DS_MIN_U64, +amdgpu_gfx908_op_DS_MSKOR_B32, +amdgpu_gfx908_op_DS_MSKOR_B64, +amdgpu_gfx908_op_DS_MSKOR_RTN_B32, +amdgpu_gfx908_op_DS_MSKOR_RTN_B64, +amdgpu_gfx908_op_DS_NOP, +amdgpu_gfx908_op_DS_ORDERED_COUNT, +amdgpu_gfx908_op_DS_OR_B32, +amdgpu_gfx908_op_DS_OR_B64, +amdgpu_gfx908_op_DS_OR_RTN_B32, +amdgpu_gfx908_op_DS_OR_RTN_B64, +amdgpu_gfx908_op_DS_OR_SRC2_B32, +amdgpu_gfx908_op_DS_OR_SRC2_B64, +amdgpu_gfx908_op_DS_PERMUTE_B32, +amdgpu_gfx908_op_DS_READ2ST64_B32, +amdgpu_gfx908_op_DS_READ2ST64_B64, +amdgpu_gfx908_op_DS_READ2_B32, +amdgpu_gfx908_op_DS_READ2_B64, +amdgpu_gfx908_op_DS_READ_ADDTID_B32, +amdgpu_gfx908_op_DS_READ_B128, +amdgpu_gfx908_op_DS_READ_B32, +amdgpu_gfx908_op_DS_READ_B64, +amdgpu_gfx908_op_DS_READ_B96, +amdgpu_gfx908_op_DS_READ_I16, +amdgpu_gfx908_op_DS_READ_I8, +amdgpu_gfx908_op_DS_READ_I8_D16, +amdgpu_gfx908_op_DS_READ_I8_D16_HI, +amdgpu_gfx908_op_DS_READ_U16, +amdgpu_gfx908_op_DS_READ_U16_D16, +amdgpu_gfx908_op_DS_READ_U16_D16_HI, +amdgpu_gfx908_op_DS_READ_U8, +amdgpu_gfx908_op_DS_READ_U8_D16, +amdgpu_gfx908_op_DS_READ_U8_D16_HI, +amdgpu_gfx908_op_DS_RSUB_RTN_U32, +amdgpu_gfx908_op_DS_RSUB_RTN_U64, +amdgpu_gfx908_op_DS_RSUB_SRC2_U32, +amdgpu_gfx908_op_DS_RSUB_SRC2_U64, +amdgpu_gfx908_op_DS_RSUB_U32, +amdgpu_gfx908_op_DS_RSUB_U64, +amdgpu_gfx908_op_DS_SUB_RTN_U32, +amdgpu_gfx908_op_DS_SUB_RTN_U64, +amdgpu_gfx908_op_DS_SUB_SRC2_U32, +amdgpu_gfx908_op_DS_SUB_SRC2_U64, +amdgpu_gfx908_op_DS_SUB_U32, +amdgpu_gfx908_op_DS_SUB_U64, +amdgpu_gfx908_op_DS_SWIZZLE_B32, +amdgpu_gfx908_op_DS_WRAP_RTN_B32, +amdgpu_gfx908_op_DS_WRITE2ST64_B32, +amdgpu_gfx908_op_DS_WRITE2ST64_B64, +amdgpu_gfx908_op_DS_WRITE2_B32, +amdgpu_gfx908_op_DS_WRITE2_B64, +amdgpu_gfx908_op_DS_WRITE_ADDTID_B32, +amdgpu_gfx908_op_DS_WRITE_B128, +amdgpu_gfx908_op_DS_WRITE_B16, +amdgpu_gfx908_op_DS_WRITE_B16_D16_HI, +amdgpu_gfx908_op_DS_WRITE_B32, +amdgpu_gfx908_op_DS_WRITE_B64, +amdgpu_gfx908_op_DS_WRITE_B8, +amdgpu_gfx908_op_DS_WRITE_B8_D16_HI, +amdgpu_gfx908_op_DS_WRITE_B96, +amdgpu_gfx908_op_DS_WRITE_SRC2_B32, +amdgpu_gfx908_op_DS_WRITE_SRC2_B64, +amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_gfx908_op_DS_WRXCHG2_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG2_RTN_B64, +amdgpu_gfx908_op_DS_WRXCHG_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG_RTN_B64, +amdgpu_gfx908_op_DS_XOR_B32, +amdgpu_gfx908_op_DS_XOR_B64, +amdgpu_gfx908_op_DS_XOR_RTN_B32, +amdgpu_gfx908_op_DS_XOR_RTN_B64, +amdgpu_gfx908_op_DS_XOR_SRC2_B32, +amdgpu_gfx908_op_DS_XOR_SRC2_B64, +amdgpu_gfx908_op_EXP, +amdgpu_gfx908_op_FLAT_ATOMIC_ADD, +amdgpu_gfx908_op_FLAT_ATOMIC_ADD_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_AND, +amdgpu_gfx908_op_FLAT_ATOMIC_AND_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_DEC, +amdgpu_gfx908_op_FLAT_ATOMIC_DEC_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_INC, +amdgpu_gfx908_op_FLAT_ATOMIC_INC_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_OR, +amdgpu_gfx908_op_FLAT_ATOMIC_OR_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SMAX, +amdgpu_gfx908_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SMIN, +amdgpu_gfx908_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SUB, +amdgpu_gfx908_op_FLAT_ATOMIC_SUB_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SWAP, +amdgpu_gfx908_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_UMAX, +amdgpu_gfx908_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_UMIN, +amdgpu_gfx908_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_XOR, +amdgpu_gfx908_op_FLAT_ATOMIC_XOR_X2, +amdgpu_gfx908_op_FLAT_LOAD_DWORD, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX2, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX3, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX4, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16, +amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_SSHORT, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_USHORT, +amdgpu_gfx908_op_FLAT_STORE_BYTE, +amdgpu_gfx908_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_FLAT_STORE_DWORD, +amdgpu_gfx908_op_FLAT_STORE_DWORDX2, +amdgpu_gfx908_op_FLAT_STORE_DWORDX3, +amdgpu_gfx908_op_FLAT_STORE_DWORDX4, +amdgpu_gfx908_op_FLAT_STORE_SHORT, +amdgpu_gfx908_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_AND, +amdgpu_gfx908_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC, +amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_INC, +amdgpu_gfx908_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_OR, +amdgpu_gfx908_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR, +amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORD, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX2, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX3, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX4, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_SSHORT, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_USHORT, +amdgpu_gfx908_op_GLOBAL_STORE_BYTE, +amdgpu_gfx908_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_STORE_DWORD, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX2, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX3, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX4, +amdgpu_gfx908_op_GLOBAL_STORE_SHORT, +amdgpu_gfx908_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_IMAGE_ATOMIC_ADD, +amdgpu_gfx908_op_IMAGE_ATOMIC_AND, +amdgpu_gfx908_op_IMAGE_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_IMAGE_ATOMIC_DEC, +amdgpu_gfx908_op_IMAGE_ATOMIC_INC, +amdgpu_gfx908_op_IMAGE_ATOMIC_OR, +amdgpu_gfx908_op_IMAGE_ATOMIC_SMAX, +amdgpu_gfx908_op_IMAGE_ATOMIC_SMIN, +amdgpu_gfx908_op_IMAGE_ATOMIC_SUB, +amdgpu_gfx908_op_IMAGE_ATOMIC_SWAP, +amdgpu_gfx908_op_IMAGE_ATOMIC_UMAX, +amdgpu_gfx908_op_IMAGE_ATOMIC_UMIN, +amdgpu_gfx908_op_IMAGE_ATOMIC_XOR, +amdgpu_gfx908_op_IMAGE_GATHER4, +amdgpu_gfx908_op_IMAGE_GATHER4H, +amdgpu_gfx908_op_IMAGE_GATHER4H_PCK, +amdgpu_gfx908_op_IMAGE_GATHER4_B, +amdgpu_gfx908_op_IMAGE_GATHER4_B_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_B_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_B_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C, +amdgpu_gfx908_op_IMAGE_GATHER4_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_C_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_L, +amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ, +amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_L_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_O, +amdgpu_gfx908_op_IMAGE_GATHER4_L, +amdgpu_gfx908_op_IMAGE_GATHER4_LZ, +amdgpu_gfx908_op_IMAGE_GATHER4_LZ_O, +amdgpu_gfx908_op_IMAGE_GATHER4_L_O, +amdgpu_gfx908_op_IMAGE_GATHER4_O, +amdgpu_gfx908_op_IMAGE_GATHER8H_PCK, +amdgpu_gfx908_op_IMAGE_GET_LOD, +amdgpu_gfx908_op_IMAGE_GET_RESINFO, +amdgpu_gfx908_op_IMAGE_LOAD, +amdgpu_gfx908_op_IMAGE_LOAD_MIP, +amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK, +amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK_SGN, +amdgpu_gfx908_op_IMAGE_LOAD_PCK, +amdgpu_gfx908_op_IMAGE_LOAD_PCK_SGN, +amdgpu_gfx908_op_IMAGE_SAMPLE, +amdgpu_gfx908_op_IMAGE_SAMPLE_B, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_L, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_L_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_D, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_L, +amdgpu_gfx908_op_IMAGE_SAMPLE_LZ, +amdgpu_gfx908_op_IMAGE_SAMPLE_LZ_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_L_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_O, +amdgpu_gfx908_op_IMAGE_STORE, +amdgpu_gfx908_op_IMAGE_STORE_MIP, +amdgpu_gfx908_op_IMAGE_STORE_MIP_PCK, +amdgpu_gfx908_op_IMAGE_STORE_PCK, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORD, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX3, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_SSHORT, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_USHORT, +amdgpu_gfx908_op_SCRATCH_STORE_BYTE, +amdgpu_gfx908_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_STORE_DWORD, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX2, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX3, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX4, +amdgpu_gfx908_op_SCRATCH_STORE_SHORT, +amdgpu_gfx908_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_S_ABSDIFF_I32, +amdgpu_gfx908_op_S_ABS_I32, +amdgpu_gfx908_op_S_ADDC_U32, +amdgpu_gfx908_op_S_ADDK_I32, +amdgpu_gfx908_op_S_ADD_I32, +amdgpu_gfx908_op_S_ADD_U32, +amdgpu_gfx908_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ANDN1_WREXEC_B64, +amdgpu_gfx908_op_S_ANDN2_B32, +amdgpu_gfx908_op_S_ANDN2_B64, +amdgpu_gfx908_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ANDN2_WREXEC_B64, +amdgpu_gfx908_op_S_AND_B32, +amdgpu_gfx908_op_S_AND_B64, +amdgpu_gfx908_op_S_AND_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ASHR_I32, +amdgpu_gfx908_op_S_ASHR_I64, +amdgpu_gfx908_op_S_ATC_PROBE, +amdgpu_gfx908_op_S_ATC_PROBE_BUFFER, +amdgpu_gfx908_op_S_ATOMIC_ADD, +amdgpu_gfx908_op_S_ATOMIC_ADD_X2, +amdgpu_gfx908_op_S_ATOMIC_AND, +amdgpu_gfx908_op_S_ATOMIC_AND_X2, +amdgpu_gfx908_op_S_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_S_ATOMIC_DEC, +amdgpu_gfx908_op_S_ATOMIC_DEC_X2, +amdgpu_gfx908_op_S_ATOMIC_INC, +amdgpu_gfx908_op_S_ATOMIC_INC_X2, +amdgpu_gfx908_op_S_ATOMIC_OR, +amdgpu_gfx908_op_S_ATOMIC_OR_X2, +amdgpu_gfx908_op_S_ATOMIC_SMAX, +amdgpu_gfx908_op_S_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_S_ATOMIC_SMIN, +amdgpu_gfx908_op_S_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_S_ATOMIC_SUB, +amdgpu_gfx908_op_S_ATOMIC_SUB_X2, +amdgpu_gfx908_op_S_ATOMIC_SWAP, +amdgpu_gfx908_op_S_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_S_ATOMIC_UMAX, +amdgpu_gfx908_op_S_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_S_ATOMIC_UMIN, +amdgpu_gfx908_op_S_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_S_ATOMIC_XOR, +amdgpu_gfx908_op_S_ATOMIC_XOR_X2, +amdgpu_gfx908_op_S_BARRIER, +amdgpu_gfx908_op_S_BCNT0_I32_B32, +amdgpu_gfx908_op_S_BCNT0_I32_B64, +amdgpu_gfx908_op_S_BCNT1_I32_B32, +amdgpu_gfx908_op_S_BCNT1_I32_B64, +amdgpu_gfx908_op_S_BFE_I32, +amdgpu_gfx908_op_S_BFE_I64, +amdgpu_gfx908_op_S_BFE_U32, +amdgpu_gfx908_op_S_BFE_U64, +amdgpu_gfx908_op_S_BFM_B32, +amdgpu_gfx908_op_S_BFM_B64, +amdgpu_gfx908_op_S_BITCMP0_B32, +amdgpu_gfx908_op_S_BITCMP0_B64, +amdgpu_gfx908_op_S_BITCMP1_B32, +amdgpu_gfx908_op_S_BITCMP1_B64, +amdgpu_gfx908_op_S_BITREPLICATE_B64_B32, +amdgpu_gfx908_op_S_BITSET0_B32, +amdgpu_gfx908_op_S_BITSET0_B64, +amdgpu_gfx908_op_S_BITSET1_B32, +amdgpu_gfx908_op_S_BITSET1_B64, +amdgpu_gfx908_op_S_BRANCH, +amdgpu_gfx908_op_S_BREV_B32, +amdgpu_gfx908_op_S_BREV_B64, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORD, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORD, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX2, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX4, +amdgpu_gfx908_op_S_CALL_B64, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_gfx908_op_S_CBRANCH_CDBGUSER, +amdgpu_gfx908_op_S_CBRANCH_EXECNZ, +amdgpu_gfx908_op_S_CBRANCH_EXECZ, +amdgpu_gfx908_op_S_CBRANCH_G_FORK, +amdgpu_gfx908_op_S_CBRANCH_I_FORK, +amdgpu_gfx908_op_S_CBRANCH_JOIN, +amdgpu_gfx908_op_S_CBRANCH_SCC0, +amdgpu_gfx908_op_S_CBRANCH_SCC1, +amdgpu_gfx908_op_S_CBRANCH_VCCNZ, +amdgpu_gfx908_op_S_CBRANCH_VCCZ, +amdgpu_gfx908_op_S_CMOVK_I32, +amdgpu_gfx908_op_S_CMOV_B32, +amdgpu_gfx908_op_S_CMOV_B64, +amdgpu_gfx908_op_S_CMPK_EQ_I32, +amdgpu_gfx908_op_S_CMPK_EQ_U32, +amdgpu_gfx908_op_S_CMPK_GE_I32, +amdgpu_gfx908_op_S_CMPK_GE_U32, +amdgpu_gfx908_op_S_CMPK_GT_I32, +amdgpu_gfx908_op_S_CMPK_GT_U32, +amdgpu_gfx908_op_S_CMPK_LE_I32, +amdgpu_gfx908_op_S_CMPK_LE_U32, +amdgpu_gfx908_op_S_CMPK_LG_I32, +amdgpu_gfx908_op_S_CMPK_LG_U32, +amdgpu_gfx908_op_S_CMPK_LT_I32, +amdgpu_gfx908_op_S_CMPK_LT_U32, +amdgpu_gfx908_op_S_CMP_EQ_I32, +amdgpu_gfx908_op_S_CMP_EQ_U32, +amdgpu_gfx908_op_S_CMP_EQ_U64, +amdgpu_gfx908_op_S_CMP_GE_I32, +amdgpu_gfx908_op_S_CMP_GE_U32, +amdgpu_gfx908_op_S_CMP_GT_I32, +amdgpu_gfx908_op_S_CMP_GT_U32, +amdgpu_gfx908_op_S_CMP_LE_I32, +amdgpu_gfx908_op_S_CMP_LE_U32, +amdgpu_gfx908_op_S_CMP_LG_I32, +amdgpu_gfx908_op_S_CMP_LG_U32, +amdgpu_gfx908_op_S_CMP_LG_U64, +amdgpu_gfx908_op_S_CMP_LT_I32, +amdgpu_gfx908_op_S_CMP_LT_U32, +amdgpu_gfx908_op_S_CSELECT_B32, +amdgpu_gfx908_op_S_CSELECT_B64, +amdgpu_gfx908_op_S_DCACHE_DISCARD, +amdgpu_gfx908_op_S_DCACHE_DISCARD_X2, +amdgpu_gfx908_op_S_DCACHE_INV, +amdgpu_gfx908_op_S_DCACHE_INV_VOL, +amdgpu_gfx908_op_S_DCACHE_WB, +amdgpu_gfx908_op_S_DCACHE_WB_VOL, +amdgpu_gfx908_op_S_DECPERFLEVEL, +amdgpu_gfx908_op_S_ENDPGM, +amdgpu_gfx908_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_gfx908_op_S_ENDPGM_SAVED, +amdgpu_gfx908_op_S_FF0_I32_B32, +amdgpu_gfx908_op_S_FF0_I32_B64, +amdgpu_gfx908_op_S_FF1_I32_B32, +amdgpu_gfx908_op_S_FF1_I32_B64, +amdgpu_gfx908_op_S_FLBIT_I32, +amdgpu_gfx908_op_S_FLBIT_I32_B32, +amdgpu_gfx908_op_S_FLBIT_I32_B64, +amdgpu_gfx908_op_S_FLBIT_I32_I64, +amdgpu_gfx908_op_S_GETPC_B64, +amdgpu_gfx908_op_S_GETREG_B32, +amdgpu_gfx908_op_S_ICACHE_INV, +amdgpu_gfx908_op_S_INCPERFLEVEL, +amdgpu_gfx908_op_S_LOAD_DWORD, +amdgpu_gfx908_op_S_LOAD_DWORDX16, +amdgpu_gfx908_op_S_LOAD_DWORDX2, +amdgpu_gfx908_op_S_LOAD_DWORDX4, +amdgpu_gfx908_op_S_LOAD_DWORDX8, +amdgpu_gfx908_op_S_LSHL1_ADD_U32, +amdgpu_gfx908_op_S_LSHL2_ADD_U32, +amdgpu_gfx908_op_S_LSHL3_ADD_U32, +amdgpu_gfx908_op_S_LSHL4_ADD_U32, +amdgpu_gfx908_op_S_LSHL_B32, +amdgpu_gfx908_op_S_LSHL_B64, +amdgpu_gfx908_op_S_LSHR_B32, +amdgpu_gfx908_op_S_LSHR_B64, +amdgpu_gfx908_op_S_MAX_I32, +amdgpu_gfx908_op_S_MAX_U32, +amdgpu_gfx908_op_S_MEMREALTIME, +amdgpu_gfx908_op_S_MEMTIME, +amdgpu_gfx908_op_S_MIN_I32, +amdgpu_gfx908_op_S_MIN_U32, +amdgpu_gfx908_op_S_MOVK_I32, +amdgpu_gfx908_op_S_MOVRELD_B32, +amdgpu_gfx908_op_S_MOVRELD_B64, +amdgpu_gfx908_op_S_MOVRELS_B32, +amdgpu_gfx908_op_S_MOVRELS_B64, +amdgpu_gfx908_op_S_MOV_B32, +amdgpu_gfx908_op_S_MOV_B64, +amdgpu_gfx908_op_S_MULK_I32, +amdgpu_gfx908_op_S_MUL_HI_I32, +amdgpu_gfx908_op_S_MUL_HI_U32, +amdgpu_gfx908_op_S_MUL_I32, +amdgpu_gfx908_op_S_NAND_B32, +amdgpu_gfx908_op_S_NAND_B64, +amdgpu_gfx908_op_S_NAND_SAVEEXEC_B64, +amdgpu_gfx908_op_S_NOP, +amdgpu_gfx908_op_S_NOR_B32, +amdgpu_gfx908_op_S_NOR_B64, +amdgpu_gfx908_op_S_NOR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_NOT_B32, +amdgpu_gfx908_op_S_NOT_B64, +amdgpu_gfx908_op_S_ORN1_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ORN2_B32, +amdgpu_gfx908_op_S_ORN2_B64, +amdgpu_gfx908_op_S_ORN2_SAVEEXEC_B64, +amdgpu_gfx908_op_S_OR_B32, +amdgpu_gfx908_op_S_OR_B64, +amdgpu_gfx908_op_S_OR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_PACK_HH_B32_B16, +amdgpu_gfx908_op_S_PACK_LH_B32_B16, +amdgpu_gfx908_op_S_PACK_LL_B32_B16, +amdgpu_gfx908_op_S_QUADMASK_B32, +amdgpu_gfx908_op_S_QUADMASK_B64, +amdgpu_gfx908_op_S_RFE_B64, +amdgpu_gfx908_op_S_RFE_RESTORE_B64, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORD, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORD, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_gfx908_op_S_SENDMSG, +amdgpu_gfx908_op_S_SENDMSGHALT, +amdgpu_gfx908_op_S_SETHALT, +amdgpu_gfx908_op_S_SETKILL, +amdgpu_gfx908_op_S_SETPC_B64, +amdgpu_gfx908_op_S_SETPRIO, +amdgpu_gfx908_op_S_SETREG_B32, +amdgpu_gfx908_op_S_SETREG_IMM32_B32, +amdgpu_gfx908_op_S_SETVSKIP, +amdgpu_gfx908_op_S_SET_GPR_IDX_IDX, +amdgpu_gfx908_op_S_SET_GPR_IDX_MODE, +amdgpu_gfx908_op_S_SET_GPR_IDX_OFF, +amdgpu_gfx908_op_S_SET_GPR_IDX_ON, +amdgpu_gfx908_op_S_SEXT_I32_I16, +amdgpu_gfx908_op_S_SEXT_I32_I8, +amdgpu_gfx908_op_S_SLEEP, +amdgpu_gfx908_op_S_STORE_DWORD, +amdgpu_gfx908_op_S_STORE_DWORDX2, +amdgpu_gfx908_op_S_STORE_DWORDX4, +amdgpu_gfx908_op_S_SUBB_U32, +amdgpu_gfx908_op_S_SUB_I32, +amdgpu_gfx908_op_S_SUB_U32, +amdgpu_gfx908_op_S_SWAPPC_B64, +amdgpu_gfx908_op_S_TRAP, +amdgpu_gfx908_op_S_TTRACEDATA, +amdgpu_gfx908_op_S_WAITCNT, +amdgpu_gfx908_op_S_WAKEUP, +amdgpu_gfx908_op_S_WQM_B32, +amdgpu_gfx908_op_S_WQM_B64, +amdgpu_gfx908_op_S_XNOR_B32, +amdgpu_gfx908_op_S_XNOR_B64, +amdgpu_gfx908_op_S_XNOR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_XOR_B32, +amdgpu_gfx908_op_S_XOR_B64, +amdgpu_gfx908_op_S_XOR_SAVEEXEC_B64, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_X, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx908_op_V_ACCVGPR_READ, +amdgpu_gfx908_op_V_ACCVGPR_WRITE, +amdgpu_gfx908_op_V_ADD3_U32, +amdgpu_gfx908_op_V_ADDC_CO_U32, +amdgpu_gfx908_op_V_ADD_CO_U32, +amdgpu_gfx908_op_V_ADD_F16, +amdgpu_gfx908_op_V_ADD_F32, +amdgpu_gfx908_op_V_ADD_F64, +amdgpu_gfx908_op_V_ADD_I16, +amdgpu_gfx908_op_V_ADD_I32, +amdgpu_gfx908_op_V_ADD_LSHL_U32, +amdgpu_gfx908_op_V_ADD_U16, +amdgpu_gfx908_op_V_ADD_U32, +amdgpu_gfx908_op_V_ALIGNBIT_B32, +amdgpu_gfx908_op_V_ALIGNBYTE_B32, +amdgpu_gfx908_op_V_AND_B32, +amdgpu_gfx908_op_V_AND_OR_B32, +amdgpu_gfx908_op_V_ASHRREV_I16, +amdgpu_gfx908_op_V_ASHRREV_I32, +amdgpu_gfx908_op_V_ASHRREV_I64, +amdgpu_gfx908_op_V_BCNT_U32_B32, +amdgpu_gfx908_op_V_BFE_I32, +amdgpu_gfx908_op_V_BFE_U32, +amdgpu_gfx908_op_V_BFI_B32, +amdgpu_gfx908_op_V_BFM_B32, +amdgpu_gfx908_op_V_BFREV_B32, +amdgpu_gfx908_op_V_CEIL_F16, +amdgpu_gfx908_op_V_CEIL_F32, +amdgpu_gfx908_op_V_CEIL_F64, +amdgpu_gfx908_op_V_CLREXCP, +amdgpu_gfx908_op_V_CMPX_CLASS_F16, +amdgpu_gfx908_op_V_CMPX_CLASS_F32, +amdgpu_gfx908_op_V_CMPX_CLASS_F64, +amdgpu_gfx908_op_V_CMPX_EQ_F16, +amdgpu_gfx908_op_V_CMPX_EQ_F32, +amdgpu_gfx908_op_V_CMPX_EQ_F64, +amdgpu_gfx908_op_V_CMPX_EQ_I16, +amdgpu_gfx908_op_V_CMPX_EQ_I32, +amdgpu_gfx908_op_V_CMPX_EQ_I64, +amdgpu_gfx908_op_V_CMPX_EQ_U16, +amdgpu_gfx908_op_V_CMPX_EQ_U32, +amdgpu_gfx908_op_V_CMPX_EQ_U64, +amdgpu_gfx908_op_V_CMPX_F_F16, +amdgpu_gfx908_op_V_CMPX_F_F32, +amdgpu_gfx908_op_V_CMPX_F_F64, +amdgpu_gfx908_op_V_CMPX_F_I16, +amdgpu_gfx908_op_V_CMPX_F_I32, +amdgpu_gfx908_op_V_CMPX_F_I64, +amdgpu_gfx908_op_V_CMPX_F_U16, +amdgpu_gfx908_op_V_CMPX_F_U32, +amdgpu_gfx908_op_V_CMPX_F_U64, +amdgpu_gfx908_op_V_CMPX_GE_F16, +amdgpu_gfx908_op_V_CMPX_GE_F32, +amdgpu_gfx908_op_V_CMPX_GE_F64, +amdgpu_gfx908_op_V_CMPX_GE_I16, +amdgpu_gfx908_op_V_CMPX_GE_I32, +amdgpu_gfx908_op_V_CMPX_GE_I64, +amdgpu_gfx908_op_V_CMPX_GE_U16, +amdgpu_gfx908_op_V_CMPX_GE_U32, +amdgpu_gfx908_op_V_CMPX_GE_U64, +amdgpu_gfx908_op_V_CMPX_GT_F16, +amdgpu_gfx908_op_V_CMPX_GT_F32, +amdgpu_gfx908_op_V_CMPX_GT_F64, +amdgpu_gfx908_op_V_CMPX_GT_I16, +amdgpu_gfx908_op_V_CMPX_GT_I32, +amdgpu_gfx908_op_V_CMPX_GT_I64, +amdgpu_gfx908_op_V_CMPX_GT_U16, +amdgpu_gfx908_op_V_CMPX_GT_U32, +amdgpu_gfx908_op_V_CMPX_GT_U64, +amdgpu_gfx908_op_V_CMPX_LE_F16, +amdgpu_gfx908_op_V_CMPX_LE_F32, +amdgpu_gfx908_op_V_CMPX_LE_F64, +amdgpu_gfx908_op_V_CMPX_LE_I16, +amdgpu_gfx908_op_V_CMPX_LE_I32, +amdgpu_gfx908_op_V_CMPX_LE_I64, +amdgpu_gfx908_op_V_CMPX_LE_U16, +amdgpu_gfx908_op_V_CMPX_LE_U32, +amdgpu_gfx908_op_V_CMPX_LE_U64, +amdgpu_gfx908_op_V_CMPX_LG_F16, +amdgpu_gfx908_op_V_CMPX_LG_F32, +amdgpu_gfx908_op_V_CMPX_LG_F64, +amdgpu_gfx908_op_V_CMPX_LT_F16, +amdgpu_gfx908_op_V_CMPX_LT_F32, +amdgpu_gfx908_op_V_CMPX_LT_F64, +amdgpu_gfx908_op_V_CMPX_LT_I16, +amdgpu_gfx908_op_V_CMPX_LT_I32, +amdgpu_gfx908_op_V_CMPX_LT_I64, +amdgpu_gfx908_op_V_CMPX_LT_U16, +amdgpu_gfx908_op_V_CMPX_LT_U32, +amdgpu_gfx908_op_V_CMPX_LT_U64, +amdgpu_gfx908_op_V_CMPX_NEQ_F16, +amdgpu_gfx908_op_V_CMPX_NEQ_F32, +amdgpu_gfx908_op_V_CMPX_NEQ_F64, +amdgpu_gfx908_op_V_CMPX_NE_I16, +amdgpu_gfx908_op_V_CMPX_NE_I32, +amdgpu_gfx908_op_V_CMPX_NE_I64, +amdgpu_gfx908_op_V_CMPX_NE_U16, +amdgpu_gfx908_op_V_CMPX_NE_U32, +amdgpu_gfx908_op_V_CMPX_NE_U64, +amdgpu_gfx908_op_V_CMPX_NGE_F16, +amdgpu_gfx908_op_V_CMPX_NGE_F32, +amdgpu_gfx908_op_V_CMPX_NGE_F64, +amdgpu_gfx908_op_V_CMPX_NGT_F16, +amdgpu_gfx908_op_V_CMPX_NGT_F32, +amdgpu_gfx908_op_V_CMPX_NGT_F64, +amdgpu_gfx908_op_V_CMPX_NLE_F16, +amdgpu_gfx908_op_V_CMPX_NLE_F32, +amdgpu_gfx908_op_V_CMPX_NLE_F64, +amdgpu_gfx908_op_V_CMPX_NLG_F16, +amdgpu_gfx908_op_V_CMPX_NLG_F32, +amdgpu_gfx908_op_V_CMPX_NLG_F64, +amdgpu_gfx908_op_V_CMPX_NLT_F16, +amdgpu_gfx908_op_V_CMPX_NLT_F32, +amdgpu_gfx908_op_V_CMPX_NLT_F64, +amdgpu_gfx908_op_V_CMPX_O_F16, +amdgpu_gfx908_op_V_CMPX_O_F32, +amdgpu_gfx908_op_V_CMPX_O_F64, +amdgpu_gfx908_op_V_CMPX_TRU_F16, +amdgpu_gfx908_op_V_CMPX_TRU_F32, +amdgpu_gfx908_op_V_CMPX_TRU_F64, +amdgpu_gfx908_op_V_CMPX_T_I16, +amdgpu_gfx908_op_V_CMPX_T_I32, +amdgpu_gfx908_op_V_CMPX_T_I64, +amdgpu_gfx908_op_V_CMPX_T_U16, +amdgpu_gfx908_op_V_CMPX_T_U32, +amdgpu_gfx908_op_V_CMPX_T_U64, +amdgpu_gfx908_op_V_CMPX_U_F16, +amdgpu_gfx908_op_V_CMPX_U_F32, +amdgpu_gfx908_op_V_CMPX_U_F64, +amdgpu_gfx908_op_V_CMP_CLASS_F16, +amdgpu_gfx908_op_V_CMP_CLASS_F32, +amdgpu_gfx908_op_V_CMP_CLASS_F64, +amdgpu_gfx908_op_V_CMP_EQ_F16, +amdgpu_gfx908_op_V_CMP_EQ_F32, +amdgpu_gfx908_op_V_CMP_EQ_F64, +amdgpu_gfx908_op_V_CMP_EQ_I16, +amdgpu_gfx908_op_V_CMP_EQ_I32, +amdgpu_gfx908_op_V_CMP_EQ_I64, +amdgpu_gfx908_op_V_CMP_EQ_U16, +amdgpu_gfx908_op_V_CMP_EQ_U32, +amdgpu_gfx908_op_V_CMP_EQ_U64, +amdgpu_gfx908_op_V_CMP_F_F16, +amdgpu_gfx908_op_V_CMP_F_F32, +amdgpu_gfx908_op_V_CMP_F_F64, +amdgpu_gfx908_op_V_CMP_F_I16, +amdgpu_gfx908_op_V_CMP_F_I32, +amdgpu_gfx908_op_V_CMP_F_I64, +amdgpu_gfx908_op_V_CMP_F_U16, +amdgpu_gfx908_op_V_CMP_F_U32, +amdgpu_gfx908_op_V_CMP_F_U64, +amdgpu_gfx908_op_V_CMP_GE_F16, +amdgpu_gfx908_op_V_CMP_GE_F32, +amdgpu_gfx908_op_V_CMP_GE_F64, +amdgpu_gfx908_op_V_CMP_GE_I16, +amdgpu_gfx908_op_V_CMP_GE_I32, +amdgpu_gfx908_op_V_CMP_GE_I64, +amdgpu_gfx908_op_V_CMP_GE_U16, +amdgpu_gfx908_op_V_CMP_GE_U32, +amdgpu_gfx908_op_V_CMP_GE_U64, +amdgpu_gfx908_op_V_CMP_GT_F16, +amdgpu_gfx908_op_V_CMP_GT_F32, +amdgpu_gfx908_op_V_CMP_GT_F64, +amdgpu_gfx908_op_V_CMP_GT_I16, +amdgpu_gfx908_op_V_CMP_GT_I32, +amdgpu_gfx908_op_V_CMP_GT_I64, +amdgpu_gfx908_op_V_CMP_GT_U16, +amdgpu_gfx908_op_V_CMP_GT_U32, +amdgpu_gfx908_op_V_CMP_GT_U64, +amdgpu_gfx908_op_V_CMP_LE_F16, +amdgpu_gfx908_op_V_CMP_LE_F32, +amdgpu_gfx908_op_V_CMP_LE_F64, +amdgpu_gfx908_op_V_CMP_LE_I16, +amdgpu_gfx908_op_V_CMP_LE_I32, +amdgpu_gfx908_op_V_CMP_LE_I64, +amdgpu_gfx908_op_V_CMP_LE_U16, +amdgpu_gfx908_op_V_CMP_LE_U32, +amdgpu_gfx908_op_V_CMP_LE_U64, +amdgpu_gfx908_op_V_CMP_LG_F16, +amdgpu_gfx908_op_V_CMP_LG_F32, +amdgpu_gfx908_op_V_CMP_LG_F64, +amdgpu_gfx908_op_V_CMP_LT_F16, +amdgpu_gfx908_op_V_CMP_LT_F32, +amdgpu_gfx908_op_V_CMP_LT_F64, +amdgpu_gfx908_op_V_CMP_LT_I16, +amdgpu_gfx908_op_V_CMP_LT_I32, +amdgpu_gfx908_op_V_CMP_LT_I64, +amdgpu_gfx908_op_V_CMP_LT_U16, +amdgpu_gfx908_op_V_CMP_LT_U32, +amdgpu_gfx908_op_V_CMP_LT_U64, +amdgpu_gfx908_op_V_CMP_NEQ_F16, +amdgpu_gfx908_op_V_CMP_NEQ_F32, +amdgpu_gfx908_op_V_CMP_NEQ_F64, +amdgpu_gfx908_op_V_CMP_NE_I16, +amdgpu_gfx908_op_V_CMP_NE_I32, +amdgpu_gfx908_op_V_CMP_NE_I64, +amdgpu_gfx908_op_V_CMP_NE_U16, +amdgpu_gfx908_op_V_CMP_NE_U32, +amdgpu_gfx908_op_V_CMP_NE_U64, +amdgpu_gfx908_op_V_CMP_NGE_F16, +amdgpu_gfx908_op_V_CMP_NGE_F32, +amdgpu_gfx908_op_V_CMP_NGE_F64, +amdgpu_gfx908_op_V_CMP_NGT_F16, +amdgpu_gfx908_op_V_CMP_NGT_F32, +amdgpu_gfx908_op_V_CMP_NGT_F64, +amdgpu_gfx908_op_V_CMP_NLE_F16, +amdgpu_gfx908_op_V_CMP_NLE_F32, +amdgpu_gfx908_op_V_CMP_NLE_F64, +amdgpu_gfx908_op_V_CMP_NLG_F16, +amdgpu_gfx908_op_V_CMP_NLG_F32, +amdgpu_gfx908_op_V_CMP_NLG_F64, +amdgpu_gfx908_op_V_CMP_NLT_F16, +amdgpu_gfx908_op_V_CMP_NLT_F32, +amdgpu_gfx908_op_V_CMP_NLT_F64, +amdgpu_gfx908_op_V_CMP_O_F16, +amdgpu_gfx908_op_V_CMP_O_F32, +amdgpu_gfx908_op_V_CMP_O_F64, +amdgpu_gfx908_op_V_CMP_TRU_F16, +amdgpu_gfx908_op_V_CMP_TRU_F32, +amdgpu_gfx908_op_V_CMP_TRU_F64, +amdgpu_gfx908_op_V_CMP_T_I16, +amdgpu_gfx908_op_V_CMP_T_I32, +amdgpu_gfx908_op_V_CMP_T_I64, +amdgpu_gfx908_op_V_CMP_T_U16, +amdgpu_gfx908_op_V_CMP_T_U32, +amdgpu_gfx908_op_V_CMP_T_U64, +amdgpu_gfx908_op_V_CMP_U_F16, +amdgpu_gfx908_op_V_CMP_U_F32, +amdgpu_gfx908_op_V_CMP_U_F64, +amdgpu_gfx908_op_V_CNDMASK_B32, +amdgpu_gfx908_op_V_COS_F16, +amdgpu_gfx908_op_V_COS_F32, +amdgpu_gfx908_op_V_CUBEID_F32, +amdgpu_gfx908_op_V_CUBEMA_F32, +amdgpu_gfx908_op_V_CUBESC_F32, +amdgpu_gfx908_op_V_CUBETC_F32, +amdgpu_gfx908_op_V_CVT_F16_F32, +amdgpu_gfx908_op_V_CVT_F16_I16, +amdgpu_gfx908_op_V_CVT_F16_U16, +amdgpu_gfx908_op_V_CVT_F32_F16, +amdgpu_gfx908_op_V_CVT_F32_F64, +amdgpu_gfx908_op_V_CVT_F32_I32, +amdgpu_gfx908_op_V_CVT_F32_U32, +amdgpu_gfx908_op_V_CVT_F32_UBYTE0, +amdgpu_gfx908_op_V_CVT_F32_UBYTE1, +amdgpu_gfx908_op_V_CVT_F32_UBYTE2, +amdgpu_gfx908_op_V_CVT_F32_UBYTE3, +amdgpu_gfx908_op_V_CVT_F64_F32, +amdgpu_gfx908_op_V_CVT_F64_I32, +amdgpu_gfx908_op_V_CVT_F64_U32, +amdgpu_gfx908_op_V_CVT_FLR_I32_F32, +amdgpu_gfx908_op_V_CVT_I16_F16, +amdgpu_gfx908_op_V_CVT_I32_F32, +amdgpu_gfx908_op_V_CVT_I32_F64, +amdgpu_gfx908_op_V_CVT_NORM_I16_F16, +amdgpu_gfx908_op_V_CVT_NORM_U16_F16, +amdgpu_gfx908_op_V_CVT_OFF_F32_I4, +amdgpu_gfx908_op_V_CVT_PKACCUM_U8_F32, +amdgpu_gfx908_op_V_CVT_PKNORM_I16_F16, +amdgpu_gfx908_op_V_CVT_PKNORM_I16_F32, +amdgpu_gfx908_op_V_CVT_PKNORM_U16_F16, +amdgpu_gfx908_op_V_CVT_PKNORM_U16_F32, +amdgpu_gfx908_op_V_CVT_PKRTZ_F16_F32, +amdgpu_gfx908_op_V_CVT_PK_I16_I32, +amdgpu_gfx908_op_V_CVT_PK_U16_U32, +amdgpu_gfx908_op_V_CVT_PK_U8_F32, +amdgpu_gfx908_op_V_CVT_RPI_I32_F32, +amdgpu_gfx908_op_V_CVT_U16_F16, +amdgpu_gfx908_op_V_CVT_U32_F32, +amdgpu_gfx908_op_V_CVT_U32_F64, +amdgpu_gfx908_op_V_DIV_FIXUP_F16, +amdgpu_gfx908_op_V_DIV_FIXUP_F32, +amdgpu_gfx908_op_V_DIV_FIXUP_F64, +amdgpu_gfx908_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_gfx908_op_V_DIV_FMAS_F32, +amdgpu_gfx908_op_V_DIV_FMAS_F64, +amdgpu_gfx908_op_V_DIV_SCALE_F32, +amdgpu_gfx908_op_V_DIV_SCALE_F64, +amdgpu_gfx908_op_V_DOT2C_F32_F16, +amdgpu_gfx908_op_V_DOT2C_I32_I16, +amdgpu_gfx908_op_V_DOT2_F32_F16, +amdgpu_gfx908_op_V_DOT2_I32_I16, +amdgpu_gfx908_op_V_DOT2_U32_U16, +amdgpu_gfx908_op_V_DOT4C_I32_I8, +amdgpu_gfx908_op_V_DOT4_I32_I8, +amdgpu_gfx908_op_V_DOT4_U32_U8, +amdgpu_gfx908_op_V_DOT8C_I32_I4, +amdgpu_gfx908_op_V_DOT8_I32_I4, +amdgpu_gfx908_op_V_DOT8_U32_U4, +amdgpu_gfx908_op_V_EXP_F16, +amdgpu_gfx908_op_V_EXP_F32, +amdgpu_gfx908_op_V_EXP_LEGACY_F32, +amdgpu_gfx908_op_V_FFBH_I32, +amdgpu_gfx908_op_V_FFBH_U32, +amdgpu_gfx908_op_V_FFBL_B32, +amdgpu_gfx908_op_V_FLOOR_F16, +amdgpu_gfx908_op_V_FLOOR_F32, +amdgpu_gfx908_op_V_FLOOR_F64, +amdgpu_gfx908_op_V_FMAC_F32, +amdgpu_gfx908_op_V_FMA_F16, +amdgpu_gfx908_op_V_FMA_F32, +amdgpu_gfx908_op_V_FMA_F64, +amdgpu_gfx908_op_V_FMA_LEGACY_F16, +amdgpu_gfx908_op_V_FRACT_F16, +amdgpu_gfx908_op_V_FRACT_F32, +amdgpu_gfx908_op_V_FRACT_F64, +amdgpu_gfx908_op_V_FREXP_EXP_I16_F16, +amdgpu_gfx908_op_V_FREXP_EXP_I32_F32, +amdgpu_gfx908_op_V_FREXP_EXP_I32_F64, +amdgpu_gfx908_op_V_FREXP_MANT_F16, +amdgpu_gfx908_op_V_FREXP_MANT_F32, +amdgpu_gfx908_op_V_FREXP_MANT_F64, +amdgpu_gfx908_op_V_INTERP_MOV_F32, +amdgpu_gfx908_op_V_INTERP_P1LL_F16, +amdgpu_gfx908_op_V_INTERP_P1LV_F16, +amdgpu_gfx908_op_V_INTERP_P1_F32, +amdgpu_gfx908_op_V_INTERP_P2_F16, +amdgpu_gfx908_op_V_INTERP_P2_F32, +amdgpu_gfx908_op_V_INTERP_P2_LEGACY_F16, +amdgpu_gfx908_op_V_LDEXP_F16, +amdgpu_gfx908_op_V_LDEXP_F32, +amdgpu_gfx908_op_V_LDEXP_F64, +amdgpu_gfx908_op_V_LERP_U8, +amdgpu_gfx908_op_V_LOG_F16, +amdgpu_gfx908_op_V_LOG_F32, +amdgpu_gfx908_op_V_LOG_LEGACY_F32, +amdgpu_gfx908_op_V_LSHLREV_B16, +amdgpu_gfx908_op_V_LSHLREV_B32, +amdgpu_gfx908_op_V_LSHLREV_B64, +amdgpu_gfx908_op_V_LSHL_ADD_U32, +amdgpu_gfx908_op_V_LSHL_OR_B32, +amdgpu_gfx908_op_V_LSHRREV_B16, +amdgpu_gfx908_op_V_LSHRREV_B32, +amdgpu_gfx908_op_V_LSHRREV_B64, +amdgpu_gfx908_op_V_MAC_F16, +amdgpu_gfx908_op_V_MAC_F32, +amdgpu_gfx908_op_V_MADAK_F16, +amdgpu_gfx908_op_V_MADAK_F32, +amdgpu_gfx908_op_V_MADMK_F16, +amdgpu_gfx908_op_V_MADMK_F32, +amdgpu_gfx908_op_V_MAD_F16, +amdgpu_gfx908_op_V_MAD_F32, +amdgpu_gfx908_op_V_MAD_I16, +amdgpu_gfx908_op_V_MAD_I32_I16, +amdgpu_gfx908_op_V_MAD_I32_I24, +amdgpu_gfx908_op_V_MAD_I64_I32, +amdgpu_gfx908_op_V_MAD_LEGACY_F16, +amdgpu_gfx908_op_V_MAD_LEGACY_F32, +amdgpu_gfx908_op_V_MAD_LEGACY_I16, +amdgpu_gfx908_op_V_MAD_LEGACY_U16, +amdgpu_gfx908_op_V_MAD_MIXHI_F16, +amdgpu_gfx908_op_V_MAD_MIXLO_F16, +amdgpu_gfx908_op_V_MAD_MIX_F32, +amdgpu_gfx908_op_V_MAD_U16, +amdgpu_gfx908_op_V_MAD_U32_U16, +amdgpu_gfx908_op_V_MAD_U32_U24, +amdgpu_gfx908_op_V_MAD_U64_U32, +amdgpu_gfx908_op_V_MAX3_F16, +amdgpu_gfx908_op_V_MAX3_F32, +amdgpu_gfx908_op_V_MAX3_I16, +amdgpu_gfx908_op_V_MAX3_I32, +amdgpu_gfx908_op_V_MAX3_U16, +amdgpu_gfx908_op_V_MAX3_U32, +amdgpu_gfx908_op_V_MAX_F16, +amdgpu_gfx908_op_V_MAX_F32, +amdgpu_gfx908_op_V_MAX_F64, +amdgpu_gfx908_op_V_MAX_I16, +amdgpu_gfx908_op_V_MAX_I32, +amdgpu_gfx908_op_V_MAX_U16, +amdgpu_gfx908_op_V_MAX_U32, +amdgpu_gfx908_op_V_MBCNT_HI_U32_B32, +amdgpu_gfx908_op_V_MBCNT_LO_U32_B32, +amdgpu_gfx908_op_V_MED3_F16, +amdgpu_gfx908_op_V_MED3_F32, +amdgpu_gfx908_op_V_MED3_I16, +amdgpu_gfx908_op_V_MED3_I32, +amdgpu_gfx908_op_V_MED3_U16, +amdgpu_gfx908_op_V_MED3_U32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X16F16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X1F32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X4F16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X4F32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X8BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X1F32, +amdgpu_gfx908_op_V_MFMA_F32_32X32X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X2F32, +amdgpu_gfx908_op_V_MFMA_F32_32X32X4BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X4F16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X8F16, +amdgpu_gfx908_op_V_MFMA_F32_4X4X1F32, +amdgpu_gfx908_op_V_MFMA_F32_4X4X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_4X4X4F16, +amdgpu_gfx908_op_V_MFMA_I32_16X16X16I8, +amdgpu_gfx908_op_V_MFMA_I32_16X16X4I8, +amdgpu_gfx908_op_V_MFMA_I32_32X32X4I8, +amdgpu_gfx908_op_V_MFMA_I32_32X32X8I8, +amdgpu_gfx908_op_V_MFMA_I32_4X4X4I8, +amdgpu_gfx908_op_V_MIN3_F16, +amdgpu_gfx908_op_V_MIN3_F32, +amdgpu_gfx908_op_V_MIN3_I16, +amdgpu_gfx908_op_V_MIN3_I32, +amdgpu_gfx908_op_V_MIN3_U16, +amdgpu_gfx908_op_V_MIN3_U32, +amdgpu_gfx908_op_V_MIN_F16, +amdgpu_gfx908_op_V_MIN_F32, +amdgpu_gfx908_op_V_MIN_F64, +amdgpu_gfx908_op_V_MIN_I16, +amdgpu_gfx908_op_V_MIN_I32, +amdgpu_gfx908_op_V_MIN_U16, +amdgpu_gfx908_op_V_MIN_U32, +amdgpu_gfx908_op_V_MOV_B32, +amdgpu_gfx908_op_V_MQSAD_PK_U16_U8, +amdgpu_gfx908_op_V_MQSAD_U32_U8, +amdgpu_gfx908_op_V_MSAD_U8, +amdgpu_gfx908_op_V_MUL_F16, +amdgpu_gfx908_op_V_MUL_F32, +amdgpu_gfx908_op_V_MUL_F64, +amdgpu_gfx908_op_V_MUL_HI_I32, +amdgpu_gfx908_op_V_MUL_HI_I32_I24, +amdgpu_gfx908_op_V_MUL_HI_U32, +amdgpu_gfx908_op_V_MUL_HI_U32_U24, +amdgpu_gfx908_op_V_MUL_I32_I24, +amdgpu_gfx908_op_V_MUL_LEGACY_F32, +amdgpu_gfx908_op_V_MUL_LO_U16, +amdgpu_gfx908_op_V_MUL_LO_U32, +amdgpu_gfx908_op_V_MUL_U32_U24, +amdgpu_gfx908_op_V_NOP, +amdgpu_gfx908_op_V_NOT_B32, +amdgpu_gfx908_op_V_OR3_B32, +amdgpu_gfx908_op_V_OR_B32, +amdgpu_gfx908_op_V_PACK_B32_F16, +amdgpu_gfx908_op_V_PERM_B32, +amdgpu_gfx908_op_V_PK_ADD_F16, +amdgpu_gfx908_op_V_PK_ADD_I16, +amdgpu_gfx908_op_V_PK_ADD_U16, +amdgpu_gfx908_op_V_PK_ASHRREV_I16, +amdgpu_gfx908_op_V_PK_FMAC_F16, +amdgpu_gfx908_op_V_PK_FMA_F16, +amdgpu_gfx908_op_V_PK_LSHLREV_B16, +amdgpu_gfx908_op_V_PK_LSHRREV_B16, +amdgpu_gfx908_op_V_PK_MAD_I16, +amdgpu_gfx908_op_V_PK_MAD_U16, +amdgpu_gfx908_op_V_PK_MAX_F16, +amdgpu_gfx908_op_V_PK_MAX_I16, +amdgpu_gfx908_op_V_PK_MAX_U16, +amdgpu_gfx908_op_V_PK_MIN_F16, +amdgpu_gfx908_op_V_PK_MIN_I16, +amdgpu_gfx908_op_V_PK_MIN_U16, +amdgpu_gfx908_op_V_PK_MUL_F16, +amdgpu_gfx908_op_V_PK_MUL_LO_U16, +amdgpu_gfx908_op_V_PK_SUB_I16, +amdgpu_gfx908_op_V_PK_SUB_U16, +amdgpu_gfx908_op_V_QSAD_PK_U16_U8, +amdgpu_gfx908_op_V_RCP_F16, +amdgpu_gfx908_op_V_RCP_F32, +amdgpu_gfx908_op_V_RCP_F64, +amdgpu_gfx908_op_V_RCP_IFLAG_F32, +amdgpu_gfx908_op_V_READFIRSTLANE_B32, +amdgpu_gfx908_op_V_READLANE_B32, +amdgpu_gfx908_op_V_RNDNE_F16, +amdgpu_gfx908_op_V_RNDNE_F32, +amdgpu_gfx908_op_V_RNDNE_F64, +amdgpu_gfx908_op_V_RSQ_F16, +amdgpu_gfx908_op_V_RSQ_F32, +amdgpu_gfx908_op_V_RSQ_F64, +amdgpu_gfx908_op_V_SAD_HI_U8, +amdgpu_gfx908_op_V_SAD_U16, +amdgpu_gfx908_op_V_SAD_U32, +amdgpu_gfx908_op_V_SAD_U8, +amdgpu_gfx908_op_V_SAT_PK_U8_I16, +amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_gfx908_op_V_SIN_F16, +amdgpu_gfx908_op_V_SIN_F32, +amdgpu_gfx908_op_V_SQRT_F16, +amdgpu_gfx908_op_V_SQRT_F32, +amdgpu_gfx908_op_V_SQRT_F64, +amdgpu_gfx908_op_V_SUBBREV_CO_U32, +amdgpu_gfx908_op_V_SUBB_CO_U32, +amdgpu_gfx908_op_V_SUBREV_CO_U32, +amdgpu_gfx908_op_V_SUBREV_F16, +amdgpu_gfx908_op_V_SUBREV_F32, +amdgpu_gfx908_op_V_SUBREV_U16, +amdgpu_gfx908_op_V_SUBREV_U32, +amdgpu_gfx908_op_V_SUB_CO_U32, +amdgpu_gfx908_op_V_SUB_F16, +amdgpu_gfx908_op_V_SUB_F32, +amdgpu_gfx908_op_V_SUB_I16, +amdgpu_gfx908_op_V_SUB_I32, +amdgpu_gfx908_op_V_SUB_U16, +amdgpu_gfx908_op_V_SUB_U32, +amdgpu_gfx908_op_V_SWAP_B32, +amdgpu_gfx908_op_V_TRIG_PREOP_F64, +amdgpu_gfx908_op_V_TRUNC_F16, +amdgpu_gfx908_op_V_TRUNC_F32, +amdgpu_gfx908_op_V_TRUNC_F64, +amdgpu_gfx908_op_V_WRITELANE_B32, +amdgpu_gfx908_op_V_XAD_U32, +amdgpu_gfx908_op_V_XNOR_B32, +amdgpu_gfx908_op_V_XOR_B32, diff --git a/common/h/AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h b/common/h/AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h new file mode 100644 index 0000000000..df4bcc1162 --- /dev/null +++ b/common/h/AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h @@ -0,0 +1,617 @@ +#ifndef DYNINST_AMDGPU_GFX908_SYS_REGS_H +#define DYNINST_AMDGPU_GFX908_SYS_REGS_H +DEF_REGISTER(s0, Arch_amdgpu_gfx908| SGPR | BITS_32 | 0 , "amdgpu_gfx908"); +DEF_REGISTER(s1, Arch_amdgpu_gfx908| SGPR | BITS_32 | 1 , "amdgpu_gfx908"); +DEF_REGISTER(s2, Arch_amdgpu_gfx908| SGPR | BITS_32 | 2 , "amdgpu_gfx908"); +DEF_REGISTER(s3, Arch_amdgpu_gfx908| SGPR | BITS_32 | 3 , "amdgpu_gfx908"); +DEF_REGISTER(s4, Arch_amdgpu_gfx908| SGPR | BITS_32 | 4 , "amdgpu_gfx908"); +DEF_REGISTER(s5, Arch_amdgpu_gfx908| SGPR | BITS_32 | 5 , "amdgpu_gfx908"); +DEF_REGISTER(s6, Arch_amdgpu_gfx908| SGPR | BITS_32 | 6 , "amdgpu_gfx908"); +DEF_REGISTER(s7, Arch_amdgpu_gfx908| SGPR | BITS_32 | 7 , "amdgpu_gfx908"); +DEF_REGISTER(s8, Arch_amdgpu_gfx908| SGPR | BITS_32 | 8 , "amdgpu_gfx908"); +DEF_REGISTER(s9, Arch_amdgpu_gfx908| SGPR | BITS_32 | 9 , "amdgpu_gfx908"); +DEF_REGISTER(s10, Arch_amdgpu_gfx908| SGPR | BITS_32 | 10 , "amdgpu_gfx908"); +DEF_REGISTER(s11, Arch_amdgpu_gfx908| SGPR | BITS_32 | 11 , "amdgpu_gfx908"); +DEF_REGISTER(s12, Arch_amdgpu_gfx908| SGPR | BITS_32 | 12 , "amdgpu_gfx908"); +DEF_REGISTER(s13, Arch_amdgpu_gfx908| SGPR | BITS_32 | 13 , "amdgpu_gfx908"); +DEF_REGISTER(s14, Arch_amdgpu_gfx908| SGPR | BITS_32 | 14 , "amdgpu_gfx908"); +DEF_REGISTER(s15, Arch_amdgpu_gfx908| SGPR | BITS_32 | 15 , "amdgpu_gfx908"); +DEF_REGISTER(s16, Arch_amdgpu_gfx908| SGPR | BITS_32 | 16 , "amdgpu_gfx908"); +DEF_REGISTER(s17, Arch_amdgpu_gfx908| SGPR | BITS_32 | 17 , "amdgpu_gfx908"); +DEF_REGISTER(s18, Arch_amdgpu_gfx908| SGPR | BITS_32 | 18 , "amdgpu_gfx908"); +DEF_REGISTER(s19, Arch_amdgpu_gfx908| SGPR | BITS_32 | 19 , "amdgpu_gfx908"); +DEF_REGISTER(s20, Arch_amdgpu_gfx908| SGPR | BITS_32 | 20 , "amdgpu_gfx908"); +DEF_REGISTER(s21, Arch_amdgpu_gfx908| SGPR | BITS_32 | 21 , "amdgpu_gfx908"); +DEF_REGISTER(s22, Arch_amdgpu_gfx908| SGPR | BITS_32 | 22 , "amdgpu_gfx908"); +DEF_REGISTER(s23, Arch_amdgpu_gfx908| SGPR | BITS_32 | 23 , "amdgpu_gfx908"); +DEF_REGISTER(s24, Arch_amdgpu_gfx908| SGPR | BITS_32 | 24 , "amdgpu_gfx908"); +DEF_REGISTER(s25, Arch_amdgpu_gfx908| SGPR | BITS_32 | 25 , "amdgpu_gfx908"); +DEF_REGISTER(s26, Arch_amdgpu_gfx908| SGPR | BITS_32 | 26 , "amdgpu_gfx908"); +DEF_REGISTER(s27, Arch_amdgpu_gfx908| SGPR | BITS_32 | 27 , "amdgpu_gfx908"); +DEF_REGISTER(s28, Arch_amdgpu_gfx908| SGPR | BITS_32 | 28 , "amdgpu_gfx908"); +DEF_REGISTER(s29, Arch_amdgpu_gfx908| SGPR | BITS_32 | 29 , "amdgpu_gfx908"); +DEF_REGISTER(s30, Arch_amdgpu_gfx908| SGPR | BITS_32 | 30 , "amdgpu_gfx908"); +DEF_REGISTER(s31, Arch_amdgpu_gfx908| SGPR | BITS_32 | 31 , "amdgpu_gfx908"); +DEF_REGISTER(s32, Arch_amdgpu_gfx908| SGPR | BITS_32 | 32 , "amdgpu_gfx908"); +DEF_REGISTER(s33, Arch_amdgpu_gfx908| SGPR | BITS_32 | 33 , "amdgpu_gfx908"); +DEF_REGISTER(s34, Arch_amdgpu_gfx908| SGPR | BITS_32 | 34 , "amdgpu_gfx908"); +DEF_REGISTER(s35, Arch_amdgpu_gfx908| SGPR | BITS_32 | 35 , "amdgpu_gfx908"); +DEF_REGISTER(s36, Arch_amdgpu_gfx908| SGPR | BITS_32 | 36 , "amdgpu_gfx908"); +DEF_REGISTER(s37, Arch_amdgpu_gfx908| SGPR | BITS_32 | 37 , "amdgpu_gfx908"); +DEF_REGISTER(s38, Arch_amdgpu_gfx908| SGPR | BITS_32 | 38 , "amdgpu_gfx908"); +DEF_REGISTER(s39, Arch_amdgpu_gfx908| SGPR | BITS_32 | 39 , "amdgpu_gfx908"); +DEF_REGISTER(s40, Arch_amdgpu_gfx908| SGPR | BITS_32 | 40 , "amdgpu_gfx908"); +DEF_REGISTER(s41, Arch_amdgpu_gfx908| SGPR | BITS_32 | 41 , "amdgpu_gfx908"); +DEF_REGISTER(s42, Arch_amdgpu_gfx908| SGPR | BITS_32 | 42 , "amdgpu_gfx908"); +DEF_REGISTER(s43, Arch_amdgpu_gfx908| SGPR | BITS_32 | 43 , "amdgpu_gfx908"); +DEF_REGISTER(s44, Arch_amdgpu_gfx908| SGPR | BITS_32 | 44 , "amdgpu_gfx908"); +DEF_REGISTER(s45, Arch_amdgpu_gfx908| SGPR | BITS_32 | 45 , "amdgpu_gfx908"); +DEF_REGISTER(s46, Arch_amdgpu_gfx908| SGPR | BITS_32 | 46 , "amdgpu_gfx908"); +DEF_REGISTER(s47, Arch_amdgpu_gfx908| SGPR | BITS_32 | 47 , "amdgpu_gfx908"); +DEF_REGISTER(s48, Arch_amdgpu_gfx908| SGPR | BITS_32 | 48 , "amdgpu_gfx908"); +DEF_REGISTER(s49, Arch_amdgpu_gfx908| SGPR | BITS_32 | 49 , "amdgpu_gfx908"); +DEF_REGISTER(s50, Arch_amdgpu_gfx908| SGPR | BITS_32 | 50 , "amdgpu_gfx908"); +DEF_REGISTER(s51, Arch_amdgpu_gfx908| SGPR | BITS_32 | 51 , "amdgpu_gfx908"); +DEF_REGISTER(s52, Arch_amdgpu_gfx908| SGPR | BITS_32 | 52 , "amdgpu_gfx908"); +DEF_REGISTER(s53, Arch_amdgpu_gfx908| SGPR | BITS_32 | 53 , "amdgpu_gfx908"); +DEF_REGISTER(s54, Arch_amdgpu_gfx908| SGPR | BITS_32 | 54 , "amdgpu_gfx908"); +DEF_REGISTER(s55, Arch_amdgpu_gfx908| SGPR | BITS_32 | 55 , "amdgpu_gfx908"); +DEF_REGISTER(s56, Arch_amdgpu_gfx908| SGPR | BITS_32 | 56 , "amdgpu_gfx908"); +DEF_REGISTER(s57, Arch_amdgpu_gfx908| SGPR | BITS_32 | 57 , "amdgpu_gfx908"); +DEF_REGISTER(s58, Arch_amdgpu_gfx908| SGPR | BITS_32 | 58 , "amdgpu_gfx908"); +DEF_REGISTER(s59, Arch_amdgpu_gfx908| SGPR | BITS_32 | 59 , "amdgpu_gfx908"); +DEF_REGISTER(s60, Arch_amdgpu_gfx908| SGPR | BITS_32 | 60 , "amdgpu_gfx908"); +DEF_REGISTER(s61, Arch_amdgpu_gfx908| SGPR | BITS_32 | 61 , "amdgpu_gfx908"); +DEF_REGISTER(s62, Arch_amdgpu_gfx908| SGPR | BITS_32 | 62 , "amdgpu_gfx908"); +DEF_REGISTER(s63, Arch_amdgpu_gfx908| SGPR | BITS_32 | 63 , "amdgpu_gfx908"); +DEF_REGISTER(s64, Arch_amdgpu_gfx908| SGPR | BITS_32 | 64 , "amdgpu_gfx908"); +DEF_REGISTER(s65, Arch_amdgpu_gfx908| SGPR | BITS_32 | 65 , "amdgpu_gfx908"); +DEF_REGISTER(s66, Arch_amdgpu_gfx908| SGPR | BITS_32 | 66 , "amdgpu_gfx908"); +DEF_REGISTER(s67, Arch_amdgpu_gfx908| SGPR | BITS_32 | 67 , "amdgpu_gfx908"); +DEF_REGISTER(s68, Arch_amdgpu_gfx908| SGPR | BITS_32 | 68 , "amdgpu_gfx908"); +DEF_REGISTER(s69, Arch_amdgpu_gfx908| SGPR | BITS_32 | 69 , "amdgpu_gfx908"); +DEF_REGISTER(s70, Arch_amdgpu_gfx908| SGPR | BITS_32 | 70 , "amdgpu_gfx908"); +DEF_REGISTER(s71, Arch_amdgpu_gfx908| SGPR | BITS_32 | 71 , "amdgpu_gfx908"); +DEF_REGISTER(s72, Arch_amdgpu_gfx908| SGPR | BITS_32 | 72 , "amdgpu_gfx908"); +DEF_REGISTER(s73, Arch_amdgpu_gfx908| SGPR | BITS_32 | 73 , "amdgpu_gfx908"); +DEF_REGISTER(s74, Arch_amdgpu_gfx908| SGPR | BITS_32 | 74 , "amdgpu_gfx908"); +DEF_REGISTER(s75, Arch_amdgpu_gfx908| SGPR | BITS_32 | 75 , "amdgpu_gfx908"); +DEF_REGISTER(s76, Arch_amdgpu_gfx908| SGPR | BITS_32 | 76 , "amdgpu_gfx908"); +DEF_REGISTER(s77, Arch_amdgpu_gfx908| SGPR | BITS_32 | 77 , "amdgpu_gfx908"); +DEF_REGISTER(s78, Arch_amdgpu_gfx908| SGPR | BITS_32 | 78 , "amdgpu_gfx908"); +DEF_REGISTER(s79, Arch_amdgpu_gfx908| SGPR | BITS_32 | 79 , "amdgpu_gfx908"); +DEF_REGISTER(s80, Arch_amdgpu_gfx908| SGPR | BITS_32 | 80 , "amdgpu_gfx908"); +DEF_REGISTER(s81, Arch_amdgpu_gfx908| SGPR | BITS_32 | 81 , "amdgpu_gfx908"); +DEF_REGISTER(s82, Arch_amdgpu_gfx908| SGPR | BITS_32 | 82 , "amdgpu_gfx908"); +DEF_REGISTER(s83, Arch_amdgpu_gfx908| SGPR | BITS_32 | 83 , "amdgpu_gfx908"); +DEF_REGISTER(s84, Arch_amdgpu_gfx908| SGPR | BITS_32 | 84 , "amdgpu_gfx908"); +DEF_REGISTER(s85, Arch_amdgpu_gfx908| SGPR | BITS_32 | 85 , "amdgpu_gfx908"); +DEF_REGISTER(s86, Arch_amdgpu_gfx908| SGPR | BITS_32 | 86 , "amdgpu_gfx908"); +DEF_REGISTER(s87, Arch_amdgpu_gfx908| SGPR | BITS_32 | 87 , "amdgpu_gfx908"); +DEF_REGISTER(s88, Arch_amdgpu_gfx908| SGPR | BITS_32 | 88 , "amdgpu_gfx908"); +DEF_REGISTER(s89, Arch_amdgpu_gfx908| SGPR | BITS_32 | 89 , "amdgpu_gfx908"); +DEF_REGISTER(s90, Arch_amdgpu_gfx908| SGPR | BITS_32 | 90 , "amdgpu_gfx908"); +DEF_REGISTER(s91, Arch_amdgpu_gfx908| SGPR | BITS_32 | 91 , "amdgpu_gfx908"); +DEF_REGISTER(s92, Arch_amdgpu_gfx908| SGPR | BITS_32 | 92 , "amdgpu_gfx908"); +DEF_REGISTER(s93, Arch_amdgpu_gfx908| SGPR | BITS_32 | 93 , "amdgpu_gfx908"); +DEF_REGISTER(s94, Arch_amdgpu_gfx908| SGPR | BITS_32 | 94 , "amdgpu_gfx908"); +DEF_REGISTER(s95, Arch_amdgpu_gfx908| SGPR | BITS_32 | 95 , "amdgpu_gfx908"); +DEF_REGISTER(s96, Arch_amdgpu_gfx908| SGPR | BITS_32 | 96 , "amdgpu_gfx908"); +DEF_REGISTER(s97, Arch_amdgpu_gfx908| SGPR | BITS_32 | 97 , "amdgpu_gfx908"); +DEF_REGISTER(s98, Arch_amdgpu_gfx908| SGPR | BITS_32 | 98 , "amdgpu_gfx908"); +DEF_REGISTER(s99, Arch_amdgpu_gfx908| SGPR | BITS_32 | 99 , "amdgpu_gfx908"); +DEF_REGISTER(s100, Arch_amdgpu_gfx908| SGPR | BITS_32 | 100 , "amdgpu_gfx908"); +DEF_REGISTER(s101, Arch_amdgpu_gfx908| SGPR | BITS_32 | 101 , "amdgpu_gfx908"); +DEF_REGISTER(v0, Arch_amdgpu_gfx908| VGPR | BITS_32 | 0 , "amdgpu_gfx908"); +DEF_REGISTER(v1, Arch_amdgpu_gfx908| VGPR | BITS_32 | 1 , "amdgpu_gfx908"); +DEF_REGISTER(v2, Arch_amdgpu_gfx908| VGPR | BITS_32 | 2 , "amdgpu_gfx908"); +DEF_REGISTER(v3, Arch_amdgpu_gfx908| VGPR | BITS_32 | 3 , "amdgpu_gfx908"); +DEF_REGISTER(v4, Arch_amdgpu_gfx908| VGPR | BITS_32 | 4 , "amdgpu_gfx908"); +DEF_REGISTER(v5, Arch_amdgpu_gfx908| VGPR | BITS_32 | 5 , "amdgpu_gfx908"); +DEF_REGISTER(v6, Arch_amdgpu_gfx908| VGPR | BITS_32 | 6 , "amdgpu_gfx908"); +DEF_REGISTER(v7, Arch_amdgpu_gfx908| VGPR | BITS_32 | 7 , "amdgpu_gfx908"); +DEF_REGISTER(v8, Arch_amdgpu_gfx908| VGPR | BITS_32 | 8 , "amdgpu_gfx908"); +DEF_REGISTER(v9, Arch_amdgpu_gfx908| VGPR | BITS_32 | 9 , "amdgpu_gfx908"); +DEF_REGISTER(v10, Arch_amdgpu_gfx908| VGPR | BITS_32 | 10 , "amdgpu_gfx908"); +DEF_REGISTER(v11, Arch_amdgpu_gfx908| VGPR | BITS_32 | 11 , "amdgpu_gfx908"); +DEF_REGISTER(v12, Arch_amdgpu_gfx908| VGPR | BITS_32 | 12 , "amdgpu_gfx908"); +DEF_REGISTER(v13, Arch_amdgpu_gfx908| VGPR | BITS_32 | 13 , "amdgpu_gfx908"); +DEF_REGISTER(v14, Arch_amdgpu_gfx908| VGPR | BITS_32 | 14 , "amdgpu_gfx908"); +DEF_REGISTER(v15, Arch_amdgpu_gfx908| VGPR | BITS_32 | 15 , "amdgpu_gfx908"); +DEF_REGISTER(v16, Arch_amdgpu_gfx908| VGPR | BITS_32 | 16 , "amdgpu_gfx908"); +DEF_REGISTER(v17, Arch_amdgpu_gfx908| VGPR | BITS_32 | 17 , "amdgpu_gfx908"); +DEF_REGISTER(v18, Arch_amdgpu_gfx908| VGPR | BITS_32 | 18 , "amdgpu_gfx908"); +DEF_REGISTER(v19, Arch_amdgpu_gfx908| VGPR | BITS_32 | 19 , "amdgpu_gfx908"); +DEF_REGISTER(v20, Arch_amdgpu_gfx908| VGPR | BITS_32 | 20 , "amdgpu_gfx908"); +DEF_REGISTER(v21, Arch_amdgpu_gfx908| VGPR | BITS_32 | 21 , "amdgpu_gfx908"); +DEF_REGISTER(v22, Arch_amdgpu_gfx908| VGPR | BITS_32 | 22 , "amdgpu_gfx908"); +DEF_REGISTER(v23, Arch_amdgpu_gfx908| VGPR | BITS_32 | 23 , "amdgpu_gfx908"); +DEF_REGISTER(v24, Arch_amdgpu_gfx908| VGPR | BITS_32 | 24 , "amdgpu_gfx908"); +DEF_REGISTER(v25, Arch_amdgpu_gfx908| VGPR | BITS_32 | 25 , "amdgpu_gfx908"); +DEF_REGISTER(v26, Arch_amdgpu_gfx908| VGPR | BITS_32 | 26 , "amdgpu_gfx908"); +DEF_REGISTER(v27, Arch_amdgpu_gfx908| VGPR | BITS_32 | 27 , "amdgpu_gfx908"); +DEF_REGISTER(v28, Arch_amdgpu_gfx908| VGPR | BITS_32 | 28 , "amdgpu_gfx908"); +DEF_REGISTER(v29, Arch_amdgpu_gfx908| VGPR | BITS_32 | 29 , "amdgpu_gfx908"); +DEF_REGISTER(v30, Arch_amdgpu_gfx908| VGPR | BITS_32 | 30 , "amdgpu_gfx908"); +DEF_REGISTER(v31, Arch_amdgpu_gfx908| VGPR | BITS_32 | 31 , "amdgpu_gfx908"); +DEF_REGISTER(v32, Arch_amdgpu_gfx908| VGPR | BITS_32 | 32 , "amdgpu_gfx908"); +DEF_REGISTER(v33, Arch_amdgpu_gfx908| VGPR | BITS_32 | 33 , "amdgpu_gfx908"); +DEF_REGISTER(v34, Arch_amdgpu_gfx908| VGPR | BITS_32 | 34 , "amdgpu_gfx908"); +DEF_REGISTER(v35, Arch_amdgpu_gfx908| VGPR | BITS_32 | 35 , "amdgpu_gfx908"); +DEF_REGISTER(v36, Arch_amdgpu_gfx908| VGPR | BITS_32 | 36 , "amdgpu_gfx908"); +DEF_REGISTER(v37, Arch_amdgpu_gfx908| VGPR | BITS_32 | 37 , "amdgpu_gfx908"); +DEF_REGISTER(v38, Arch_amdgpu_gfx908| VGPR | BITS_32 | 38 , "amdgpu_gfx908"); +DEF_REGISTER(v39, Arch_amdgpu_gfx908| VGPR | BITS_32 | 39 , "amdgpu_gfx908"); +DEF_REGISTER(v40, Arch_amdgpu_gfx908| VGPR | BITS_32 | 40 , "amdgpu_gfx908"); +DEF_REGISTER(v41, Arch_amdgpu_gfx908| VGPR | BITS_32 | 41 , "amdgpu_gfx908"); +DEF_REGISTER(v42, Arch_amdgpu_gfx908| VGPR | BITS_32 | 42 , "amdgpu_gfx908"); +DEF_REGISTER(v43, Arch_amdgpu_gfx908| VGPR | BITS_32 | 43 , "amdgpu_gfx908"); +DEF_REGISTER(v44, Arch_amdgpu_gfx908| VGPR | BITS_32 | 44 , "amdgpu_gfx908"); +DEF_REGISTER(v45, Arch_amdgpu_gfx908| VGPR | BITS_32 | 45 , "amdgpu_gfx908"); +DEF_REGISTER(v46, Arch_amdgpu_gfx908| VGPR | BITS_32 | 46 , "amdgpu_gfx908"); +DEF_REGISTER(v47, Arch_amdgpu_gfx908| VGPR | BITS_32 | 47 , "amdgpu_gfx908"); +DEF_REGISTER(v48, Arch_amdgpu_gfx908| VGPR | BITS_32 | 48 , "amdgpu_gfx908"); +DEF_REGISTER(v49, Arch_amdgpu_gfx908| VGPR | BITS_32 | 49 , "amdgpu_gfx908"); +DEF_REGISTER(v50, Arch_amdgpu_gfx908| VGPR | BITS_32 | 50 , "amdgpu_gfx908"); +DEF_REGISTER(v51, Arch_amdgpu_gfx908| VGPR | BITS_32 | 51 , "amdgpu_gfx908"); +DEF_REGISTER(v52, Arch_amdgpu_gfx908| VGPR | BITS_32 | 52 , "amdgpu_gfx908"); +DEF_REGISTER(v53, Arch_amdgpu_gfx908| VGPR | BITS_32 | 53 , "amdgpu_gfx908"); +DEF_REGISTER(v54, Arch_amdgpu_gfx908| VGPR | BITS_32 | 54 , "amdgpu_gfx908"); +DEF_REGISTER(v55, Arch_amdgpu_gfx908| VGPR | BITS_32 | 55 , "amdgpu_gfx908"); +DEF_REGISTER(v56, Arch_amdgpu_gfx908| VGPR | BITS_32 | 56 , "amdgpu_gfx908"); +DEF_REGISTER(v57, Arch_amdgpu_gfx908| VGPR | BITS_32 | 57 , "amdgpu_gfx908"); +DEF_REGISTER(v58, Arch_amdgpu_gfx908| VGPR | BITS_32 | 58 , "amdgpu_gfx908"); +DEF_REGISTER(v59, Arch_amdgpu_gfx908| VGPR | BITS_32 | 59 , "amdgpu_gfx908"); +DEF_REGISTER(v60, Arch_amdgpu_gfx908| VGPR | BITS_32 | 60 , "amdgpu_gfx908"); +DEF_REGISTER(v61, Arch_amdgpu_gfx908| VGPR | BITS_32 | 61 , "amdgpu_gfx908"); +DEF_REGISTER(v62, Arch_amdgpu_gfx908| VGPR | BITS_32 | 62 , "amdgpu_gfx908"); +DEF_REGISTER(v63, Arch_amdgpu_gfx908| VGPR | BITS_32 | 63 , "amdgpu_gfx908"); +DEF_REGISTER(v64, Arch_amdgpu_gfx908| VGPR | BITS_32 | 64 , "amdgpu_gfx908"); +DEF_REGISTER(v65, Arch_amdgpu_gfx908| VGPR | BITS_32 | 65 , "amdgpu_gfx908"); +DEF_REGISTER(v66, Arch_amdgpu_gfx908| VGPR | BITS_32 | 66 , "amdgpu_gfx908"); +DEF_REGISTER(v67, Arch_amdgpu_gfx908| VGPR | BITS_32 | 67 , "amdgpu_gfx908"); +DEF_REGISTER(v68, Arch_amdgpu_gfx908| VGPR | BITS_32 | 68 , "amdgpu_gfx908"); +DEF_REGISTER(v69, Arch_amdgpu_gfx908| VGPR | BITS_32 | 69 , "amdgpu_gfx908"); +DEF_REGISTER(v70, Arch_amdgpu_gfx908| VGPR | BITS_32 | 70 , "amdgpu_gfx908"); +DEF_REGISTER(v71, Arch_amdgpu_gfx908| VGPR | BITS_32 | 71 , "amdgpu_gfx908"); +DEF_REGISTER(v72, Arch_amdgpu_gfx908| VGPR | BITS_32 | 72 , "amdgpu_gfx908"); +DEF_REGISTER(v73, Arch_amdgpu_gfx908| VGPR | BITS_32 | 73 , "amdgpu_gfx908"); +DEF_REGISTER(v74, Arch_amdgpu_gfx908| VGPR | BITS_32 | 74 , "amdgpu_gfx908"); +DEF_REGISTER(v75, Arch_amdgpu_gfx908| VGPR | BITS_32 | 75 , "amdgpu_gfx908"); +DEF_REGISTER(v76, Arch_amdgpu_gfx908| VGPR | BITS_32 | 76 , "amdgpu_gfx908"); +DEF_REGISTER(v77, Arch_amdgpu_gfx908| VGPR | BITS_32 | 77 , "amdgpu_gfx908"); +DEF_REGISTER(v78, Arch_amdgpu_gfx908| VGPR | BITS_32 | 78 , "amdgpu_gfx908"); +DEF_REGISTER(v79, Arch_amdgpu_gfx908| VGPR | BITS_32 | 79 , "amdgpu_gfx908"); +DEF_REGISTER(v80, Arch_amdgpu_gfx908| VGPR | BITS_32 | 80 , "amdgpu_gfx908"); +DEF_REGISTER(v81, Arch_amdgpu_gfx908| VGPR | BITS_32 | 81 , "amdgpu_gfx908"); +DEF_REGISTER(v82, Arch_amdgpu_gfx908| VGPR | BITS_32 | 82 , "amdgpu_gfx908"); +DEF_REGISTER(v83, Arch_amdgpu_gfx908| VGPR | BITS_32 | 83 , "amdgpu_gfx908"); +DEF_REGISTER(v84, Arch_amdgpu_gfx908| VGPR | BITS_32 | 84 , "amdgpu_gfx908"); +DEF_REGISTER(v85, Arch_amdgpu_gfx908| VGPR | BITS_32 | 85 , "amdgpu_gfx908"); +DEF_REGISTER(v86, Arch_amdgpu_gfx908| VGPR | BITS_32 | 86 , "amdgpu_gfx908"); +DEF_REGISTER(v87, Arch_amdgpu_gfx908| VGPR | BITS_32 | 87 , "amdgpu_gfx908"); +DEF_REGISTER(v88, Arch_amdgpu_gfx908| VGPR | BITS_32 | 88 , "amdgpu_gfx908"); +DEF_REGISTER(v89, Arch_amdgpu_gfx908| VGPR | BITS_32 | 89 , "amdgpu_gfx908"); +DEF_REGISTER(v90, Arch_amdgpu_gfx908| VGPR | BITS_32 | 90 , "amdgpu_gfx908"); +DEF_REGISTER(v91, Arch_amdgpu_gfx908| VGPR | BITS_32 | 91 , "amdgpu_gfx908"); +DEF_REGISTER(v92, Arch_amdgpu_gfx908| VGPR | BITS_32 | 92 , "amdgpu_gfx908"); +DEF_REGISTER(v93, Arch_amdgpu_gfx908| VGPR | BITS_32 | 93 , "amdgpu_gfx908"); +DEF_REGISTER(v94, Arch_amdgpu_gfx908| VGPR | BITS_32 | 94 , "amdgpu_gfx908"); +DEF_REGISTER(v95, Arch_amdgpu_gfx908| VGPR | BITS_32 | 95 , "amdgpu_gfx908"); +DEF_REGISTER(v96, Arch_amdgpu_gfx908| VGPR | BITS_32 | 96 , "amdgpu_gfx908"); +DEF_REGISTER(v97, Arch_amdgpu_gfx908| VGPR | BITS_32 | 97 , "amdgpu_gfx908"); +DEF_REGISTER(v98, Arch_amdgpu_gfx908| VGPR | BITS_32 | 98 , "amdgpu_gfx908"); +DEF_REGISTER(v99, Arch_amdgpu_gfx908| VGPR | BITS_32 | 99 , "amdgpu_gfx908"); +DEF_REGISTER(v100, Arch_amdgpu_gfx908| VGPR | BITS_32 | 100 , "amdgpu_gfx908"); +DEF_REGISTER(v101, Arch_amdgpu_gfx908| VGPR | BITS_32 | 101 , "amdgpu_gfx908"); +DEF_REGISTER(v102, Arch_amdgpu_gfx908| VGPR | BITS_32 | 102 , "amdgpu_gfx908"); +DEF_REGISTER(v103, Arch_amdgpu_gfx908| VGPR | BITS_32 | 103 , "amdgpu_gfx908"); +DEF_REGISTER(v104, Arch_amdgpu_gfx908| VGPR | BITS_32 | 104 , "amdgpu_gfx908"); +DEF_REGISTER(v105, Arch_amdgpu_gfx908| VGPR | BITS_32 | 105 , "amdgpu_gfx908"); +DEF_REGISTER(v106, Arch_amdgpu_gfx908| VGPR | BITS_32 | 106 , "amdgpu_gfx908"); +DEF_REGISTER(v107, Arch_amdgpu_gfx908| VGPR | BITS_32 | 107 , "amdgpu_gfx908"); +DEF_REGISTER(v108, Arch_amdgpu_gfx908| VGPR | BITS_32 | 108 , "amdgpu_gfx908"); +DEF_REGISTER(v109, Arch_amdgpu_gfx908| VGPR | BITS_32 | 109 , "amdgpu_gfx908"); +DEF_REGISTER(v110, Arch_amdgpu_gfx908| VGPR | BITS_32 | 110 , "amdgpu_gfx908"); +DEF_REGISTER(v111, Arch_amdgpu_gfx908| VGPR | BITS_32 | 111 , "amdgpu_gfx908"); +DEF_REGISTER(v112, Arch_amdgpu_gfx908| VGPR | BITS_32 | 112 , "amdgpu_gfx908"); +DEF_REGISTER(v113, Arch_amdgpu_gfx908| VGPR | BITS_32 | 113 , "amdgpu_gfx908"); +DEF_REGISTER(v114, Arch_amdgpu_gfx908| VGPR | BITS_32 | 114 , "amdgpu_gfx908"); +DEF_REGISTER(v115, Arch_amdgpu_gfx908| VGPR | BITS_32 | 115 , "amdgpu_gfx908"); +DEF_REGISTER(v116, Arch_amdgpu_gfx908| VGPR | BITS_32 | 116 , "amdgpu_gfx908"); +DEF_REGISTER(v117, Arch_amdgpu_gfx908| VGPR | BITS_32 | 117 , "amdgpu_gfx908"); +DEF_REGISTER(v118, Arch_amdgpu_gfx908| VGPR | BITS_32 | 118 , "amdgpu_gfx908"); +DEF_REGISTER(v119, Arch_amdgpu_gfx908| VGPR | BITS_32 | 119 , "amdgpu_gfx908"); +DEF_REGISTER(v120, Arch_amdgpu_gfx908| VGPR | BITS_32 | 120 , "amdgpu_gfx908"); +DEF_REGISTER(v121, Arch_amdgpu_gfx908| VGPR | BITS_32 | 121 , "amdgpu_gfx908"); +DEF_REGISTER(v122, Arch_amdgpu_gfx908| VGPR | BITS_32 | 122 , "amdgpu_gfx908"); +DEF_REGISTER(v123, Arch_amdgpu_gfx908| VGPR | BITS_32 | 123 , "amdgpu_gfx908"); +DEF_REGISTER(v124, Arch_amdgpu_gfx908| VGPR | BITS_32 | 124 , "amdgpu_gfx908"); +DEF_REGISTER(v125, Arch_amdgpu_gfx908| VGPR | BITS_32 | 125 , "amdgpu_gfx908"); +DEF_REGISTER(v126, Arch_amdgpu_gfx908| VGPR | BITS_32 | 126 , "amdgpu_gfx908"); +DEF_REGISTER(v127, Arch_amdgpu_gfx908| VGPR | BITS_32 | 127 , "amdgpu_gfx908"); +DEF_REGISTER(v128, Arch_amdgpu_gfx908| VGPR | BITS_32 | 128 , "amdgpu_gfx908"); +DEF_REGISTER(v129, Arch_amdgpu_gfx908| VGPR | BITS_32 | 129 , "amdgpu_gfx908"); +DEF_REGISTER(v130, Arch_amdgpu_gfx908| VGPR | BITS_32 | 130 , "amdgpu_gfx908"); +DEF_REGISTER(v131, Arch_amdgpu_gfx908| VGPR | BITS_32 | 131 , "amdgpu_gfx908"); +DEF_REGISTER(v132, Arch_amdgpu_gfx908| VGPR | BITS_32 | 132 , "amdgpu_gfx908"); +DEF_REGISTER(v133, Arch_amdgpu_gfx908| VGPR | BITS_32 | 133 , "amdgpu_gfx908"); +DEF_REGISTER(v134, Arch_amdgpu_gfx908| VGPR | BITS_32 | 134 , "amdgpu_gfx908"); +DEF_REGISTER(v135, Arch_amdgpu_gfx908| VGPR | BITS_32 | 135 , "amdgpu_gfx908"); +DEF_REGISTER(v136, Arch_amdgpu_gfx908| VGPR | BITS_32 | 136 , "amdgpu_gfx908"); +DEF_REGISTER(v137, Arch_amdgpu_gfx908| VGPR | BITS_32 | 137 , "amdgpu_gfx908"); +DEF_REGISTER(v138, Arch_amdgpu_gfx908| VGPR | BITS_32 | 138 , "amdgpu_gfx908"); +DEF_REGISTER(v139, Arch_amdgpu_gfx908| VGPR | BITS_32 | 139 , "amdgpu_gfx908"); +DEF_REGISTER(v140, Arch_amdgpu_gfx908| VGPR | BITS_32 | 140 , "amdgpu_gfx908"); +DEF_REGISTER(v141, Arch_amdgpu_gfx908| VGPR | BITS_32 | 141 , "amdgpu_gfx908"); +DEF_REGISTER(v142, Arch_amdgpu_gfx908| VGPR | BITS_32 | 142 , "amdgpu_gfx908"); +DEF_REGISTER(v143, Arch_amdgpu_gfx908| VGPR | BITS_32 | 143 , "amdgpu_gfx908"); +DEF_REGISTER(v144, Arch_amdgpu_gfx908| VGPR | BITS_32 | 144 , "amdgpu_gfx908"); +DEF_REGISTER(v145, Arch_amdgpu_gfx908| VGPR | BITS_32 | 145 , "amdgpu_gfx908"); +DEF_REGISTER(v146, Arch_amdgpu_gfx908| VGPR | BITS_32 | 146 , "amdgpu_gfx908"); +DEF_REGISTER(v147, Arch_amdgpu_gfx908| VGPR | BITS_32 | 147 , "amdgpu_gfx908"); +DEF_REGISTER(v148, Arch_amdgpu_gfx908| VGPR | BITS_32 | 148 , "amdgpu_gfx908"); +DEF_REGISTER(v149, Arch_amdgpu_gfx908| VGPR | BITS_32 | 149 , "amdgpu_gfx908"); +DEF_REGISTER(v150, Arch_amdgpu_gfx908| VGPR | BITS_32 | 150 , "amdgpu_gfx908"); +DEF_REGISTER(v151, Arch_amdgpu_gfx908| VGPR | BITS_32 | 151 , "amdgpu_gfx908"); +DEF_REGISTER(v152, Arch_amdgpu_gfx908| VGPR | BITS_32 | 152 , "amdgpu_gfx908"); +DEF_REGISTER(v153, Arch_amdgpu_gfx908| VGPR | BITS_32 | 153 , "amdgpu_gfx908"); +DEF_REGISTER(v154, Arch_amdgpu_gfx908| VGPR | BITS_32 | 154 , "amdgpu_gfx908"); +DEF_REGISTER(v155, Arch_amdgpu_gfx908| VGPR | BITS_32 | 155 , "amdgpu_gfx908"); +DEF_REGISTER(v156, Arch_amdgpu_gfx908| VGPR | BITS_32 | 156 , "amdgpu_gfx908"); +DEF_REGISTER(v157, Arch_amdgpu_gfx908| VGPR | BITS_32 | 157 , "amdgpu_gfx908"); +DEF_REGISTER(v158, Arch_amdgpu_gfx908| VGPR | BITS_32 | 158 , "amdgpu_gfx908"); +DEF_REGISTER(v159, Arch_amdgpu_gfx908| VGPR | BITS_32 | 159 , "amdgpu_gfx908"); +DEF_REGISTER(v160, Arch_amdgpu_gfx908| VGPR | BITS_32 | 160 , "amdgpu_gfx908"); +DEF_REGISTER(v161, Arch_amdgpu_gfx908| VGPR | BITS_32 | 161 , "amdgpu_gfx908"); +DEF_REGISTER(v162, Arch_amdgpu_gfx908| VGPR | BITS_32 | 162 , "amdgpu_gfx908"); +DEF_REGISTER(v163, Arch_amdgpu_gfx908| VGPR | BITS_32 | 163 , "amdgpu_gfx908"); +DEF_REGISTER(v164, Arch_amdgpu_gfx908| VGPR | BITS_32 | 164 , "amdgpu_gfx908"); +DEF_REGISTER(v165, Arch_amdgpu_gfx908| VGPR | BITS_32 | 165 , "amdgpu_gfx908"); +DEF_REGISTER(v166, Arch_amdgpu_gfx908| VGPR | BITS_32 | 166 , "amdgpu_gfx908"); +DEF_REGISTER(v167, Arch_amdgpu_gfx908| VGPR | BITS_32 | 167 , "amdgpu_gfx908"); +DEF_REGISTER(v168, Arch_amdgpu_gfx908| VGPR | BITS_32 | 168 , "amdgpu_gfx908"); +DEF_REGISTER(v169, Arch_amdgpu_gfx908| VGPR | BITS_32 | 169 , "amdgpu_gfx908"); +DEF_REGISTER(v170, Arch_amdgpu_gfx908| VGPR | BITS_32 | 170 , "amdgpu_gfx908"); +DEF_REGISTER(v171, Arch_amdgpu_gfx908| VGPR | BITS_32 | 171 , "amdgpu_gfx908"); +DEF_REGISTER(v172, Arch_amdgpu_gfx908| VGPR | BITS_32 | 172 , "amdgpu_gfx908"); +DEF_REGISTER(v173, Arch_amdgpu_gfx908| VGPR | BITS_32 | 173 , "amdgpu_gfx908"); +DEF_REGISTER(v174, Arch_amdgpu_gfx908| VGPR | BITS_32 | 174 , "amdgpu_gfx908"); +DEF_REGISTER(v175, Arch_amdgpu_gfx908| VGPR | BITS_32 | 175 , "amdgpu_gfx908"); +DEF_REGISTER(v176, Arch_amdgpu_gfx908| VGPR | BITS_32 | 176 , "amdgpu_gfx908"); +DEF_REGISTER(v177, Arch_amdgpu_gfx908| VGPR | BITS_32 | 177 , "amdgpu_gfx908"); +DEF_REGISTER(v178, Arch_amdgpu_gfx908| VGPR | BITS_32 | 178 , "amdgpu_gfx908"); +DEF_REGISTER(v179, Arch_amdgpu_gfx908| VGPR | BITS_32 | 179 , "amdgpu_gfx908"); +DEF_REGISTER(v180, Arch_amdgpu_gfx908| VGPR | BITS_32 | 180 , "amdgpu_gfx908"); +DEF_REGISTER(v181, Arch_amdgpu_gfx908| VGPR | BITS_32 | 181 , "amdgpu_gfx908"); +DEF_REGISTER(v182, Arch_amdgpu_gfx908| VGPR | BITS_32 | 182 , "amdgpu_gfx908"); +DEF_REGISTER(v183, Arch_amdgpu_gfx908| VGPR | BITS_32 | 183 , "amdgpu_gfx908"); +DEF_REGISTER(v184, Arch_amdgpu_gfx908| VGPR | BITS_32 | 184 , "amdgpu_gfx908"); +DEF_REGISTER(v185, Arch_amdgpu_gfx908| VGPR | BITS_32 | 185 , "amdgpu_gfx908"); +DEF_REGISTER(v186, Arch_amdgpu_gfx908| VGPR | BITS_32 | 186 , "amdgpu_gfx908"); +DEF_REGISTER(v187, Arch_amdgpu_gfx908| VGPR | BITS_32 | 187 , "amdgpu_gfx908"); +DEF_REGISTER(v188, Arch_amdgpu_gfx908| VGPR | BITS_32 | 188 , "amdgpu_gfx908"); +DEF_REGISTER(v189, Arch_amdgpu_gfx908| VGPR | BITS_32 | 189 , "amdgpu_gfx908"); +DEF_REGISTER(v190, Arch_amdgpu_gfx908| VGPR | BITS_32 | 190 , "amdgpu_gfx908"); +DEF_REGISTER(v191, Arch_amdgpu_gfx908| VGPR | BITS_32 | 191 , "amdgpu_gfx908"); +DEF_REGISTER(v192, Arch_amdgpu_gfx908| VGPR | BITS_32 | 192 , "amdgpu_gfx908"); +DEF_REGISTER(v193, Arch_amdgpu_gfx908| VGPR | BITS_32 | 193 , "amdgpu_gfx908"); +DEF_REGISTER(v194, Arch_amdgpu_gfx908| VGPR | BITS_32 | 194 , "amdgpu_gfx908"); +DEF_REGISTER(v195, Arch_amdgpu_gfx908| VGPR | BITS_32 | 195 , "amdgpu_gfx908"); +DEF_REGISTER(v196, Arch_amdgpu_gfx908| VGPR | BITS_32 | 196 , "amdgpu_gfx908"); +DEF_REGISTER(v197, Arch_amdgpu_gfx908| VGPR | BITS_32 | 197 , "amdgpu_gfx908"); +DEF_REGISTER(v198, Arch_amdgpu_gfx908| VGPR | BITS_32 | 198 , "amdgpu_gfx908"); +DEF_REGISTER(v199, Arch_amdgpu_gfx908| VGPR | BITS_32 | 199 , "amdgpu_gfx908"); +DEF_REGISTER(v200, Arch_amdgpu_gfx908| VGPR | BITS_32 | 200 , "amdgpu_gfx908"); +DEF_REGISTER(v201, Arch_amdgpu_gfx908| VGPR | BITS_32 | 201 , "amdgpu_gfx908"); +DEF_REGISTER(v202, Arch_amdgpu_gfx908| VGPR | BITS_32 | 202 , "amdgpu_gfx908"); +DEF_REGISTER(v203, Arch_amdgpu_gfx908| VGPR | BITS_32 | 203 , "amdgpu_gfx908"); +DEF_REGISTER(v204, Arch_amdgpu_gfx908| VGPR | BITS_32 | 204 , "amdgpu_gfx908"); +DEF_REGISTER(v205, Arch_amdgpu_gfx908| VGPR | BITS_32 | 205 , "amdgpu_gfx908"); +DEF_REGISTER(v206, Arch_amdgpu_gfx908| VGPR | BITS_32 | 206 , "amdgpu_gfx908"); +DEF_REGISTER(v207, Arch_amdgpu_gfx908| VGPR | BITS_32 | 207 , "amdgpu_gfx908"); +DEF_REGISTER(v208, Arch_amdgpu_gfx908| VGPR | BITS_32 | 208 , "amdgpu_gfx908"); +DEF_REGISTER(v209, Arch_amdgpu_gfx908| VGPR | BITS_32 | 209 , "amdgpu_gfx908"); +DEF_REGISTER(v210, Arch_amdgpu_gfx908| VGPR | BITS_32 | 210 , "amdgpu_gfx908"); +DEF_REGISTER(v211, Arch_amdgpu_gfx908| VGPR | BITS_32 | 211 , "amdgpu_gfx908"); +DEF_REGISTER(v212, Arch_amdgpu_gfx908| VGPR | BITS_32 | 212 , "amdgpu_gfx908"); +DEF_REGISTER(v213, Arch_amdgpu_gfx908| VGPR | BITS_32 | 213 , "amdgpu_gfx908"); +DEF_REGISTER(v214, Arch_amdgpu_gfx908| VGPR | BITS_32 | 214 , "amdgpu_gfx908"); +DEF_REGISTER(v215, Arch_amdgpu_gfx908| VGPR | BITS_32 | 215 , "amdgpu_gfx908"); +DEF_REGISTER(v216, Arch_amdgpu_gfx908| VGPR | BITS_32 | 216 , "amdgpu_gfx908"); +DEF_REGISTER(v217, Arch_amdgpu_gfx908| VGPR | BITS_32 | 217 , "amdgpu_gfx908"); +DEF_REGISTER(v218, Arch_amdgpu_gfx908| VGPR | BITS_32 | 218 , "amdgpu_gfx908"); +DEF_REGISTER(v219, Arch_amdgpu_gfx908| VGPR | BITS_32 | 219 , "amdgpu_gfx908"); +DEF_REGISTER(v220, Arch_amdgpu_gfx908| VGPR | BITS_32 | 220 , "amdgpu_gfx908"); +DEF_REGISTER(v221, Arch_amdgpu_gfx908| VGPR | BITS_32 | 221 , "amdgpu_gfx908"); +DEF_REGISTER(v222, Arch_amdgpu_gfx908| VGPR | BITS_32 | 222 , "amdgpu_gfx908"); +DEF_REGISTER(v223, Arch_amdgpu_gfx908| VGPR | BITS_32 | 223 , "amdgpu_gfx908"); +DEF_REGISTER(v224, Arch_amdgpu_gfx908| VGPR | BITS_32 | 224 , "amdgpu_gfx908"); +DEF_REGISTER(v225, Arch_amdgpu_gfx908| VGPR | BITS_32 | 225 , "amdgpu_gfx908"); +DEF_REGISTER(v226, Arch_amdgpu_gfx908| VGPR | BITS_32 | 226 , "amdgpu_gfx908"); +DEF_REGISTER(v227, Arch_amdgpu_gfx908| VGPR | BITS_32 | 227 , "amdgpu_gfx908"); +DEF_REGISTER(v228, Arch_amdgpu_gfx908| VGPR | BITS_32 | 228 , "amdgpu_gfx908"); +DEF_REGISTER(v229, Arch_amdgpu_gfx908| VGPR | BITS_32 | 229 , "amdgpu_gfx908"); +DEF_REGISTER(v230, Arch_amdgpu_gfx908| VGPR | BITS_32 | 230 , "amdgpu_gfx908"); +DEF_REGISTER(v231, Arch_amdgpu_gfx908| VGPR | BITS_32 | 231 , "amdgpu_gfx908"); +DEF_REGISTER(v232, Arch_amdgpu_gfx908| VGPR | BITS_32 | 232 , "amdgpu_gfx908"); +DEF_REGISTER(v233, Arch_amdgpu_gfx908| VGPR | BITS_32 | 233 , "amdgpu_gfx908"); +DEF_REGISTER(v234, Arch_amdgpu_gfx908| VGPR | BITS_32 | 234 , "amdgpu_gfx908"); +DEF_REGISTER(v235, Arch_amdgpu_gfx908| VGPR | BITS_32 | 235 , "amdgpu_gfx908"); +DEF_REGISTER(v236, Arch_amdgpu_gfx908| VGPR | BITS_32 | 236 , "amdgpu_gfx908"); +DEF_REGISTER(v237, Arch_amdgpu_gfx908| VGPR | BITS_32 | 237 , "amdgpu_gfx908"); +DEF_REGISTER(v238, Arch_amdgpu_gfx908| VGPR | BITS_32 | 238 , "amdgpu_gfx908"); +DEF_REGISTER(v239, Arch_amdgpu_gfx908| VGPR | BITS_32 | 239 , "amdgpu_gfx908"); +DEF_REGISTER(v240, Arch_amdgpu_gfx908| VGPR | BITS_32 | 240 , "amdgpu_gfx908"); +DEF_REGISTER(v241, Arch_amdgpu_gfx908| VGPR | BITS_32 | 241 , "amdgpu_gfx908"); +DEF_REGISTER(v242, Arch_amdgpu_gfx908| VGPR | BITS_32 | 242 , "amdgpu_gfx908"); +DEF_REGISTER(v243, Arch_amdgpu_gfx908| VGPR | BITS_32 | 243 , "amdgpu_gfx908"); +DEF_REGISTER(v244, Arch_amdgpu_gfx908| VGPR | BITS_32 | 244 , "amdgpu_gfx908"); +DEF_REGISTER(v245, Arch_amdgpu_gfx908| VGPR | BITS_32 | 245 , "amdgpu_gfx908"); +DEF_REGISTER(v246, Arch_amdgpu_gfx908| VGPR | BITS_32 | 246 , "amdgpu_gfx908"); +DEF_REGISTER(v247, Arch_amdgpu_gfx908| VGPR | BITS_32 | 247 , "amdgpu_gfx908"); +DEF_REGISTER(v248, Arch_amdgpu_gfx908| VGPR | BITS_32 | 248 , "amdgpu_gfx908"); +DEF_REGISTER(v249, Arch_amdgpu_gfx908| VGPR | BITS_32 | 249 , "amdgpu_gfx908"); +DEF_REGISTER(v250, Arch_amdgpu_gfx908| VGPR | BITS_32 | 250 , "amdgpu_gfx908"); +DEF_REGISTER(v251, Arch_amdgpu_gfx908| VGPR | BITS_32 | 251 , "amdgpu_gfx908"); +DEF_REGISTER(v252, Arch_amdgpu_gfx908| VGPR | BITS_32 | 252 , "amdgpu_gfx908"); +DEF_REGISTER(v253, Arch_amdgpu_gfx908| VGPR | BITS_32 | 253 , "amdgpu_gfx908"); +DEF_REGISTER(v254, Arch_amdgpu_gfx908| VGPR | BITS_32 | 254 , "amdgpu_gfx908"); +DEF_REGISTER(v255, Arch_amdgpu_gfx908| VGPR | BITS_32 | 255 , "amdgpu_gfx908"); +DEF_REGISTER(acc0, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 0 , "amdgpu_gfx908"); +DEF_REGISTER(acc1, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 1 , "amdgpu_gfx908"); +DEF_REGISTER(acc2, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 2 , "amdgpu_gfx908"); +DEF_REGISTER(acc3, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 3 , "amdgpu_gfx908"); +DEF_REGISTER(acc4, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 4 , "amdgpu_gfx908"); +DEF_REGISTER(acc5, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 5 , "amdgpu_gfx908"); +DEF_REGISTER(acc6, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 6 , "amdgpu_gfx908"); +DEF_REGISTER(acc7, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 7 , "amdgpu_gfx908"); +DEF_REGISTER(acc8, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 8 , "amdgpu_gfx908"); +DEF_REGISTER(acc9, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 9 , "amdgpu_gfx908"); +DEF_REGISTER(acc10, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 10 , "amdgpu_gfx908"); +DEF_REGISTER(acc11, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 11 , "amdgpu_gfx908"); +DEF_REGISTER(acc12, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 12 , "amdgpu_gfx908"); +DEF_REGISTER(acc13, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 13 , "amdgpu_gfx908"); +DEF_REGISTER(acc14, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 14 , "amdgpu_gfx908"); +DEF_REGISTER(acc15, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 15 , "amdgpu_gfx908"); +DEF_REGISTER(acc16, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 16 , "amdgpu_gfx908"); +DEF_REGISTER(acc17, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 17 , "amdgpu_gfx908"); +DEF_REGISTER(acc18, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 18 , "amdgpu_gfx908"); +DEF_REGISTER(acc19, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 19 , "amdgpu_gfx908"); +DEF_REGISTER(acc20, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 20 , "amdgpu_gfx908"); +DEF_REGISTER(acc21, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 21 , "amdgpu_gfx908"); +DEF_REGISTER(acc22, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 22 , "amdgpu_gfx908"); +DEF_REGISTER(acc23, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 23 , "amdgpu_gfx908"); +DEF_REGISTER(acc24, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 24 , "amdgpu_gfx908"); +DEF_REGISTER(acc25, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 25 , "amdgpu_gfx908"); +DEF_REGISTER(acc26, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 26 , "amdgpu_gfx908"); +DEF_REGISTER(acc27, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 27 , "amdgpu_gfx908"); +DEF_REGISTER(acc28, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 28 , "amdgpu_gfx908"); +DEF_REGISTER(acc29, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 29 , "amdgpu_gfx908"); +DEF_REGISTER(acc30, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 30 , "amdgpu_gfx908"); +DEF_REGISTER(acc31, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 31 , "amdgpu_gfx908"); +DEF_REGISTER(acc32, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 32 , "amdgpu_gfx908"); +DEF_REGISTER(acc33, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 33 , "amdgpu_gfx908"); +DEF_REGISTER(acc34, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 34 , "amdgpu_gfx908"); +DEF_REGISTER(acc35, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 35 , "amdgpu_gfx908"); +DEF_REGISTER(acc36, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 36 , "amdgpu_gfx908"); +DEF_REGISTER(acc37, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 37 , "amdgpu_gfx908"); +DEF_REGISTER(acc38, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 38 , "amdgpu_gfx908"); +DEF_REGISTER(acc39, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 39 , "amdgpu_gfx908"); +DEF_REGISTER(acc40, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 40 , "amdgpu_gfx908"); +DEF_REGISTER(acc41, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 41 , "amdgpu_gfx908"); +DEF_REGISTER(acc42, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 42 , "amdgpu_gfx908"); +DEF_REGISTER(acc43, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 43 , "amdgpu_gfx908"); +DEF_REGISTER(acc44, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 44 , "amdgpu_gfx908"); +DEF_REGISTER(acc45, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 45 , "amdgpu_gfx908"); +DEF_REGISTER(acc46, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 46 , "amdgpu_gfx908"); +DEF_REGISTER(acc47, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 47 , "amdgpu_gfx908"); +DEF_REGISTER(acc48, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 48 , "amdgpu_gfx908"); +DEF_REGISTER(acc49, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 49 , "amdgpu_gfx908"); +DEF_REGISTER(acc50, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 50 , "amdgpu_gfx908"); +DEF_REGISTER(acc51, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 51 , "amdgpu_gfx908"); +DEF_REGISTER(acc52, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 52 , "amdgpu_gfx908"); +DEF_REGISTER(acc53, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 53 , "amdgpu_gfx908"); +DEF_REGISTER(acc54, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 54 , "amdgpu_gfx908"); +DEF_REGISTER(acc55, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 55 , "amdgpu_gfx908"); +DEF_REGISTER(acc56, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 56 , "amdgpu_gfx908"); +DEF_REGISTER(acc57, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 57 , "amdgpu_gfx908"); +DEF_REGISTER(acc58, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 58 , "amdgpu_gfx908"); +DEF_REGISTER(acc59, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 59 , "amdgpu_gfx908"); +DEF_REGISTER(acc60, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 60 , "amdgpu_gfx908"); +DEF_REGISTER(acc61, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 61 , "amdgpu_gfx908"); +DEF_REGISTER(acc62, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 62 , "amdgpu_gfx908"); +DEF_REGISTER(acc63, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 63 , "amdgpu_gfx908"); +DEF_REGISTER(acc64, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 64 , "amdgpu_gfx908"); +DEF_REGISTER(acc65, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 65 , "amdgpu_gfx908"); +DEF_REGISTER(acc66, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 66 , "amdgpu_gfx908"); +DEF_REGISTER(acc67, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 67 , "amdgpu_gfx908"); +DEF_REGISTER(acc68, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 68 , "amdgpu_gfx908"); +DEF_REGISTER(acc69, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 69 , "amdgpu_gfx908"); +DEF_REGISTER(acc70, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 70 , "amdgpu_gfx908"); +DEF_REGISTER(acc71, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 71 , "amdgpu_gfx908"); +DEF_REGISTER(acc72, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 72 , "amdgpu_gfx908"); +DEF_REGISTER(acc73, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 73 , "amdgpu_gfx908"); +DEF_REGISTER(acc74, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 74 , "amdgpu_gfx908"); +DEF_REGISTER(acc75, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 75 , "amdgpu_gfx908"); +DEF_REGISTER(acc76, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 76 , "amdgpu_gfx908"); +DEF_REGISTER(acc77, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 77 , "amdgpu_gfx908"); +DEF_REGISTER(acc78, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 78 , "amdgpu_gfx908"); +DEF_REGISTER(acc79, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 79 , "amdgpu_gfx908"); +DEF_REGISTER(acc80, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 80 , "amdgpu_gfx908"); +DEF_REGISTER(acc81, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 81 , "amdgpu_gfx908"); +DEF_REGISTER(acc82, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 82 , "amdgpu_gfx908"); +DEF_REGISTER(acc83, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 83 , "amdgpu_gfx908"); +DEF_REGISTER(acc84, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 84 , "amdgpu_gfx908"); +DEF_REGISTER(acc85, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 85 , "amdgpu_gfx908"); +DEF_REGISTER(acc86, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 86 , "amdgpu_gfx908"); +DEF_REGISTER(acc87, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 87 , "amdgpu_gfx908"); +DEF_REGISTER(acc88, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 88 , "amdgpu_gfx908"); +DEF_REGISTER(acc89, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 89 , "amdgpu_gfx908"); +DEF_REGISTER(acc90, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 90 , "amdgpu_gfx908"); +DEF_REGISTER(acc91, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 91 , "amdgpu_gfx908"); +DEF_REGISTER(acc92, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 92 , "amdgpu_gfx908"); +DEF_REGISTER(acc93, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 93 , "amdgpu_gfx908"); +DEF_REGISTER(acc94, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 94 , "amdgpu_gfx908"); +DEF_REGISTER(acc95, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 95 , "amdgpu_gfx908"); +DEF_REGISTER(acc96, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 96 , "amdgpu_gfx908"); +DEF_REGISTER(acc97, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 97 , "amdgpu_gfx908"); +DEF_REGISTER(acc98, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 98 , "amdgpu_gfx908"); +DEF_REGISTER(acc99, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 99 , "amdgpu_gfx908"); +DEF_REGISTER(acc100, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 100 , "amdgpu_gfx908"); +DEF_REGISTER(acc101, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 101 , "amdgpu_gfx908"); +DEF_REGISTER(acc102, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 102 , "amdgpu_gfx908"); +DEF_REGISTER(acc103, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 103 , "amdgpu_gfx908"); +DEF_REGISTER(acc104, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 104 , "amdgpu_gfx908"); +DEF_REGISTER(acc105, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 105 , "amdgpu_gfx908"); +DEF_REGISTER(acc106, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 106 , "amdgpu_gfx908"); +DEF_REGISTER(acc107, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 107 , "amdgpu_gfx908"); +DEF_REGISTER(acc108, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 108 , "amdgpu_gfx908"); +DEF_REGISTER(acc109, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 109 , "amdgpu_gfx908"); +DEF_REGISTER(acc110, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 110 , "amdgpu_gfx908"); +DEF_REGISTER(acc111, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 111 , "amdgpu_gfx908"); +DEF_REGISTER(acc112, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 112 , "amdgpu_gfx908"); +DEF_REGISTER(acc113, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 113 , "amdgpu_gfx908"); +DEF_REGISTER(acc114, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 114 , "amdgpu_gfx908"); +DEF_REGISTER(acc115, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 115 , "amdgpu_gfx908"); +DEF_REGISTER(acc116, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 116 , "amdgpu_gfx908"); +DEF_REGISTER(acc117, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 117 , "amdgpu_gfx908"); +DEF_REGISTER(acc118, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 118 , "amdgpu_gfx908"); +DEF_REGISTER(acc119, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 119 , "amdgpu_gfx908"); +DEF_REGISTER(acc120, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 120 , "amdgpu_gfx908"); +DEF_REGISTER(acc121, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 121 , "amdgpu_gfx908"); +DEF_REGISTER(acc122, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 122 , "amdgpu_gfx908"); +DEF_REGISTER(acc123, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 123 , "amdgpu_gfx908"); +DEF_REGISTER(acc124, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 124 , "amdgpu_gfx908"); +DEF_REGISTER(acc125, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 125 , "amdgpu_gfx908"); +DEF_REGISTER(acc126, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 126 , "amdgpu_gfx908"); +DEF_REGISTER(acc127, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 127 , "amdgpu_gfx908"); +DEF_REGISTER(acc128, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 128 , "amdgpu_gfx908"); +DEF_REGISTER(acc129, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 129 , "amdgpu_gfx908"); +DEF_REGISTER(acc130, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 130 , "amdgpu_gfx908"); +DEF_REGISTER(acc131, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 131 , "amdgpu_gfx908"); +DEF_REGISTER(acc132, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 132 , "amdgpu_gfx908"); +DEF_REGISTER(acc133, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 133 , "amdgpu_gfx908"); +DEF_REGISTER(acc134, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 134 , "amdgpu_gfx908"); +DEF_REGISTER(acc135, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 135 , "amdgpu_gfx908"); +DEF_REGISTER(acc136, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 136 , "amdgpu_gfx908"); +DEF_REGISTER(acc137, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 137 , "amdgpu_gfx908"); +DEF_REGISTER(acc138, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 138 , "amdgpu_gfx908"); +DEF_REGISTER(acc139, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 139 , "amdgpu_gfx908"); +DEF_REGISTER(acc140, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 140 , "amdgpu_gfx908"); +DEF_REGISTER(acc141, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 141 , "amdgpu_gfx908"); +DEF_REGISTER(acc142, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 142 , "amdgpu_gfx908"); +DEF_REGISTER(acc143, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 143 , "amdgpu_gfx908"); +DEF_REGISTER(acc144, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 144 , "amdgpu_gfx908"); +DEF_REGISTER(acc145, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 145 , "amdgpu_gfx908"); +DEF_REGISTER(acc146, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 146 , "amdgpu_gfx908"); +DEF_REGISTER(acc147, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 147 , "amdgpu_gfx908"); +DEF_REGISTER(acc148, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 148 , "amdgpu_gfx908"); +DEF_REGISTER(acc149, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 149 , "amdgpu_gfx908"); +DEF_REGISTER(acc150, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 150 , "amdgpu_gfx908"); +DEF_REGISTER(acc151, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 151 , "amdgpu_gfx908"); +DEF_REGISTER(acc152, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 152 , "amdgpu_gfx908"); +DEF_REGISTER(acc153, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 153 , "amdgpu_gfx908"); +DEF_REGISTER(acc154, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 154 , "amdgpu_gfx908"); +DEF_REGISTER(acc155, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 155 , "amdgpu_gfx908"); +DEF_REGISTER(acc156, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 156 , "amdgpu_gfx908"); +DEF_REGISTER(acc157, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 157 , "amdgpu_gfx908"); +DEF_REGISTER(acc158, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 158 , "amdgpu_gfx908"); +DEF_REGISTER(acc159, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 159 , "amdgpu_gfx908"); +DEF_REGISTER(acc160, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 160 , "amdgpu_gfx908"); +DEF_REGISTER(acc161, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 161 , "amdgpu_gfx908"); +DEF_REGISTER(acc162, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 162 , "amdgpu_gfx908"); +DEF_REGISTER(acc163, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 163 , "amdgpu_gfx908"); +DEF_REGISTER(acc164, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 164 , "amdgpu_gfx908"); +DEF_REGISTER(acc165, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 165 , "amdgpu_gfx908"); +DEF_REGISTER(acc166, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 166 , "amdgpu_gfx908"); +DEF_REGISTER(acc167, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 167 , "amdgpu_gfx908"); +DEF_REGISTER(acc168, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 168 , "amdgpu_gfx908"); +DEF_REGISTER(acc169, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 169 , "amdgpu_gfx908"); +DEF_REGISTER(acc170, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 170 , "amdgpu_gfx908"); +DEF_REGISTER(acc171, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 171 , "amdgpu_gfx908"); +DEF_REGISTER(acc172, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 172 , "amdgpu_gfx908"); +DEF_REGISTER(acc173, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 173 , "amdgpu_gfx908"); +DEF_REGISTER(acc174, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 174 , "amdgpu_gfx908"); +DEF_REGISTER(acc175, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 175 , "amdgpu_gfx908"); +DEF_REGISTER(acc176, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 176 , "amdgpu_gfx908"); +DEF_REGISTER(acc177, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 177 , "amdgpu_gfx908"); +DEF_REGISTER(acc178, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 178 , "amdgpu_gfx908"); +DEF_REGISTER(acc179, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 179 , "amdgpu_gfx908"); +DEF_REGISTER(acc180, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 180 , "amdgpu_gfx908"); +DEF_REGISTER(acc181, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 181 , "amdgpu_gfx908"); +DEF_REGISTER(acc182, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 182 , "amdgpu_gfx908"); +DEF_REGISTER(acc183, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 183 , "amdgpu_gfx908"); +DEF_REGISTER(acc184, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 184 , "amdgpu_gfx908"); +DEF_REGISTER(acc185, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 185 , "amdgpu_gfx908"); +DEF_REGISTER(acc186, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 186 , "amdgpu_gfx908"); +DEF_REGISTER(acc187, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 187 , "amdgpu_gfx908"); +DEF_REGISTER(acc188, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 188 , "amdgpu_gfx908"); +DEF_REGISTER(acc189, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 189 , "amdgpu_gfx908"); +DEF_REGISTER(acc190, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 190 , "amdgpu_gfx908"); +DEF_REGISTER(acc191, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 191 , "amdgpu_gfx908"); +DEF_REGISTER(acc192, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 192 , "amdgpu_gfx908"); +DEF_REGISTER(acc193, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 193 , "amdgpu_gfx908"); +DEF_REGISTER(acc194, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 194 , "amdgpu_gfx908"); +DEF_REGISTER(acc195, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 195 , "amdgpu_gfx908"); +DEF_REGISTER(acc196, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 196 , "amdgpu_gfx908"); +DEF_REGISTER(acc197, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 197 , "amdgpu_gfx908"); +DEF_REGISTER(acc198, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 198 , "amdgpu_gfx908"); +DEF_REGISTER(acc199, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 199 , "amdgpu_gfx908"); +DEF_REGISTER(acc200, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 200 , "amdgpu_gfx908"); +DEF_REGISTER(acc201, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 201 , "amdgpu_gfx908"); +DEF_REGISTER(acc202, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 202 , "amdgpu_gfx908"); +DEF_REGISTER(acc203, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 203 , "amdgpu_gfx908"); +DEF_REGISTER(acc204, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 204 , "amdgpu_gfx908"); +DEF_REGISTER(acc205, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 205 , "amdgpu_gfx908"); +DEF_REGISTER(acc206, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 206 , "amdgpu_gfx908"); +DEF_REGISTER(acc207, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 207 , "amdgpu_gfx908"); +DEF_REGISTER(acc208, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 208 , "amdgpu_gfx908"); +DEF_REGISTER(acc209, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 209 , "amdgpu_gfx908"); +DEF_REGISTER(acc210, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 210 , "amdgpu_gfx908"); +DEF_REGISTER(acc211, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 211 , "amdgpu_gfx908"); +DEF_REGISTER(acc212, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 212 , "amdgpu_gfx908"); +DEF_REGISTER(acc213, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 213 , "amdgpu_gfx908"); +DEF_REGISTER(acc214, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 214 , "amdgpu_gfx908"); +DEF_REGISTER(acc215, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 215 , "amdgpu_gfx908"); +DEF_REGISTER(acc216, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 216 , "amdgpu_gfx908"); +DEF_REGISTER(acc217, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 217 , "amdgpu_gfx908"); +DEF_REGISTER(acc218, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 218 , "amdgpu_gfx908"); +DEF_REGISTER(acc219, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 219 , "amdgpu_gfx908"); +DEF_REGISTER(acc220, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 220 , "amdgpu_gfx908"); +DEF_REGISTER(acc221, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 221 , "amdgpu_gfx908"); +DEF_REGISTER(acc222, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 222 , "amdgpu_gfx908"); +DEF_REGISTER(acc223, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 223 , "amdgpu_gfx908"); +DEF_REGISTER(acc224, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 224 , "amdgpu_gfx908"); +DEF_REGISTER(acc225, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 225 , "amdgpu_gfx908"); +DEF_REGISTER(acc226, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 226 , "amdgpu_gfx908"); +DEF_REGISTER(acc227, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 227 , "amdgpu_gfx908"); +DEF_REGISTER(acc228, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 228 , "amdgpu_gfx908"); +DEF_REGISTER(acc229, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 229 , "amdgpu_gfx908"); +DEF_REGISTER(acc230, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 230 , "amdgpu_gfx908"); +DEF_REGISTER(acc231, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 231 , "amdgpu_gfx908"); +DEF_REGISTER(acc232, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 232 , "amdgpu_gfx908"); +DEF_REGISTER(acc233, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 233 , "amdgpu_gfx908"); +DEF_REGISTER(acc234, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 234 , "amdgpu_gfx908"); +DEF_REGISTER(acc235, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 235 , "amdgpu_gfx908"); +DEF_REGISTER(acc236, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 236 , "amdgpu_gfx908"); +DEF_REGISTER(acc237, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 237 , "amdgpu_gfx908"); +DEF_REGISTER(acc238, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 238 , "amdgpu_gfx908"); +DEF_REGISTER(acc239, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 239 , "amdgpu_gfx908"); +DEF_REGISTER(acc240, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 240 , "amdgpu_gfx908"); +DEF_REGISTER(acc241, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 241 , "amdgpu_gfx908"); +DEF_REGISTER(acc242, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 242 , "amdgpu_gfx908"); +DEF_REGISTER(acc243, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 243 , "amdgpu_gfx908"); +DEF_REGISTER(acc244, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 244 , "amdgpu_gfx908"); +DEF_REGISTER(acc245, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 245 , "amdgpu_gfx908"); +DEF_REGISTER(acc246, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 246 , "amdgpu_gfx908"); +DEF_REGISTER(acc247, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 247 , "amdgpu_gfx908"); +DEF_REGISTER(acc248, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 248 , "amdgpu_gfx908"); +DEF_REGISTER(acc249, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 249 , "amdgpu_gfx908"); +DEF_REGISTER(acc250, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 250 , "amdgpu_gfx908"); +DEF_REGISTER(acc251, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 251 , "amdgpu_gfx908"); +DEF_REGISTER(acc252, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 252 , "amdgpu_gfx908"); +DEF_REGISTER(acc253, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 253 , "amdgpu_gfx908"); +DEF_REGISTER(acc254, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 254 , "amdgpu_gfx908"); +DEF_REGISTER(acc255, Arch_amdgpu_gfx908| ACC_VGPR | BITS_32 | 255 , "amdgpu_gfx908"); +#endif diff --git a/common/h/dyn_regs.h b/common/h/dyn_regs.h index d1463d88a3..9bbdf5fc3d 100644 --- a/common/h/dyn_regs.h +++ b/common/h/dyn_regs.h @@ -60,6 +60,7 @@ namespace Dyninst Arch_amdgpu_vega = 0x84000000, Arch_cuda = 0x88000000, Arch_amdgpu_cdna2 = 0x94000000, //future support for cdna2 + Arch_amdgpu_gfx908 = 0x98000000, //future support for gfx908 Arch_intelGen9 = 0xb6000000 //same as machine no. retrevied from eu-readelf } Architecture; @@ -1616,6 +1617,208 @@ namespace Dyninst #include "AMDGPU/vega/amdgpu_vega_sys_regs.h" } + namespace amdgpu_gfx908{ + //0xff000000 0x00ff0000 0x0000ff00 0x000000ff + //arch reg cat:GPR alias&subrange reg ID + const signed int SGPR = 0x00010000; + const signed int SGPR_VEC2 = 0x00020000; + const signed int SGPR_VEC4 = 0x00030000; + const signed int SGPR_VEC8 = 0x00040000; + const signed int SGPR_VEC16 = 0x00050000; + + const signed int VGPR = 0x00060000; + const signed int VGPR_VEC2 = 0x00070000; + const signed int VGPR_VEC4 = 0x00080000; + const signed int VGPR_VEC8 = 0x00090000; + const signed int VGPR_VEC16 = 0x000A0000; + + const signed int ACC_VGPR = 0x000B0000; + + const signed int HWR = 0x000C0000; + const signed int TTMP_SGPR = 0x000D0000; + const signed int FLAGS = 0x000E0000; + const signed int PC = 0x000F0000; + const signed int SYSREG = 0x00100000; + const signed int TGT = 0x00110000; // I have no idea what TGT is yet + const signed int ATTR = 0x00120000; + const signed int PARAM = 0x00130000; // LDS Parameter + + // aliasing for flags + // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 + // so we use that part to encode the low offset in the base register + // + + + const signed int BITS_1 = 0x00000100; + const signed int BITS_2 = 0x00000200; + const signed int BITS_3 = 0x00000300; + const signed int BITS_4 = 0x00000400; + const signed int BITS_6 = 0x00000500; + const signed int BITS_7 = 0x00000600; + const signed int BITS_8 = 0x00000700; + const signed int BITS_9 = 0x00000800; + const signed int BITS_15 = 0x00000900; + const signed int BITS_16 = 0x00000A00; + const signed int BITS_32 = 0x00000B00; + const signed int BITS_48 = 0x00000C00; + const signed int BITS_64 = 0x00000D00; + const signed int BITS_128 = 0x00000E00; + const signed int BITS_256 = 0x00000F00; + const signed int BITS_512 = 0x00001000; + + + + DEF_REGISTER(tid, Arch_amdgpu_gfx908| SYSREG | BITS_32 | 0 , "amdgpu_gfx908"); + + DEF_REGISTER(invalid, Arch_amdgpu_gfx908| SYSREG | BITS_32 | 1 , "amdgpu_gfx908"); + DEF_REGISTER(pc_all, Arch_amdgpu_gfx908| PC | BITS_48 | 0 , "amdgpu_gfx908"); + + + DEF_REGISTER(src_scc, Arch_amdgpu_gfx908| HWR | BITS_32 | 0 , "amdgpu_gfx908"); + + + DEF_REGISTER(src_vccz, Arch_amdgpu_gfx908| HWR | BITS_1 | 1 , "amdgpu_gfx908"); + DEF_REGISTER(vcc_lo, Arch_amdgpu_gfx908| HWR | BITS_32 | 2 , "amdgpu_gfx908"); + DEF_REGISTER(vcc_hi, Arch_amdgpu_gfx908| HWR | BITS_32 | 3 , "amdgpu_gfx908"); + DEF_REGISTER(vcc, Arch_amdgpu_gfx908| HWR | BITS_64 | 2 , "amdgpu_gfx908"); + + + + DEF_REGISTER(src_execz, Arch_amdgpu_gfx908| HWR | BITS_1 | 4 , "amdgpu_gfx908"); + DEF_REGISTER(exec_lo, Arch_amdgpu_gfx908| HWR | BITS_32 | 5 , "amdgpu_gfx908"); + DEF_REGISTER(exec_hi, Arch_amdgpu_gfx908| HWR | BITS_32 | 6 , "amdgpu_gfx908"); + DEF_REGISTER(exec, Arch_amdgpu_gfx908| HWR | BITS_64 | 5 , "amdgpu_gfx908"); + + + DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_gfx908| HWR | BITS_64 | 7 , "amdgpu_gfx908"); + DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_gfx908| HWR | BITS_32 | 8 , "amdgpu_gfx908"); + DEF_REGISTER(flat_scratch_all, Arch_amdgpu_gfx908| HWR | BITS_32 | 7 , "amdgpu_gfx908"); + + DEF_REGISTER(m0, Arch_amdgpu_gfx908| HWR | BITS_32 | 10 , "amdgpu_gfx908"); + + DEF_REGISTER(src_literal, Arch_amdgpu_gfx908| HWR | BITS_32 | 11 , "amdgpu_gfx908");// TODO + DEF_REGISTER(src_pops_exiting_wave_id, Arch_amdgpu_gfx908| HWR | BITS_32 | 12 , "amdgpu_gfx908");// TODO + + DEF_REGISTER(src_private_base, Arch_amdgpu_gfx908| HWR | BITS_32 | 13 , "amdgpu_gfx908"); + DEF_REGISTER(src_private_limit, Arch_amdgpu_gfx908| HWR | BITS_32 | 14 , "amdgpu_gfx908"); + DEF_REGISTER(src_shared_base, Arch_amdgpu_gfx908| HWR | BITS_32 | 15 , "amdgpu_gfx908"); + DEF_REGISTER(src_shared_limit, Arch_amdgpu_gfx908| HWR | BITS_32 | 16, "amdgpu_gfx908"); + + DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_gfx908| HWR | BITS_32 | 17, "amdgpu_gfx908"); + DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_gfx908| HWR | BITS_32 | 18, "amdgpu_gfx908"); + + DEF_REGISTER(src_lds_direct, Arch_amdgpu_gfx908| HWR | BITS_32 | 19 , "amdgpu_gfx908"); + + + DEF_REGISTER(ttmp0, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 0 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp1, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 1 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp2, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 2 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp3, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 3 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp4, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 4 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp5, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 5 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp6, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 6 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp7, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 7 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp8, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 8 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp9, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 9 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp10, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 10 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp11, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 11 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp12, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 12 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp13, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 13 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp14, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 14 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp15, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 15 , "amdgpu_gfx908"); + + + + DEF_REGISTER(mrt0, Arch_amdgpu_gfx908| TGT | BITS_32 | 0 , "amdgpu_gfx908"); + DEF_REGISTER(mrt1, Arch_amdgpu_gfx908| TGT | BITS_32 | 1 , "amdgpu_gfx908"); + DEF_REGISTER(mrt2, Arch_amdgpu_gfx908| TGT | BITS_32 | 2 , "amdgpu_gfx908"); + DEF_REGISTER(mrt3, Arch_amdgpu_gfx908| TGT | BITS_32 | 3 , "amdgpu_gfx908"); + DEF_REGISTER(mrt4, Arch_amdgpu_gfx908| TGT | BITS_32 | 4 , "amdgpu_gfx908"); + DEF_REGISTER(mrt5, Arch_amdgpu_gfx908| TGT | BITS_32 | 5 , "amdgpu_gfx908"); + DEF_REGISTER(mrt6, Arch_amdgpu_gfx908| TGT | BITS_32 | 6 , "amdgpu_gfx908"); + DEF_REGISTER(mrt7, Arch_amdgpu_gfx908| TGT | BITS_32 | 7 , "amdgpu_gfx908"); + DEF_REGISTER(mrtz, Arch_amdgpu_gfx908| TGT | BITS_32 | 8 , "amdgpu_gfx908"); + DEF_REGISTER(null, Arch_amdgpu_gfx908| TGT | BITS_32 | 9 , "amdgpu_gfx908"); + DEF_REGISTER(pos0, Arch_amdgpu_gfx908| TGT | BITS_32 | 12 , "amdgpu_gfx908"); + DEF_REGISTER(pos1, Arch_amdgpu_gfx908| TGT | BITS_32 | 13 , "amdgpu_gfx908"); + DEF_REGISTER(pos2, Arch_amdgpu_gfx908| TGT | BITS_32 | 14 , "amdgpu_gfx908"); + DEF_REGISTER(pos3, Arch_amdgpu_gfx908| TGT | BITS_32 | 15 , "amdgpu_gfx908"); + DEF_REGISTER(param0, Arch_amdgpu_gfx908| TGT | BITS_32 | 32 , "amdgpu_gfx908"); + DEF_REGISTER(param1, Arch_amdgpu_gfx908| TGT | BITS_32 | 33 , "amdgpu_gfx908"); + DEF_REGISTER(param2, Arch_amdgpu_gfx908| TGT | BITS_32 | 34 , "amdgpu_gfx908"); + DEF_REGISTER(param3, Arch_amdgpu_gfx908| TGT | BITS_32 | 35 , "amdgpu_gfx908"); + DEF_REGISTER(param4, Arch_amdgpu_gfx908| TGT | BITS_32 | 36 , "amdgpu_gfx908"); + DEF_REGISTER(param5, Arch_amdgpu_gfx908| TGT | BITS_32 | 37 , "amdgpu_gfx908"); + DEF_REGISTER(param6, Arch_amdgpu_gfx908| TGT | BITS_32 | 38 , "amdgpu_gfx908"); + DEF_REGISTER(param7, Arch_amdgpu_gfx908| TGT | BITS_32 | 39 , "amdgpu_gfx908"); + DEF_REGISTER(param8, Arch_amdgpu_gfx908| TGT | BITS_32 | 40 , "amdgpu_gfx908"); + DEF_REGISTER(param9, Arch_amdgpu_gfx908| TGT | BITS_32 | 41 , "amdgpu_gfx908"); + DEF_REGISTER(param10, Arch_amdgpu_gfx908| TGT | BITS_32 | 42 , "amdgpu_gfx908"); + DEF_REGISTER(param11, Arch_amdgpu_gfx908| TGT | BITS_32 | 43 , "amdgpu_gfx908"); + DEF_REGISTER(param12, Arch_amdgpu_gfx908| TGT | BITS_32 | 44 , "amdgpu_gfx908"); + DEF_REGISTER(param13, Arch_amdgpu_gfx908| TGT | BITS_32 | 45 , "amdgpu_gfx908"); + DEF_REGISTER(param14, Arch_amdgpu_gfx908| TGT | BITS_32 | 46 , "amdgpu_gfx908"); + DEF_REGISTER(param15, Arch_amdgpu_gfx908| TGT | BITS_32 | 47 , "amdgpu_gfx908"); + DEF_REGISTER(param16, Arch_amdgpu_gfx908| TGT | BITS_32 | 48 , "amdgpu_gfx908"); + DEF_REGISTER(param17, Arch_amdgpu_gfx908| TGT | BITS_32 | 49 , "amdgpu_gfx908"); + DEF_REGISTER(param18, Arch_amdgpu_gfx908| TGT | BITS_32 | 50 , "amdgpu_gfx908"); + DEF_REGISTER(param19, Arch_amdgpu_gfx908| TGT | BITS_32 | 51 , "amdgpu_gfx908"); + DEF_REGISTER(param20, Arch_amdgpu_gfx908| TGT | BITS_32 | 52 , "amdgpu_gfx908"); + DEF_REGISTER(param21, Arch_amdgpu_gfx908| TGT | BITS_32 | 53 , "amdgpu_gfx908"); + DEF_REGISTER(param22, Arch_amdgpu_gfx908| TGT | BITS_32 | 54 , "amdgpu_gfx908"); + DEF_REGISTER(param23, Arch_amdgpu_gfx908| TGT | BITS_32 | 55 , "amdgpu_gfx908"); + DEF_REGISTER(param24, Arch_amdgpu_gfx908| TGT | BITS_32 | 56 , "amdgpu_gfx908"); + DEF_REGISTER(param25, Arch_amdgpu_gfx908| TGT | BITS_32 | 57 , "amdgpu_gfx908"); + DEF_REGISTER(param26, Arch_amdgpu_gfx908| TGT | BITS_32 | 58 , "amdgpu_gfx908"); + DEF_REGISTER(param27, Arch_amdgpu_gfx908| TGT | BITS_32 | 59 , "amdgpu_gfx908"); + DEF_REGISTER(param28, Arch_amdgpu_gfx908| TGT | BITS_32 | 60 , "amdgpu_gfx908"); + DEF_REGISTER(param29, Arch_amdgpu_gfx908| TGT | BITS_32 | 61 , "amdgpu_gfx908"); + DEF_REGISTER(param30, Arch_amdgpu_gfx908| TGT | BITS_32 | 62 , "amdgpu_gfx908"); + DEF_REGISTER(param31, Arch_amdgpu_gfx908| TGT | BITS_32 | 63 , "amdgpu_gfx908"); + + DEF_REGISTER(attr0, Arch_amdgpu_gfx908| ATTR | BITS_32 | 0 , "amdgpu_gfx908"); + DEF_REGISTER(attr1, Arch_amdgpu_gfx908| ATTR | BITS_32 | 1 , "amdgpu_gfx908"); + DEF_REGISTER(attr2, Arch_amdgpu_gfx908| ATTR | BITS_32 | 2 , "amdgpu_gfx908"); + DEF_REGISTER(attr3, Arch_amdgpu_gfx908| ATTR | BITS_32 | 3 , "amdgpu_gfx908"); + DEF_REGISTER(attr4, Arch_amdgpu_gfx908| ATTR | BITS_32 | 4 , "amdgpu_gfx908"); + DEF_REGISTER(attr5, Arch_amdgpu_gfx908| ATTR | BITS_32 | 5 , "amdgpu_gfx908"); + DEF_REGISTER(attr6, Arch_amdgpu_gfx908| ATTR | BITS_32 | 6 , "amdgpu_gfx908"); + DEF_REGISTER(attr7, Arch_amdgpu_gfx908| ATTR | BITS_32 | 7 , "amdgpu_gfx908"); + DEF_REGISTER(attr8, Arch_amdgpu_gfx908| ATTR | BITS_32 | 8 , "amdgpu_gfx908"); + DEF_REGISTER(attr9, Arch_amdgpu_gfx908| ATTR | BITS_32 | 9 , "amdgpu_gfx908"); + DEF_REGISTER(attr10, Arch_amdgpu_gfx908| ATTR | BITS_32 | 10 , "amdgpu_gfx908"); + DEF_REGISTER(attr11, Arch_amdgpu_gfx908| ATTR | BITS_32 | 11 , "amdgpu_gfx908"); + DEF_REGISTER(attr12, Arch_amdgpu_gfx908| ATTR | BITS_32 | 12 , "amdgpu_gfx908"); + DEF_REGISTER(attr13, Arch_amdgpu_gfx908| ATTR | BITS_32 | 13 , "amdgpu_gfx908"); + DEF_REGISTER(attr14, Arch_amdgpu_gfx908| ATTR | BITS_32 | 14 , "amdgpu_gfx908"); + DEF_REGISTER(attr15, Arch_amdgpu_gfx908| ATTR | BITS_32 | 15 , "amdgpu_gfx908"); + DEF_REGISTER(attr16, Arch_amdgpu_gfx908| ATTR | BITS_32 | 16 , "amdgpu_gfx908"); + DEF_REGISTER(attr17, Arch_amdgpu_gfx908| ATTR | BITS_32 | 17 , "amdgpu_gfx908"); + DEF_REGISTER(attr18, Arch_amdgpu_gfx908| ATTR | BITS_32 | 18 , "amdgpu_gfx908"); + DEF_REGISTER(attr19, Arch_amdgpu_gfx908| ATTR | BITS_32 | 19 , "amdgpu_gfx908"); + DEF_REGISTER(attr20, Arch_amdgpu_gfx908| ATTR | BITS_32 | 20 , "amdgpu_gfx908"); + DEF_REGISTER(attr21, Arch_amdgpu_gfx908| ATTR | BITS_32 | 21 , "amdgpu_gfx908"); + DEF_REGISTER(attr22, Arch_amdgpu_gfx908| ATTR | BITS_32 | 22 , "amdgpu_gfx908"); + DEF_REGISTER(attr23, Arch_amdgpu_gfx908| ATTR | BITS_32 | 23 , "amdgpu_gfx908"); + DEF_REGISTER(attr24, Arch_amdgpu_gfx908| ATTR | BITS_32 | 24 , "amdgpu_gfx908"); + DEF_REGISTER(attr25, Arch_amdgpu_gfx908| ATTR | BITS_32 | 25 , "amdgpu_gfx908"); + DEF_REGISTER(attr26, Arch_amdgpu_gfx908| ATTR | BITS_32 | 26 , "amdgpu_gfx908"); + DEF_REGISTER(attr27, Arch_amdgpu_gfx908| ATTR | BITS_32 | 27 , "amdgpu_gfx908"); + DEF_REGISTER(attr28, Arch_amdgpu_gfx908| ATTR | BITS_32 | 28 , "amdgpu_gfx908"); + DEF_REGISTER(attr29, Arch_amdgpu_gfx908| ATTR | BITS_32 | 29 , "amdgpu_gfx908"); + DEF_REGISTER(attr30, Arch_amdgpu_gfx908| ATTR | BITS_32 | 30 , "amdgpu_gfx908"); + DEF_REGISTER(attr31, Arch_amdgpu_gfx908| ATTR | BITS_32 | 31 , "amdgpu_gfx908"); + DEF_REGISTER(attr32, Arch_amdgpu_gfx908| ATTR | BITS_32 | 32 , "amdgpu_gfx908"); + + + + DEF_REGISTER(p10, Arch_amdgpu_gfx908| PARAM | BITS_32 | 32 , "amdgpu_gfx908"); + DEF_REGISTER(p20, Arch_amdgpu_gfx908| PARAM | BITS_32 | 32 , "amdgpu_gfx908"); + DEF_REGISTER(p0, Arch_amdgpu_gfx908| PARAM | BITS_32 | 32 , "amdgpu_gfx908"); + +#include "AMDGPU/gfx908/amdgpu_gfx908_sys_regs.h" + } + namespace amdgpu_cdna2{ //0xff000000 0x00ff0000 0x0000ff00 0x000000ff diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index df44c39b71..5a150eb05f 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -3010,6 +3010,7 @@ power_op_dxex, aarch64_op_zip2_advsimd, amdgpu_op_sop1_nop, #include "AMDGPU/vega/amdgpu_vega_op_table.h" +#include "AMDGPU/gfx908/amdgpu_gfx908_op_table.h" #include "AMDGPU/cdna2/amdgpu_cdna2_op_table.h" cuda_op_general, cuda_op_call, diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index 88be3da518..770ba92a90 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -109,6 +109,27 @@ MachRegister MachRegister::getBaseRegister() const { default: return *this; } + case Arch_amdgpu_gfx908: + switch (category){ + case amdgpu_gfx908::SGPR: + case amdgpu_gfx908::SGPR_VEC2: + case amdgpu_gfx908::SGPR_VEC4: + case amdgpu_gfx908::SGPR_VEC8: + case amdgpu_gfx908::SGPR_VEC16: + return MachRegister( (reg & 0x000000ff) | amdgpu_gfx908::s0); + case amdgpu_gfx908::VGPR: + case amdgpu_gfx908::VGPR_VEC2: + case amdgpu_gfx908::VGPR_VEC4: + case amdgpu_gfx908::VGPR_VEC8: + case amdgpu_gfx908::VGPR_VEC16: + return MachRegister( (reg & 0x000000ff) | amdgpu_gfx908::v0); + case amdgpu_gfx908::HWR: + return MachRegister(reg); + + default: + return *this; + } + case Arch_amdgpu_cdna2: switch (category){ case amdgpu_cdna2::SGPR: @@ -217,7 +238,7 @@ std::string MachRegister::name() const { break; } return ret; - }else if(getArchitecture() == Arch_amdgpu_cdna2){ + }else if(getArchitecture() == Arch_amdgpu_cdna2 || getArchitecture() == Arch_amdgpu_gfx908){ return iter->second; }else{ return iter->second; @@ -342,6 +363,51 @@ unsigned int MachRegister::size() const { assert(0); } } + case Arch_amdgpu_gfx908:{ + int reg_class = (reg&0x00ff0000 ) ; + if ( reg_class == amdgpu_gfx908::SGPR || reg_class == amdgpu_gfx908::VGPR){ + return 4; + }else if (reg_class == amdgpu_gfx908::SGPR_VEC2 || reg_class == amdgpu_gfx908::VGPR_VEC2){ + return 8; + }else if (reg_class == amdgpu_gfx908::SGPR_VEC4 || reg_class == amdgpu_gfx908::VGPR_VEC4){ + return 16; + }else if (reg_class == amdgpu_gfx908::SGPR_VEC8 || reg_class == amdgpu_gfx908::VGPR_VEC8){ + return 32; + }else if (reg_class == amdgpu_gfx908::SGPR_VEC16 || reg_class == amdgpu_gfx908::VGPR_VEC16){ + return 64; + }else{ + switch(reg & 0x00007f00){ + case amdgpu_gfx908::BITS_1: + case amdgpu_gfx908::BITS_2: + case amdgpu_gfx908::BITS_3: + case amdgpu_gfx908::BITS_4: + case amdgpu_gfx908::BITS_6: + case amdgpu_gfx908::BITS_7: + case amdgpu_gfx908::BITS_8: + return 1; + case amdgpu_gfx908::BITS_9: + case amdgpu_gfx908::BITS_15: + case amdgpu_gfx908::BITS_16: + return 2; + case amdgpu_gfx908::BITS_32: + return 4; + case amdgpu_gfx908::BITS_48: + return 6; + case amdgpu_gfx908::BITS_64: + return 8; + case amdgpu_gfx908::BITS_128: + return 16; + case amdgpu_gfx908::BITS_256: + return 32; + case amdgpu_gfx908::BITS_512: + return 64; + } + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + + case Arch_amdgpu_cdna2:{ int reg_class = (reg&0x00ff0000 ) ; if ( reg_class == amdgpu_cdna2::SGPR || reg_class == amdgpu_cdna2::VGPR){ @@ -466,6 +532,8 @@ MachRegister MachRegister::getPC(Dyninst::Architecture arch) return InvalidReg; case Arch_amdgpu_vega: return amdgpu_vega::pc; + case Arch_amdgpu_gfx908: + return amdgpu_gfx908::pc_all; case Arch_amdgpu_cdna2: return amdgpu_cdna2::pc_all; case Arch_none: @@ -492,6 +560,7 @@ MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch) case Arch_aarch32: case Arch_cuda: case Arch_amdgpu_vega: // TODO:Since amdgpu functions are all inlined, the return address is highly likely in sgpr[30:31] + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: case Arch_intelGen9: assert(0); @@ -517,6 +586,7 @@ MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch) return aarch64::x29; //aarch64: frame pointer is X29 by convention case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: case Arch_none: return InvalidReg; @@ -547,7 +617,7 @@ MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch) assert(0); case Arch_none: case Arch_amdgpu_vega: - + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: return InvalidReg; default: @@ -574,6 +644,7 @@ MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch) case Arch_aarch32: case Arch_cuda: case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: assert(0); case Arch_none: @@ -686,7 +757,7 @@ bool MachRegister::isPC() const { return (*this == x86_64::rip || *this == x86::eip || *this == ppc32::pc || *this == ppc64::pc || - *this == aarch64::pc || *this == amdgpu_cdna2::pc_all ); + *this == aarch64::pc || *this == amdgpu_gfx908::pc_all ||*this == amdgpu_cdna2::pc_all ); } bool MachRegister::isFramePointer() const @@ -741,6 +812,7 @@ bool MachRegister::isFlag() const return (baseID <= 731 && baseID >= 700) || (baseID <= 629 && baseID >= 621); } case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: { return (reg & 0x0000F000); @@ -838,7 +910,7 @@ void MachRegister::getROSERegister(int &c, int &n, int &p) // Rose: class, number, position // Dyninst: category, base id, subrange Architecture maybe_amdgpu = getArchitecture(); - if (maybe_amdgpu==Arch_amdgpu_vega || maybe_amdgpu == Arch_amdgpu_cdna2){ + if (maybe_amdgpu==Arch_amdgpu_vega || maybe_amdgpu == Arch_amdgpu_gfx908 || maybe_amdgpu == Arch_amdgpu_cdna2){ getAMDGPUROSERegister(c,n,p); return; } @@ -2289,6 +2361,7 @@ unsigned Dyninst::getArchAddressWidth(Dyninst::Architecture arch) case Arch_cuda: case Arch_intelGen9: case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: return 8; default: diff --git a/dwarf/src/dwarfHandle.C b/dwarf/src/dwarfHandle.C index 937d08a913..e26f30a2df 100644 --- a/dwarf/src/dwarfHandle.C +++ b/dwarf/src/dwarfHandle.C @@ -203,7 +203,10 @@ bool DwarfHandle::init_dbg() case 0x3f: arch = Dyninst::Arch_amdgpu_cdna2; break; - case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: + case 0x30: + arch = Dyninst::Arch_amdgpu_gfx908; + break; + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x31: arch = Dyninst::Arch_amdgpu_vega; break; case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: diff --git a/elf/src/Elf_X.C b/elf/src/Elf_X.C index 6a750dac4b..949b2a5815 100644 --- a/elf/src/Elf_X.C +++ b/elf/src/Elf_X.C @@ -1831,7 +1831,9 @@ Dyninst::Architecture Elf_X::getArch() const switch(ef_amdgpu_mach){ case 0x3f: return Dyninst::Arch_amdgpu_cdna2; - case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: + case 0x30: + return Dyninst::Arch_amdgpu_gfx908; + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x31: return Dyninst::Arch_amdgpu_vega; case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index 3d81cec4e5..337b3f903c 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -2,10 +2,11 @@ include_directories( ${PROJECT_SOURCE_DIR}/instructionAPI/src - ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/cdna2 + ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/gfx908 ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/vega) set(SRC_LIST + src/debug_decode.C src/Instruction.C src/InstructionAST.C src/Operation.C @@ -22,6 +23,7 @@ set(SRC_LIST src/InstructionDecoder-power.C src/InstructionDecoder-aarch64.C src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C + src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C src/InstructionDecoderImpl.C) set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) @@ -81,6 +83,8 @@ endif() if(NOT finalizeOperandsExtraFlags STREQUAL "") set_source_files_properties(src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") + set_source_files_properties(src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") endif() add_definitions(-DINSTRUCTION_LIB) diff --git a/instructionAPI/h/Instruction.h b/instructionAPI/h/Instruction.h index e9298c82d1..bac7bebbdd 100644 --- a/instructionAPI/h/Instruction.h +++ b/instructionAPI/h/Instruction.h @@ -92,7 +92,7 @@ namespace Dyninst friend class InstructionDecoder_power; friend class InstructionDecoder_aarch64; friend class InstructionDecoder_amdgpu_vega; - friend class InstructionDecoder_amdgpu_cdna; + friend class InstructionDecoder_amdgpu_gfx908; friend class InstructionDecoder_amdgpu_cdna2; struct CFT diff --git a/instructionAPI/h/Operation_impl.h b/instructionAPI/h/Operation_impl.h index 34902f3041..7da897f42a 100644 --- a/instructionAPI/h/Operation_impl.h +++ b/instructionAPI/h/Operation_impl.h @@ -102,7 +102,7 @@ namespace Dyninst friend class InstructionDecoder_power; // for editing mnemonics after creation friend class InstructionDecoder_aarch64; friend class InstructionDecoder_amdgpu_vega; - friend class InstructionDecoder_amdgpu_cdna; + friend class InstructionDecoder_amdgpu_gfx908; friend class InstructionDecoder_amdgpu_cdna2; friend class Instruction; // to make use of the update size function diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C index c17c20e6b9..e852f47437 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -184,7 +184,7 @@ namespace Dyninst { #include "finalizeOperands.C" inline unsigned int InstructionDecoder_amdgpu_cdna2::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ assert(offset %4 ==0 ); - if(b.start + offset + 4 < b.end) + if(b.start + offset + 4 <= b.end) return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; return 0; } @@ -218,7 +218,6 @@ namespace Dyninst { imm_at_64 = get32bit(b,8); insn_long = ( ((uint64_t) insn_high) << 32) | insn; - } void InstructionDecoder_amdgpu_cdna2::decodeOpcode(InstructionDecoder::buffer &b) { setupInsnWord(b); diff --git a/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C b/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C index f93b63d1c4..db789288b6 100644 --- a/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C @@ -4002,11 +4002,15 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); break; case 29:// S_SETPC_B64 +setBranch(); +setModifyPC(); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; case 30:// S_SWAPPC_B64 +setBranch(); +setModifyPC(); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); @@ -4768,31 +4772,51 @@ break; case 1:// S_ENDPGM break; case 2:// S_BRANCH +setBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; case 3:// S_WAKEUP break; case 4:// S_CBRANCH_SCC0 +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; case 5:// S_CBRANCH_SCC1 +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; case 6:// S_CBRANCH_VCCZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; case 7:// S_CBRANCH_VCCNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; case 8:// S_CBRANCH_EXECZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); break; case 9:// S_CBRANCH_EXECNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); break; diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C new file mode 100644 index 0000000000..852743bda0 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -0,0 +1,261 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Ternary.h" +#include "InstructionDecoder-amdgpu-gfx908.h" +#include "debug_decode.h" + +namespace Dyninst { + namespace InstructionAPI { + typedef void (InstructionDecoder_amdgpu_gfx908::*operandFactory)(); + + typedef amdgpu_gfx908_insn_entry amdgpu_gfx908_insn_table[]; + typedef amdgpu_mask_entry amdgpu_decoder_table[]; + + const std::array InstructionDecoder_amdgpu_gfx908::condNames = { { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", + "lt", "gt", "le", "al", "nv", + } }; + + const char* InstructionDecoder_amdgpu_gfx908::bitfieldInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + const char* InstructionDecoder_amdgpu_gfx908::condInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + +#include "amdgpu_gfx908_insn_entry.h" + struct amdgpu_mask_entry { + unsigned int mask; + std::size_t branchCnt; + const std::pair* nodeBranches; + int insnTableIndex; + + static const amdgpu_decoder_table main_decoder_table; + static const std::pair branchTable[]; + }; + +#include "amdgpu_gfx908_opcode_tables.C" + + using namespace std; + void InstructionDecoder_amdgpu_gfx908::NOTHING() { + } + + Result_Type InstructionDecoder_amdgpu_gfx908::makeSizeType(unsigned int) { + assert(0); //not implemented + return u32; + } + + // **************** + // decoding opcodes + // **************** + + MachRegister InstructionDecoder_amdgpu_gfx908::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { + return MachRegister(base.val() + encoding); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makePCExpr() { + MachRegister baseReg = amdgpu_gfx908::pc_all; + return makeRegisterExpression(baseReg); + } + + void InstructionDecoder_amdgpu_gfx908::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, + int immLen_ = 16) { + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + int64_t offset = sign_extend64(immLen_, immVal * 4); + + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + + insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, + false); + if (bIsConditional || branchIsCall) { + insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); + } + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeFallThroughExpr() { + // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long + return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); + } + + + bool InstructionDecoder_amdgpu_gfx908::decodeOperands(const Instruction *) { + assert(0 && "decodeOperands deprecated for amdgpu"); + return true; + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeSGPRorM0(unsigned int offset){ + if( offset <= 104) + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx908::s0,offset)); + if (offset == 124) + return makeRegisterExpression(amdgpu_gfx908::m0); + cerr << " unknown offset in sgpr or m0 " << offset << endl; + assert(0 && "shouldn't reach here"); + return {}; + } + + + uint32_t InstructionDecoder_amdgpu_gfx908::decodeOPR_LITERAL(){ + if (!useImm){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + + } + return immLiteral; + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_LABEL(uint64_t input){ + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + int64_t offset = sign_extend64(immLen, input * 4); + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + return makeAddExpression(lhs, rhs, s64); + + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SIMM4(uint64_t input){ + return Immediate::makeImmediate(Result(s8, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SIMM8(uint64_t input){ + return Immediate::makeImmediate(Result(s8, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SIMM16(uint64_t input){ + return Immediate::makeImmediate(Result(s16, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SIMM32(uint64_t input){ + return Immediate::makeImmediate(Result(s32, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_WAITCNT(uint64_t input){ + return Immediate::makeImmediate(Result(s16, input)); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID){ + if(registerID == amdgpu_gfx908::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID, uint32_t low, uint32_t high ){ + if(registerID == amdgpu_gfx908::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID, low, high ); + } + + + +#include "amdgpu_gfx908_decoder_impl.C" +#include "decodeOperands.C" +#include "finalizeOperands.C" + inline unsigned int InstructionDecoder_amdgpu_gfx908::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ + assert(offset %4 ==0 ); + if(b.start + offset + 4 <= b.end) + return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; + return 0; + } + + + void InstructionDecoder_amdgpu_gfx908::reset(){ + immLen = 0; + insn_size = 0; + num_elements =1; + isBranch = false; + isConditional = false; + isModifyPC =false; + isSMEM = false; + isLoad = false ; + isStore =false; + isBuffer =false ; + isScratch = false; + insn = insn_high = insn_long = 0; + useImm = false; + isCall = false; + } + // here we assemble the first 64 bit (if available) as an instruction + + void InstructionDecoder_amdgpu_gfx908::setupInsnWord(InstructionDecoder::buffer &b) { + reset(); + + + insn = get32bit(b,0); + + imm_at_32 = insn_high = get32bit(b,4); + imm_at_64 = get32bit(b,8); + + insn_long = ( ((uint64_t) insn_high) << 32) | insn; + decoding_printf("[%s:%d]: setting up insnword, bits = %llu\n",FILE__,__LINE__, insn_long ); + + + } + void InstructionDecoder_amdgpu_gfx908::decodeOpcode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + } + + void InstructionDecoder_amdgpu_gfx908::debug_instr(){ + cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family + << " length = " << insn_in_progress->size()<< endl << endl; + + } + + Instruction InstructionDecoder_amdgpu_gfx908::decode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){ + //cout << "Is Branch Instruction !! , name = " << insn_in_progress -> getOperation().mnemonic << endl; + //std::mem_fun(decode_lookup_table[instr_family])(this); + } + decoding_printf("[%s:%d]: decoded instruction = %s\n",FILE__,__LINE__, insn_in_progress->getOperation().mnemonic.c_str() ); + b.start += insn_in_progress->size(); + return *insn_in_progress; + } + + void InstructionDecoder_amdgpu_gfx908::doDelayedDecode(const Instruction *insn_to_complete) { + + InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); + setupInsnWord(b); + mainDecode(); + decoding_printf("[%s:%d]: decoded instruction = %s\n",FILE__,__LINE__, insn_in_progress->getOperation().mnemonic.c_str() ); + cout.clear(); + Instruction* iptr = const_cast(insn_to_complete); + *iptr = *(insn_in_progress.get()); + } + } +} + + + diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h new file mode 100644 index 0000000000..d05c2971ef --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h @@ -0,0 +1,317 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "InstructionDecoderImpl.h" +#include +#include "Immediate.h" +#include "dyn_regs.h" + +namespace Dyninst { + namespace InstructionAPI { + +#define insn_printf(format, ...) \ + do{ \ + printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ + }while(0) + + struct amdgpu_gfx908_insn_entry; + struct amdgpu_mask_entry; + + class InstructionDecoder_amdgpu_gfx908 : public InstructionDecoderImpl { + friend struct amdgpu_gfx908_insn_entry; + friend struct amdgpu_mask_entry; + enum DecodeFamily {sopp}; + + public: + InstructionDecoder_amdgpu_gfx908(Architecture a) : InstructionDecoderImpl(a) {} + + virtual ~InstructionDecoder_amdgpu_gfx908() = default; + + virtual void decodeOpcode(InstructionDecoder::buffer &b); + + // decode one instruction starting from b.start + // will advance b.start whenver a instruction is successfully decoded + virtual Instruction decode(InstructionDecoder::buffer &b); + + virtual void setMode(bool) { } + + virtual bool decodeOperands(const Instruction *insn_to_complete); + + bool decodeOperands(const amdgpu_gfx908_insn_entry & insn_entry); + + virtual void doDelayedDecode(const Instruction *insn_to_complete); + + static const std::array condNames; + static MachRegister sysRegMap(unsigned int); + static const char* bitfieldInsnAliasMap(entryID); + static const char* condInsnAliasMap(entryID); + + + + private: + virtual Result_Type makeSizeType(unsigned int opType); + + bool is64Bit{}; + + unsigned int insn_size{}; // size of the instruction that we are currently working on + unsigned int insn{}; // the first 32 bit + unsigned int insn_high{}; // the second 32 bit + unsigned long long int insn_long{}; // the combined 64 bit: insn_high << 32 | insn + + // the main process of decoding an instruciton, won't advance buffer + void mainDecode(); + + void mainDecodeOpcode(); + + + void setupInsnWord(InstructionDecoder::buffer &b); + // pointer to the instruction that we are currently working on + boost::shared_ptr insn_in_progress; + + template + int field(unsigned int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFF >> (31 - (end - start)))) << " "; +#endif + return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); + } + + template + int longfield(unsigned long long int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; +#endif + return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); + } + + int32_t sign_extend32(int size_, int in) { + int32_t val = 0 | in; + + return (val << (32 - size_)) >> (32 - size_); + } + + int64_t sign_extend64(int size_, int in) { + int64_t val = 0 | in; + + return (val << (64 - size_)) >> (64 - size_); + } + + uint32_t unsign_extend32(int size_, int in) { + uint32_t mask = ~0; + + return (mask >> (32 - size_)) & in; + } + + uint64_t unsign_extend64(int size_, int in) { + uint64_t mask = ~0; + + return (mask >> (64 - size_)) & in; + } + + int highest_set_bit(int32_t val) { + for (int bit_index = 31; bit_index >= 0; bit_index--) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + int lowest_set_bit(int32_t val) { + for (int bit_index = 0; bit_index <= 31; bit_index++) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + + bool hasHw{}; + int hwField{}; + + void processHwFieldInsn(int, int); + + bool hasShift{}; + int shiftField{}; + + void makeBranchTarget(bool, bool, int, int); + + Expression::Ptr makeFallThroughExpr(); + + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; + + void processAlphabetImm(); + + void NOTHING(); + bool fix_bitfieldinsn_alias(int, int); + void fix_condinsn_alias_and_cond(int &); + void modify_mnemonic_simd_upperhalf_insns(); + + MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); + + MachRegister getLoadStoreSimdRegister(int encoding); + + Expression::Ptr makePCExpr(); + + + template + Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); + + + //for load store + void insnSize(unsigned int insn_size ); + + Expression::Ptr decodeSSRC(unsigned int index); + Expression::Ptr decodeVSRC(unsigned int index); + Expression::Ptr decodeVDST(unsigned int index); + + Expression::Ptr decodeSGPRorM0(unsigned int offset); + + + bool useImm{}; + uint32_t immLen{}; + uint32_t immLiteral{}; + uint32_t imm_at_32{}; + uint32_t imm_at_64{}; + uint32_t imm_at_96{}; + + bool setSCC{}; + +#define IS_LD_ST() (isLoad || isStore ) + + unsigned int num_elements{1}; // the number of elements that will be load or store by each instruction + bool isSMEM{}; // this is set when using smem instruction + bool isLoad{}; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time + bool isStore{}; // similar to isLoad, but for store instructions + bool isBuffer{}; // + bool isScratch{}; + + bool isBranch{}; // this is set for all branch instructions, + bool isConditional{}; // this is set for all conditional branch instruction, will set branchCond + bool isCall{}; // this is a call function + + + + // this is set for instructions that directly modify pc + // namely s_setpc and s_swappc + bool isModifyPC{}; + + // reset the decoder internal state for decoding the next instruction + void reset(); + + Expression::Ptr branchCond; + Expression::Ptr branchTarget; + + void setBranch(){ + isBranch = true; + } + + void setConditionalBranch(){ + isConditional = true; + // TODO : set conditional branch + } + void setModifyPC(){ + isModifyPC = true; + } + + void setCall(){ + isCall = true; + } + + inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ); + + template + void setUseImm(InstructionDecoder::buffer & b, unsigned int offset){ + if ( longfield(insn_long) == candidate ){ + useImm = true; + immLen = 4; + immLiteral = get32bit(b,offset); + } + + } + + void setSMEM() {isSMEM = true;} + + + + template + void setLoad(){isLoad = true; this->num_elements = num_elements; } + + template + void setStore() {isStore = true;this->num_elements = num_elements;} + + void setScratch() {isScratch = true;} + + void setBuffer() {isBuffer = true;} + + typedef struct buffer_resource_desc{ + unsigned long long base_address; + unsigned stride; + unsigned cache_swizzle; + unsigned swizzle_enable; + unsigned num_records; + unsigned dst_sel_x; + unsigned dst_sel_y; + unsigned dst_sel_z; + unsigned dst_sel_w; + unsigned num_format; + unsigned data_format; + unsigned user_vm_enable; + unsigned user_vm_mode; + unsigned index_stride; + unsigned add_tid_enable; + unsigned non_volatile; + unsigned type; + }buffer_resource_desc; + + void debug_instr(); + + uint32_t decodeOPR_LITERAL(); + Expression::Ptr decodeOPR_LABEL(uint64_t input); + Expression::Ptr decodeOPR_SIMM4(uint64_t input); + Expression::Ptr decodeOPR_SIMM8(uint64_t input); + Expression::Ptr decodeOPR_SIMM16(uint64_t input); + Expression::Ptr decodeOPR_SIMM32(uint64_t input); + Expression::Ptr decodeOPR_WAITCNT(uint64_t input); + using InstructionDecoderImpl::makeRegisterExpression; + Expression::Ptr makeRegisterExpression(MachRegister registerID); + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high ); + void specialHandle(); + #include "amdgpu_gfx908_decoder_impl.h" + #include "decodeOperands.h" + }; + } +} + diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C new file mode 100644 index 0000000000..8727c7a553 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C @@ -0,0 +1,2387 @@ +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOP1(uint64_t I){ + switch( I & 4286643968 ){ + case 3196059648: + case 3196059904: + case 3196060672: + case 3196060160: + case 3196060416: + case 3196060928: + case 3196061184: + case 3196061440: + case 3196061696: + case 3196061952: + case 3196063744: + case 3196064000: + case 3196068096: + case 3196067840: + case 3196064256: + case 3196068352: + case 3196071936: + case 3196072448: + case 3196064512: + case 3196068608: + case 3196072704: + case 3196064768: + case 3196068864: + case 3196072960: + case 3196065024: + case 3196069120: + case 3196073216: + case 3196065280: + case 3196069376: + case 3196073472: + case 3196065536: + case 3196069632: + case 3196073728: + case 3196065792: + case 3196069888: + case 3196066048: + case 3196070144: + case 3196062208: + case 3196066304: + case 3196070400: + case 3196062464: + case 3196066560: + case 3196070656: + case 3196062720: + case 3196066816: + case 3196070912: + case 3196067584: + case 3196062976: + case 3196067072: + case 3196071168: + case 3196063232: + case 3196067328: + case 3196071424: + case 3196063488: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPC(uint64_t I){ + switch( I & 4294901760 ){ + case 3204448256: + case 3204513792: + case 3204644864: + case 3204579328: + case 3204710400: + case 3204775936: + case 3204841472: + case 3204907008: + case 3204972544: + case 3205038080: + case 3205103616: + case 3205169152: + case 3205234688: + case 3205300224: + case 3205365760: + case 3205431296: + case 3205693440: + case 3205562368: + case 3205627904: + case 3205496832: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPP(uint64_t I){ + switch( I & 4294901760 ){ + case 3212836864: + case 3212902400: + case 3213033472: + case 3212967936: + case 3213099008: + case 3213164544: + case 3213230080: + case 3213295616: + case 3213361152: + case 3213426688: + case 3213492224: + case 3213623296: + case 3213754368: + case 3214016512: + case 3214147584: + case 3213885440: + case 3214606336: + case 3214737408: + case 3213557760: + case 3213688832: + case 3213819904: + case 3214082048: + case 3213950976: + case 3214213120: + case 3214278656: + case 3214344192: + case 3214475264: + case 3214409728: + case 3214540800: + case 3214671872: + case 3214802944: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPK(uint64_t I){ + switch( I & 4286578688 ){ + case 2952790016: + case 2961178624: + case 2986344448: + case 2969567232: + case 2977955840: + case 2994733056: + case 3003121664: + case 3011510272: + case 3019898880: + case 3028287488: + case 3036676096: + case 3045064704: + case 3053453312: + case 3061841920: + case 3070230528: + case 3078619136: + case 3103784960: + case 3095396352: + case 3128950784: + case 3087007744: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOP2(uint64_t I){ + switch( I & 4286578688 ){ + case 2147483648: + case 2155872256: + case 2181038080: + case 2164260864: + case 2172649472: + case 2189426688: + case 2197815296: + case 2206203904: + case 2214592512: + case 2222981120: + case 2231369728: + case 2239758336: + case 2248146944: + case 2256535552: + case 2264924160: + case 2273312768: + case 2399141888: + case 2533359616: + case 2407530496: + case 2541748224: + case 2415919104: + case 2550136832: + case 2298478592: + case 2306867200: + case 2290089984: + case 2315255808: + case 2281701376: + case 2323644416: + case 2332033024: + case 2340421632: + case 2348810240: + case 2357198848: + case 2424307712: + case 2558525440: + case 2432696320: + case 2566914048: + case 2441084928: + case 2575302656: + case 2516582400: + case 2449473536: + case 2583691264: + case 2457862144: + case 2466250752: + case 2474639360: + case 2390753280: + case 2483027968: + case 2524971008: + case 2491416576: + case 2365587456: + case 2499805184: + case 2373976064: + case 2508193792: + case 2382364672: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SMEM(uint64_t I){ + switch( I & 4294705152 ){ + case 3221225472: + case 3221487616: + case 3222274048: + case 3221749760: + case 3222011904: + case 3222536192: + case 3222798336: + case 3223060480: + case 3223322624: + case 3223584768: + case 3223846912: + case 3224109056: + case 3224371200: + case 3225419776: + case 3225681920: + case 3225944064: + case 3249537024: + case 3229614080: + case 3238002688: + case 3246391296: + case 3254779904: + case 3257925632: + case 3263168512: + case 3229876224: + case 3238264832: + case 3246653440: + case 3255042048: + case 3263430656: + case 3266314240: + case 3230138368: + case 3238526976: + case 3246915584: + case 3255304192: + case 3263692800: + case 3230400512: + case 3238789120: + case 3247177728: + case 3255566336: + case 3263954944: + case 3230662656: + case 3239051264: + case 3247439872: + case 3255828480: + case 3264217088: + case 3226730496: + case 3230924800: + case 3239313408: + case 3247702016: + case 3256090624: + case 3264479232: + case 3226992640: + case 3231186944: + case 3239575552: + case 3247964160: + case 3256352768: + case 3264741376: + case 3227254784: + case 3231449088: + case 3239837696: + case 3248226304: + case 3256614912: + case 3265003520: + case 3227516928: + case 3231711232: + case 3240099840: + case 3248488448: + case 3256877056: + case 3265265664: + case 3227779072: + case 3231973376: + case 3240361984: + case 3248750592: + case 3257139200: + case 3265527808: + case 3249274880: + case 3228041216: + case 3240624128: + case 3249012736: + case 3257401344: + case 3265789952: + case 3257663488: + case 3240886272: + case 3266052096: + case 3241148416: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP1(uint64_t I){ + switch( I & 4261543424 ){ + case 2113929216: + case 2113929728: + case 2113930752: + case 2113931264: + case 2113930240: + case 2113931776: + case 2113932288: + case 2113932800: + case 2113933312: + case 2113934336: + case 2113937408: + case 2113937920: + case 2113941504: + case 2113942016: + case 2113946112: + case 2113950208: + case 2113945600: + case 2113954304: + case 2113958400: + case 2113962496: + case 2113949696: + case 2113953792: + case 2113938432: + case 2113942528: + case 2113946624: + case 2113950720: + case 2113954816: + case 2113958912: + case 2113961984: + case 2113963008: + case 2113967104: + case 2113966080: + case 2113934848: + case 2113938944: + case 2113943040: + case 2113947136: + case 2113951232: + case 2113955328: + case 2113959424: + case 2113963520: + case 2113967616: + case 2113935360: + case 2113939456: + case 2113943552: + case 2113947648: + case 2113951744: + case 2113955840: + case 2113959936: + case 2113964032: + case 2113968128: + case 2113935872: + case 2113939968: + case 2113944064: + case 2113948160: + case 2113952256: + case 2113956352: + case 2113960448: + case 2113964544: + case 2113968640: + case 2113936384: + case 2113940480: + case 2113944576: + case 2113948672: + case 2113952768: + case 2113960960: + case 2113965056: + case 2113969152: + case 2113936896: + case 2113940992: + case 2113945088: + case 2113949184: + case 2113953280: + case 2113957376: + case 2113961472: + case 2113965568: + case 2113969664: + case 2113966592: + case 2113970688: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOPC(uint64_t I){ + switch( I & 4294836224 ){ + case 2082471936: + case 2082603008: + case 2082865152: + case 2082734080: + case 2082996224: + case 2083127296: + case 2084569088: + case 2084700160: + case 2084831232: + case 2084962304: + case 2085093376: + case 2085617664: + case 2088239104: + case 2092433408: + case 2088763392: + case 2092957696: + case 2096627712: + case 2113404928: + case 2109341696: + case 2105278464: + case 2109865984: + case 2105802752: + case 2101739520: + case 2110390272: + case 2106327040: + case 2102263808: + case 2110914560: + case 2090074112: + case 2106851328: + case 2086010880: + case 2102788096: + case 2094661632: + case 2111438848: + case 2090598400: + case 2107375616: + case 2086535168: + case 2103312384: + case 2095185920: + case 2111963136: + case 2091122688: + case 2107899904: + case 2087059456: + case 2103836672: + case 2095710208: + case 2112487424: + case 2108424192: + case 2087583744: + case 2104360960: + case 2108948480: + case 2096234496: + case 2113011712: + case 2085224448: + case 2085748736: + case 2088370176: + case 2092564480: + case 2088894464: + case 2093088768: + case 2089418752: + case 2093613056: + case 2089943040: + case 2094137344: + case 2092171264: + case 2104885248: + case 2096758784: + case 2113536000: + case 2109472768: + case 2105409536: + case 2101346304: + case 2109997056: + case 2105933824: + case 2101870592: + case 2110521344: + case 2106458112: + case 2102394880: + case 2094268416: + case 2111045632: + case 2090205184: + case 2106982400: + case 2086141952: + case 2102919168: + case 2094792704: + case 2111569920: + case 2090729472: + case 2107506688: + case 2086666240: + case 2103443456: + case 2095316992: + case 2112094208: + case 2091253760: + case 2108030976: + case 2087190528: + case 2103967744: + case 2095841280: + case 2112618496: + case 2108555264: + case 2087714816: + case 2104492032: + case 2113142784: + case 2085355520: + case 2087976960: + case 2088501248: + case 2092695552: + case 2091646976: + case 2089025536: + case 2093219840: + case 2089549824: + case 2093744128: + case 2085879808: + case 2096365568: + case 2105016320: + case 2109079552: + case 2096889856: + case 2113667072: + case 2109603840: + case 2105540608: + case 2101477376: + case 2110128128: + case 2089287680: + case 2106064896: + case 2102001664: + case 2110652416: + case 2089811968: + case 2106589184: + case 2102525952: + case 2094399488: + case 2111176704: + case 2090336256: + case 2107113472: + case 2086273024: + case 2103050240: + case 2094923776: + case 2111700992: + case 2090860544: + case 2107637760: + case 2086797312: + case 2103574528: + case 2095448064: + case 2112225280: + case 2091384832: + case 2108162048: + case 2087321600: + case 2104098816: + case 2095972352: + case 2112749568: + case 2091909120: + case 2108686336: + case 2087845888: + case 2104623104: + case 2085486592: + case 2088108032: + case 2092302336: + case 2088632320: + case 2092826624: + case 2089156608: + case 2093350912: + case 2091778048: + case 2089680896: + case 2093875200: + case 2096496640: + case 2109210624: + case 2113273856: + case 2105147392: + case 2097020928: + case 2113798144: + case 2109734912: + case 2105671680: + case 2101608448: + case 2104229888: + case 2093481984: + case 2110259200: + case 2106195968: + case 2102132736: + case 2094006272: + case 2110783488: + case 2106720256: + case 2102657024: + case 2094530560: + case 2111307776: + case 2090467328: + case 2107244544: + case 2086404096: + case 2103181312: + case 2092040192: + case 2112880640: + case 2095054848: + case 2111832064: + case 2090991616: + case 2107768832: + case 2086928384: + case 2103705600: + case 2108817408: + case 2095579136: + case 2112356352: + case 2091515904: + case 2108293120: + case 2087452672: + case 2104754176: + case 2096103424: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP2(uint64_t I){ + switch( I & 4261412864 ){ + case 0: + case 33554432: + case 134217728: + case 67108864: + case 100663296: + case 167772160: + case 201326592: + case 234881024: + case 268435456: + case 301989888: + case 335544320: + case 369098752: + case 402653184: + case 436207616: + case 469762048: + case 503316480: + case 1174405120: + case 1577058304: + case 1308622848: + case 1442840576: + case 939524096: + case 1073741824: + case 1342177280: + case 603979776: + case 637534208: + case 671088640: + case 570425344: + case 536870912: + case 704643072: + case 738197504: + case 838860800: + case 872415232: + case 905969664: + case 1711276032: + case 1845493760: + case 1979711488: + case 1476395008: + case 973078528: + case 1107296256: + case 1375731712: + case 1509949440: + case 1610612736: + case 1644167168: + case 1744830464: + case 1778384896: + case 1912602624: + case 1879048192: + case 2013265920: + case 1006632960: + case 1140850688: + case 1275068416: + case 1409286144: + case 1543503872: + case 1677721600: + case 1811939328: + case 1946157056: + case 2046820352: + case 1040187392: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VINTRP(uint64_t I){ + switch( I & 4228055040 ){ + case 3556769792: + case 3556835328: + case 3556900864: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3P(uint64_t I){ + switch( I & 4294901760 ){ + case 3548381184: + case 3548446720: + case 3548577792: + case 3548512256: + case 3548643328: + case 3548708864: + case 3548774400: + case 3548839936: + case 3548905472: + case 3548971008: + case 3549036544: + case 3549167616: + case 3549298688: + case 3549560832: + case 3550478336: + case 3549429760: + case 3554213888: + case 3549102080: + case 3549233152: + case 3549364224: + case 3550543872: + case 3549495296: + case 3550674944: + case 3550937088: + case 3551068160: + case 3551199232: + case 3554148352: + case 3550609408: + case 3550871552: + case 3551002624: + case 3551133696: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3(uint64_t I){ + switch( I & 4294901760 ){ + case 3530555392: + case 3530620928: + case 3510697984: + case 3530686464: + case 3510632448: + case 3510763520: + case 3510829056: + case 3510894592: + case 3510960128: + case 3511025664: + case 3511091200: + case 3514826752: + case 3506438144: + case 3523215360: + case 3508535296: + case 3491758080: + case 3505913856: + case 3504668672: + case 3503423488: + case 3496017920: + case 3512795136: + case 3514892288: + case 3506503680: + case 3531669504: + case 3500212224: + case 3519086592: + case 3523280896: + case 3508600832: + case 3491823616: + case 3500933120: + case 3505520640: + case 3519152128: + case 3521249280: + case 3514957824: + case 3506569216: + case 3512860672: + case 3523346432: + case 3508666368: + case 3491889152: + case 3493986304: + case 3496083456: + case 3504275456: + case 3493855232: + case 3503030272: + case 3508731904: + case 3491954688: + case 3494051840: + case 3496148992: + case 3512926208: + case 3515023360: + case 3506634752: + case 3531800576: + case 3519217664: + case 3521314816: + case 3501785088: + case 3506372608: + case 3495952384: + case 3500539904: + case 3505127424: + case 3531866112: + case 3519283200: + case 3521380352: + case 3515088896: + case 3512991744: + case 3506700288: + case 3523477504: + case 3492020224: + case 3494117376: + case 3496214528: + case 3503882240: + case 3502637056: + case 3501391872: + case 3521445888: + case 3523543040: + case 3492085760: + case 3494182912: + case 3496280064: + case 3513057280: + case 3515154432: + case 3506765824: + case 3531931648: + case 3519348736: + case 3505979392: + case 3500146688: + case 3504734208: + case 3503489024: + case 3494248448: + case 3496345600: + case 3531997184: + case 3519414272: + case 3521511424: + case 3515219968: + case 3513122816: + case 3506831360: + case 3523608576: + case 3508928512: + case 3502243840: + case 3501457408: + case 3532259328: + case 3500998656: + case 3505586176: + case 3519479808: + case 3521576960: + case 3523674112: + case 3508994048: + case 3492216832: + case 3494313984: + case 3496411136: + case 3513188352: + case 3515285504: + case 3506896896: + case 3495165952: + case 3504340992: + case 3493920768: + case 3503095808: + case 3511156736: + case 3515351040: + case 3506962432: + case 3509059584: + case 3492282368: + case 3494379520: + case 3513253888: + case 3496476672: + case 3532128256: + case 3519545344: + case 3500605440: + case 3505192960: + case 3496542208: + case 3513319424: + case 3515416576: + case 3532193792: + case 3519610880: + case 3507027968: + case 3509125120: + case 3492347904: + case 3494445056: + case 3500736512: + case 3503947776: + case 3502702592: + case 3519676416: + case 3521773568: + case 3511287808: + case 3515482112: + case 3513384960: + case 3507093504: + case 3509190656: + case 3492413440: + case 3494510592: + case 3496607744: + case 3491037184: + case 3506044928: + case 3504799744: + case 3509256192: + case 3492478976: + case 3494576128: + case 3496673280: + case 3513450496: + case 3511353344: + case 3515547648: + case 3532324864: + case 3519741952: + case 3521839104: + case 3503554560: + case 3512729600: + case 3502309376: + case 3501064192: + case 3532390400: + case 3519807488: + case 3521904640: + case 3511418880: + case 3515613184: + case 3513516032: + case 3507224576: + case 3509321728: + case 3492544512: + case 3494641664: + case 3505651712: + case 3504406528: + case 3503161344: + case 3521970176: + case 3507290112: + case 3509387264: + case 3492610048: + case 3494707200: + case 3496804352: + case 3513581568: + case 3511484416: + case 3515678720: + case 3532455936: + case 3500670976: + case 3505258496: + case 3494772736: + case 3496869888: + case 3492675584: + case 3519938560: + case 3522035712: + case 3511549952: + case 3515744256: + case 3513647104: + case 3507355648: + case 3509846016: + case 3519021056: + case 3502768128: + case 3532783616: + case 3522363392: + case 3520004096: + case 3522101248: + case 3507421184: + case 3509518336: + case 3492741120: + case 3494838272: + case 3496935424: + case 3513712640: + case 3511615488: + case 3515809792: + case 3501522944: + case 3506110464: + case 3500277760: + case 3504865280: + case 3519873024: + case 3509452800: + case 3511681024: + case 3507486720: + case 3490709504: + case 3509583872: + case 3492806656: + case 3494903808: + case 3513778176: + case 3497000960: + case 3532652544: + case 3520069632: + case 3503620096: + case 3502374912: + case 3501129728: + case 3497066496: + case 3515940864: + case 3513843712: + case 3511746560: + case 3532718080: + case 3520135168: + case 3494969344: + case 3522232320: + case 3507552256: + case 3490775040: + case 3505717248: + case 3504472064: + case 3503226880: + case 3520200704: + case 3522297856: + case 3511812096: + case 3513909248: + case 3507617792: + case 3490840576: + case 3509714944: + case 3492937728: + case 3495034880: + case 3497132032: + case 3505324032: + case 3509780480: + case 3493003264: + case 3495100416: + case 3497197568: + case 3513974784: + case 3511877632: + case 3532849152: + case 3490906112: + case 3507683328: + case 3520266240: + case 3504078848: + case 3502833664: + case 3532914688: + case 3493068800: + case 3520331776: + case 3514040320: + case 3511943168: + case 3522428928: + case 3497263104: + case 3507748864: + case 3530817536: + case 3490971648: + case 3501588480: + case 3506176000: + case 3501326336: + case 3531603968: + case 3500343296: + case 3504930816: + case 3520397312: + case 3495231488: + case 3522494464: + case 3507814400: + case 3509911552: + case 3493134336: + case 3512008704: + case 3514105856: + case 3497328640: + case 3532980224: + case 3503685632: + case 3533701120: + case 3502440448: + case 3501195264: + case 3509977088: + case 3493199872: + case 3495297024: + case 3530948608: + case 3533045760: + case 3520462848: + case 3512074240: + case 3522560000: + case 3497394176: + case 3507879936: + case 3505782784: + case 3504537600: + case 3503292416: + case 3492872192: + case 3533111296: + case 3520528384: + case 3497459712: + case 3522625536: + case 3510042624: + case 3493265408: + case 3495362560: + case 3512139776: + case 3514236928: + case 3531014144: + case 3502047232: + case 3532062720: + case 3500802048: + case 3505389568: + case 3522691072: + case 3510108160: + case 3493330944: + case 3512205312: + case 3495428096: + case 3497525248: + case 3533176832: + case 3520593920: + case 3501719552: + case 3503816704: + case 3504144384: + case 3502899200: + case 3495493632: + case 3512270848: + case 3514368000: + case 3497590784: + case 3533242368: + case 3520659456: + case 3522756608: + case 3510173696: + case 3493396480: + case 3501654016: + case 3506241536: + case 3500408832: + case 3504996352: + case 3520724992: + case 3514433536: + case 3512336384: + case 3522822144: + case 3510239232: + case 3493462016: + case 3495559168: + case 3497656320: + case 3533307904: + case 3501850624: + case 3503751168: + case 3502505984: + case 3501260800: + case 3510304768: + case 3493527552: + case 3495624704: + case 3512401920: + case 3514499072: + case 3497721856: + case 3520790528: + case 3522887680: + case 3501916160: + case 3504013312: + case 3505848320: + case 3504603136: + case 3503357952: + case 3497787392: + case 3533438976: + case 3520856064: + case 3514564608: + case 3512467456: + case 3522953216: + case 3510370304: + case 3493593088: + case 3495690240: + case 3501981696: + case 3500867584: + case 3505455104: + case 3520921600: + case 3523018752: + case 3510435840: + case 3493658624: + case 3495755776: + case 3512532992: + case 3514630144: + case 3497852928: + case 3530883072: + case 3533504512: + case 3502964736: + case 3493724160: + case 3495821312: + case 3497918464: + case 3533570048: + case 3520987136: + case 3514695680: + case 3512598528: + case 3523084288: + case 3502112768: + case 3504209920: + case 3506307072: + case 3531735040: + case 3500474368: + case 3505061888: + case 3509649408: + case 3533635584: + case 3521052672: + case 3523149824: + case 3508469760: + case 3493789696: + case 3495886848: + case 3512664064: + case 3514761216: + case 3497984000: + case 3502178304: + case 3523411968: + case 3502571520: + case 3492151296: + case 3507159040: + case 3496738816: + case 3532587008: + case 3522166784: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_DS(uint64_t I){ + switch( I & 4261281792 ){ + case 3623878656: + case 3624009728: + case 3624271872: + case 3624140800: + case 3624402944: + case 3624534016: + case 3624665088: + case 3624796160: + case 3624927232: + case 3625058304: + case 3625189376: + case 3625451520: + case 3631742976: + case 3635412992: + case 3628072960: + case 3632267264: + case 3644194816: + case 3648782336: + case 3640655872: + case 3636592640: + case 3649306624: + case 3641180160: + case 3637116928: + case 3649830912: + case 3641704448: + case 3637641216: + case 3633577984: + case 3650355200: + case 3629514752: + case 3638165504: + case 3634102272: + case 3630039040: + case 3625975808: + case 3638689792: + case 3634626560: + case 3651403776: + case 3630563328: + case 3626500096: + case 3635150848: + case 3631087616: + case 3643801600: + case 3625582592: + case 3627679744: + case 3631874048: + case 3631349760: + case 3635544064: + case 3628204032: + case 3632398336: + case 3628728320: + case 3632922624: + case 3629252608: + case 3644325888: + case 3652976640: + case 3648913408: + case 3640786944: + case 3636723712: + case 3649437696: + case 3628597248: + case 3641311232: + case 3637248000: + case 3649961984: + case 3629121536: + case 3641835520: + case 3637772288: + case 3633709056: + case 3650486272: + case 3629645824: + case 3642359808: + case 3638296576: + case 3634233344: + case 3630170112: + case 3626106880: + case 3638820864: + case 3634757632: + case 3651534848: + case 3630694400: + case 3626631168: + case 3643408384: + case 3639345152: + case 3635281920: + case 3631218688: + case 3643932672: + case 3625713664: + case 3631480832: + case 3627810816: + case 3632005120: + case 3628335104: + case 3632529408: + case 3635675136: + case 3628859392: + case 3633053696: + case 3629383680: + case 3644456960: + case 3640393728: + case 3657170944: + case 3653107712: + case 3649044480: + case 3640918016: + case 3636854784: + case 3632791552: + case 3649568768: + case 3641442304: + case 3637379072: + case 3633315840: + case 3650093056: + case 3641966592: + case 3637903360: + case 3633840128: + case 3629776896: + case 3638427648: + case 3634364416: + case 3630301184: + case 3626237952: + case 3643015168: + case 3647733760: + case 3638951936: + case 3634888704: + case 3630825472: + case 3639476224: + case 3625320448: + case 3625844736: + case 3631611904: + case 3627941888: + case 3632136192: + case 3628466176: + case 3632660480: + case 3628990464: + case 3633184768: + case 3635806208: + case 3644063744: + case 3648651264: + case 3657302016: + case 3636461568: + case 3649175552: + case 3641049088: + case 3636985856: + case 3649699840: + case 3641573376: + case 3637510144: + case 3633446912: + case 3650224128: + case 3642097664: + case 3638034432: + case 3633971200: + case 3650748416: + case 3629907968: + case 3638558720: + case 3634495488: + case 3630432256: + case 3626369024: + case 3643146240: + case 3635019776: + case 3630956544: + case 3639607296: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MUBUF(uint64_t I){ + switch( I & 4261150720 ){ + case 3758096384: + case 3758358528: + case 3759144960: + case 3758620672: + case 3758882816: + case 3759407104: + case 3759669248: + case 3759931392: + case 3760193536: + case 3760455680: + case 3760717824: + case 3760979968: + case 3761242112: + case 3761504256: + case 3761766400: + case 3762028544: + case 3765698560: + case 3765960704: + case 3774349312: + case 3778019328: + case 3778543616: + case 3766222848: + case 3774611456: + case 3786407936: + case 3762290688: + case 3766484992: + case 3774873600: + case 3783262208: + case 3762552832: + case 3766747136: + case 3775135744: + case 3783524352: + case 3762814976: + case 3767009280: + case 3775397888: + case 3783786496: + case 3774087168: + case 3763077120: + case 3767271424: + case 3775660032: + case 3778281472: + case 3784048640: + case 3763339264: + case 3767533568: + case 3775922176: + case 3784310784: + case 3763601408: + case 3767795712: + case 3776184320: + case 3784572928: + case 3763863552: + case 3768057856: + case 3776446464: + case 3784835072: + case 3764125696: + case 3768320000: + case 3776708608: + case 3785097216: + case 3764387840: + case 3776970752: + case 3785359360: + case 3777757184: + case 3764649984: + case 3777232896: + case 3785621504: + case 3786145792: + case 3764912128: + case 3777495040: + case 3785883648: + case 3765174272: + case 3765436416: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MTBUF(uint64_t I){ + switch( I & 4228349952 ){ + case 3892314112: + case 3892346880: + case 3892412416: + case 3892445184: + case 3892379648: + case 3892477952: + case 3892510720: + case 3892543488: + case 3892576256: + case 3892609024: + case 3892641792: + case 3892674560: + case 3892707328: + case 3892740096: + case 3892772864: + case 3892805632: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MIMG(uint64_t I){ + switch( I & 4261150720 ){ + case 4026531840: + case 4026793984: + case 4027580416: + case 4027056128: + case 4027318272: + case 4027842560: + case 4028628992: + case 4028891136: + case 4029153280: + case 4029415424: + case 4030201856: + case 4030726144: + case 4031250432: + case 4031774720: + case 4038066176: + case 4038590464: + case 4042784768: + case 4043309056: + case 4043833344: + case 4035706880: + case 4044357632: + case 4036231168: + case 4044881920: + case 4036755456: + case 4045406208: + case 4037279744: + case 4054056960: + case 4045930496: + case 4037804032: + case 4054581248: + case 4046454784: + case 4038328320: + case 4055105536: + case 4046979072: + case 4055629824: + case 4047503360: + case 4039901184: + case 4048551936: + case 4040425472: + case 4032299008: + case 4049076224: + case 4040949760: + case 4032823296: + case 4049600512: + case 4041474048: + case 4033347584: + case 4041998336: + case 4050649088: + case 4033871872: + case 4030988288: + case 4031512576: + case 4038852608: + case 4043046912: + case 4047241216: + case 4051435520: + case 4035182592: + case 4039376896: + case 4043571200: + case 4047765504: + case 4042522624: + case 4051173376: + case 4034920448: + case 4051697664: + case 4035444736: + case 4050911232: + case 4035969024: + case 4044619776: + case 4036493312: + case 4045144064: + case 4037017600: + case 4053794816: + case 4045668352: + case 4037541888: + case 4054319104: + case 4046192640: + case 4054843392: + case 4046716928: + case 4055367680: + case 4039114752: + case 4039639040: + case 4040163328: + case 4032036864: + case 4048814080: + case 4040687616: + case 4032561152: + case 4049338368: + case 4041211904: + case 4033085440: + case 4049862656: + case 4041736192: + case 4033609728: + case 4042260480: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_EXP(uint64_t I){ + switch( I & 4227858432 ){ + case 3288334336: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT(uint64_t I){ + switch( I & 4261199872 ){ + case 3695181824: + case 3695443968: + case 3696230400: + case 3695706112: + case 3695968256: + case 3696492544: + case 3696754688: + case 3697016832: + case 3697278976: + case 3697541120: + case 3697803264: + case 3698065408: + case 3698327552: + case 3698589696: + case 3698851840: + case 3699113984: + case 3699376128: + case 3707764736: + case 3716153344: + case 3699638272: + case 3708026880: + case 3716415488: + case 3719036928: + case 3699900416: + case 3708289024: + case 3716677632: + case 3700162560: + case 3708551168: + case 3716939776: + case 3700424704: + case 3708813312: + case 3717201920: + case 3700686848: + case 3709075456: + case 3717464064: + case 3709337600: + case 3717726208: + case 3709599744: + case 3717988352: + case 3719299072: + case 3709861888: + case 3718250496: + case 3710124032: + case 3718512640: + case 3710386176: + case 3718774784: + case 3710648320: + case 3710910464: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT_GLBL(uint64_t I){ + switch( I & 4261199872 ){ + case 3695214592: + case 3695476736: + case 3696263168: + case 3696001024: + case 3695738880: + case 3696525312: + case 3696787456: + case 3697049600: + case 3697311744: + case 3697573888: + case 3697836032: + case 3710156800: + case 3718545408: + case 3710418944: + case 3718807552: + case 3710681088: + case 3719069696: + case 3710943232: + case 3719331840: + case 3698098176: + case 3698360320: + case 3698622464: + case 3698884608: + case 3699146752: + case 3699408896: + case 3699671040: + case 3699933184: + case 3700457472: + case 3700195328: + case 3711205376: + case 3711467520: + case 3718021120: + case 3707797504: + case 3716186112: + case 3708059648: + case 3716448256: + case 3708321792: + case 3716710400: + case 3709894656: + case 3708583936: + case 3716972544: + case 3718283264: + case 3708846080: + case 3717234688: + case 3700719616: + case 3709108224: + case 3717496832: + case 3709370368: + case 3717758976: + case 3709632512: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT_SCRATCH(uint64_t I){ + switch( I & 4261199872 ){ + case 3695198208: + case 3695460352: + case 3696246784: + case 3695722496: + case 3695984640: + case 3696508928: + case 3696771072: + case 3697033216: + case 3697295360: + case 3697557504: + case 3697819648: + case 3698081792: + case 3698343936: + case 3698606080: + case 3698868224: + case 3699130368: + case 3699392512: + case 3699654656: + case 3699916800: + case 3700178944: + case 3700441088: + case 3700703232: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_SOPK_INST_LITERAL_(uint64_t I){ + switch( I & 4286578688 ){ + case 3120562176: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP2_LITERAL(uint64_t I){ + switch( I & 4261412864 ){ + case 771751936: + case 805306368: + case 1207959552: + case 1241513984: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3B(uint64_t I){ + switch( I & 4294901760 ){ + case 3508076544: + case 3508142080: + case 3508338688: + case 3508207616: + case 3508273152: + case 3508404224: + case 3521118208: + case 3521183744: + case 3521642496: + case 3521708032: + return true; + default: + return false; + } +} +bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3P_MFMA(uint64_t I){ + switch( I & 4294901760 ){ + case 3552575488: + case 3552641024: + case 3552903168: + case 3552706560: + case 3552837632: + case 3553099776: + case 3553165312: + case 3553230848: + case 3553361920: + case 3553427456: + case 3553624064: + case 3553689600: + case 3553755136: + case 3553886208: + case 3553951744: + case 3555196928: + case 3555262464: + case 3555393536: + case 3555459072: + case 3555524608: + return true; + default: + return false; + } +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SOP1(){ + insn_size = 4; + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<8,15>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPC(){ + insn_size = 4; + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPP(){ + insn_size = 4; + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPK(){ + insn_size = 4; + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPKOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SOP2(){ + insn_size = 4; + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + layout.ENCODING = longfield<30,31>(insn_long); + layout.OP = longfield<23,29>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_SMEM(){ + insn_size = 8; + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.IMM = longfield<17,17>(insn_long); + layout.NV = longfield<15,15>(insn_long); + layout.OFFSET = longfield<32,52>(insn_long); + layout.OP = longfield<18,25>(insn_long); + layout.SBASE = (longfield<0,5>(insn_long) << 1 ) | 0 ; + layout.SDATA = longfield<6,12>(insn_long); + layout.SOFFSET = longfield<57,63>(insn_long); + layout.SOFFSET_EN = longfield<14,14>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SMEMOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP1(){ + insn_size = 4; + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<9,16>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOPC(){ + insn_size = 4; + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2(){ + insn_size = 4; + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VINTRP(){ + insn_size = 4; + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + layout.ATTR = longfield<10,15>(insn_long); + layout.ATTRCHAN = longfield<8,9>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.OP = longfield<16,17>(insn_long); + layout.VDST = longfield<18,25>(insn_long); + layout.VSRC = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VINTRPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P(){ + insn_size = 8; + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.NEG_HI = longfield<8,10>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.OP_SEL = longfield<11,13>(insn_long); + layout.OP_SEL_HI = longfield<59,60>(insn_long); + layout.OP_SEL_HI_2 = longfield<14,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3POperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3(){ + insn_size = 8; + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + layout.ABS = longfield<8,10>(insn_long); + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.OP_SEL = longfield<11,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_DS(){ + insn_size = 8; + layout_ENC_DS & layout = insn_layout.ENC_DS; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA0 = longfield<40,47>(insn_long); + layout.DATA1 = longfield<48,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GDS = longfield<16,16>(insn_long); + layout.OFFSET0 = longfield<0,7>(insn_long); + layout.OFFSET1 = longfield<8,15>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_DS_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_DS_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_DS_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_DSOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_MUBUF(){ + insn_size = 8; + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.LDS = longfield<16,16>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<55,55>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MUBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_MTBUF(){ + insn_size = 8; + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + layout.DFMT = longfield<19,22>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.NFMT = longfield<23,25>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<15,18>(insn_long); + layout.SLC = longfield<54,54>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<55,55>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MTBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_MIMG(){ + insn_size = 8; + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + layout.A16 = longfield<15,15>(insn_long); + layout.D16 = longfield<63,63>(insn_long); + layout.DA = longfield<14,14>(insn_long); + layout.DMASK = longfield<8,11>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<13,13>(insn_long); + layout.LWE = longfield<17,17>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.OPM = longfield<0,0>(insn_long); + layout.SLC = longfield<25,25>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.SSAMP = (longfield<53,57>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<16,16>(insn_long); + layout.UNORM = longfield<12,12>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MIMGOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_EXP(){ + insn_size = 8; + layout_ENC_EXP & layout = insn_layout.ENC_EXP; +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT(){ + insn_size = 8; + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLATOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_GLBL(){ + insn_size = 8; + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_GLBLOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_SCRATCH(){ + insn_size = 8; + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_SCRATCHOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeSOPK_INST_LITERAL_(){ + insn_size = 8; + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table) / sizeof(amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeSOPK_INST_LITERAL_Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2_LITERAL(){ + insn_size = 8; + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2_LITERALOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3B(){ + insn_size = 8; + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.SDST = longfield<8,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3BOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P_MFMA(){ + insn_size = 8; + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + layout.ABID = longfield<11,14>(insn_long); + layout.ACC = longfield<59,60>(insn_long); + layout.BLGP = longfield<61,63>(insn_long); + layout.CBSZ = longfield<8,10>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert( layout.OP >= 0 && layout.OP < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3P_MFMAOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); +} +void InstructionDecoder_amdgpu_gfx908::mainDecodeOpcode(){ + if(IS_ENC_SOP1(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<8,15>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP1; + } + else if(IS_ENC_SOPC(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPC; + } + else if(IS_ENC_SOPP(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPP; + } + else if(IS_ENC_SOPK(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<23,27>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPK; + } + else if(IS_ENC_SOP2(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<23,29>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP2; + } + else if(IS_ENC_SMEM(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,25>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SMEM; + } + else if(IS_ENC_VOP1(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<9,16>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP1; + } + else if(IS_ENC_VOPC(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<17,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOPC; + } + else if(IS_ENC_VOP2(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<25,30>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2; + } + else if(IS_ENC_VINTRP(insn_long)){ + insn_size = 4; + uint32_t op_value = longfield<16,17>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VINTRP; + } + else if(IS_ENC_VOP3P(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P; + } + else if(IS_ENC_VOP3(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3; + } + else if(IS_ENC_DS(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<17,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_DS_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_DS_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_DS_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_DS; + } + else if(IS_ENC_MUBUF(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MUBUF; + } + else if(IS_ENC_MTBUF(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<15,18>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MTBUF; + } + else if(IS_ENC_MIMG(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MIMG; + } + else if(IS_ENC_EXP(insn_long)){ + insn_size = 8; + instr_family = ENC_EXP; + } + else if(IS_ENC_FLAT(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT; + } + else if(IS_ENC_FLAT_GLBL(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_GLBL; + } + else if(IS_ENC_FLAT_SCRATCH(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_SCRATCH; + } + else if(IS_SOPK_INST_LITERAL_(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<23,27>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table) / sizeof(amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = SOPK_INST_LITERAL_; + } + else if(IS_ENC_VOP2_LITERAL(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<25,30>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2_LITERAL; + } + else if(IS_ENC_VOP3B(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3B; + } + else if(IS_ENC_VOP3P_MFMA(insn_long)){ + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert( op_value < sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table) / sizeof(amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table[0]) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P_MFMA; + } +} +void InstructionDecoder_amdgpu_gfx908::mainDecode(){ + if(IS_ENC_SOP1(insn_long)){ + decodeENC_SOP1(); + } + else if(IS_ENC_SOPC(insn_long)){ + decodeENC_SOPC(); + } + else if(IS_ENC_SOPP(insn_long)){ + decodeENC_SOPP(); + } + else if(IS_ENC_SOPK(insn_long)){ + decodeENC_SOPK(); + } + else if(IS_ENC_SOP2(insn_long)){ + decodeENC_SOP2(); + } + else if(IS_ENC_SMEM(insn_long)){ + decodeENC_SMEM(); + } + else if(IS_ENC_VOP1(insn_long)){ + decodeENC_VOP1(); + } + else if(IS_ENC_VOPC(insn_long)){ + decodeENC_VOPC(); + } + else if(IS_ENC_VOP2(insn_long)){ + decodeENC_VOP2(); + } + else if(IS_ENC_VINTRP(insn_long)){ + decodeENC_VINTRP(); + } + else if(IS_ENC_VOP3P(insn_long)){ + decodeENC_VOP3P(); + } + else if(IS_ENC_VOP3(insn_long)){ + decodeENC_VOP3(); + } + else if(IS_ENC_DS(insn_long)){ + decodeENC_DS(); + } + else if(IS_ENC_MUBUF(insn_long)){ + decodeENC_MUBUF(); + } + else if(IS_ENC_MTBUF(insn_long)){ + decodeENC_MTBUF(); + } + else if(IS_ENC_MIMG(insn_long)){ + decodeENC_MIMG(); + } + else if(IS_ENC_EXP(insn_long)){ + decodeENC_EXP(); + } + else if(IS_ENC_FLAT(insn_long)){ + decodeENC_FLAT(); + } + else if(IS_ENC_FLAT_GLBL(insn_long)){ + decodeENC_FLAT_GLBL(); + } + else if(IS_ENC_FLAT_SCRATCH(insn_long)){ + decodeENC_FLAT_SCRATCH(); + } + else if(IS_SOPK_INST_LITERAL_(insn_long)){ + decodeSOPK_INST_LITERAL_(); + } + else if(IS_ENC_VOP2_LITERAL(insn_long)){ + decodeENC_VOP2_LITERAL(); + } + else if(IS_ENC_VOP3B(insn_long)){ + decodeENC_VOP3B(); + } + else if(IS_ENC_VOP3P_MFMA(insn_long)){ + decodeENC_VOP3P_MFMA(); + } +} diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.h b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.h new file mode 100644 index 0000000000..41849f55a7 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.h @@ -0,0 +1,401 @@ +static bool IS_ENC_SOP1(uint64_t I); +static bool IS_ENC_SOPC(uint64_t I); +static bool IS_ENC_SOPP(uint64_t I); +static bool IS_ENC_SOPK(uint64_t I); +static bool IS_ENC_SOP2(uint64_t I); +static bool IS_ENC_SMEM(uint64_t I); +static bool IS_ENC_VOP1(uint64_t I); +static bool IS_ENC_VOPC(uint64_t I); +static bool IS_ENC_VOP2(uint64_t I); +static bool IS_ENC_VINTRP(uint64_t I); +static bool IS_ENC_VOP3P(uint64_t I); +static bool IS_ENC_VOP3(uint64_t I); +static bool IS_ENC_DS(uint64_t I); +static bool IS_ENC_MUBUF(uint64_t I); +static bool IS_ENC_MTBUF(uint64_t I); +static bool IS_ENC_MIMG(uint64_t I); +static bool IS_ENC_EXP(uint64_t I); +static bool IS_ENC_FLAT(uint64_t I); +static bool IS_ENC_FLAT_GLBL(uint64_t I); +static bool IS_ENC_FLAT_SCRATCH(uint64_t I); +static bool IS_SOPK_INST_LITERAL_(uint64_t I); +static bool IS_ENC_VOP2_LITERAL(uint64_t I); +static bool IS_ENC_VOP3B(uint64_t I); +static bool IS_ENC_VOP3P_MFMA(uint64_t I); +enum InstructionFamily{ + ENC_SOP1 = -1, + ENC_SOPC = 0, + ENC_SOPP = 1, + ENC_SOPK = 2, + ENC_SOP2 = 3, + ENC_SMEM = 4, + ENC_VOP1 = 5, + ENC_VOPC = 6, + ENC_VOP2 = 7, + ENC_VINTRP = 8, + ENC_VOP3P = 9, + ENC_VOP3 = 10, + ENC_DS = 11, + ENC_MUBUF = 12, + ENC_MTBUF = 13, + ENC_MIMG = 14, + ENC_EXP = 15, + ENC_FLAT = 16, + ENC_FLAT_GLBL = 17, + ENC_FLAT_SCRATCH = 18, + SOPK_INST_LITERAL_ = 19, + ENC_VOP2_LITERAL = 20, + ENC_VOP3B = 21, + ENC_VOP3P_MFMA = 22, +}; +InstructionFamily instr_family; +typedef void (InstructionDecoder_amdgpu_gfx908::*func_ptr)(void); +func_ptr decode_lookup_table [24] = { + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SOP1), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SOPC), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SOPP), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SOPK), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SOP2), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_SMEM), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP1), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOPC), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VINTRP), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_DS), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_MUBUF), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_MTBUF), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_MIMG), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_EXP), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_GLBL), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_SCRATCH), + (&InstructionDecoder_amdgpu_gfx908::decodeSOPK_INST_LITERAL_), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2_LITERAL), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3B), + (&InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P_MFMA), +}; +typedef struct layout_ENC_SOP1{ + uint16_t ENCODING : 9 ; + uint8_t OP : 8 ; + uint8_t SDST : 7 ; + uint8_t SSRC0 : 8 ; +}layout_ENC_SOP1; +typedef struct layout_ENC_SOPC{ + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint8_t SSRC0 : 8 ; + uint8_t SSRC1 : 8 ; +}layout_ENC_SOPC; +typedef struct layout_ENC_SOPP{ + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint16_t SIMM16 : 16 ; +}layout_ENC_SOPP; +typedef struct layout_ENC_SOPK{ + uint8_t ENCODING : 4 ; + uint8_t OP : 5 ; + uint8_t SDST : 7 ; + uint16_t SIMM16 : 16 ; +}layout_ENC_SOPK; +typedef struct layout_ENC_SOP2{ + uint8_t ENCODING : 2 ; + uint8_t OP : 7 ; + uint8_t SDST : 7 ; + uint8_t SSRC0 : 8 ; + uint8_t SSRC1 : 8 ; +}layout_ENC_SOP2; +typedef struct layout_ENC_SMEM{ + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IMM : 1 ; + uint8_t NV : 1 ; + uint32_t OFFSET : 21 ; + uint8_t OP : 8 ; + uint8_t SBASE : 6 ; + uint8_t SDATA : 7 ; + uint8_t SOFFSET : 7 ; + uint8_t SOFFSET_EN : 1 ; +}layout_ENC_SMEM; +typedef struct layout_ENC_VOP1{ + uint8_t ENCODING : 7 ; + uint8_t OP : 8 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP1; +typedef struct layout_ENC_VOPC{ + uint8_t ENCODING : 7 ; + uint8_t OP : 8 ; + uint16_t SRC0 : 9 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOPC; +typedef struct layout_ENC_VOP2{ + uint8_t ENCODING : 1 ; + uint8_t OP : 6 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOP2; +typedef struct layout_ENC_VINTRP{ + uint8_t ATTR : 6 ; + uint8_t ATTRCHAN : 2 ; + uint8_t ENCODING : 6 ; + uint8_t OP : 2 ; + uint8_t VDST : 8 ; + uint8_t VSRC : 8 ; +}layout_ENC_VINTRP; +typedef struct layout_ENC_VOP3P{ + uint8_t CLAMP : 1 ; + uint16_t ENCODING : 9 ; + uint8_t NEG : 3 ; + uint8_t NEG_HI : 3 ; + uint8_t OP : 7 ; + uint8_t OP_SEL : 3 ; + uint8_t OP_SEL_HI : 2 ; + uint8_t OP_SEL_HI_2 : 1 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3P; +typedef struct layout_ENC_VOP3{ + uint8_t ABS : 3 ; + uint8_t CLAMP : 1 ; + uint8_t ENCODING : 6 ; + uint8_t NEG : 3 ; + uint8_t OMOD : 2 ; + uint16_t OP : 10 ; + uint8_t OP_SEL : 4 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3; +typedef struct layout_ENC_DS{ + uint8_t ADDR : 8 ; + uint8_t DATA0 : 8 ; + uint8_t DATA1 : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GDS : 1 ; + uint8_t OFFSET0 : 8 ; + uint8_t OFFSET1 : 8 ; + uint8_t OP : 8 ; + uint8_t VDST : 8 ; +}layout_ENC_DS; +typedef struct layout_ENC_MUBUF{ + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IDXEN : 1 ; + uint8_t LDS : 1 ; + uint8_t OFFEN : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 7 ; + uint8_t SLC : 1 ; + uint8_t SOFFSET : 8 ; + uint8_t SRSRC : 5 ; + uint8_t TFE : 1 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MUBUF; +typedef struct layout_ENC_MTBUF{ + uint8_t DFMT : 4 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t IDXEN : 1 ; + uint8_t NFMT : 3 ; + uint8_t OFFEN : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 4 ; + uint8_t SLC : 1 ; + uint8_t SOFFSET : 8 ; + uint8_t SRSRC : 5 ; + uint8_t TFE : 1 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MTBUF; +typedef struct layout_ENC_MIMG{ + uint8_t A16 : 1 ; + uint8_t D16 : 1 ; + uint8_t DA : 1 ; + uint8_t DMASK : 4 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LWE : 1 ; + uint8_t OP : 7 ; + uint8_t OPM : 1 ; + uint8_t SLC : 1 ; + uint8_t SRSRC : 5 ; + uint8_t SSAMP : 5 ; + uint8_t TFE : 1 ; + uint8_t UNORM : 1 ; + uint8_t VADDR : 8 ; + uint8_t VDATA : 8 ; +}layout_ENC_MIMG; +typedef struct layout_ENC_EXP{ + uint8_t COMPR : 1 ; + uint8_t DONE : 1 ; + uint8_t EN : 4 ; + uint8_t ENCODING : 6 ; + uint8_t TGT : 6 ; + uint8_t VM : 1 ; + uint8_t VSRC0 : 8 ; + uint8_t VSRC1 : 8 ; + uint8_t VSRC2 : 8 ; + uint8_t VSRC3 : 8 ; +}layout_ENC_EXP; +typedef struct layout_ENC_FLAT{ + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint8_t NV : 1 ; + uint16_t OFFSET : 12 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT; +typedef struct layout_ENC_FLAT_GLBL{ + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint8_t NV : 1 ; + uint16_t OFFSET : 13 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT_GLBL; +typedef struct layout_ENC_FLAT_SCRATCH{ + uint8_t ADDR : 8 ; + uint8_t DATA : 8 ; + uint8_t ENCODING : 6 ; + uint8_t GLC : 1 ; + uint8_t LDS : 1 ; + uint8_t NV : 1 ; + uint16_t OFFSET : 13 ; + uint8_t OP : 7 ; + uint8_t SADDR : 7 ; + uint8_t SEG : 2 ; + uint8_t SLC : 1 ; + uint8_t VDST : 8 ; +}layout_ENC_FLAT_SCRATCH; +typedef struct layout_SOPK_INST_LITERAL_{ + uint8_t ENCODING : 4 ; + uint8_t OP : 5 ; + uint8_t SDST : 7 ; + uint16_t SIMM16 : 16 ; + uint32_t SIMM32 : 32 ; +}layout_SOPK_INST_LITERAL_; +typedef struct layout_ENC_VOP2_LITERAL{ + uint8_t ENCODING : 1 ; + uint8_t OP : 6 ; + uint32_t SIMM32 : 32 ; + uint16_t SRC0 : 9 ; + uint8_t VDST : 8 ; + uint8_t VSRC1 : 8 ; +}layout_ENC_VOP2_LITERAL; +typedef struct layout_ENC_VOP3B{ + uint8_t CLAMP : 1 ; + uint8_t ENCODING : 6 ; + uint8_t NEG : 3 ; + uint8_t OMOD : 2 ; + uint16_t OP : 10 ; + uint8_t SDST : 7 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3B; +typedef struct layout_ENC_VOP3P_MFMA{ + uint8_t ABID : 4 ; + uint8_t ACC : 2 ; + uint8_t BLGP : 3 ; + uint8_t CBSZ : 3 ; + uint16_t ENCODING : 9 ; + uint8_t OP : 7 ; + uint16_t SRC0 : 9 ; + uint16_t SRC1 : 9 ; + uint16_t SRC2 : 9 ; + uint8_t VDST : 8 ; +}layout_ENC_VOP3P_MFMA; +union insn_layout{ + layout_ENC_SOP1 ENC_SOP1; + layout_ENC_SOPC ENC_SOPC; + layout_ENC_SOPP ENC_SOPP; + layout_ENC_SOPK ENC_SOPK; + layout_ENC_SOP2 ENC_SOP2; + layout_ENC_SMEM ENC_SMEM; + layout_ENC_VOP1 ENC_VOP1; + layout_ENC_VOPC ENC_VOPC; + layout_ENC_VOP2 ENC_VOP2; + layout_ENC_VINTRP ENC_VINTRP; + layout_ENC_VOP3P ENC_VOP3P; + layout_ENC_VOP3 ENC_VOP3; + layout_ENC_DS ENC_DS; + layout_ENC_MUBUF ENC_MUBUF; + layout_ENC_MTBUF ENC_MTBUF; + layout_ENC_MIMG ENC_MIMG; + layout_ENC_EXP ENC_EXP; + layout_ENC_FLAT ENC_FLAT; + layout_ENC_FLAT_GLBL ENC_FLAT_GLBL; + layout_ENC_FLAT_SCRATCH ENC_FLAT_SCRATCH; + layout_SOPK_INST_LITERAL_ SOPK_INST_LITERAL_; + layout_ENC_VOP2_LITERAL ENC_VOP2_LITERAL; + layout_ENC_VOP3B ENC_VOP3B; + layout_ENC_VOP3P_MFMA ENC_VOP3P_MFMA; +}insn_layout; +void decodeENC_SOP1(); +void finalizeENC_SOP1Operands(); +void decodeENC_SOPC(); +void finalizeENC_SOPCOperands(); +void decodeENC_SOPP(); +void finalizeENC_SOPPOperands(); +void decodeENC_SOPK(); +void finalizeENC_SOPKOperands(); +void decodeENC_SOP2(); +void finalizeENC_SOP2Operands(); +void decodeENC_SMEM(); +void finalizeENC_SMEMOperands(); +void decodeENC_VOP1(); +void finalizeENC_VOP1Operands(); +void decodeENC_VOPC(); +void finalizeENC_VOPCOperands(); +void decodeENC_VOP2(); +void finalizeENC_VOP2Operands(); +void decodeENC_VINTRP(); +void finalizeENC_VINTRPOperands(); +void decodeENC_VOP3P(); +void finalizeENC_VOP3POperands(); +void decodeENC_VOP3(); +void finalizeENC_VOP3Operands(); +void decodeENC_DS(); +void finalizeENC_DSOperands(); +void decodeENC_MUBUF(); +void finalizeENC_MUBUFOperands(); +void decodeENC_MTBUF(); +void finalizeENC_MTBUFOperands(); +void decodeENC_MIMG(); +void finalizeENC_MIMGOperands(); +void decodeENC_EXP(); +void finalizeENC_EXPOperands(); +void decodeENC_FLAT(); +void finalizeENC_FLATOperands(); +void decodeENC_FLAT_GLBL(); +void finalizeENC_FLAT_GLBLOperands(); +void decodeENC_FLAT_SCRATCH(); +void finalizeENC_FLAT_SCRATCHOperands(); +void decodeSOPK_INST_LITERAL_(); +void finalizeSOPK_INST_LITERAL_Operands(); +void decodeENC_VOP2_LITERAL(); +void finalizeENC_VOP2_LITERALOperands(); +void decodeENC_VOP3B(); +void finalizeENC_VOP3BOperands(); +void decodeENC_VOP3P_MFMA(); +void finalizeENC_VOP3P_MFMAOperands(); diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h new file mode 100644 index 0000000000..1f68358749 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h @@ -0,0 +1,32 @@ +struct amdgpu_gfx908_insn_entry { + entryID op; + const char *mnemonic; + std::size_t operandCnt; + const operandFactory *operands; + static const amdgpu_gfx908_insn_table main_insn_table ; + static const operandFactory operandTable[] ; + static const amdgpu_gfx908_insn_table ENC_DS_insn_table ; + static const amdgpu_gfx908_insn_table ENC_EXP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_GLBL_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_SCRATCH_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MIMG_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MTBUF_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MUBUF_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SMEM_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOP1_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOP2_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPC_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPK_insn_table ; + static const amdgpu_gfx908_insn_table SOPK_INST_LITERAL__insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VINTRP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP1_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP2_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP2_LITERAL_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3B_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3P_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3P_MFMA_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOPC_insn_table ; +}; diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_opcode_tables.C b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_opcode_tables.C new file mode 100644 index 0000000000..efcd206364 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_opcode_tables.C @@ -0,0 +1,2982 @@ +#define fn(...) (&InstructionDecoder_amdgpu_gfx908::__VA_ARGS__) +const operandFactory amdgpu_gfx908_insn_entry::operandTable[] = { + fn(NOTHING), +}; +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_DS_insn_table = { +{amdgpu_gfx908_op_DS_ADD_U32,"DS_ADD_U32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_DS_SUB_U32,"DS_SUB_U32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_DS_RSUB_U32,"DS_RSUB_U32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_DS_INC_U32,"DS_INC_U32",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_DS_DEC_U32,"DS_DEC_U32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_DS_MIN_I32,"DS_MIN_I32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_DS_MAX_I32,"DS_MAX_I32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_DS_MIN_U32,"DS_MIN_U32",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_DS_MAX_U32,"DS_MAX_U32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_DS_AND_B32,"DS_AND_B32",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_DS_OR_B32,"DS_OR_B32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_DS_XOR_B32,"DS_XOR_B32",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_DS_MSKOR_B32,"DS_MSKOR_B32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_DS_WRITE_B32,"DS_WRITE_B32",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_DS_WRITE2_B32,"DS_WRITE2_B32",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_DS_CMPST_B32,"DS_CMPST_B32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_DS_CMPST_F32,"DS_CMPST_F32",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_DS_MIN_F32,"DS_MIN_F32",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_DS_MAX_F32,"DS_MAX_F32",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_DS_NOP,"DS_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_DS_ADD_F32,"DS_ADD_F32",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_DS_WRITE_B8,"DS_WRITE_B8",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_DS_WRITE_B16,"DS_WRITE_B16",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_DS_INC_RTN_U32,"DS_INC_RTN_U32",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_DS_AND_RTN_B32,"DS_AND_RTN_B32",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_DS_OR_RTN_B32,"DS_OR_RTN_B32",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_DS_READ_B32,"DS_READ_B32",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_DS_READ2_B32,"DS_READ2_B32",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_DS_READ2ST64_B32,"DS_READ2ST64_B32",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_DS_READ_I8,"DS_READ_I8",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_DS_READ_U8,"DS_READ_U8",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_DS_READ_I16,"DS_READ_I16",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_DS_READ_U16,"DS_READ_U16",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_DS_PERMUTE_B32,"DS_PERMUTE_B32",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_DS_ADD_U64,"DS_ADD_U64",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_DS_SUB_U64,"DS_SUB_U64",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_DS_RSUB_U64,"DS_RSUB_U64",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_DS_INC_U64,"DS_INC_U64",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_DS_DEC_U64,"DS_DEC_U64",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_DS_MIN_I64,"DS_MIN_I64",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_DS_MAX_I64,"DS_MAX_I64",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_DS_MIN_U64,"DS_MIN_U64",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_DS_MAX_U64,"DS_MAX_U64",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_DS_AND_B64,"DS_AND_B64",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_DS_OR_B64,"DS_OR_B64",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_DS_XOR_B64,"DS_XOR_B64",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_DS_MSKOR_B64,"DS_MSKOR_B64",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_DS_WRITE_B64,"DS_WRITE_B64",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_DS_WRITE2_B64,"DS_WRITE2_B64",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_DS_CMPST_B64,"DS_CMPST_B64",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_DS_CMPST_F64,"DS_CMPST_F64",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_DS_MIN_F64,"DS_MIN_F64",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_DS_MAX_F64,"DS_MAX_F64",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_DS_READ_U8_D16,"DS_READ_U8_D16",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_DS_READ_I8_D16,"DS_READ_I8_D16",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_DS_READ_U16_D16,"DS_READ_U16_D16",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_DS_INC_RTN_U64,"DS_INC_RTN_U64",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_DS_AND_RTN_B64,"DS_AND_RTN_B64",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_DS_OR_RTN_B64,"DS_OR_RTN_B64",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64",0,&operandTable[0]} ,//111 +{amdgpu_gfx908_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64",0,&operandTable[0]} ,//112 +{amdgpu_gfx908_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64",0,&operandTable[0]} ,//113 +{amdgpu_gfx908_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64",0,&operandTable[0]} ,//114 +{amdgpu_gfx908_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64",0,&operandTable[0]} ,//115 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_gfx908_op_DS_READ_B64,"DS_READ_B64",0,&operandTable[0]} ,//118 +{amdgpu_gfx908_op_DS_READ2_B64,"DS_READ2_B64",0,&operandTable[0]} ,//119 +{amdgpu_gfx908_op_DS_READ2ST64_B64,"DS_READ2ST64_B64",0,&operandTable[0]} ,//120 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_gfx908_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64",0,&operandTable[0]} ,//126 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_gfx908_op_DS_ADD_SRC2_U32,"DS_ADD_SRC2_U32",0,&operandTable[0]} ,//128 +{amdgpu_gfx908_op_DS_SUB_SRC2_U32,"DS_SUB_SRC2_U32",0,&operandTable[0]} ,//129 +{amdgpu_gfx908_op_DS_RSUB_SRC2_U32,"DS_RSUB_SRC2_U32",0,&operandTable[0]} ,//130 +{amdgpu_gfx908_op_DS_INC_SRC2_U32,"DS_INC_SRC2_U32",0,&operandTable[0]} ,//131 +{amdgpu_gfx908_op_DS_DEC_SRC2_U32,"DS_DEC_SRC2_U32",0,&operandTable[0]} ,//132 +{amdgpu_gfx908_op_DS_MIN_SRC2_I32,"DS_MIN_SRC2_I32",0,&operandTable[0]} ,//133 +{amdgpu_gfx908_op_DS_MAX_SRC2_I32,"DS_MAX_SRC2_I32",0,&operandTable[0]} ,//134 +{amdgpu_gfx908_op_DS_MIN_SRC2_U32,"DS_MIN_SRC2_U32",0,&operandTable[0]} ,//135 +{amdgpu_gfx908_op_DS_MAX_SRC2_U32,"DS_MAX_SRC2_U32",0,&operandTable[0]} ,//136 +{amdgpu_gfx908_op_DS_AND_SRC2_B32,"DS_AND_SRC2_B32",0,&operandTable[0]} ,//137 +{amdgpu_gfx908_op_DS_OR_SRC2_B32,"DS_OR_SRC2_B32",0,&operandTable[0]} ,//138 +{amdgpu_gfx908_op_DS_XOR_SRC2_B32,"DS_XOR_SRC2_B32",0,&operandTable[0]} ,//139 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_gfx908_op_DS_WRITE_SRC2_B32,"DS_WRITE_SRC2_B32",0,&operandTable[0]} ,//141 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_gfx908_op_DS_MIN_SRC2_F32,"DS_MIN_SRC2_F32",0,&operandTable[0]} ,//146 +{amdgpu_gfx908_op_DS_MAX_SRC2_F32,"DS_MAX_SRC2_F32",0,&operandTable[0]} ,//147 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_gfx908_op_DS_ADD_SRC2_F32,"DS_ADD_SRC2_F32",0,&operandTable[0]} ,//149 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_gfx908_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL",0,&operandTable[0]} ,//152 +{amdgpu_gfx908_op_DS_GWS_INIT,"DS_GWS_INIT",0,&operandTable[0]} ,//153 +{amdgpu_gfx908_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V",0,&operandTable[0]} ,//154 +{amdgpu_gfx908_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR",0,&operandTable[0]} ,//155 +{amdgpu_gfx908_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P",0,&operandTable[0]} ,//156 +{amdgpu_gfx908_op_DS_GWS_BARRIER,"DS_GWS_BARRIER",0,&operandTable[0]} ,//157 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181 +{amdgpu_gfx908_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32",0,&operandTable[0]} ,//182 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188 +{amdgpu_gfx908_op_DS_CONSUME,"DS_CONSUME",0,&operandTable[0]} ,//189 +{amdgpu_gfx908_op_DS_APPEND,"DS_APPEND",0,&operandTable[0]} ,//190 +{amdgpu_gfx908_op_DS_ORDERED_COUNT,"DS_ORDERED_COUNT",0,&operandTable[0]} ,//191 +{amdgpu_gfx908_op_DS_ADD_SRC2_U64,"DS_ADD_SRC2_U64",0,&operandTable[0]} ,//192 +{amdgpu_gfx908_op_DS_SUB_SRC2_U64,"DS_SUB_SRC2_U64",0,&operandTable[0]} ,//193 +{amdgpu_gfx908_op_DS_RSUB_SRC2_U64,"DS_RSUB_SRC2_U64",0,&operandTable[0]} ,//194 +{amdgpu_gfx908_op_DS_INC_SRC2_U64,"DS_INC_SRC2_U64",0,&operandTable[0]} ,//195 +{amdgpu_gfx908_op_DS_DEC_SRC2_U64,"DS_DEC_SRC2_U64",0,&operandTable[0]} ,//196 +{amdgpu_gfx908_op_DS_MIN_SRC2_I64,"DS_MIN_SRC2_I64",0,&operandTable[0]} ,//197 +{amdgpu_gfx908_op_DS_MAX_SRC2_I64,"DS_MAX_SRC2_I64",0,&operandTable[0]} ,//198 +{amdgpu_gfx908_op_DS_MIN_SRC2_U64,"DS_MIN_SRC2_U64",0,&operandTable[0]} ,//199 +{amdgpu_gfx908_op_DS_MAX_SRC2_U64,"DS_MAX_SRC2_U64",0,&operandTable[0]} ,//200 +{amdgpu_gfx908_op_DS_AND_SRC2_B64,"DS_AND_SRC2_B64",0,&operandTable[0]} ,//201 +{amdgpu_gfx908_op_DS_OR_SRC2_B64,"DS_OR_SRC2_B64",0,&operandTable[0]} ,//202 +{amdgpu_gfx908_op_DS_XOR_SRC2_B64,"DS_XOR_SRC2_B64",0,&operandTable[0]} ,//203 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204 +{amdgpu_gfx908_op_DS_WRITE_SRC2_B64,"DS_WRITE_SRC2_B64",0,&operandTable[0]} ,//205 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209 +{amdgpu_gfx908_op_DS_MIN_SRC2_F64,"DS_MIN_SRC2_F64",0,&operandTable[0]} ,//210 +{amdgpu_gfx908_op_DS_MAX_SRC2_F64,"DS_MAX_SRC2_F64",0,&operandTable[0]} ,//211 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221 +{amdgpu_gfx908_op_DS_WRITE_B96,"DS_WRITE_B96",0,&operandTable[0]} ,//222 +{amdgpu_gfx908_op_DS_WRITE_B128,"DS_WRITE_B128",0,&operandTable[0]} ,//223 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253 +{amdgpu_gfx908_op_DS_READ_B96,"DS_READ_B96",0,&operandTable[0]} ,//254 +{amdgpu_gfx908_op_DS_READ_B128,"DS_READ_B128",0,&operandTable[0]} ,//255 +}; // end ENC_DS_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_EXP_insn_table = { +{amdgpu_gfx908_op_EXP,"EXP",0,&operandTable[0]} ,//0 +}; // end ENC_EXP_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_FLAT_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_FLAT_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_FLAT_GLBL_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_FLAT_GLBL_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_FLAT_SCRATCH_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +}; // end ENC_FLAT_SCRATCH_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_MIMG_insn_table = { +{amdgpu_gfx908_op_IMAGE_LOAD,"IMAGE_LOAD",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_IMAGE_STORE,"IMAGE_STORE",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_IMAGE_SAMPLE,"IMAGE_SAMPLE",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CL,"IMAGE_SAMPLE_CL",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_IMAGE_SAMPLE_D,"IMAGE_SAMPLE_D",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL,"IMAGE_SAMPLE_D_CL",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_IMAGE_SAMPLE_L,"IMAGE_SAMPLE_L",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_IMAGE_SAMPLE_B,"IMAGE_SAMPLE_B",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL,"IMAGE_SAMPLE_B_CL",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_IMAGE_SAMPLE_LZ,"IMAGE_SAMPLE_LZ",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C,"IMAGE_SAMPLE_C",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL,"IMAGE_SAMPLE_C_CL",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_D,"IMAGE_SAMPLE_C_D",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL,"IMAGE_SAMPLE_C_D_CL",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_L,"IMAGE_SAMPLE_C_L",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_B,"IMAGE_SAMPLE_C_B",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL,"IMAGE_SAMPLE_C_B_CL",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ,"IMAGE_SAMPLE_C_LZ",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_IMAGE_SAMPLE_O,"IMAGE_SAMPLE_O",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CL_O,"IMAGE_SAMPLE_CL_O",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_IMAGE_SAMPLE_D_O,"IMAGE_SAMPLE_D_O",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL_O,"IMAGE_SAMPLE_D_CL_O",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_IMAGE_SAMPLE_L_O,"IMAGE_SAMPLE_L_O",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_IMAGE_SAMPLE_B_O,"IMAGE_SAMPLE_B_O",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL_O,"IMAGE_SAMPLE_B_CL_O",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_IMAGE_SAMPLE_LZ_O,"IMAGE_SAMPLE_LZ_O",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_O,"IMAGE_SAMPLE_C_O",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL_O,"IMAGE_SAMPLE_C_CL_O",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_O,"IMAGE_SAMPLE_C_D_O",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL_O,"IMAGE_SAMPLE_C_D_CL_O",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_L_O,"IMAGE_SAMPLE_C_L_O",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_O,"IMAGE_SAMPLE_C_B_O",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL_O,"IMAGE_SAMPLE_C_B_CL_O",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ_O,"IMAGE_SAMPLE_C_LZ_O",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_IMAGE_GATHER4,"IMAGE_GATHER4",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_IMAGE_GATHER4_CL,"IMAGE_GATHER4_CL",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_IMAGE_GATHER4H,"IMAGE_GATHER4H",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_IMAGE_GATHER4_L,"IMAGE_GATHER4_L",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_IMAGE_GATHER4_B,"IMAGE_GATHER4_B",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_IMAGE_GATHER4_B_CL,"IMAGE_GATHER4_B_CL",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_IMAGE_GATHER4_LZ,"IMAGE_GATHER4_LZ",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_IMAGE_GATHER4_C,"IMAGE_GATHER4_C",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_CL,"IMAGE_GATHER4_C_CL",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_IMAGE_GATHER4H_PCK,"IMAGE_GATHER4H_PCK",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_IMAGE_GATHER8H_PCK,"IMAGE_GATHER8H_PCK",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_L,"IMAGE_GATHER4_C_L",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_B,"IMAGE_GATHER4_C_B",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL,"IMAGE_GATHER4_C_B_CL",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ,"IMAGE_GATHER4_C_LZ",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_IMAGE_GATHER4_O,"IMAGE_GATHER4_O",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_IMAGE_GATHER4_CL_O,"IMAGE_GATHER4_CL_O",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_IMAGE_GATHER4_L_O,"IMAGE_GATHER4_L_O",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_IMAGE_GATHER4_B_O,"IMAGE_GATHER4_B_O",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_IMAGE_GATHER4_B_CL_O,"IMAGE_GATHER4_B_CL_O",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_IMAGE_GATHER4_LZ_O,"IMAGE_GATHER4_LZ_O",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_O,"IMAGE_GATHER4_C_O",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_CL_O,"IMAGE_GATHER4_C_CL_O",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_L_O,"IMAGE_GATHER4_C_L_O",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_B_O,"IMAGE_GATHER4_C_B_O",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL_O,"IMAGE_GATHER4_C_B_CL_O",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ_O,"IMAGE_GATHER4_C_LZ_O",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_IMAGE_GET_LOD,"IMAGE_GET_LOD",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CD,"IMAGE_SAMPLE_CD",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL,"IMAGE_SAMPLE_CD_CL",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD,"IMAGE_SAMPLE_C_CD",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL,"IMAGE_SAMPLE_C_CD_CL",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CD_O,"IMAGE_SAMPLE_CD_O",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL_O,"IMAGE_SAMPLE_CD_CL_O",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_O,"IMAGE_SAMPLE_C_CD_O",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL_O,"IMAGE_SAMPLE_C_CD_CL_O",0,&operandTable[0]} ,//111 +}; // end ENC_MIMG_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_MTBUF_insn_table = { +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15 +}; // end ENC_MTBUF_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_MUBUF_insn_table = { +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_BUFFER_WBINVL1,"BUFFER_WBINVL1",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +}; // end ENC_MUBUF_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SMEM_insn_table = { +{amdgpu_gfx908_op_S_LOAD_DWORD,"S_LOAD_DWORD",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_STORE_DWORD,"S_STORE_DWORD",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_STORE_DWORDX2,"S_STORE_DWORDX2",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_STORE_DWORDX4,"S_STORE_DWORDX4",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_DCACHE_INV,"S_DCACHE_INV",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_DCACHE_WB,"S_DCACHE_WB",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_MEMTIME,"S_MEMTIME",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_MEMREALTIME,"S_MEMREALTIME",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_ATC_PROBE,"S_ATC_PROBE",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_gfx908_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP",0,&operandTable[0]} ,//128 +{amdgpu_gfx908_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP",0,&operandTable[0]} ,//129 +{amdgpu_gfx908_op_S_ATOMIC_ADD,"S_ATOMIC_ADD",0,&operandTable[0]} ,//130 +{amdgpu_gfx908_op_S_ATOMIC_SUB,"S_ATOMIC_SUB",0,&operandTable[0]} ,//131 +{amdgpu_gfx908_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN",0,&operandTable[0]} ,//132 +{amdgpu_gfx908_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN",0,&operandTable[0]} ,//133 +{amdgpu_gfx908_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX",0,&operandTable[0]} ,//134 +{amdgpu_gfx908_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX",0,&operandTable[0]} ,//135 +{amdgpu_gfx908_op_S_ATOMIC_AND,"S_ATOMIC_AND",0,&operandTable[0]} ,//136 +{amdgpu_gfx908_op_S_ATOMIC_OR,"S_ATOMIC_OR",0,&operandTable[0]} ,//137 +{amdgpu_gfx908_op_S_ATOMIC_XOR,"S_ATOMIC_XOR",0,&operandTable[0]} ,//138 +{amdgpu_gfx908_op_S_ATOMIC_INC,"S_ATOMIC_INC",0,&operandTable[0]} ,//139 +{amdgpu_gfx908_op_S_ATOMIC_DEC,"S_ATOMIC_DEC",0,&operandTable[0]} ,//140 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_gfx908_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2",0,&operandTable[0]} ,//160 +{amdgpu_gfx908_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2",0,&operandTable[0]} ,//161 +{amdgpu_gfx908_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2",0,&operandTable[0]} ,//162 +{amdgpu_gfx908_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2",0,&operandTable[0]} ,//163 +{amdgpu_gfx908_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2",0,&operandTable[0]} ,//164 +{amdgpu_gfx908_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2",0,&operandTable[0]} ,//165 +{amdgpu_gfx908_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2",0,&operandTable[0]} ,//166 +{amdgpu_gfx908_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2",0,&operandTable[0]} ,//167 +{amdgpu_gfx908_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2",0,&operandTable[0]} ,//168 +{amdgpu_gfx908_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2",0,&operandTable[0]} ,//169 +{amdgpu_gfx908_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2",0,&operandTable[0]} ,//170 +{amdgpu_gfx908_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2",0,&operandTable[0]} ,//171 +{amdgpu_gfx908_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2",0,&operandTable[0]} ,//172 +}; // end ENC_SMEM_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SOP1_insn_table = { +{amdgpu_gfx908_op_S_MOV_B32,"S_MOV_B32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_MOV_B64,"S_MOV_B64",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_CMOV_B32,"S_CMOV_B32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_CMOV_B64,"S_CMOV_B64",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOT_B32,"S_NOT_B32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOT_B64,"S_NOT_B64",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_WQM_B32,"S_WQM_B32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_WQM_B64,"S_WQM_B64",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_BREV_B32,"S_BREV_B32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_BREV_B64,"S_BREV_B64",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_FF0_I32_B32,"S_FF0_I32_B32",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_FF0_I32_B64,"S_FF0_I32_B64",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_FF1_I32_B32,"S_FF1_I32_B32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_FF1_I32_B64,"S_FF1_I32_B64",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_FLBIT_I32,"S_FLBIT_I32",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_SEXT_I32_I8,"S_SEXT_I32_I8",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_SEXT_I32_I16,"S_SEXT_I32_I16",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_BITSET0_B32,"S_BITSET0_B32",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_BITSET0_B64,"S_BITSET0_B64",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_BITSET1_B32,"S_BITSET1_B32",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_BITSET1_B64,"S_BITSET1_B64",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_GETPC_B64,"S_GETPC_B64",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_SETPC_B64,"S_SETPC_B64",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_SWAPPC_B64,"S_SWAPPC_B64",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_RFE_B64,"S_RFE_B64",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_QUADMASK_B32,"S_QUADMASK_B32",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_QUADMASK_B64,"S_QUADMASK_B64",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_MOVRELS_B32,"S_MOVRELS_B32",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_MOVRELS_B64,"S_MOVRELS_B64",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_MOVRELD_B32,"S_MOVRELD_B32",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_MOVRELD_B64,"S_MOVRELD_B64",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_ABS_I32,"S_ABS_I32",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32",0,&operandTable[0]} ,//55 +}; // end ENC_SOP1_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SOP2_insn_table = { +{amdgpu_gfx908_op_S_ADD_U32,"S_ADD_U32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_SUB_U32,"S_SUB_U32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_ADD_I32,"S_ADD_I32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_SUB_I32,"S_SUB_I32",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_ADDC_U32,"S_ADDC_U32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_SUBB_U32,"S_SUBB_U32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_MIN_I32,"S_MIN_I32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_MIN_U32,"S_MIN_U32",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_MAX_I32,"S_MAX_I32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_MAX_U32,"S_MAX_U32",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_CSELECT_B32,"S_CSELECT_B32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_CSELECT_B64,"S_CSELECT_B64",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_AND_B32,"S_AND_B32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_AND_B64,"S_AND_B64",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_OR_B32,"S_OR_B32",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_OR_B64,"S_OR_B64",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_XOR_B32,"S_XOR_B32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_XOR_B64,"S_XOR_B64",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_ANDN2_B32,"S_ANDN2_B32",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_ANDN2_B64,"S_ANDN2_B64",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_ORN2_B32,"S_ORN2_B32",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_ORN2_B64,"S_ORN2_B64",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NAND_B32,"S_NAND_B32",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NAND_B64,"S_NAND_B64",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOR_B32,"S_NOR_B32",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOR_B64,"S_NOR_B64",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_XNOR_B32,"S_XNOR_B32",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_XNOR_B64,"S_XNOR_B64",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_LSHL_B32,"S_LSHL_B32",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_LSHL_B64,"S_LSHL_B64",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_LSHR_B32,"S_LSHR_B32",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_LSHR_B64,"S_LSHR_B64",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_ASHR_I32,"S_ASHR_I32",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_ASHR_I64,"S_ASHR_I64",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_BFM_B32,"S_BFM_B32",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_BFM_B64,"S_BFM_B64",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_MUL_I32,"S_MUL_I32",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_BFE_U32,"S_BFE_U32",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_BFE_I32,"S_BFE_I32",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_BFE_U64,"S_BFE_U64",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_BFE_I64,"S_BFE_I64",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_ABSDIFF_I32,"S_ABSDIFF_I32",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_MUL_HI_U32,"S_MUL_HI_U32",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_MUL_HI_I32,"S_MUL_HI_I32",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16",0,&operandTable[0]} ,//52 +}; // end ENC_SOP2_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SOPC_insn_table = { +{amdgpu_gfx908_op_S_CMP_EQ_I32,"S_CMP_EQ_I32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_CMP_LG_I32,"S_CMP_LG_I32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_CMP_GT_I32,"S_CMP_GT_I32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_CMP_GE_I32,"S_CMP_GE_I32",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_CMP_LT_I32,"S_CMP_LT_I32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_CMP_LE_I32,"S_CMP_LE_I32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_CMP_EQ_U32,"S_CMP_EQ_U32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_CMP_LG_U32,"S_CMP_LG_U32",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_CMP_GT_U32,"S_CMP_GT_U32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_CMP_GE_U32,"S_CMP_GE_U32",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_CMP_LT_U32,"S_CMP_LT_U32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_CMP_LE_U32,"S_CMP_LE_U32",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_BITCMP0_B32,"S_BITCMP0_B32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_BITCMP1_B32,"S_BITCMP1_B32",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_BITCMP0_B64,"S_BITCMP0_B64",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_BITCMP1_B64,"S_BITCMP1_B64",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_SETVSKIP,"S_SETVSKIP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_CMP_EQ_U64,"S_CMP_EQ_U64",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_CMP_LG_U64,"S_CMP_LG_U64",0,&operandTable[0]} ,//19 +}; // end ENC_SOPC_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SOPK_insn_table = { +{amdgpu_gfx908_op_S_MOVK_I32,"S_MOVK_I32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_CMOVK_I32,"S_CMOVK_I32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_CMPK_LG_I32,"S_CMPK_LG_I32",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_CMPK_GT_I32,"S_CMPK_GT_I32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_CMPK_GE_I32,"S_CMPK_GE_I32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_CMPK_LT_I32,"S_CMPK_LT_I32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_CMPK_LE_I32,"S_CMPK_LE_I32",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_CMPK_LG_U32,"S_CMPK_LG_U32",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_CMPK_GT_U32,"S_CMPK_GT_U32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_CMPK_GE_U32,"S_CMPK_GE_U32",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_CMPK_LT_U32,"S_CMPK_LT_U32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_CMPK_LE_U32,"S_CMPK_LE_U32",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_ADDK_I32,"S_ADDK_I32",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_MULK_I32,"S_MULK_I32",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_GETREG_B32,"S_GETREG_B32",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_SETREG_B32,"S_SETREG_B32",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_CALL_B64,"S_CALL_B64",0,&operandTable[0]} ,//21 +}; // end ENC_SOPK_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::SOPK_INST_LITERAL__insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32",0,&operandTable[0]} ,//20 +}; // end SOPK_INST_LITERAL__insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_SOPP_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_ENDPGM,"S_ENDPGM",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_BRANCH,"S_BRANCH",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_WAKEUP,"S_WAKEUP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_BARRIER,"S_BARRIER",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_SETKILL,"S_SETKILL",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_WAITCNT,"S_WAITCNT",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_SETHALT,"S_SETHALT",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_SLEEP,"S_SLEEP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_SETPRIO,"S_SETPRIO",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_SENDMSG,"S_SENDMSG",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_SENDMSGHALT,"S_SENDMSGHALT",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_TRAP,"S_TRAP",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_ICACHE_INV,"S_ICACHE_INV",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_INCPERFLEVEL,"S_INCPERFLEVEL",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_DECPERFLEVEL,"S_DECPERFLEVEL",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_TTRACEDATA,"S_TTRACEDATA",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE",0,&operandTable[0]} ,//30 +}; // end ENC_SOPP_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VINTRP_insn_table = { +{amdgpu_gfx908_op_V_INTERP_P1_F32,"V_INTERP_P1_F32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_V_INTERP_P2_F32,"V_INTERP_P2_F32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_V_INTERP_MOV_F32,"V_INTERP_MOV_F32",0,&operandTable[0]} ,//2 +}; // end ENC_VINTRP_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP3_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111 +{amdgpu_gfx908_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112 +{amdgpu_gfx908_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113 +{amdgpu_gfx908_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114 +{amdgpu_gfx908_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115 +{amdgpu_gfx908_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116 +{amdgpu_gfx908_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117 +{amdgpu_gfx908_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118 +{amdgpu_gfx908_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119 +{amdgpu_gfx908_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120 +{amdgpu_gfx908_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121 +{amdgpu_gfx908_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122 +{amdgpu_gfx908_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123 +{amdgpu_gfx908_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124 +{amdgpu_gfx908_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125 +{amdgpu_gfx908_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126 +{amdgpu_gfx908_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_gfx908_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160 +{amdgpu_gfx908_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161 +{amdgpu_gfx908_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162 +{amdgpu_gfx908_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163 +{amdgpu_gfx908_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164 +{amdgpu_gfx908_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165 +{amdgpu_gfx908_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166 +{amdgpu_gfx908_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167 +{amdgpu_gfx908_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168 +{amdgpu_gfx908_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169 +{amdgpu_gfx908_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170 +{amdgpu_gfx908_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171 +{amdgpu_gfx908_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172 +{amdgpu_gfx908_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173 +{amdgpu_gfx908_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174 +{amdgpu_gfx908_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175 +{amdgpu_gfx908_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176 +{amdgpu_gfx908_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177 +{amdgpu_gfx908_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178 +{amdgpu_gfx908_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179 +{amdgpu_gfx908_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180 +{amdgpu_gfx908_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181 +{amdgpu_gfx908_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182 +{amdgpu_gfx908_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183 +{amdgpu_gfx908_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184 +{amdgpu_gfx908_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185 +{amdgpu_gfx908_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186 +{amdgpu_gfx908_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187 +{amdgpu_gfx908_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188 +{amdgpu_gfx908_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189 +{amdgpu_gfx908_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190 +{amdgpu_gfx908_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191 +{amdgpu_gfx908_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192 +{amdgpu_gfx908_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193 +{amdgpu_gfx908_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194 +{amdgpu_gfx908_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195 +{amdgpu_gfx908_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196 +{amdgpu_gfx908_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197 +{amdgpu_gfx908_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198 +{amdgpu_gfx908_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199 +{amdgpu_gfx908_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200 +{amdgpu_gfx908_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201 +{amdgpu_gfx908_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202 +{amdgpu_gfx908_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203 +{amdgpu_gfx908_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204 +{amdgpu_gfx908_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205 +{amdgpu_gfx908_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206 +{amdgpu_gfx908_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207 +{amdgpu_gfx908_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208 +{amdgpu_gfx908_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209 +{amdgpu_gfx908_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210 +{amdgpu_gfx908_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211 +{amdgpu_gfx908_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212 +{amdgpu_gfx908_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213 +{amdgpu_gfx908_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214 +{amdgpu_gfx908_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215 +{amdgpu_gfx908_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216 +{amdgpu_gfx908_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217 +{amdgpu_gfx908_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218 +{amdgpu_gfx908_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219 +{amdgpu_gfx908_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220 +{amdgpu_gfx908_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221 +{amdgpu_gfx908_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222 +{amdgpu_gfx908_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223 +{amdgpu_gfx908_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224 +{amdgpu_gfx908_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225 +{amdgpu_gfx908_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226 +{amdgpu_gfx908_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227 +{amdgpu_gfx908_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228 +{amdgpu_gfx908_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229 +{amdgpu_gfx908_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230 +{amdgpu_gfx908_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231 +{amdgpu_gfx908_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232 +{amdgpu_gfx908_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233 +{amdgpu_gfx908_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234 +{amdgpu_gfx908_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235 +{amdgpu_gfx908_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236 +{amdgpu_gfx908_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237 +{amdgpu_gfx908_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238 +{amdgpu_gfx908_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239 +{amdgpu_gfx908_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240 +{amdgpu_gfx908_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241 +{amdgpu_gfx908_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242 +{amdgpu_gfx908_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243 +{amdgpu_gfx908_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244 +{amdgpu_gfx908_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245 +{amdgpu_gfx908_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246 +{amdgpu_gfx908_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247 +{amdgpu_gfx908_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248 +{amdgpu_gfx908_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249 +{amdgpu_gfx908_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250 +{amdgpu_gfx908_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251 +{amdgpu_gfx908_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252 +{amdgpu_gfx908_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253 +{amdgpu_gfx908_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254 +{amdgpu_gfx908_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255 +{amdgpu_gfx908_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//256 +{amdgpu_gfx908_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//257 +{amdgpu_gfx908_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//258 +{amdgpu_gfx908_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//259 +{amdgpu_gfx908_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32",0,&operandTable[0]} ,//260 +{amdgpu_gfx908_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//261 +{amdgpu_gfx908_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//262 +{amdgpu_gfx908_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//263 +{amdgpu_gfx908_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//264 +{amdgpu_gfx908_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//265 +{amdgpu_gfx908_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//266 +{amdgpu_gfx908_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//267 +{amdgpu_gfx908_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//268 +{amdgpu_gfx908_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//269 +{amdgpu_gfx908_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//270 +{amdgpu_gfx908_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//271 +{amdgpu_gfx908_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//272 +{amdgpu_gfx908_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//273 +{amdgpu_gfx908_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//274 +{amdgpu_gfx908_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//275 +{amdgpu_gfx908_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//276 +{amdgpu_gfx908_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//277 +{amdgpu_gfx908_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//278 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//281 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//282 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//283 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//284 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//285 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//286 +{amdgpu_gfx908_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//287 +{amdgpu_gfx908_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//288 +{amdgpu_gfx908_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//289 +{amdgpu_gfx908_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//290 +{amdgpu_gfx908_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//291 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293 +{amdgpu_gfx908_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//294 +{amdgpu_gfx908_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//295 +{amdgpu_gfx908_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//296 +{amdgpu_gfx908_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//297 +{amdgpu_gfx908_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//298 +{amdgpu_gfx908_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//299 +{amdgpu_gfx908_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//300 +{amdgpu_gfx908_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//301 +{amdgpu_gfx908_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//302 +{amdgpu_gfx908_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//303 +{amdgpu_gfx908_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//304 +{amdgpu_gfx908_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//305 +{amdgpu_gfx908_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//306 +{amdgpu_gfx908_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//307 +{amdgpu_gfx908_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//308 +{amdgpu_gfx908_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//309 +{amdgpu_gfx908_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//310 +{amdgpu_gfx908_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//311 +{amdgpu_gfx908_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//312 +{amdgpu_gfx908_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//313 +{amdgpu_gfx908_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//314 +{amdgpu_gfx908_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//315 +{amdgpu_gfx908_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//316 +{amdgpu_gfx908_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//317 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319 +{amdgpu_gfx908_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//320 +{amdgpu_gfx908_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//321 +{amdgpu_gfx908_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//322 +{amdgpu_gfx908_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//323 +{amdgpu_gfx908_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//324 +{amdgpu_gfx908_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//325 +{amdgpu_gfx908_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//326 +{amdgpu_gfx908_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//327 +{amdgpu_gfx908_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//328 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329 +{amdgpu_gfx908_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//330 +{amdgpu_gfx908_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//331 +{amdgpu_gfx908_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//332 +{amdgpu_gfx908_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//333 +{amdgpu_gfx908_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//334 +{amdgpu_gfx908_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//335 +{amdgpu_gfx908_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//336 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//337 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//338 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//339 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//340 +{amdgpu_gfx908_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//341 +{amdgpu_gfx908_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//342 +{amdgpu_gfx908_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//343 +{amdgpu_gfx908_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//344 +{amdgpu_gfx908_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//345 +{amdgpu_gfx908_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//346 +{amdgpu_gfx908_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//347 +{amdgpu_gfx908_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//348 +{amdgpu_gfx908_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//349 +{amdgpu_gfx908_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//350 +{amdgpu_gfx908_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//351 +{amdgpu_gfx908_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//352 +{amdgpu_gfx908_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//353 +{amdgpu_gfx908_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//354 +{amdgpu_gfx908_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//355 +{amdgpu_gfx908_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//356 +{amdgpu_gfx908_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//357 +{amdgpu_gfx908_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//358 +{amdgpu_gfx908_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//359 +{amdgpu_gfx908_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//360 +{amdgpu_gfx908_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//361 +{amdgpu_gfx908_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//362 +{amdgpu_gfx908_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//363 +{amdgpu_gfx908_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//364 +{amdgpu_gfx908_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//365 +{amdgpu_gfx908_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//366 +{amdgpu_gfx908_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//367 +{amdgpu_gfx908_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//368 +{amdgpu_gfx908_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//369 +{amdgpu_gfx908_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//370 +{amdgpu_gfx908_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//371 +{amdgpu_gfx908_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//372 +{amdgpu_gfx908_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//373 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374 +{amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//375 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376 +{amdgpu_gfx908_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//377 +{amdgpu_gfx908_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//378 +{amdgpu_gfx908_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//379 +{amdgpu_gfx908_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//380 +{amdgpu_gfx908_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//381 +{amdgpu_gfx908_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//382 +{amdgpu_gfx908_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//383 +{amdgpu_gfx908_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//384 +{amdgpu_gfx908_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//385 +{amdgpu_gfx908_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//386 +{amdgpu_gfx908_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//387 +{amdgpu_gfx908_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//388 +{amdgpu_gfx908_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//389 +{amdgpu_gfx908_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//390 +{amdgpu_gfx908_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//391 +{amdgpu_gfx908_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//392 +{amdgpu_gfx908_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//393 +{amdgpu_gfx908_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//394 +{amdgpu_gfx908_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//395 +{amdgpu_gfx908_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//396 +{amdgpu_gfx908_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//397 +{amdgpu_gfx908_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//398 +{amdgpu_gfx908_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//399 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400 +{amdgpu_gfx908_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//401 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//402 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447 +{amdgpu_gfx908_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32",0,&operandTable[0]} ,//448 +{amdgpu_gfx908_op_V_MAD_F32,"V_MAD_F32",0,&operandTable[0]} ,//449 +{amdgpu_gfx908_op_V_MAD_I32_I24,"V_MAD_I32_I24",0,&operandTable[0]} ,//450 +{amdgpu_gfx908_op_V_MAD_U32_U24,"V_MAD_U32_U24",0,&operandTable[0]} ,//451 +{amdgpu_gfx908_op_V_CUBEID_F32,"V_CUBEID_F32",0,&operandTable[0]} ,//452 +{amdgpu_gfx908_op_V_CUBESC_F32,"V_CUBESC_F32",0,&operandTable[0]} ,//453 +{amdgpu_gfx908_op_V_CUBETC_F32,"V_CUBETC_F32",0,&operandTable[0]} ,//454 +{amdgpu_gfx908_op_V_CUBEMA_F32,"V_CUBEMA_F32",0,&operandTable[0]} ,//455 +{amdgpu_gfx908_op_V_BFE_U32,"V_BFE_U32",0,&operandTable[0]} ,//456 +{amdgpu_gfx908_op_V_BFE_I32,"V_BFE_I32",0,&operandTable[0]} ,//457 +{amdgpu_gfx908_op_V_BFI_B32,"V_BFI_B32",0,&operandTable[0]} ,//458 +{amdgpu_gfx908_op_V_FMA_F32,"V_FMA_F32",0,&operandTable[0]} ,//459 +{amdgpu_gfx908_op_V_FMA_F64,"V_FMA_F64",0,&operandTable[0]} ,//460 +{amdgpu_gfx908_op_V_LERP_U8,"V_LERP_U8",0,&operandTable[0]} ,//461 +{amdgpu_gfx908_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32",0,&operandTable[0]} ,//462 +{amdgpu_gfx908_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32",0,&operandTable[0]} ,//463 +{amdgpu_gfx908_op_V_MIN3_F32,"V_MIN3_F32",0,&operandTable[0]} ,//464 +{amdgpu_gfx908_op_V_MIN3_I32,"V_MIN3_I32",0,&operandTable[0]} ,//465 +{amdgpu_gfx908_op_V_MIN3_U32,"V_MIN3_U32",0,&operandTable[0]} ,//466 +{amdgpu_gfx908_op_V_MAX3_F32,"V_MAX3_F32",0,&operandTable[0]} ,//467 +{amdgpu_gfx908_op_V_MAX3_I32,"V_MAX3_I32",0,&operandTable[0]} ,//468 +{amdgpu_gfx908_op_V_MAX3_U32,"V_MAX3_U32",0,&operandTable[0]} ,//469 +{amdgpu_gfx908_op_V_MED3_F32,"V_MED3_F32",0,&operandTable[0]} ,//470 +{amdgpu_gfx908_op_V_MED3_I32,"V_MED3_I32",0,&operandTable[0]} ,//471 +{amdgpu_gfx908_op_V_MED3_U32,"V_MED3_U32",0,&operandTable[0]} ,//472 +{amdgpu_gfx908_op_V_SAD_U8,"V_SAD_U8",0,&operandTable[0]} ,//473 +{amdgpu_gfx908_op_V_SAD_HI_U8,"V_SAD_HI_U8",0,&operandTable[0]} ,//474 +{amdgpu_gfx908_op_V_SAD_U16,"V_SAD_U16",0,&operandTable[0]} ,//475 +{amdgpu_gfx908_op_V_SAD_U32,"V_SAD_U32",0,&operandTable[0]} ,//476 +{amdgpu_gfx908_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32",0,&operandTable[0]} ,//477 +{amdgpu_gfx908_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32",0,&operandTable[0]} ,//478 +{amdgpu_gfx908_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64",0,&operandTable[0]} ,//479 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//480 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//481 +{amdgpu_gfx908_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32",0,&operandTable[0]} ,//482 +{amdgpu_gfx908_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64",0,&operandTable[0]} ,//483 +{amdgpu_gfx908_op_V_MSAD_U8,"V_MSAD_U8",0,&operandTable[0]} ,//484 +{amdgpu_gfx908_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8",0,&operandTable[0]} ,//485 +{amdgpu_gfx908_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8",0,&operandTable[0]} ,//486 +{amdgpu_gfx908_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8",0,&operandTable[0]} ,//487 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//488 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//489 +{amdgpu_gfx908_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16",0,&operandTable[0]} ,//490 +{amdgpu_gfx908_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16",0,&operandTable[0]} ,//491 +{amdgpu_gfx908_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16",0,&operandTable[0]} ,//492 +{amdgpu_gfx908_op_V_PERM_B32,"V_PERM_B32",0,&operandTable[0]} ,//493 +{amdgpu_gfx908_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16",0,&operandTable[0]} ,//494 +{amdgpu_gfx908_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16",0,&operandTable[0]} ,//495 +{amdgpu_gfx908_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32",0,&operandTable[0]} ,//496 +{amdgpu_gfx908_op_V_MAD_U32_U16,"V_MAD_U32_U16",0,&operandTable[0]} ,//497 +{amdgpu_gfx908_op_V_MAD_I32_I16,"V_MAD_I32_I16",0,&operandTable[0]} ,//498 +{amdgpu_gfx908_op_V_XAD_U32,"V_XAD_U32",0,&operandTable[0]} ,//499 +{amdgpu_gfx908_op_V_MIN3_F16,"V_MIN3_F16",0,&operandTable[0]} ,//500 +{amdgpu_gfx908_op_V_MIN3_I16,"V_MIN3_I16",0,&operandTable[0]} ,//501 +{amdgpu_gfx908_op_V_MIN3_U16,"V_MIN3_U16",0,&operandTable[0]} ,//502 +{amdgpu_gfx908_op_V_MAX3_F16,"V_MAX3_F16",0,&operandTable[0]} ,//503 +{amdgpu_gfx908_op_V_MAX3_I16,"V_MAX3_I16",0,&operandTable[0]} ,//504 +{amdgpu_gfx908_op_V_MAX3_U16,"V_MAX3_U16",0,&operandTable[0]} ,//505 +{amdgpu_gfx908_op_V_MED3_F16,"V_MED3_F16",0,&operandTable[0]} ,//506 +{amdgpu_gfx908_op_V_MED3_I16,"V_MED3_I16",0,&operandTable[0]} ,//507 +{amdgpu_gfx908_op_V_MED3_U16,"V_MED3_U16",0,&operandTable[0]} ,//508 +{amdgpu_gfx908_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32",0,&operandTable[0]} ,//509 +{amdgpu_gfx908_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32",0,&operandTable[0]} ,//510 +{amdgpu_gfx908_op_V_ADD3_U32,"V_ADD3_U32",0,&operandTable[0]} ,//511 +{amdgpu_gfx908_op_V_LSHL_OR_B32,"V_LSHL_OR_B32",0,&operandTable[0]} ,//512 +{amdgpu_gfx908_op_V_AND_OR_B32,"V_AND_OR_B32",0,&operandTable[0]} ,//513 +{amdgpu_gfx908_op_V_OR3_B32,"V_OR3_B32",0,&operandTable[0]} ,//514 +{amdgpu_gfx908_op_V_MAD_F16,"V_MAD_F16",0,&operandTable[0]} ,//515 +{amdgpu_gfx908_op_V_MAD_U16,"V_MAD_U16",0,&operandTable[0]} ,//516 +{amdgpu_gfx908_op_V_MAD_I16,"V_MAD_I16",0,&operandTable[0]} ,//517 +{amdgpu_gfx908_op_V_FMA_F16,"V_FMA_F16",0,&operandTable[0]} ,//518 +{amdgpu_gfx908_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16",0,&operandTable[0]} ,//519 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//520 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//521 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//522 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//523 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//524 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//525 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//526 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//527 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//528 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//529 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//530 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//531 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//532 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//533 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//534 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//535 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//536 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//537 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//538 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//539 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//540 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//541 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//542 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//543 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//544 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//545 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//546 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//547 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//548 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//549 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//550 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//551 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//552 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//553 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//554 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//555 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//556 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//557 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//558 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//559 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//560 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//561 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//562 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//563 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//564 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//565 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//566 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//567 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//568 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//569 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//570 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//571 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//572 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//573 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//574 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//575 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//576 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//577 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//578 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//579 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//580 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//581 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//582 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//583 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//584 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//585 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//586 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//587 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//588 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//589 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//590 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//591 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//592 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//593 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//594 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//595 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//596 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//597 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//598 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//599 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//600 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//601 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//602 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//603 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//604 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//605 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//606 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//607 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//608 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//609 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//610 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//611 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//612 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//613 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//614 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//615 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//616 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//617 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//618 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//619 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//620 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//621 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//622 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//623 +{amdgpu_gfx908_op_V_INTERP_P1_F32,"V_INTERP_P1_F32",0,&operandTable[0]} ,//624 +{amdgpu_gfx908_op_V_INTERP_P2_F32,"V_INTERP_P2_F32",0,&operandTable[0]} ,//625 +{amdgpu_gfx908_op_V_INTERP_MOV_F32,"V_INTERP_MOV_F32",0,&operandTable[0]} ,//626 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//627 +{amdgpu_gfx908_op_V_INTERP_P1LL_F16,"V_INTERP_P1LL_F16",0,&operandTable[0]} ,//628 +{amdgpu_gfx908_op_V_INTERP_P1LV_F16,"V_INTERP_P1LV_F16",0,&operandTable[0]} ,//629 +{amdgpu_gfx908_op_V_INTERP_P2_LEGACY_F16,"V_INTERP_P2_LEGACY_F16",0,&operandTable[0]} ,//630 +{amdgpu_gfx908_op_V_INTERP_P2_F16,"V_INTERP_P2_F16",0,&operandTable[0]} ,//631 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//632 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//633 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//634 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//635 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//636 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//637 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//638 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//639 +{amdgpu_gfx908_op_V_ADD_F64,"V_ADD_F64",0,&operandTable[0]} ,//640 +{amdgpu_gfx908_op_V_MUL_F64,"V_MUL_F64",0,&operandTable[0]} ,//641 +{amdgpu_gfx908_op_V_MIN_F64,"V_MIN_F64",0,&operandTable[0]} ,//642 +{amdgpu_gfx908_op_V_MAX_F64,"V_MAX_F64",0,&operandTable[0]} ,//643 +{amdgpu_gfx908_op_V_LDEXP_F64,"V_LDEXP_F64",0,&operandTable[0]} ,//644 +{amdgpu_gfx908_op_V_MUL_LO_U32,"V_MUL_LO_U32",0,&operandTable[0]} ,//645 +{amdgpu_gfx908_op_V_MUL_HI_U32,"V_MUL_HI_U32",0,&operandTable[0]} ,//646 +{amdgpu_gfx908_op_V_MUL_HI_I32,"V_MUL_HI_I32",0,&operandTable[0]} ,//647 +{amdgpu_gfx908_op_V_LDEXP_F32,"V_LDEXP_F32",0,&operandTable[0]} ,//648 +{amdgpu_gfx908_op_V_READLANE_B32,"V_READLANE_B32",0,&operandTable[0]} ,//649 +{amdgpu_gfx908_op_V_WRITELANE_B32,"V_WRITELANE_B32",0,&operandTable[0]} ,//650 +{amdgpu_gfx908_op_V_BCNT_U32_B32,"V_BCNT_U32_B32",0,&operandTable[0]} ,//651 +{amdgpu_gfx908_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32",0,&operandTable[0]} ,//652 +{amdgpu_gfx908_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32",0,&operandTable[0]} ,//653 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//654 +{amdgpu_gfx908_op_V_LSHLREV_B64,"V_LSHLREV_B64",0,&operandTable[0]} ,//655 +{amdgpu_gfx908_op_V_LSHRREV_B64,"V_LSHRREV_B64",0,&operandTable[0]} ,//656 +{amdgpu_gfx908_op_V_ASHRREV_I64,"V_ASHRREV_I64",0,&operandTable[0]} ,//657 +{amdgpu_gfx908_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64",0,&operandTable[0]} ,//658 +{amdgpu_gfx908_op_V_BFM_B32,"V_BFM_B32",0,&operandTable[0]} ,//659 +{amdgpu_gfx908_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32",0,&operandTable[0]} ,//660 +{amdgpu_gfx908_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32",0,&operandTable[0]} ,//661 +{amdgpu_gfx908_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32",0,&operandTable[0]} ,//662 +{amdgpu_gfx908_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32",0,&operandTable[0]} ,//663 +{amdgpu_gfx908_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32",0,&operandTable[0]} ,//664 +{amdgpu_gfx908_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16",0,&operandTable[0]} ,//665 +{amdgpu_gfx908_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16",0,&operandTable[0]} ,//666 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//667 +{amdgpu_gfx908_op_V_ADD_I32,"V_ADD_I32",0,&operandTable[0]} ,//668 +{amdgpu_gfx908_op_V_SUB_I32,"V_SUB_I32",0,&operandTable[0]} ,//669 +{amdgpu_gfx908_op_V_ADD_I16,"V_ADD_I16",0,&operandTable[0]} ,//670 +{amdgpu_gfx908_op_V_SUB_I16,"V_SUB_I16",0,&operandTable[0]} ,//671 +{amdgpu_gfx908_op_V_PACK_B32_F16,"V_PACK_B32_F16",0,&operandTable[0]} ,//672 +}; // end ENC_VOP3_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP1_insn_table = { +{amdgpu_gfx908_op_V_NOP,"V_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_V_MOV_B32,"V_MOV_B32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_V_CVT_I32_F64,"V_CVT_I32_F64",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_V_CVT_F64_I32,"V_CVT_F64_I32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_V_CVT_F32_I32,"V_CVT_F32_I32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_V_CVT_F32_U32,"V_CVT_F32_U32",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_V_CVT_U32_F32,"V_CVT_U32_F32",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_V_CVT_I32_F32,"V_CVT_I32_F32",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_V_CVT_F16_F32,"V_CVT_F16_F32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_V_CVT_F32_F16,"V_CVT_F32_F16",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_V_CVT_F32_F64,"V_CVT_F32_F64",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_V_CVT_F64_F32,"V_CVT_F64_F32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_V_CVT_U32_F64,"V_CVT_U32_F64",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_V_CVT_F64_U32,"V_CVT_F64_U32",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_V_TRUNC_F64,"V_TRUNC_F64",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_V_CEIL_F64,"V_CEIL_F64",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_V_RNDNE_F64,"V_RNDNE_F64",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_V_FLOOR_F64,"V_FLOOR_F64",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_V_FRACT_F32,"V_FRACT_F32",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_V_TRUNC_F32,"V_TRUNC_F32",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_V_CEIL_F32,"V_CEIL_F32",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_V_RNDNE_F32,"V_RNDNE_F32",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_V_FLOOR_F32,"V_FLOOR_F32",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_V_EXP_F32,"V_EXP_F32",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_V_LOG_F32,"V_LOG_F32",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_V_RCP_F32,"V_RCP_F32",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_V_RSQ_F32,"V_RSQ_F32",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_V_RCP_F64,"V_RCP_F64",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_V_RSQ_F64,"V_RSQ_F64",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_V_SQRT_F32,"V_SQRT_F32",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_V_SQRT_F64,"V_SQRT_F64",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_V_SIN_F32,"V_SIN_F32",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_V_COS_F32,"V_COS_F32",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_V_NOT_B32,"V_NOT_B32",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_V_BFREV_B32,"V_BFREV_B32",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_V_FFBH_U32,"V_FFBH_U32",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_V_FFBL_B32,"V_FFBL_B32",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_V_FFBH_I32,"V_FFBH_I32",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_V_FRACT_F64,"V_FRACT_F64",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_V_CLREXCP,"V_CLREXCP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_V_CVT_F16_U16,"V_CVT_F16_U16",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_V_CVT_F16_I16,"V_CVT_F16_I16",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_V_CVT_U16_F16,"V_CVT_U16_F16",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_V_CVT_I16_F16,"V_CVT_I16_F16",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_V_RCP_F16,"V_RCP_F16",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_V_SQRT_F16,"V_SQRT_F16",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_V_RSQ_F16,"V_RSQ_F16",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_V_LOG_F16,"V_LOG_F16",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_V_EXP_F16,"V_EXP_F16",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_V_FLOOR_F16,"V_FLOOR_F16",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_V_CEIL_F16,"V_CEIL_F16",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_V_TRUNC_F16,"V_TRUNC_F16",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_V_RNDNE_F16,"V_RNDNE_F16",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_V_FRACT_F16,"V_FRACT_F16",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_V_SIN_F16,"V_SIN_F16",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_V_COS_F16,"V_COS_F16",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_V_SWAP_B32,"V_SWAP_B32",0,&operandTable[0]} ,//81 +}; // end ENC_VOP1_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP2_insn_table = { +{amdgpu_gfx908_op_V_CNDMASK_B32,"V_CNDMASK_B32",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_V_ADD_F32,"V_ADD_F32",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_V_SUB_F32,"V_SUB_F32",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_V_SUBREV_F32,"V_SUBREV_F32",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_V_MUL_F32,"V_MUL_F32",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_V_MUL_I32_I24,"V_MUL_I32_I24",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_V_MUL_U32_U24,"V_MUL_U32_U24",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_V_MIN_F32,"V_MIN_F32",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_V_MAX_F32,"V_MAX_F32",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_V_MIN_I32,"V_MIN_I32",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_V_MAX_I32,"V_MAX_I32",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_V_MIN_U32,"V_MIN_U32",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_V_MAX_U32,"V_MAX_U32",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_V_LSHRREV_B32,"V_LSHRREV_B32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_V_ASHRREV_I32,"V_ASHRREV_I32",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_V_LSHLREV_B32,"V_LSHLREV_B32",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_V_AND_B32,"V_AND_B32",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_V_OR_B32,"V_OR_B32",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_V_XOR_B32,"V_XOR_B32",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_V_MAC_F32,"V_MAC_F32",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_V_ADD_F16,"V_ADD_F16",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_V_SUB_F16,"V_SUB_F16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_V_SUBREV_F16,"V_SUBREV_F16",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_V_MUL_F16,"V_MUL_F16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_V_MAC_F16,"V_MAC_F16",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_V_ADD_U16,"V_ADD_U16",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_V_SUB_U16,"V_SUB_U16",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_V_SUBREV_U16,"V_SUBREV_U16",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_V_MUL_LO_U16,"V_MUL_LO_U16",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_V_LSHLREV_B16,"V_LSHLREV_B16",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_V_LSHRREV_B16,"V_LSHRREV_B16",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_V_ASHRREV_I16,"V_ASHRREV_I16",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_V_MAX_F16,"V_MAX_F16",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_V_MIN_F16,"V_MIN_F16",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_V_MAX_U16,"V_MAX_U16",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_V_MAX_I16,"V_MAX_I16",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_V_MIN_U16,"V_MIN_U16",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_V_MIN_I16,"V_MIN_I16",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_V_LDEXP_F16,"V_LDEXP_F16",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_V_ADD_U32,"V_ADD_U32",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_V_SUB_U32,"V_SUB_U32",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_V_SUBREV_U32,"V_SUBREV_U32",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_V_FMAC_F32,"V_FMAC_F32",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_V_PK_FMAC_F16,"V_PK_FMAC_F16",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_V_XNOR_B32,"V_XNOR_B32",0,&operandTable[0]} ,//61 +}; // end ENC_VOP2_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP2_LITERAL_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_V_MADMK_F32,"V_MADMK_F32",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_V_MADAK_F32,"V_MADAK_F32",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_V_MADMK_F16,"V_MADMK_F16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_V_MADAK_F16,"V_MADAK_F16",0,&operandTable[0]} ,//37 +}; // end ENC_VOP2_LITERAL_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP3B_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//111 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//112 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//113 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//114 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//115 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//116 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//117 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//118 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//119 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//120 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//121 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//122 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//123 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//124 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//125 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//126 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//127 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//160 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//161 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//162 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//163 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//164 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//165 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//166 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//167 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//168 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//169 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//170 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//171 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//172 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//173 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//174 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//175 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//176 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//177 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//178 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//179 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//180 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//181 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//182 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//183 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//184 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//185 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//186 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//187 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//188 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//189 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//190 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//191 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//192 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//193 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//194 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//195 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//196 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//197 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//198 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//199 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//200 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//201 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//202 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//203 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//204 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//205 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//206 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//207 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//208 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//209 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//210 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//211 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//212 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//213 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//214 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//215 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//216 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//217 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//218 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//219 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//220 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//221 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//222 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//223 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//224 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//225 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//226 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//227 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//228 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//229 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//230 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//231 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//232 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//233 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//234 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//235 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//236 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//237 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//238 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//239 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//240 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//241 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//242 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//243 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//244 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//245 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//246 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//247 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//248 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//249 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//250 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//251 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//252 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//253 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//254 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//255 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//256 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//257 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//258 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//259 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//260 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//261 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//262 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//263 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//264 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//265 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//266 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//267 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//268 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//269 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//270 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//271 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//272 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//273 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//274 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//275 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//276 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//277 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//278 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//279 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//280 +{amdgpu_gfx908_op_V_ADD_CO_U32,"V_ADD_CO_U32",0,&operandTable[0]} ,//281 +{amdgpu_gfx908_op_V_SUB_CO_U32,"V_SUB_CO_U32",0,&operandTable[0]} ,//282 +{amdgpu_gfx908_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32",0,&operandTable[0]} ,//283 +{amdgpu_gfx908_op_V_ADDC_CO_U32,"V_ADDC_CO_U32",0,&operandTable[0]} ,//284 +{amdgpu_gfx908_op_V_SUBB_CO_U32,"V_SUBB_CO_U32",0,&operandTable[0]} ,//285 +{amdgpu_gfx908_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32",0,&operandTable[0]} ,//286 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//287 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//288 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//289 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//290 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//291 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//292 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//293 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//294 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//295 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//296 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//297 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//298 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//299 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//300 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//301 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//302 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//303 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//304 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//305 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//306 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//307 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//308 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//309 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//310 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//311 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//312 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//313 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//314 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//315 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//316 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//317 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//318 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//319 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//320 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//321 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//322 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//323 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//324 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//325 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//326 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//327 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//328 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//329 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//330 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//331 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//332 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//333 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//334 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//335 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//336 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//337 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//338 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//339 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//340 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//341 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//342 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//343 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//344 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//345 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//346 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//347 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//348 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//349 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//350 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//351 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//352 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//353 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//354 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//355 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//356 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//357 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//358 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//359 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//360 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//361 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//362 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//363 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//364 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//365 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//366 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//367 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//368 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//369 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//370 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//371 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//372 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//373 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//374 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//375 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//376 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//377 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//378 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//379 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//380 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//381 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//382 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//383 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//384 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//385 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//386 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//387 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//388 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//389 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//390 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//391 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//392 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//393 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//394 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//395 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//396 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//397 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//398 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//399 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//400 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//401 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//402 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//403 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//404 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//405 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//406 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//407 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//408 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//409 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//410 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//411 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//412 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//413 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//414 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//415 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//416 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//417 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//418 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//419 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//420 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//421 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//422 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//423 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//424 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//425 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//426 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//427 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//428 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//429 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//430 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//431 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//432 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//433 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//434 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//435 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//436 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//437 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//438 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//439 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//440 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//441 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//442 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//443 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//444 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//445 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//446 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//447 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//448 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//449 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//450 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//451 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//452 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//453 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//454 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//455 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//456 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//457 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//458 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//459 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//460 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//461 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//462 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//463 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//464 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//465 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//466 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//467 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//468 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//469 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//470 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//471 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//472 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//473 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//474 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//475 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//476 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//477 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//478 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//479 +{amdgpu_gfx908_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32",0,&operandTable[0]} ,//480 +{amdgpu_gfx908_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64",0,&operandTable[0]} ,//481 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//482 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//483 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//484 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//485 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//486 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//487 +{amdgpu_gfx908_op_V_MAD_U64_U32,"V_MAD_U64_U32",0,&operandTable[0]} ,//488 +{amdgpu_gfx908_op_V_MAD_I64_I32,"V_MAD_I64_I32",0,&operandTable[0]} ,//489 +}; // end ENC_VOP3B_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP3P_insn_table = { +{amdgpu_gfx908_op_V_PK_MAD_I16,"V_PK_MAD_I16",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_V_PK_ADD_I16,"V_PK_ADD_I16",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_V_PK_SUB_I16,"V_PK_SUB_I16",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_V_PK_MAX_I16,"V_PK_MAX_I16",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_V_PK_MIN_I16,"V_PK_MIN_I16",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_V_PK_MAD_U16,"V_PK_MAD_U16",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_V_PK_ADD_U16,"V_PK_ADD_U16",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_V_PK_SUB_U16,"V_PK_SUB_U16",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_V_PK_MAX_U16,"V_PK_MAX_U16",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_V_PK_MIN_U16,"V_PK_MIN_U16",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_V_PK_FMA_F16,"V_PK_FMA_F16",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_V_PK_ADD_F16,"V_PK_ADD_F16",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_V_PK_MUL_F16,"V_PK_MUL_F16",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_V_PK_MIN_F16,"V_PK_MIN_F16",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_V_PK_MAX_F16,"V_PK_MAX_F16",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_V_MAD_MIX_F32,"V_MAD_MIX_F32",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_V_DOT2_F32_F16,"V_DOT2_F32_F16",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_V_DOT2_I32_I16,"V_DOT2_I32_I16",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_V_DOT2_U32_U16,"V_DOT2_U32_U16",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_V_DOT4_I32_I8,"V_DOT4_I32_I8",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_V_DOT4_U32_U8,"V_DOT4_U32_U8",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_V_DOT8_I32_I4,"V_DOT8_I32_I4",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_V_DOT8_U32_U4,"V_DOT8_U32_U4",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_V_ACCVGPR_READ,"V_ACCVGPR_READ",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE",0,&operandTable[0]} ,//89 +}; // end ENC_VOP3P_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOP3P_MFMA_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16",0,&operandTable[0]} ,//109 +}; // end ENC_VOP3P_MFMA_insn_table +const amdgpu_gfx908_insn_table amdgpu_gfx908_insn_entry::ENC_VOPC_insn_table = { +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//0 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//1 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//2 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//3 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//4 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//5 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//6 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//7 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//8 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//9 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//10 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//11 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//12 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//13 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//14 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//15 +{amdgpu_gfx908_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32",0,&operandTable[0]} ,//16 +{amdgpu_gfx908_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32",0,&operandTable[0]} ,//17 +{amdgpu_gfx908_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64",0,&operandTable[0]} ,//18 +{amdgpu_gfx908_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64",0,&operandTable[0]} ,//19 +{amdgpu_gfx908_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16",0,&operandTable[0]} ,//20 +{amdgpu_gfx908_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16",0,&operandTable[0]} ,//21 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//22 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//23 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//24 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//25 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//26 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//27 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//28 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//29 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//30 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//31 +{amdgpu_gfx908_op_V_CMP_F_F16,"V_CMP_F_F16",0,&operandTable[0]} ,//32 +{amdgpu_gfx908_op_V_CMP_LT_F16,"V_CMP_LT_F16",0,&operandTable[0]} ,//33 +{amdgpu_gfx908_op_V_CMP_EQ_F16,"V_CMP_EQ_F16",0,&operandTable[0]} ,//34 +{amdgpu_gfx908_op_V_CMP_LE_F16,"V_CMP_LE_F16",0,&operandTable[0]} ,//35 +{amdgpu_gfx908_op_V_CMP_GT_F16,"V_CMP_GT_F16",0,&operandTable[0]} ,//36 +{amdgpu_gfx908_op_V_CMP_LG_F16,"V_CMP_LG_F16",0,&operandTable[0]} ,//37 +{amdgpu_gfx908_op_V_CMP_GE_F16,"V_CMP_GE_F16",0,&operandTable[0]} ,//38 +{amdgpu_gfx908_op_V_CMP_O_F16,"V_CMP_O_F16",0,&operandTable[0]} ,//39 +{amdgpu_gfx908_op_V_CMP_U_F16,"V_CMP_U_F16",0,&operandTable[0]} ,//40 +{amdgpu_gfx908_op_V_CMP_NGE_F16,"V_CMP_NGE_F16",0,&operandTable[0]} ,//41 +{amdgpu_gfx908_op_V_CMP_NLG_F16,"V_CMP_NLG_F16",0,&operandTable[0]} ,//42 +{amdgpu_gfx908_op_V_CMP_NGT_F16,"V_CMP_NGT_F16",0,&operandTable[0]} ,//43 +{amdgpu_gfx908_op_V_CMP_NLE_F16,"V_CMP_NLE_F16",0,&operandTable[0]} ,//44 +{amdgpu_gfx908_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16",0,&operandTable[0]} ,//45 +{amdgpu_gfx908_op_V_CMP_NLT_F16,"V_CMP_NLT_F16",0,&operandTable[0]} ,//46 +{amdgpu_gfx908_op_V_CMP_TRU_F16,"V_CMP_TRU_F16",0,&operandTable[0]} ,//47 +{amdgpu_gfx908_op_V_CMPX_F_F16,"V_CMPX_F_F16",0,&operandTable[0]} ,//48 +{amdgpu_gfx908_op_V_CMPX_LT_F16,"V_CMPX_LT_F16",0,&operandTable[0]} ,//49 +{amdgpu_gfx908_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16",0,&operandTable[0]} ,//50 +{amdgpu_gfx908_op_V_CMPX_LE_F16,"V_CMPX_LE_F16",0,&operandTable[0]} ,//51 +{amdgpu_gfx908_op_V_CMPX_GT_F16,"V_CMPX_GT_F16",0,&operandTable[0]} ,//52 +{amdgpu_gfx908_op_V_CMPX_LG_F16,"V_CMPX_LG_F16",0,&operandTable[0]} ,//53 +{amdgpu_gfx908_op_V_CMPX_GE_F16,"V_CMPX_GE_F16",0,&operandTable[0]} ,//54 +{amdgpu_gfx908_op_V_CMPX_O_F16,"V_CMPX_O_F16",0,&operandTable[0]} ,//55 +{amdgpu_gfx908_op_V_CMPX_U_F16,"V_CMPX_U_F16",0,&operandTable[0]} ,//56 +{amdgpu_gfx908_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16",0,&operandTable[0]} ,//57 +{amdgpu_gfx908_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16",0,&operandTable[0]} ,//58 +{amdgpu_gfx908_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16",0,&operandTable[0]} ,//59 +{amdgpu_gfx908_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16",0,&operandTable[0]} ,//60 +{amdgpu_gfx908_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16",0,&operandTable[0]} ,//61 +{amdgpu_gfx908_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16",0,&operandTable[0]} ,//62 +{amdgpu_gfx908_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16",0,&operandTable[0]} ,//63 +{amdgpu_gfx908_op_V_CMP_F_F32,"V_CMP_F_F32",0,&operandTable[0]} ,//64 +{amdgpu_gfx908_op_V_CMP_LT_F32,"V_CMP_LT_F32",0,&operandTable[0]} ,//65 +{amdgpu_gfx908_op_V_CMP_EQ_F32,"V_CMP_EQ_F32",0,&operandTable[0]} ,//66 +{amdgpu_gfx908_op_V_CMP_LE_F32,"V_CMP_LE_F32",0,&operandTable[0]} ,//67 +{amdgpu_gfx908_op_V_CMP_GT_F32,"V_CMP_GT_F32",0,&operandTable[0]} ,//68 +{amdgpu_gfx908_op_V_CMP_LG_F32,"V_CMP_LG_F32",0,&operandTable[0]} ,//69 +{amdgpu_gfx908_op_V_CMP_GE_F32,"V_CMP_GE_F32",0,&operandTable[0]} ,//70 +{amdgpu_gfx908_op_V_CMP_O_F32,"V_CMP_O_F32",0,&operandTable[0]} ,//71 +{amdgpu_gfx908_op_V_CMP_U_F32,"V_CMP_U_F32",0,&operandTable[0]} ,//72 +{amdgpu_gfx908_op_V_CMP_NGE_F32,"V_CMP_NGE_F32",0,&operandTable[0]} ,//73 +{amdgpu_gfx908_op_V_CMP_NLG_F32,"V_CMP_NLG_F32",0,&operandTable[0]} ,//74 +{amdgpu_gfx908_op_V_CMP_NGT_F32,"V_CMP_NGT_F32",0,&operandTable[0]} ,//75 +{amdgpu_gfx908_op_V_CMP_NLE_F32,"V_CMP_NLE_F32",0,&operandTable[0]} ,//76 +{amdgpu_gfx908_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32",0,&operandTable[0]} ,//77 +{amdgpu_gfx908_op_V_CMP_NLT_F32,"V_CMP_NLT_F32",0,&operandTable[0]} ,//78 +{amdgpu_gfx908_op_V_CMP_TRU_F32,"V_CMP_TRU_F32",0,&operandTable[0]} ,//79 +{amdgpu_gfx908_op_V_CMPX_F_F32,"V_CMPX_F_F32",0,&operandTable[0]} ,//80 +{amdgpu_gfx908_op_V_CMPX_LT_F32,"V_CMPX_LT_F32",0,&operandTable[0]} ,//81 +{amdgpu_gfx908_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32",0,&operandTable[0]} ,//82 +{amdgpu_gfx908_op_V_CMPX_LE_F32,"V_CMPX_LE_F32",0,&operandTable[0]} ,//83 +{amdgpu_gfx908_op_V_CMPX_GT_F32,"V_CMPX_GT_F32",0,&operandTable[0]} ,//84 +{amdgpu_gfx908_op_V_CMPX_LG_F32,"V_CMPX_LG_F32",0,&operandTable[0]} ,//85 +{amdgpu_gfx908_op_V_CMPX_GE_F32,"V_CMPX_GE_F32",0,&operandTable[0]} ,//86 +{amdgpu_gfx908_op_V_CMPX_O_F32,"V_CMPX_O_F32",0,&operandTable[0]} ,//87 +{amdgpu_gfx908_op_V_CMPX_U_F32,"V_CMPX_U_F32",0,&operandTable[0]} ,//88 +{amdgpu_gfx908_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32",0,&operandTable[0]} ,//89 +{amdgpu_gfx908_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32",0,&operandTable[0]} ,//90 +{amdgpu_gfx908_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32",0,&operandTable[0]} ,//91 +{amdgpu_gfx908_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32",0,&operandTable[0]} ,//92 +{amdgpu_gfx908_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32",0,&operandTable[0]} ,//93 +{amdgpu_gfx908_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32",0,&operandTable[0]} ,//94 +{amdgpu_gfx908_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32",0,&operandTable[0]} ,//95 +{amdgpu_gfx908_op_V_CMP_F_F64,"V_CMP_F_F64",0,&operandTable[0]} ,//96 +{amdgpu_gfx908_op_V_CMP_LT_F64,"V_CMP_LT_F64",0,&operandTable[0]} ,//97 +{amdgpu_gfx908_op_V_CMP_EQ_F64,"V_CMP_EQ_F64",0,&operandTable[0]} ,//98 +{amdgpu_gfx908_op_V_CMP_LE_F64,"V_CMP_LE_F64",0,&operandTable[0]} ,//99 +{amdgpu_gfx908_op_V_CMP_GT_F64,"V_CMP_GT_F64",0,&operandTable[0]} ,//100 +{amdgpu_gfx908_op_V_CMP_LG_F64,"V_CMP_LG_F64",0,&operandTable[0]} ,//101 +{amdgpu_gfx908_op_V_CMP_GE_F64,"V_CMP_GE_F64",0,&operandTable[0]} ,//102 +{amdgpu_gfx908_op_V_CMP_O_F64,"V_CMP_O_F64",0,&operandTable[0]} ,//103 +{amdgpu_gfx908_op_V_CMP_U_F64,"V_CMP_U_F64",0,&operandTable[0]} ,//104 +{amdgpu_gfx908_op_V_CMP_NGE_F64,"V_CMP_NGE_F64",0,&operandTable[0]} ,//105 +{amdgpu_gfx908_op_V_CMP_NLG_F64,"V_CMP_NLG_F64",0,&operandTable[0]} ,//106 +{amdgpu_gfx908_op_V_CMP_NGT_F64,"V_CMP_NGT_F64",0,&operandTable[0]} ,//107 +{amdgpu_gfx908_op_V_CMP_NLE_F64,"V_CMP_NLE_F64",0,&operandTable[0]} ,//108 +{amdgpu_gfx908_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64",0,&operandTable[0]} ,//109 +{amdgpu_gfx908_op_V_CMP_NLT_F64,"V_CMP_NLT_F64",0,&operandTable[0]} ,//110 +{amdgpu_gfx908_op_V_CMP_TRU_F64,"V_CMP_TRU_F64",0,&operandTable[0]} ,//111 +{amdgpu_gfx908_op_V_CMPX_F_F64,"V_CMPX_F_F64",0,&operandTable[0]} ,//112 +{amdgpu_gfx908_op_V_CMPX_LT_F64,"V_CMPX_LT_F64",0,&operandTable[0]} ,//113 +{amdgpu_gfx908_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64",0,&operandTable[0]} ,//114 +{amdgpu_gfx908_op_V_CMPX_LE_F64,"V_CMPX_LE_F64",0,&operandTable[0]} ,//115 +{amdgpu_gfx908_op_V_CMPX_GT_F64,"V_CMPX_GT_F64",0,&operandTable[0]} ,//116 +{amdgpu_gfx908_op_V_CMPX_LG_F64,"V_CMPX_LG_F64",0,&operandTable[0]} ,//117 +{amdgpu_gfx908_op_V_CMPX_GE_F64,"V_CMPX_GE_F64",0,&operandTable[0]} ,//118 +{amdgpu_gfx908_op_V_CMPX_O_F64,"V_CMPX_O_F64",0,&operandTable[0]} ,//119 +{amdgpu_gfx908_op_V_CMPX_U_F64,"V_CMPX_U_F64",0,&operandTable[0]} ,//120 +{amdgpu_gfx908_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64",0,&operandTable[0]} ,//121 +{amdgpu_gfx908_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64",0,&operandTable[0]} ,//122 +{amdgpu_gfx908_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64",0,&operandTable[0]} ,//123 +{amdgpu_gfx908_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64",0,&operandTable[0]} ,//124 +{amdgpu_gfx908_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64",0,&operandTable[0]} ,//125 +{amdgpu_gfx908_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64",0,&operandTable[0]} ,//126 +{amdgpu_gfx908_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64",0,&operandTable[0]} ,//127 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//128 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//129 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//130 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//131 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//132 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//133 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//134 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//135 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//136 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//137 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//138 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//139 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//140 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//141 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//142 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//143 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//144 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//145 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//146 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//147 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//148 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//149 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//150 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//151 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//152 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//153 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//154 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//155 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//156 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//157 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//158 +{amdgpu_gfx908_op_S_NOP,"S_NOP",0,&operandTable[0]} ,//159 +{amdgpu_gfx908_op_V_CMP_F_I16,"V_CMP_F_I16",0,&operandTable[0]} ,//160 +{amdgpu_gfx908_op_V_CMP_LT_I16,"V_CMP_LT_I16",0,&operandTable[0]} ,//161 +{amdgpu_gfx908_op_V_CMP_EQ_I16,"V_CMP_EQ_I16",0,&operandTable[0]} ,//162 +{amdgpu_gfx908_op_V_CMP_LE_I16,"V_CMP_LE_I16",0,&operandTable[0]} ,//163 +{amdgpu_gfx908_op_V_CMP_GT_I16,"V_CMP_GT_I16",0,&operandTable[0]} ,//164 +{amdgpu_gfx908_op_V_CMP_NE_I16,"V_CMP_NE_I16",0,&operandTable[0]} ,//165 +{amdgpu_gfx908_op_V_CMP_GE_I16,"V_CMP_GE_I16",0,&operandTable[0]} ,//166 +{amdgpu_gfx908_op_V_CMP_T_I16,"V_CMP_T_I16",0,&operandTable[0]} ,//167 +{amdgpu_gfx908_op_V_CMP_F_U16,"V_CMP_F_U16",0,&operandTable[0]} ,//168 +{amdgpu_gfx908_op_V_CMP_LT_U16,"V_CMP_LT_U16",0,&operandTable[0]} ,//169 +{amdgpu_gfx908_op_V_CMP_EQ_U16,"V_CMP_EQ_U16",0,&operandTable[0]} ,//170 +{amdgpu_gfx908_op_V_CMP_LE_U16,"V_CMP_LE_U16",0,&operandTable[0]} ,//171 +{amdgpu_gfx908_op_V_CMP_GT_U16,"V_CMP_GT_U16",0,&operandTable[0]} ,//172 +{amdgpu_gfx908_op_V_CMP_NE_U16,"V_CMP_NE_U16",0,&operandTable[0]} ,//173 +{amdgpu_gfx908_op_V_CMP_GE_U16,"V_CMP_GE_U16",0,&operandTable[0]} ,//174 +{amdgpu_gfx908_op_V_CMP_T_U16,"V_CMP_T_U16",0,&operandTable[0]} ,//175 +{amdgpu_gfx908_op_V_CMPX_F_I16,"V_CMPX_F_I16",0,&operandTable[0]} ,//176 +{amdgpu_gfx908_op_V_CMPX_LT_I16,"V_CMPX_LT_I16",0,&operandTable[0]} ,//177 +{amdgpu_gfx908_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16",0,&operandTable[0]} ,//178 +{amdgpu_gfx908_op_V_CMPX_LE_I16,"V_CMPX_LE_I16",0,&operandTable[0]} ,//179 +{amdgpu_gfx908_op_V_CMPX_GT_I16,"V_CMPX_GT_I16",0,&operandTable[0]} ,//180 +{amdgpu_gfx908_op_V_CMPX_NE_I16,"V_CMPX_NE_I16",0,&operandTable[0]} ,//181 +{amdgpu_gfx908_op_V_CMPX_GE_I16,"V_CMPX_GE_I16",0,&operandTable[0]} ,//182 +{amdgpu_gfx908_op_V_CMPX_T_I16,"V_CMPX_T_I16",0,&operandTable[0]} ,//183 +{amdgpu_gfx908_op_V_CMPX_F_U16,"V_CMPX_F_U16",0,&operandTable[0]} ,//184 +{amdgpu_gfx908_op_V_CMPX_LT_U16,"V_CMPX_LT_U16",0,&operandTable[0]} ,//185 +{amdgpu_gfx908_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16",0,&operandTable[0]} ,//186 +{amdgpu_gfx908_op_V_CMPX_LE_U16,"V_CMPX_LE_U16",0,&operandTable[0]} ,//187 +{amdgpu_gfx908_op_V_CMPX_GT_U16,"V_CMPX_GT_U16",0,&operandTable[0]} ,//188 +{amdgpu_gfx908_op_V_CMPX_NE_U16,"V_CMPX_NE_U16",0,&operandTable[0]} ,//189 +{amdgpu_gfx908_op_V_CMPX_GE_U16,"V_CMPX_GE_U16",0,&operandTable[0]} ,//190 +{amdgpu_gfx908_op_V_CMPX_T_U16,"V_CMPX_T_U16",0,&operandTable[0]} ,//191 +{amdgpu_gfx908_op_V_CMP_F_I32,"V_CMP_F_I32",0,&operandTable[0]} ,//192 +{amdgpu_gfx908_op_V_CMP_LT_I32,"V_CMP_LT_I32",0,&operandTable[0]} ,//193 +{amdgpu_gfx908_op_V_CMP_EQ_I32,"V_CMP_EQ_I32",0,&operandTable[0]} ,//194 +{amdgpu_gfx908_op_V_CMP_LE_I32,"V_CMP_LE_I32",0,&operandTable[0]} ,//195 +{amdgpu_gfx908_op_V_CMP_GT_I32,"V_CMP_GT_I32",0,&operandTable[0]} ,//196 +{amdgpu_gfx908_op_V_CMP_NE_I32,"V_CMP_NE_I32",0,&operandTable[0]} ,//197 +{amdgpu_gfx908_op_V_CMP_GE_I32,"V_CMP_GE_I32",0,&operandTable[0]} ,//198 +{amdgpu_gfx908_op_V_CMP_T_I32,"V_CMP_T_I32",0,&operandTable[0]} ,//199 +{amdgpu_gfx908_op_V_CMP_F_U32,"V_CMP_F_U32",0,&operandTable[0]} ,//200 +{amdgpu_gfx908_op_V_CMP_LT_U32,"V_CMP_LT_U32",0,&operandTable[0]} ,//201 +{amdgpu_gfx908_op_V_CMP_EQ_U32,"V_CMP_EQ_U32",0,&operandTable[0]} ,//202 +{amdgpu_gfx908_op_V_CMP_LE_U32,"V_CMP_LE_U32",0,&operandTable[0]} ,//203 +{amdgpu_gfx908_op_V_CMP_GT_U32,"V_CMP_GT_U32",0,&operandTable[0]} ,//204 +{amdgpu_gfx908_op_V_CMP_NE_U32,"V_CMP_NE_U32",0,&operandTable[0]} ,//205 +{amdgpu_gfx908_op_V_CMP_GE_U32,"V_CMP_GE_U32",0,&operandTable[0]} ,//206 +{amdgpu_gfx908_op_V_CMP_T_U32,"V_CMP_T_U32",0,&operandTable[0]} ,//207 +{amdgpu_gfx908_op_V_CMPX_F_I32,"V_CMPX_F_I32",0,&operandTable[0]} ,//208 +{amdgpu_gfx908_op_V_CMPX_LT_I32,"V_CMPX_LT_I32",0,&operandTable[0]} ,//209 +{amdgpu_gfx908_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32",0,&operandTable[0]} ,//210 +{amdgpu_gfx908_op_V_CMPX_LE_I32,"V_CMPX_LE_I32",0,&operandTable[0]} ,//211 +{amdgpu_gfx908_op_V_CMPX_GT_I32,"V_CMPX_GT_I32",0,&operandTable[0]} ,//212 +{amdgpu_gfx908_op_V_CMPX_NE_I32,"V_CMPX_NE_I32",0,&operandTable[0]} ,//213 +{amdgpu_gfx908_op_V_CMPX_GE_I32,"V_CMPX_GE_I32",0,&operandTable[0]} ,//214 +{amdgpu_gfx908_op_V_CMPX_T_I32,"V_CMPX_T_I32",0,&operandTable[0]} ,//215 +{amdgpu_gfx908_op_V_CMPX_F_U32,"V_CMPX_F_U32",0,&operandTable[0]} ,//216 +{amdgpu_gfx908_op_V_CMPX_LT_U32,"V_CMPX_LT_U32",0,&operandTable[0]} ,//217 +{amdgpu_gfx908_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32",0,&operandTable[0]} ,//218 +{amdgpu_gfx908_op_V_CMPX_LE_U32,"V_CMPX_LE_U32",0,&operandTable[0]} ,//219 +{amdgpu_gfx908_op_V_CMPX_GT_U32,"V_CMPX_GT_U32",0,&operandTable[0]} ,//220 +{amdgpu_gfx908_op_V_CMPX_NE_U32,"V_CMPX_NE_U32",0,&operandTable[0]} ,//221 +{amdgpu_gfx908_op_V_CMPX_GE_U32,"V_CMPX_GE_U32",0,&operandTable[0]} ,//222 +{amdgpu_gfx908_op_V_CMPX_T_U32,"V_CMPX_T_U32",0,&operandTable[0]} ,//223 +{amdgpu_gfx908_op_V_CMP_F_I64,"V_CMP_F_I64",0,&operandTable[0]} ,//224 +{amdgpu_gfx908_op_V_CMP_LT_I64,"V_CMP_LT_I64",0,&operandTable[0]} ,//225 +{amdgpu_gfx908_op_V_CMP_EQ_I64,"V_CMP_EQ_I64",0,&operandTable[0]} ,//226 +{amdgpu_gfx908_op_V_CMP_LE_I64,"V_CMP_LE_I64",0,&operandTable[0]} ,//227 +{amdgpu_gfx908_op_V_CMP_GT_I64,"V_CMP_GT_I64",0,&operandTable[0]} ,//228 +{amdgpu_gfx908_op_V_CMP_NE_I64,"V_CMP_NE_I64",0,&operandTable[0]} ,//229 +{amdgpu_gfx908_op_V_CMP_GE_I64,"V_CMP_GE_I64",0,&operandTable[0]} ,//230 +{amdgpu_gfx908_op_V_CMP_T_I64,"V_CMP_T_I64",0,&operandTable[0]} ,//231 +{amdgpu_gfx908_op_V_CMP_F_U64,"V_CMP_F_U64",0,&operandTable[0]} ,//232 +{amdgpu_gfx908_op_V_CMP_LT_U64,"V_CMP_LT_U64",0,&operandTable[0]} ,//233 +{amdgpu_gfx908_op_V_CMP_EQ_U64,"V_CMP_EQ_U64",0,&operandTable[0]} ,//234 +{amdgpu_gfx908_op_V_CMP_LE_U64,"V_CMP_LE_U64",0,&operandTable[0]} ,//235 +{amdgpu_gfx908_op_V_CMP_GT_U64,"V_CMP_GT_U64",0,&operandTable[0]} ,//236 +{amdgpu_gfx908_op_V_CMP_NE_U64,"V_CMP_NE_U64",0,&operandTable[0]} ,//237 +{amdgpu_gfx908_op_V_CMP_GE_U64,"V_CMP_GE_U64",0,&operandTable[0]} ,//238 +{amdgpu_gfx908_op_V_CMP_T_U64,"V_CMP_T_U64",0,&operandTable[0]} ,//239 +{amdgpu_gfx908_op_V_CMPX_F_I64,"V_CMPX_F_I64",0,&operandTable[0]} ,//240 +{amdgpu_gfx908_op_V_CMPX_LT_I64,"V_CMPX_LT_I64",0,&operandTable[0]} ,//241 +{amdgpu_gfx908_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64",0,&operandTable[0]} ,//242 +{amdgpu_gfx908_op_V_CMPX_LE_I64,"V_CMPX_LE_I64",0,&operandTable[0]} ,//243 +{amdgpu_gfx908_op_V_CMPX_GT_I64,"V_CMPX_GT_I64",0,&operandTable[0]} ,//244 +{amdgpu_gfx908_op_V_CMPX_NE_I64,"V_CMPX_NE_I64",0,&operandTable[0]} ,//245 +{amdgpu_gfx908_op_V_CMPX_GE_I64,"V_CMPX_GE_I64",0,&operandTable[0]} ,//246 +{amdgpu_gfx908_op_V_CMPX_T_I64,"V_CMPX_T_I64",0,&operandTable[0]} ,//247 +{amdgpu_gfx908_op_V_CMPX_F_U64,"V_CMPX_F_U64",0,&operandTable[0]} ,//248 +{amdgpu_gfx908_op_V_CMPX_LT_U64,"V_CMPX_LT_U64",0,&operandTable[0]} ,//249 +{amdgpu_gfx908_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64",0,&operandTable[0]} ,//250 +{amdgpu_gfx908_op_V_CMPX_LE_U64,"V_CMPX_LE_U64",0,&operandTable[0]} ,//251 +{amdgpu_gfx908_op_V_CMPX_GT_U64,"V_CMPX_GT_U64",0,&operandTable[0]} ,//252 +{amdgpu_gfx908_op_V_CMPX_NE_U64,"V_CMPX_NE_U64",0,&operandTable[0]} ,//253 +{amdgpu_gfx908_op_V_CMPX_GE_U64,"V_CMPX_GE_U64",0,&operandTable[0]} ,//254 +{amdgpu_gfx908_op_V_CMPX_T_U64,"V_CMPX_T_U64",0,&operandTable[0]} ,//255 +}; // end ENC_VOPC_insn_table diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C new file mode 100644 index 0000000000..0f85a19260 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -0,0 +1,5884 @@ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::attr0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::attr1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::attr2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::attr3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::attr4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::attr5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::attr6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::attr7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::attr8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::attr9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::attr10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::attr11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::attr12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::attr13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::attr14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::attr15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::attr16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::attr17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::attr18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::attr19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::attr20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::attr21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::attr22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::attr23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::attr24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::attr25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::attr26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::attr27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::attr28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::attr29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::attr30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::attr31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::attr32,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_all,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::p10,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::p20,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::p0,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::pc_all); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SMEM_OFFSET(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LDS(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 128 : return Immediate::makeImmediate(Result(u32, 0)); +case 129 : return Immediate::makeImmediate(Result(u32, 1)); +case 130 : return Immediate::makeImmediate(Result(u32, 2)); +case 131 : return Immediate::makeImmediate(Result(u32, 3)); +case 132 : return Immediate::makeImmediate(Result(u32, 4)); +case 133 : return Immediate::makeImmediate(Result(u32, 5)); +case 134 : return Immediate::makeImmediate(Result(u32, 6)); +case 135 : return Immediate::makeImmediate(Result(u32, 7)); +case 136 : return Immediate::makeImmediate(Result(u32, 8)); +case 137 : return Immediate::makeImmediate(Result(u32, 9)); +case 138 : return Immediate::makeImmediate(Result(u32, 10)); +case 139 : return Immediate::makeImmediate(Result(u32, 11)); +case 140 : return Immediate::makeImmediate(Result(u32, 12)); +case 141 : return Immediate::makeImmediate(Result(u32, 13)); +case 142 : return Immediate::makeImmediate(Result(u32, 14)); +case 143 : return Immediate::makeImmediate(Result(u32, 15)); +case 144 : return Immediate::makeImmediate(Result(u32, 16)); +case 145 : return Immediate::makeImmediate(Result(u32, 17)); +case 146 : return Immediate::makeImmediate(Result(u32, 18)); +case 147 : return Immediate::makeImmediate(Result(u32, 19)); +case 148 : return Immediate::makeImmediate(Result(u32, 20)); +case 149 : return Immediate::makeImmediate(Result(u32, 21)); +case 150 : return Immediate::makeImmediate(Result(u32, 22)); +case 151 : return Immediate::makeImmediate(Result(u32, 23)); +case 152 : return Immediate::makeImmediate(Result(u32, 24)); +case 153 : return Immediate::makeImmediate(Result(u32, 25)); +case 154 : return Immediate::makeImmediate(Result(u32, 26)); +case 155 : return Immediate::makeImmediate(Result(u32, 27)); +case 156 : return Immediate::makeImmediate(Result(u32, 28)); +case 157 : return Immediate::makeImmediate(Result(u32, 29)); +case 158 : return Immediate::makeImmediate(Result(u32, 30)); +case 159 : return Immediate::makeImmediate(Result(u32, 31)); +case 160 : return Immediate::makeImmediate(Result(u32, 32)); +case 161 : return Immediate::makeImmediate(Result(u32, 33)); +case 162 : return Immediate::makeImmediate(Result(u32, 34)); +case 163 : return Immediate::makeImmediate(Result(u32, 35)); +case 164 : return Immediate::makeImmediate(Result(u32, 36)); +case 165 : return Immediate::makeImmediate(Result(u32, 37)); +case 166 : return Immediate::makeImmediate(Result(u32, 38)); +case 167 : return Immediate::makeImmediate(Result(u32, 39)); +case 168 : return Immediate::makeImmediate(Result(u32, 40)); +case 169 : return Immediate::makeImmediate(Result(u32, 41)); +case 170 : return Immediate::makeImmediate(Result(u32, 42)); +case 171 : return Immediate::makeImmediate(Result(u32, 43)); +case 172 : return Immediate::makeImmediate(Result(u32, 44)); +case 173 : return Immediate::makeImmediate(Result(u32, 45)); +case 174 : return Immediate::makeImmediate(Result(u32, 46)); +case 175 : return Immediate::makeImmediate(Result(u32, 47)); +case 176 : return Immediate::makeImmediate(Result(u32, 48)); +case 177 : return Immediate::makeImmediate(Result(u32, 49)); +case 178 : return Immediate::makeImmediate(Result(u32, 50)); +case 179 : return Immediate::makeImmediate(Result(u32, 51)); +case 180 : return Immediate::makeImmediate(Result(u32, 52)); +case 181 : return Immediate::makeImmediate(Result(u32, 53)); +case 182 : return Immediate::makeImmediate(Result(u32, 54)); +case 183 : return Immediate::makeImmediate(Result(u32, 55)); +case 184 : return Immediate::makeImmediate(Result(u32, 56)); +case 185 : return Immediate::makeImmediate(Result(u32, 57)); +case 186 : return Immediate::makeImmediate(Result(u32, 58)); +case 187 : return Immediate::makeImmediate(Result(u32, 59)); +case 188 : return Immediate::makeImmediate(Result(u32, 60)); +case 189 : return Immediate::makeImmediate(Result(u32, 61)); +case 190 : return Immediate::makeImmediate(Result(u32, 62)); +case 191 : return Immediate::makeImmediate(Result(u32, 63)); +case 192 : return Immediate::makeImmediate(Result(u32, 64)); +case 193 : return Immediate::makeImmediate(Result(u32, -1)); +case 194 : return Immediate::makeImmediate(Result(u32, -2)); +case 195 : return Immediate::makeImmediate(Result(u32, -3)); +case 196 : return Immediate::makeImmediate(Result(u32, -4)); +case 197 : return Immediate::makeImmediate(Result(u32, -5)); +case 198 : return Immediate::makeImmediate(Result(u32, -6)); +case 199 : return Immediate::makeImmediate(Result(u32, -7)); +case 200 : return Immediate::makeImmediate(Result(u32, -8)); +case 201 : return Immediate::makeImmediate(Result(u32, -9)); +case 202 : return Immediate::makeImmediate(Result(u32, -10)); +case 203 : return Immediate::makeImmediate(Result(u32, -11)); +case 204 : return Immediate::makeImmediate(Result(u32, -12)); +case 205 : return Immediate::makeImmediate(Result(u32, -13)); +case 206 : return Immediate::makeImmediate(Result(u32, -14)); +case 207 : return Immediate::makeImmediate(Result(u32, -15)); +case 208 : return Immediate::makeImmediate(Result(u32, -16)); +case 240 : return Immediate::makeImmediate(Result(sp_float, 0.5)); +case 241 : return Immediate::makeImmediate(Result(sp_float, -0.5)); +case 242 : return Immediate::makeImmediate(Result(sp_float, 1.0)); +case 243 : return Immediate::makeImmediate(Result(sp_float, -1.0)); +case 244 : return Immediate::makeImmediate(Result(sp_float, 2.0)); +case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); +case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); +case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); +case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::mrt0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::mrt1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::mrt2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::mrt3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::mrt4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::mrt5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::mrt6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::mrt7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::mrtz,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::null,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::pos0,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::pos1,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::pos2,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::pos3,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::param0,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::param1,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::param2,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::param3,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::param4,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::param5,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::param6,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::param7,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::param8,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::param9,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::param10,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::param11,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::param12,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::param13,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::param14,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::param15,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::param16,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::param17,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::param18,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::param19,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::param20,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::param21,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::param22,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::param23,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::param24,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::param25,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::param26,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::param27,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::param28,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::param29,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::param30,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::param31,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TRAP(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::vcc); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 0 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 1 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 2 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 3 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 4 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 5 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 6 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 7 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 8 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 9 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 10 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 11 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 12 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 13 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 14 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 15 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 16 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 17 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 18 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 19 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 20 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 21 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 22 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 23 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 24 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 25 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 26 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 27 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 28 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 29 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 30 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 31 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 32 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 33 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 34 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 35 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 36 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 37 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 38 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 39 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 40 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 41 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 42 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 43 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 44 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 45 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 46 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 47 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 48 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 49 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 50 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 51 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 52 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 53 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 54 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 55 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 56 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 57 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 58 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 59 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 60 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 61 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 62 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 63 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 64 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 65 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 66 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 67 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 68 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 69 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 70 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 71 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 72 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 73 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 74 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 75 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 76 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 77 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 78 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 79 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 80 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 81 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 82 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 83 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 84 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 85 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 86 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 87 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 88 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 89 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 90 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 91 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 92 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 93 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 94 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 95 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 96 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 97 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 98 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 99 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 100 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 101 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 103 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 107 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 109 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 110 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 111 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 112 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 113 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 114 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 115 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 116 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 117 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 118 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 119 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 120 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 121 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 122 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 123 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 125 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 127 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 128 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 129 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 130 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 131 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 132 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 133 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 134 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 135 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 136 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 137 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 138 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 139 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 140 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 141 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 142 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 143 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 144 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 145 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 146 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 147 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 148 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 149 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 150 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 151 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 152 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 153 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 154 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 155 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 156 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 157 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 158 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 159 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 160 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 161 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 162 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 163 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 164 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 165 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 166 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 167 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 168 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 169 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 170 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 171 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 172 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 173 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 174 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 175 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 176 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 177 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 178 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 179 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 180 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 181 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 182 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 183 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 184 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 185 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 186 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 187 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 188 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 189 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 190 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 191 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 192 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 193 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 194 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 195 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 196 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 197 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 198 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 199 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 200 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 201 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 202 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 203 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 204 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 205 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 206 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 207 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 208 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 209 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 210 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 211 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 212 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 213 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 214 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 215 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 216 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 217 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 218 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 219 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 220 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 221 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 222 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 223 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 224 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 225 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 226 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 227 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 228 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 229 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 230 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 231 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 232 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 233 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 234 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 236 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 237 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 238 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 240 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 241 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 242 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 243 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 244 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 245 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 246 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 247 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 248 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 249 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 250 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_XNACK_MASK_LOHI(uint64_t input,uint32_t opr_size ){ +switch(input){ +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +default: return makeRegisterExpression(amdgpu_gfx908::invalid); +} +} diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h new file mode 100644 index 0000000000..9aed56c56f --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h @@ -0,0 +1,41 @@ +Expression::Ptr decodeOPR_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_ATTR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_PARAM(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_PC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_M0(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_TGT(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_TRAP(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input ,uint32_t opr_size ); diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C new file mode 100644 index 0000000000..21d2ad3ffd --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -0,0 +1,11469 @@ +void InstructionDecoder_amdgpu_gfx908::finalizeENC_DSOperands(){ +layout_ENC_DS & layout = insn_layout.ENC_DS; +switch(layout.OP){ +case 0:// DS_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 1:// DS_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 2:// DS_RSUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 3:// DS_INC_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 4:// DS_DEC_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 5:// DS_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 6:// DS_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 7:// DS_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 8:// DS_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 9:// DS_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 10:// DS_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 11:// DS_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 12:// DS_MSKOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 13:// DS_WRITE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 14:// DS_WRITE2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 15:// DS_WRITE2ST64_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 16:// DS_CMPST_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 17:// DS_CMPST_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 18:// DS_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 19:// DS_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 20:// DS_NOP +break; +case 21:// DS_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 29:// DS_WRITE_ADDTID_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// DS_WRITE_B8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 31:// DS_WRITE_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 32:// DS_ADD_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 33:// DS_SUB_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 34:// DS_RSUB_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 35:// DS_INC_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 36:// DS_DEC_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 37:// DS_MIN_RTN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 38:// DS_MAX_RTN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 39:// DS_MIN_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 40:// DS_MAX_RTN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 41:// DS_AND_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 42:// DS_OR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 43:// DS_XOR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 44:// DS_MSKOR_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 45:// DS_WRXCHG_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 46:// DS_WRXCHG2_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 47:// DS_WRXCHG2ST64_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 48:// DS_CMPST_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 49:// DS_CMPST_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 50:// DS_MIN_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 51:// DS_MAX_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 52:// DS_WRAP_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +break; +case 53:// DS_ADD_RTN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 54:// DS_READ_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 55:// DS_READ2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 56:// DS_READ2ST64_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 57:// DS_READ_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 58:// DS_READ_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 59:// DS_READ_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 60:// DS_READ_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 61:// DS_SWIZZLE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 62:// DS_PERMUTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 63:// DS_BPERMUTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 64:// DS_ADD_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 65:// DS_SUB_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 66:// DS_RSUB_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 67:// DS_INC_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 68:// DS_DEC_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 69:// DS_MIN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 70:// DS_MAX_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 71:// DS_MIN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 72:// DS_MAX_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 73:// DS_AND_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 74:// DS_OR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 75:// DS_XOR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 76:// DS_MSKOR_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 77:// DS_WRITE_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 78:// DS_WRITE2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 79:// DS_WRITE2ST64_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 80:// DS_CMPST_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 81:// DS_CMPST_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 82:// DS_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 83:// DS_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 84:// DS_WRITE_B8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 85:// DS_WRITE_B16_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +break; +case 86:// DS_READ_U8_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 87:// DS_READ_U8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 88:// DS_READ_I8_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 89:// DS_READ_I8_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 90:// DS_READ_U16_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 91:// DS_READ_U16_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 96:// DS_ADD_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 97:// DS_SUB_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 98:// DS_RSUB_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 99:// DS_INC_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 100:// DS_DEC_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 101:// DS_MIN_RTN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 102:// DS_MAX_RTN_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 103:// DS_MIN_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 104:// DS_MAX_RTN_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 105:// DS_AND_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 106:// DS_OR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 107:// DS_XOR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 108:// DS_MSKOR_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 109:// DS_WRXCHG_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 110:// DS_WRXCHG2_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 111:// DS_WRXCHG2ST64_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 112:// DS_CMPST_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 113:// DS_CMPST_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +break; +case 114:// DS_MIN_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 115:// DS_MAX_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 118:// DS_READ_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 119:// DS_READ2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 120:// DS_READ2ST64_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 126:// DS_CONDXCHG32_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +break; +case 128:// DS_ADD_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 129:// DS_SUB_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 130:// DS_RSUB_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 131:// DS_INC_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 132:// DS_DEC_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 133:// DS_MIN_SRC2_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 134:// DS_MAX_SRC2_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 135:// DS_MIN_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 136:// DS_MAX_SRC2_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 137:// DS_AND_SRC2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 138:// DS_OR_SRC2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 139:// DS_XOR_SRC2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 141:// DS_WRITE_SRC2_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 146:// DS_MIN_SRC2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 147:// DS_MAX_SRC2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 149:// DS_ADD_SRC2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 152:// DS_GWS_SEMA_RELEASE_ALL +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 153:// DS_GWS_INIT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 154:// DS_GWS_SEMA_V +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 155:// DS_GWS_SEMA_BR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 156:// DS_GWS_SEMA_P +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 157:// DS_GWS_BARRIER +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 182:// DS_READ_ADDTID_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 189:// DS_CONSUME +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 190:// DS_APPEND +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 191:// DS_ORDERED_COUNT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 192:// DS_ADD_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 193:// DS_SUB_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 194:// DS_RSUB_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 195:// DS_INC_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 196:// DS_DEC_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 197:// DS_MIN_SRC2_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 198:// DS_MAX_SRC2_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 199:// DS_MIN_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 200:// DS_MAX_SRC2_U64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 201:// DS_AND_SRC2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 202:// DS_OR_SRC2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 203:// DS_XOR_SRC2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 205:// DS_WRITE_SRC2_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 210:// DS_MIN_SRC2_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 211:// DS_MAX_SRC2_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 222:// DS_WRITE_B96 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); +break; +case 223:// DS_WRITE_B128 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+3,32),true,false); +break; +case 254:// DS_READ_B96 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +case 255:// DS_READ_B128 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLATOperands(){ +layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; +switch(layout.OP){ +case 16:// FLAT_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// FLAT_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// FLAT_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// FLAT_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// FLAT_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// FLAT_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// FLAT_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// FLAT_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// FLAT_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// FLAT_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// FLAT_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// FLAT_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// FLAT_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// FLAT_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// FLAT_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// FLAT_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// FLAT_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// FLAT_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// FLAT_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// FLAT_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// FLAT_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// FLAT_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 64:// FLAT_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 65:// FLAT_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 66:// FLAT_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 67:// FLAT_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 68:// FLAT_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 69:// FLAT_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 70:// FLAT_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 71:// FLAT_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 72:// FLAT_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 73:// FLAT_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 74:// FLAT_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 75:// FLAT_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 76:// FLAT_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 96:// FLAT_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 97:// FLAT_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 98:// FLAT_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 99:// FLAT_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 100:// FLAT_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 101:// FLAT_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 102:// FLAT_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 103:// FLAT_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 104:// FLAT_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 105:// FLAT_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 106:// FLAT_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 107:// FLAT_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 108:// FLAT_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_GLBLOperands(){ +layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; +switch(layout.OP){ +case 16:// GLOBAL_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// GLOBAL_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// GLOBAL_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// GLOBAL_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// GLOBAL_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// GLOBAL_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// GLOBAL_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// GLOBAL_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// GLOBAL_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// GLOBAL_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// GLOBAL_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// GLOBAL_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// GLOBAL_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// GLOBAL_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// GLOBAL_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// GLOBAL_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// GLOBAL_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// GLOBAL_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// GLOBAL_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// GLOBAL_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// GLOBAL_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// GLOBAL_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 64:// GLOBAL_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 65:// GLOBAL_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 66:// GLOBAL_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 67:// GLOBAL_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 68:// GLOBAL_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 69:// GLOBAL_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 70:// GLOBAL_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 71:// GLOBAL_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 72:// GLOBAL_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 73:// GLOBAL_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 74:// GLOBAL_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 75:// GLOBAL_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 76:// GLOBAL_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 77:// GLOBAL_ATOMIC_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 78:// GLOBAL_ATOMIC_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 96:// GLOBAL_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 97:// GLOBAL_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 98:// GLOBAL_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 99:// GLOBAL_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 100:// GLOBAL_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 101:// GLOBAL_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 102:// GLOBAL_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 103:// GLOBAL_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 104:// GLOBAL_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 105:// GLOBAL_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 106:// GLOBAL_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 107:// GLOBAL_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 108:// GLOBAL_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_SCRATCHOperands(){ +layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; +switch(layout.OP){ +case 16:// SCRATCH_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// SCRATCH_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// SCRATCH_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 19:// SCRATCH_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 20:// SCRATCH_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 21:// SCRATCH_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 22:// SCRATCH_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// SCRATCH_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 24:// SCRATCH_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 25:// SCRATCH_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 26:// SCRATCH_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 27:// SCRATCH_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 28:// SCRATCH_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 29:// SCRATCH_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// SCRATCH_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 31:// SCRATCH_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 32:// SCRATCH_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 33:// SCRATCH_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 34:// SCRATCH_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 35:// SCRATCH_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 36:// SCRATCH_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 37:// SCRATCH_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MIMGOperands(){ +layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; +switch(layout.OP){ +case 0:// IMAGE_LOAD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 1:// IMAGE_LOAD_MIP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 2:// IMAGE_LOAD_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 3:// IMAGE_LOAD_PCK_SGN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 4:// IMAGE_LOAD_MIP_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 5:// IMAGE_LOAD_MIP_PCK_SGN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 8:// IMAGE_STORE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 9:// IMAGE_STORE_MIP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 10:// IMAGE_STORE_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 11:// IMAGE_STORE_MIP_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 14:// IMAGE_GET_RESINFO +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 16:// IMAGE_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 17:// IMAGE_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 18:// IMAGE_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 19:// IMAGE_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 20:// IMAGE_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 21:// IMAGE_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 22:// IMAGE_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 23:// IMAGE_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 24:// IMAGE_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 25:// IMAGE_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 26:// IMAGE_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 27:// IMAGE_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 28:// IMAGE_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +break; +case 32:// IMAGE_SAMPLE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 33:// IMAGE_SAMPLE_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 34:// IMAGE_SAMPLE_D +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 35:// IMAGE_SAMPLE_D_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 36:// IMAGE_SAMPLE_L +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 37:// IMAGE_SAMPLE_B +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 38:// IMAGE_SAMPLE_B_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 39:// IMAGE_SAMPLE_LZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 40:// IMAGE_SAMPLE_C +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 41:// IMAGE_SAMPLE_C_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 42:// IMAGE_SAMPLE_C_D +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 43:// IMAGE_SAMPLE_C_D_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 44:// IMAGE_SAMPLE_C_L +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 45:// IMAGE_SAMPLE_C_B +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 46:// IMAGE_SAMPLE_C_B_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 47:// IMAGE_SAMPLE_C_LZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 48:// IMAGE_SAMPLE_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 49:// IMAGE_SAMPLE_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 50:// IMAGE_SAMPLE_D_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 51:// IMAGE_SAMPLE_D_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 52:// IMAGE_SAMPLE_L_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 53:// IMAGE_SAMPLE_B_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 54:// IMAGE_SAMPLE_B_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 55:// IMAGE_SAMPLE_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 56:// IMAGE_SAMPLE_C_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 57:// IMAGE_SAMPLE_C_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 58:// IMAGE_SAMPLE_C_D_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 59:// IMAGE_SAMPLE_C_D_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 60:// IMAGE_SAMPLE_C_L_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 61:// IMAGE_SAMPLE_C_B_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 62:// IMAGE_SAMPLE_C_B_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 63:// IMAGE_SAMPLE_C_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 64:// IMAGE_GATHER4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 65:// IMAGE_GATHER4_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 66:// IMAGE_GATHER4H +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 68:// IMAGE_GATHER4_L +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 69:// IMAGE_GATHER4_B +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 70:// IMAGE_GATHER4_B_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 71:// IMAGE_GATHER4_LZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 72:// IMAGE_GATHER4_C +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 73:// IMAGE_GATHER4_C_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 74:// IMAGE_GATHER4H_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 75:// IMAGE_GATHER8H_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 76:// IMAGE_GATHER4_C_L +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 77:// IMAGE_GATHER4_C_B +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 78:// IMAGE_GATHER4_C_B_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 79:// IMAGE_GATHER4_C_LZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 80:// IMAGE_GATHER4_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 81:// IMAGE_GATHER4_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 84:// IMAGE_GATHER4_L_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 85:// IMAGE_GATHER4_B_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 86:// IMAGE_GATHER4_B_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 87:// IMAGE_GATHER4_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 88:// IMAGE_GATHER4_C_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 89:// IMAGE_GATHER4_C_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 92:// IMAGE_GATHER4_C_L_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 93:// IMAGE_GATHER4_C_B_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 94:// IMAGE_GATHER4_C_B_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 95:// IMAGE_GATHER4_C_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 96:// IMAGE_GET_LOD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 104:// IMAGE_SAMPLE_CD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 105:// IMAGE_SAMPLE_CD_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 106:// IMAGE_SAMPLE_C_CD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 107:// IMAGE_SAMPLE_C_CD_CL +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 108:// IMAGE_SAMPLE_CD_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 109:// IMAGE_SAMPLE_CD_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 110:// IMAGE_SAMPLE_C_CD_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +case 111:// IMAGE_SAMPLE_C_CD_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MTBUFOperands(){ +layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; +switch(layout.OP){ +case 0:// TBUFFER_LOAD_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 1:// TBUFFER_LOAD_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 2:// TBUFFER_LOAD_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 3:// TBUFFER_LOAD_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 4:// TBUFFER_STORE_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 5:// TBUFFER_STORE_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 6:// TBUFFER_STORE_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 7:// TBUFFER_STORE_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 8:// TBUFFER_LOAD_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 9:// TBUFFER_LOAD_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 10:// TBUFFER_LOAD_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 11:// TBUFFER_LOAD_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 12:// TBUFFER_STORE_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 13:// TBUFFER_STORE_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 14:// TBUFFER_STORE_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 15:// TBUFFER_STORE_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MUBUFOperands(){ +layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; +switch(layout.OP){ +case 0:// BUFFER_LOAD_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 1:// BUFFER_LOAD_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 2:// BUFFER_LOAD_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 3:// BUFFER_LOAD_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 4:// BUFFER_STORE_FORMAT_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 5:// BUFFER_STORE_FORMAT_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 6:// BUFFER_STORE_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 7:// BUFFER_STORE_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 8:// BUFFER_LOAD_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 9:// BUFFER_LOAD_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 10:// BUFFER_LOAD_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 11:// BUFFER_LOAD_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 12:// BUFFER_STORE_FORMAT_D16_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 13:// BUFFER_STORE_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 14:// BUFFER_STORE_FORMAT_D16_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 15:// BUFFER_STORE_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 16:// BUFFER_LOAD_UBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 17:// BUFFER_LOAD_SBYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 18:// BUFFER_LOAD_USHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 19:// BUFFER_LOAD_SSHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 20:// BUFFER_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 21:// BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 22:// BUFFER_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 23:// BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 24:// BUFFER_STORE_BYTE +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 25:// BUFFER_STORE_BYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 26:// BUFFER_STORE_SHORT +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 27:// BUFFER_STORE_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 28:// BUFFER_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 29:// BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 30:// BUFFER_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 31:// BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 32:// BUFFER_LOAD_UBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 33:// BUFFER_LOAD_UBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 34:// BUFFER_LOAD_SBYTE_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 35:// BUFFER_LOAD_SBYTE_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 36:// BUFFER_LOAD_SHORT_D16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 37:// BUFFER_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 38:// BUFFER_LOAD_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 39:// BUFFER_STORE_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 61:// BUFFER_STORE_LDS_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 62:// BUFFER_WBINVL1 +break; +case 63:// BUFFER_WBINVL1_VOL +break; +case 64:// BUFFER_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 65:// BUFFER_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 66:// BUFFER_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 67:// BUFFER_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 68:// BUFFER_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 69:// BUFFER_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 70:// BUFFER_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 71:// BUFFER_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 72:// BUFFER_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 73:// BUFFER_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 74:// BUFFER_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 75:// BUFFER_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 76:// BUFFER_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 77:// BUFFER_ATOMIC_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 78:// BUFFER_ATOMIC_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 96:// BUFFER_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 97:// BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 98:// BUFFER_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 99:// BUFFER_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 100:// BUFFER_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 101:// BUFFER_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 102:// BUFFER_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 103:// BUFFER_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 104:// BUFFER_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 105:// BUFFER_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 106:// BUFFER_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 107:// BUFFER_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 108:// BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SMEMOperands(){ +layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; +switch(layout.OP){ +case 0:// S_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 1:// S_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 2:// S_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 3:// S_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 4:// S_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 5:// S_SCRATCH_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 6:// S_SCRATCH_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 7:// S_SCRATCH_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 8:// S_BUFFER_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 9:// S_BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 10:// S_BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 11:// S_BUFFER_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 12:// S_BUFFER_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 16:// S_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 17:// S_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 18:// S_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 21:// S_SCRATCH_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 22:// S_SCRATCH_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 23:// S_SCRATCH_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 24:// S_BUFFER_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 25:// S_BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 26:// S_BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 32:// S_DCACHE_INV +break; +case 33:// S_DCACHE_WB +break; +case 34:// S_DCACHE_INV_VOL +break; +case 35:// S_DCACHE_WB_VOL +break; +case 36:// S_MEMTIME +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +break; +case 37:// S_MEMREALTIME +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +break; +case 38:// S_ATC_PROBE +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 39:// S_ATC_PROBE_BUFFER +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 40:// S_DCACHE_DISCARD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 41:// S_DCACHE_DISCARD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 64:// S_BUFFER_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 65:// S_BUFFER_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 66:// S_BUFFER_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 67:// S_BUFFER_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 68:// S_BUFFER_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 69:// S_BUFFER_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 70:// S_BUFFER_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 71:// S_BUFFER_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 72:// S_BUFFER_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 73:// S_BUFFER_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 74:// S_BUFFER_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 75:// S_BUFFER_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 76:// S_BUFFER_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 96:// S_BUFFER_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 97:// S_BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 98:// S_BUFFER_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 99:// S_BUFFER_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 100:// S_BUFFER_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 101:// S_BUFFER_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 102:// S_BUFFER_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 103:// S_BUFFER_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 104:// S_BUFFER_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 105:// S_BUFFER_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 106:// S_BUFFER_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 107:// S_BUFFER_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 108:// S_BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 128:// S_ATOMIC_SWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 129:// S_ATOMIC_CMPSWAP +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 130:// S_ATOMIC_ADD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 131:// S_ATOMIC_SUB +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 132:// S_ATOMIC_SMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 133:// S_ATOMIC_UMIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 134:// S_ATOMIC_SMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 135:// S_ATOMIC_UMAX +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 136:// S_ATOMIC_AND +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 137:// S_ATOMIC_OR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 138:// S_ATOMIC_XOR +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 139:// S_ATOMIC_INC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 140:// S_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 160:// S_ATOMIC_SWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 161:// S_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 162:// S_ATOMIC_ADD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 163:// S_ATOMIC_SUB_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 164:// S_ATOMIC_SMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 165:// S_ATOMIC_UMIN_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 166:// S_ATOMIC_SMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 167:// S_ATOMIC_UMAX_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 168:// S_ATOMIC_AND_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 169:// S_ATOMIC_OR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 170:// S_ATOMIC_XOR_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 171:// S_ATOMIC_INC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 172:// S_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP1Operands(){ +layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; +switch(layout.OP){ +case 0:// S_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 1:// S_MOV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 2:// S_CMOV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 3:// S_CMOV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 4:// S_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_NOT_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_WQM_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_WQM_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_BREV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 9:// S_BREV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 10:// S_BCNT0_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_BCNT0_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_BCNT1_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_BCNT1_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_FF0_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 15:// S_FF0_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 16:// S_FF1_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 17:// S_FF1_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 18:// S_FLBIT_I32_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 19:// S_FLBIT_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 20:// S_FLBIT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 21:// S_FLBIT_I32_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +break; +case 22:// S_SEXT_I32_I8 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +break; +case 23:// S_SEXT_I32_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +break; +case 24:// S_BITSET0_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 25:// S_BITSET0_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 26:// S_BITSET1_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 27:// S_BITSET1_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +case 28:// S_GETPC_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +case 29:// S_SETPC_B64 +setBranch(); +setModifyPC(); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 30:// S_SWAPPC_B64 +setBranch(); +setModifyPC(); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +case 31:// S_RFE_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 32:// S_AND_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 33:// S_OR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 34:// S_XOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 35:// S_ANDN2_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 36:// S_ORN2_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 37:// S_NAND_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 38:// S_NOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 39:// S_XNOR_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 40:// S_QUADMASK_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 41:// S_QUADMASK_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 42:// S_MOVRELS_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 43:// S_MOVRELS_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 44:// S_MOVRELD_B32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 45:// S_MOVRELD_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 46:// S_CBRANCH_JOIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 48:// S_ABS_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 50:// S_SET_GPR_IDX_IDX +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 51:// S_ANDN1_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 52:// S_ORN1_SAVEEXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 53:// S_ANDN1_WREXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 54:// S_ANDN2_WREXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 55:// S_BITREPLICATE_B64_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP2Operands(){ +layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; +switch(layout.OP){ +case 0:// S_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 1:// S_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 2:// S_ADD_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_SUB_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_ADDC_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 5:// S_SUBB_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 6:// S_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CSELECT_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 11:// S_CSELECT_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 12:// S_AND_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_AND_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_OR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_OR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 16:// S_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 17:// S_XOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 18:// S_ANDN2_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 19:// S_ANDN2_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 20:// S_ORN2_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 21:// S_ORN2_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 22:// S_NAND_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 23:// S_NAND_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 24:// S_NOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 25:// S_NOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 26:// S_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 27:// S_XNOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 28:// S_LSHL_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 29:// S_LSHL_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 30:// S_LSHR_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 31:// S_LSHR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 32:// S_ASHR_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 33:// S_ASHR_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 34:// S_BFM_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 35:// S_BFM_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 36:// S_MUL_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 37:// S_BFE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 38:// S_BFE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 39:// S_BFE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 40:// S_BFE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 41:// S_CBRANCH_G_FORK +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 42:// S_ABSDIFF_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 43:// S_RFE_RESTORE_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +break; +case 44:// S_MUL_HI_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 45:// S_MUL_HI_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 46:// S_LSHL1_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 47:// S_LSHL2_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 48:// S_LSHL3_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 49:// S_LSHL4_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 50:// S_PACK_LL_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,16),true,false); +break; +case 51:// S_PACK_LH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 52:// S_PACK_HH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPCOperands(){ +layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; +switch(layout.OP){ +case 0:// S_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 1:// S_CMP_LG_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 2:// S_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_CMP_LG_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_BITCMP0_B32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_BITCMP1_B32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_BITCMP0_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_BITCMP1_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 16:// S_SETVSKIP +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +break; +case 17:// S_SET_GPR_IDX_ON +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// S_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 19:// S_CMP_LG_U64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPKOperands(){ +layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; +switch(layout.OP){ +case 0:// S_MOVK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 1:// S_CMOVK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 2:// S_CMPK_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 3:// S_CMPK_LG_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 4:// S_CMPK_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 5:// S_CMPK_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 6:// S_CMPK_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 7:// S_CMPK_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 8:// S_CMPK_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 9:// S_CMPK_LG_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 10:// S_CMPK_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 11:// S_CMPK_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 12:// S_CMPK_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 13:// S_CMPK_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 14:// S_ADDK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 15:// S_MULK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 16:// S_CBRANCH_I_FORK +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 17:// S_GETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 18:// S_SETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +break; +case 21:// S_CALL_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeSOPK_INST_LITERAL_Operands(){ +layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; +switch(layout.OP){ +case 20:// S_SETREG_IMM32_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM32(decodeOPR_LITERAL()),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPPOperands(){ +layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; +switch(layout.OP){ +case 0:// S_NOP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 1:// S_ENDPGM +break; +case 2:// S_BRANCH +setBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 3:// S_WAKEUP +break; +case 4:// S_CBRANCH_SCC0 +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 5:// S_CBRANCH_SCC1 +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +break; +case 6:// S_CBRANCH_VCCZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 7:// S_CBRANCH_VCCNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 8:// S_CBRANCH_EXECZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 9:// S_CBRANCH_EXECNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +break; +case 10:// S_BARRIER +break; +case 11:// S_SETKILL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 12:// S_WAITCNT +insn_in_progress->appendOperand(decodeOPR_WAITCNT(layout.SIMM16),true,false); +break; +case 13:// S_SETHALT +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 14:// S_SLEEP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 15:// S_SETPRIO +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 16:// S_SENDMSG +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 17:// S_SENDMSGHALT +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 18:// S_TRAP +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 19:// S_ICACHE_INV +break; +case 20:// S_INCPERFLEVEL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 21:// S_DECPERFLEVEL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +break; +case 22:// S_TTRACEDATA +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 23:// S_CBRANCH_CDBGSYS +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 24:// S_CBRANCH_CDBGUSER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 25:// S_CBRANCH_CDBGSYS_OR_USER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 26:// S_CBRANCH_CDBGSYS_AND_USER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +break; +case 27:// S_ENDPGM_SAVED +break; +case 28:// S_SET_GPR_IDX_OFF +break; +case 29:// S_SET_GPR_IDX_MODE +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 30:// S_ENDPGM_ORDERED_PS_DONE +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VINTRPOperands(){ +layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; +switch(layout.OP){ +case 0:// V_INTERP_P1_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 1:// V_INTERP_P2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 2:// V_INTERP_MOV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3Operands(){ +layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; +switch(layout.OP){ +case 624:// V_INTERP_P1_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 625:// V_INTERP_P2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 626:// V_INTERP_MOV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +case 320:// V_NOP +break; +case 321:// V_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 322:// V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +break; +case 323:// V_CVT_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 324:// V_CVT_F64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 325:// V_CVT_F32_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 326:// V_CVT_F32_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 327:// V_CVT_U32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 328:// V_CVT_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 330:// V_CVT_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 331:// V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 332:// V_CVT_RPI_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 333:// V_CVT_FLR_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 334:// V_CVT_OFF_F32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 335:// V_CVT_F32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 336:// V_CVT_F64_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 337:// V_CVT_F32_UBYTE0 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 338:// V_CVT_F32_UBYTE1 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 339:// V_CVT_F32_UBYTE2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 340:// V_CVT_F32_UBYTE3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 341:// V_CVT_U32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 342:// V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 343:// V_TRUNC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 344:// V_CEIL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 345:// V_RNDNE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 346:// V_FLOOR_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 347:// V_FRACT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 348:// V_TRUNC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 349:// V_CEIL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 350:// V_RNDNE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 351:// V_FLOOR_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 352:// V_EXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 353:// V_LOG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 354:// V_RCP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 355:// V_RCP_IFLAG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 356:// V_RSQ_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 357:// V_RCP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 358:// V_RSQ_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 359:// V_SQRT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 360:// V_SQRT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 361:// V_SIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 362:// V_COS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 363:// V_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 364:// V_BFREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 365:// V_FFBH_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 366:// V_FFBL_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 367:// V_FFBH_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 368:// V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 369:// V_FREXP_MANT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 370:// V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +break; +case 371:// V_FREXP_EXP_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 372:// V_FREXP_MANT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 373:// V_CLREXCP +break; +case 375:// V_SCREEN_PARTITION_4SE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 377:// V_CVT_F16_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 378:// V_CVT_F16_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 379:// V_CVT_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 380:// V_CVT_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 381:// V_RCP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 382:// V_SQRT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 383:// V_RSQ_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 384:// V_LOG_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 385:// V_EXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 386:// V_FREXP_MANT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 387:// V_FREXP_EXP_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 388:// V_FLOOR_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 389:// V_CEIL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 390:// V_TRUNC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 391:// V_RNDNE_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 392:// V_FRACT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 393:// V_SIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 394:// V_COS_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 395:// V_EXP_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 396:// V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 397:// V_CVT_NORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 398:// V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +break; +case 399:// V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +case 401:// V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +break; +case 256:// V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 257:// V_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 258:// V_SUB_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 259:// V_SUBREV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 260:// V_MUL_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 261:// V_MUL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 262:// V_MUL_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 263:// V_MUL_HI_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 264:// V_MUL_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 265:// V_MUL_HI_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 266:// V_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 267:// V_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 268:// V_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 269:// V_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 270:// V_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 271:// V_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 272:// V_LSHRREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 273:// V_ASHRREV_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 274:// V_LSHLREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 275:// V_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 276:// V_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 277:// V_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 278:// V_MAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 287:// V_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 288:// V_SUB_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 289:// V_SUBREV_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 290:// V_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 291:// V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 294:// V_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 295:// V_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 296:// V_SUBREV_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 297:// V_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 298:// V_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 299:// V_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 300:// V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 301:// V_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 302:// V_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 303:// V_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 304:// V_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 305:// V_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 306:// V_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 307:// V_LDEXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 308:// V_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 309:// V_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 310:// V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 311:// V_DOT2C_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 312:// V_DOT2C_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 313:// V_DOT4C_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 314:// V_DOT8C_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 315:// V_FMAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 316:// V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 317:// V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 448:// V_MAD_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 449:// V_MAD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 450:// V_MAD_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 451:// V_MAD_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 452:// V_CUBEID_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 453:// V_CUBESC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 454:// V_CUBETC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 455:// V_CUBEMA_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 456:// V_BFE_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 457:// V_BFE_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 458:// V_BFI_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 459:// V_FMA_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 460:// V_FMA_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 461:// V_LERP_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 462:// V_ALIGNBIT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 463:// V_ALIGNBYTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 464:// V_MIN3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 465:// V_MIN3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 466:// V_MIN3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 467:// V_MAX3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 468:// V_MAX3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 469:// V_MAX3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 470:// V_MED3_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 471:// V_MED3_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 472:// V_MED3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 473:// V_SAD_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 474:// V_SAD_HI_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 475:// V_SAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 476:// V_SAD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 477:// V_CVT_PK_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 478:// V_DIV_FIXUP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 479:// V_DIV_FIXUP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 482:// V_DIV_FMAS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 483:// V_DIV_FMAS_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 484:// V_MSAD_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 485:// V_QSAD_PK_U16_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 486:// V_MQSAD_PK_U16_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 487:// V_MQSAD_U32_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,32),true,false); +break; +case 490:// V_MAD_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 491:// V_MAD_LEGACY_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 492:// V_MAD_LEGACY_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 493:// V_PERM_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 494:// V_FMA_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 495:// V_DIV_FIXUP_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 496:// V_CVT_PKACCUM_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 497:// V_MAD_U32_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 498:// V_MAD_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 499:// V_XAD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 500:// V_MIN3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 501:// V_MIN3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 502:// V_MIN3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 503:// V_MAX3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 504:// V_MAX3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 505:// V_MAX3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 506:// V_MED3_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 507:// V_MED3_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 508:// V_MED3_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 509:// V_LSHL_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 510:// V_ADD_LSHL_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 511:// V_ADD3_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 512:// V_LSHL_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 513:// V_AND_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 514:// V_OR3_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 515:// V_MAD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 516:// V_MAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 517:// V_MAD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 518:// V_FMA_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 519:// V_DIV_FIXUP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 628:// V_INTERP_P1LL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +break; +case 629:// V_INTERP_P1LV_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); +break; +case 630:// V_INTERP_P2_LEGACY_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); +break; +case 631:// V_INTERP_P2_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); +break; +case 640:// V_ADD_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 641:// V_MUL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 642:// V_MIN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 643:// V_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 644:// V_LDEXP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 645:// V_MUL_LO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 646:// V_MUL_HI_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 647:// V_MUL_HI_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 648:// V_LDEXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 649:// V_READLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +break; +case 650:// V_WRITELANE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +break; +case 651:// V_BCNT_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 652:// V_MBCNT_LO_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 653:// V_MBCNT_HI_U32_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 655:// V_LSHLREV_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 656:// V_LSHRREV_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 657:// V_ASHRREV_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 658:// V_TRIG_PREOP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 659:// V_BFM_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 660:// V_CVT_PKNORM_I16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 661:// V_CVT_PKNORM_U16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 662:// V_CVT_PKRTZ_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 663:// V_CVT_PK_U16_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 664:// V_CVT_PK_I16_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 665:// V_CVT_PKNORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 666:// V_CVT_PKNORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 668:// V_ADD_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 669:// V_SUB_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 670:// V_ADD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 671:// V_SUB_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 672:// V_PACK_B32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 16:// V_CMP_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 17:// V_CMPX_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 18:// V_CMP_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 19:// V_CMPX_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 20:// V_CMP_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 21:// V_CMPX_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 32:// V_CMP_F_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 33:// V_CMP_LT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 34:// V_CMP_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 35:// V_CMP_LE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 36:// V_CMP_GT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 37:// V_CMP_LG_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 38:// V_CMP_GE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 39:// V_CMP_O_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 40:// V_CMP_U_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 41:// V_CMP_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 42:// V_CMP_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 43:// V_CMP_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 44:// V_CMP_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 45:// V_CMP_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 46:// V_CMP_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 47:// V_CMP_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 48:// V_CMPX_F_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 49:// V_CMPX_LT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 50:// V_CMPX_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 51:// V_CMPX_LE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 52:// V_CMPX_GT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 53:// V_CMPX_LG_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 54:// V_CMPX_GE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 55:// V_CMPX_O_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 56:// V_CMPX_U_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 57:// V_CMPX_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 58:// V_CMPX_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 59:// V_CMPX_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 60:// V_CMPX_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 61:// V_CMPX_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 62:// V_CMPX_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 63:// V_CMPX_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 64:// V_CMP_F_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 65:// V_CMP_LT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 66:// V_CMP_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 67:// V_CMP_LE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 68:// V_CMP_GT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 69:// V_CMP_LG_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 70:// V_CMP_GE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 71:// V_CMP_O_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 72:// V_CMP_U_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 73:// V_CMP_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 74:// V_CMP_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 75:// V_CMP_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 76:// V_CMP_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 77:// V_CMP_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 78:// V_CMP_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 79:// V_CMP_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 80:// V_CMPX_F_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 81:// V_CMPX_LT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 82:// V_CMPX_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 83:// V_CMPX_LE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 84:// V_CMPX_GT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 85:// V_CMPX_LG_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 86:// V_CMPX_GE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 87:// V_CMPX_O_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 88:// V_CMPX_U_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 89:// V_CMPX_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 90:// V_CMPX_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 91:// V_CMPX_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 92:// V_CMPX_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 93:// V_CMPX_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 94:// V_CMPX_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 95:// V_CMPX_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 96:// V_CMP_F_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 97:// V_CMP_LT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 98:// V_CMP_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 99:// V_CMP_LE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 100:// V_CMP_GT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 101:// V_CMP_LG_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 102:// V_CMP_GE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 103:// V_CMP_O_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 104:// V_CMP_U_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 105:// V_CMP_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 106:// V_CMP_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 107:// V_CMP_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 108:// V_CMP_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 109:// V_CMP_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 110:// V_CMP_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 111:// V_CMP_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 112:// V_CMPX_F_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 113:// V_CMPX_LT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 114:// V_CMPX_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 115:// V_CMPX_LE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 116:// V_CMPX_GT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 117:// V_CMPX_LG_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 118:// V_CMPX_GE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 119:// V_CMPX_O_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 120:// V_CMPX_U_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 121:// V_CMPX_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 122:// V_CMPX_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 123:// V_CMPX_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 124:// V_CMPX_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 125:// V_CMPX_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 126:// V_CMPX_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 127:// V_CMPX_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 160:// V_CMP_F_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 161:// V_CMP_LT_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 162:// V_CMP_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 163:// V_CMP_LE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 164:// V_CMP_GT_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 165:// V_CMP_NE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 166:// V_CMP_GE_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 167:// V_CMP_T_I16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 168:// V_CMP_F_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 169:// V_CMP_LT_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 170:// V_CMP_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 171:// V_CMP_LE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 172:// V_CMP_GT_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 173:// V_CMP_NE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 174:// V_CMP_GE_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 175:// V_CMP_T_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 176:// V_CMPX_F_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 177:// V_CMPX_LT_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 178:// V_CMPX_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 179:// V_CMPX_LE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 180:// V_CMPX_GT_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 181:// V_CMPX_NE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 182:// V_CMPX_GE_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 183:// V_CMPX_T_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 184:// V_CMPX_F_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 185:// V_CMPX_LT_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 186:// V_CMPX_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 187:// V_CMPX_LE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 188:// V_CMPX_GT_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 189:// V_CMPX_NE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 190:// V_CMPX_GE_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 191:// V_CMPX_T_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 192:// V_CMP_F_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 193:// V_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 194:// V_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 195:// V_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 196:// V_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 197:// V_CMP_NE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 198:// V_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 199:// V_CMP_T_I32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 200:// V_CMP_F_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 201:// V_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 202:// V_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 203:// V_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 204:// V_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 205:// V_CMP_NE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 206:// V_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 207:// V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 208:// V_CMPX_F_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 209:// V_CMPX_LT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 210:// V_CMPX_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 211:// V_CMPX_LE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 212:// V_CMPX_GT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 213:// V_CMPX_NE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 214:// V_CMPX_GE_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 215:// V_CMPX_T_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 216:// V_CMPX_F_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 217:// V_CMPX_LT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 218:// V_CMPX_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 219:// V_CMPX_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 220:// V_CMPX_GT_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 221:// V_CMPX_NE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 222:// V_CMPX_GE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 223:// V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 224:// V_CMP_F_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 225:// V_CMP_LT_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 226:// V_CMP_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 227:// V_CMP_LE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 228:// V_CMP_GT_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 229:// V_CMP_NE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 230:// V_CMP_GE_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 231:// V_CMP_T_I64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 232:// V_CMP_F_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 233:// V_CMP_LT_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 234:// V_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 235:// V_CMP_LE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 236:// V_CMP_GT_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 237:// V_CMP_NE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 238:// V_CMP_GE_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 239:// V_CMP_T_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +break; +case 240:// V_CMPX_F_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 241:// V_CMPX_LT_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 242:// V_CMPX_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 243:// V_CMPX_LE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 244:// V_CMPX_GT_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 245:// V_CMPX_NE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 246:// V_CMPX_GE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 247:// V_CMPX_T_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 248:// V_CMPX_F_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 249:// V_CMPX_LT_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 250:// V_CMPX_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 251:// V_CMPX_LE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 252:// V_CMPX_GT_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 253:// V_CMPX_NE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 254:// V_CMPX_GE_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 255:// V_CMPX_T_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP1Operands(){ +layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; +switch(layout.OP){ +case 0:// V_NOP +break; +case 1:// V_MOV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 2:// V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +break; +case 3:// V_CVT_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 4:// V_CVT_F64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 5:// V_CVT_F32_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 6:// V_CVT_F32_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 7:// V_CVT_U32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 8:// V_CVT_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 10:// V_CVT_F16_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 11:// V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 12:// V_CVT_RPI_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 13:// V_CVT_FLR_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 14:// V_CVT_OFF_F32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 15:// V_CVT_F32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 16:// V_CVT_F64_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 17:// V_CVT_F32_UBYTE0 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 18:// V_CVT_F32_UBYTE1 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 19:// V_CVT_F32_UBYTE2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 20:// V_CVT_F32_UBYTE3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 21:// V_CVT_U32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 22:// V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 23:// V_TRUNC_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 24:// V_CEIL_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 25:// V_RNDNE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 26:// V_FLOOR_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 27:// V_FRACT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 28:// V_TRUNC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 29:// V_CEIL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 30:// V_RNDNE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 31:// V_FLOOR_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 32:// V_EXP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 33:// V_LOG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 34:// V_RCP_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 35:// V_RCP_IFLAG_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 36:// V_RSQ_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 37:// V_RCP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 38:// V_RSQ_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 39:// V_SQRT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 40:// V_SQRT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 41:// V_SIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 42:// V_COS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 43:// V_NOT_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 44:// V_BFREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 45:// V_FFBH_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 46:// V_FFBL_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 47:// V_FFBH_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 48:// V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 49:// V_FREXP_MANT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 50:// V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +break; +case 51:// V_FREXP_EXP_I32_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 52:// V_FREXP_MANT_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 53:// V_CLREXCP +break; +case 55:// V_SCREEN_PARTITION_4SE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 57:// V_CVT_F16_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 58:// V_CVT_F16_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 59:// V_CVT_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 60:// V_CVT_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 61:// V_RCP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 62:// V_SQRT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 63:// V_RSQ_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 64:// V_LOG_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 65:// V_EXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 66:// V_FREXP_MANT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 67:// V_FREXP_EXP_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 68:// V_FLOOR_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 69:// V_CEIL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 70:// V_TRUNC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 71:// V_RNDNE_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 72:// V_FRACT_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 73:// V_SIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 74:// V_COS_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 75:// V_EXP_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 76:// V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 77:// V_CVT_NORM_I16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 78:// V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +break; +case 79:// V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +break; +case 81:// V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2Operands(){ +layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; +switch(layout.OP){ +case 0:// V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 1:// V_ADD_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 2:// V_SUB_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 3:// V_SUBREV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 4:// V_MUL_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 5:// V_MUL_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 6:// V_MUL_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 7:// V_MUL_HI_I32_I24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 8:// V_MUL_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 9:// V_MUL_HI_U32_U24 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 10:// V_MIN_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 11:// V_MAX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 12:// V_MIN_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 13:// V_MAX_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 14:// V_MIN_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 15:// V_MAX_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 16:// V_LSHRREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 17:// V_ASHRREV_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 18:// V_LSHLREV_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 19:// V_AND_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 20:// V_OR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 21:// V_XOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 22:// V_MAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 25:// V_ADD_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 26:// V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 27:// V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 28:// V_ADDC_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 29:// V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 30:// V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +break; +case 31:// V_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 32:// V_SUB_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 33:// V_SUBREV_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 34:// V_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 35:// V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 38:// V_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 39:// V_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 40:// V_SUBREV_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 41:// V_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 42:// V_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 43:// V_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 44:// V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 45:// V_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 46:// V_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 47:// V_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 48:// V_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 49:// V_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 50:// V_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 51:// V_LDEXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 52:// V_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 53:// V_SUB_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 54:// V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 55:// V_DOT2C_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 56:// V_DOT2C_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 57:// V_DOT4C_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 58:// V_DOT8C_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 59:// V_FMAC_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 60:// V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 61:// V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2_LITERALOperands(){ +layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; +switch(layout.OP){ +case 23:// V_MADMK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 24:// V_MADAK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +break; +case 36:// V_MADMK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 37:// V_MADAK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3BOperands(){ +layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; +switch(layout.OP){ +case 281:// V_ADD_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 282:// V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 283:// V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 284:// V_ADDC_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 285:// V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 286:// V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +break; +case 480:// V_DIV_SCALE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 481:// V_DIV_SCALE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 488:// V_MAD_U64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +case 489:// V_MAD_I64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3POperands(){ +layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; +switch(layout.OP){ +case 0:// V_PK_MAD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 1:// V_PK_MUL_LO_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 2:// V_PK_ADD_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 3:// V_PK_SUB_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 4:// V_PK_LSHLREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 5:// V_PK_LSHRREV_B16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 6:// V_PK_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +break; +case 7:// V_PK_MAX_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 8:// V_PK_MIN_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 9:// V_PK_MAD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 10:// V_PK_ADD_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 11:// V_PK_SUB_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 12:// V_PK_MAX_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 13:// V_PK_MIN_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 14:// V_PK_FMA_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 15:// V_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 16:// V_PK_MUL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 17:// V_PK_MIN_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 18:// V_PK_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +break; +case 32:// V_MAD_MIX_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 33:// V_MAD_MIXLO_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 34:// V_MAD_MIXHI_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 35:// V_DOT2_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 38:// V_DOT2_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 39:// V_DOT2_U32_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 40:// V_DOT4_I32_I8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 41:// V_DOT4_U32_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 42:// V_DOT8_I32_I4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 43:// V_DOT8_U32_U4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +break; +case 88:// V_ACCVGPR_READ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +break; +case 89:// V_ACCVGPR_WRITE +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3P_MFMAOperands(){ +layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; +switch(layout.OP){ +case 64:// V_MFMA_F32_32X32X1F32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 65:// V_MFMA_F32_16X16X1F32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 66:// V_MFMA_F32_4X4X1F32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 68:// V_MFMA_F32_32X32X2F32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 69:// V_MFMA_F32_16X16X4F32 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 72:// V_MFMA_F32_32X32X4F16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 73:// V_MFMA_F32_16X16X4F16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 74:// V_MFMA_F32_4X4X4F16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 76:// V_MFMA_F32_32X32X8F16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 77:// V_MFMA_F32_16X16X16F16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 80:// V_MFMA_I32_32X32X4I8 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 81:// V_MFMA_I32_16X16X4I8 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 82:// V_MFMA_I32_4X4X4I8 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 84:// V_MFMA_I32_32X32X8I8 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 85:// V_MFMA_I32_16X16X16I8 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 104:// V_MFMA_F32_32X32X2BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 105:// V_MFMA_F32_16X16X2BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 107:// V_MFMA_F32_4X4X2BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 108:// V_MFMA_F32_32X32X4BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +case 109:// V_MFMA_F32_16X16X8BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOPCOperands(){ +layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; +switch(layout.OP){ +case 16:// V_CMP_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 17:// V_CMPX_CLASS_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 18:// V_CMP_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 19:// V_CMPX_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 20:// V_CMP_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 21:// V_CMPX_CLASS_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 32:// V_CMP_F_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 33:// V_CMP_LT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 34:// V_CMP_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 35:// V_CMP_LE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 36:// V_CMP_GT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 37:// V_CMP_LG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 38:// V_CMP_GE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 39:// V_CMP_O_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 40:// V_CMP_U_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 41:// V_CMP_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 42:// V_CMP_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 43:// V_CMP_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 44:// V_CMP_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 45:// V_CMP_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 46:// V_CMP_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 47:// V_CMP_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 48:// V_CMPX_F_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 49:// V_CMPX_LT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 50:// V_CMPX_EQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 51:// V_CMPX_LE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 52:// V_CMPX_GT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 53:// V_CMPX_LG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 54:// V_CMPX_GE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 55:// V_CMPX_O_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 56:// V_CMPX_U_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 57:// V_CMPX_NGE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 58:// V_CMPX_NLG_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 59:// V_CMPX_NGT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 60:// V_CMPX_NLE_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 61:// V_CMPX_NEQ_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 62:// V_CMPX_NLT_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 63:// V_CMPX_TRU_F16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 64:// V_CMP_F_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 65:// V_CMP_LT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 66:// V_CMP_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 67:// V_CMP_LE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 68:// V_CMP_GT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 69:// V_CMP_LG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 70:// V_CMP_GE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 71:// V_CMP_O_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 72:// V_CMP_U_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 73:// V_CMP_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 74:// V_CMP_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 75:// V_CMP_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 76:// V_CMP_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 77:// V_CMP_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 78:// V_CMP_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 79:// V_CMP_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 80:// V_CMPX_F_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 81:// V_CMPX_LT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 82:// V_CMPX_EQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 83:// V_CMPX_LE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 84:// V_CMPX_GT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 85:// V_CMPX_LG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 86:// V_CMPX_GE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 87:// V_CMPX_O_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 88:// V_CMPX_U_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 89:// V_CMPX_NGE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 90:// V_CMPX_NLG_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 91:// V_CMPX_NGT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 92:// V_CMPX_NLE_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 93:// V_CMPX_NEQ_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 94:// V_CMPX_NLT_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 95:// V_CMPX_TRU_F32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 96:// V_CMP_F_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 97:// V_CMP_LT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 98:// V_CMP_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 99:// V_CMP_LE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 100:// V_CMP_GT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 101:// V_CMP_LG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 102:// V_CMP_GE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 103:// V_CMP_O_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 104:// V_CMP_U_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 105:// V_CMP_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 106:// V_CMP_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 107:// V_CMP_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 108:// V_CMP_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 109:// V_CMP_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 110:// V_CMP_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 111:// V_CMP_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 112:// V_CMPX_F_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 113:// V_CMPX_LT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 114:// V_CMPX_EQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 115:// V_CMPX_LE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 116:// V_CMPX_GT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 117:// V_CMPX_LG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 118:// V_CMPX_GE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 119:// V_CMPX_O_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 120:// V_CMPX_U_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 121:// V_CMPX_NGE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 122:// V_CMPX_NLG_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 123:// V_CMPX_NGT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 124:// V_CMPX_NLE_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 125:// V_CMPX_NEQ_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 126:// V_CMPX_NLT_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 127:// V_CMPX_TRU_F64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 160:// V_CMP_F_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 161:// V_CMP_LT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 162:// V_CMP_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 163:// V_CMP_LE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 164:// V_CMP_GT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 165:// V_CMP_NE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 166:// V_CMP_GE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 167:// V_CMP_T_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 168:// V_CMP_F_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 169:// V_CMP_LT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 170:// V_CMP_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 171:// V_CMP_LE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 172:// V_CMP_GT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 173:// V_CMP_NE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 174:// V_CMP_GE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 175:// V_CMP_T_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +break; +case 176:// V_CMPX_F_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 177:// V_CMPX_LT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 178:// V_CMPX_EQ_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 179:// V_CMPX_LE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 180:// V_CMPX_GT_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 181:// V_CMPX_NE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 182:// V_CMPX_GE_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 183:// V_CMPX_T_I16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 184:// V_CMPX_F_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 185:// V_CMPX_LT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 186:// V_CMPX_EQ_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 187:// V_CMPX_LE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 188:// V_CMPX_GT_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 189:// V_CMPX_NE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 190:// V_CMPX_GE_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 191:// V_CMPX_T_U16 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 192:// V_CMP_F_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 193:// V_CMP_LT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 194:// V_CMP_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 195:// V_CMP_LE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 196:// V_CMP_GT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 197:// V_CMP_NE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 198:// V_CMP_GE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 199:// V_CMP_T_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 200:// V_CMP_F_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 201:// V_CMP_LT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 202:// V_CMP_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 203:// V_CMP_LE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 204:// V_CMP_GT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 205:// V_CMP_NE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 206:// V_CMP_GE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 207:// V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +break; +case 208:// V_CMPX_F_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 209:// V_CMPX_LT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 210:// V_CMPX_EQ_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 211:// V_CMPX_LE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 212:// V_CMPX_GT_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 213:// V_CMPX_NE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 214:// V_CMPX_GE_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 215:// V_CMPX_T_I32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 216:// V_CMPX_F_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 217:// V_CMPX_LT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 218:// V_CMPX_EQ_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 219:// V_CMPX_LE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 220:// V_CMPX_GT_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 221:// V_CMPX_NE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 222:// V_CMPX_GE_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 223:// V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 224:// V_CMP_F_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 225:// V_CMP_LT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 226:// V_CMP_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 227:// V_CMP_LE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 228:// V_CMP_GT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 229:// V_CMP_NE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 230:// V_CMP_GE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 231:// V_CMP_T_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 232:// V_CMP_F_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 233:// V_CMP_LT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 234:// V_CMP_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 235:// V_CMP_LE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 236:// V_CMP_GT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 237:// V_CMP_NE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 238:// V_CMP_GE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 239:// V_CMP_T_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +break; +case 240:// V_CMPX_F_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 241:// V_CMPX_LT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 242:// V_CMPX_EQ_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 243:// V_CMPX_LE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 244:// V_CMPX_GT_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 245:// V_CMPX_NE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 246:// V_CMPX_GE_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 247:// V_CMPX_T_I64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 248:// V_CMPX_F_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 249:// V_CMPX_LT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 250:// V_CMPX_EQ_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 251:// V_CMPX_LE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 252:// V_CMPX_GT_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 253:// V_CMPX_NE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 254:// V_CMPX_GE_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +case 255:// V_CMPX_T_U64 +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +break; +} +} diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index bcc16621bf..e1badc6e05 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -59,7 +59,7 @@ using namespace NS_x86; #define DECODE_OPERANDS() \ do { \ - if (arch_decoded_from != Arch_cuda && arch_decoded_from != Arch_amdgpu_cdna2 && m_Operands.empty()) { \ + if (arch_decoded_from != Arch_cuda && arch_decoded_from != Arch_amdgpu_gfx908 && arch_decoded_from != Arch_amdgpu_cdna2 && m_Operands.empty()) { \ decodeOperands(); \ }\ }while(0) diff --git a/instructionAPI/src/InstructionCategories.C b/instructionAPI/src/InstructionCategories.C index 703e018c16..7fe6cf179d 100644 --- a/instructionAPI/src/InstructionCategories.C +++ b/instructionAPI/src/InstructionCategories.C @@ -44,6 +44,7 @@ namespace Dyninst case aarch64_op_ret: return c_ReturnInsn; case amdgpu_op_s_endpgm: // special treatment for endpgm + case amdgpu_gfx908_op_S_ENDPGM: // special treatment for endpgm case amdgpu_cdna2_op_S_ENDPGM: // special treatment for endpgm return c_GPUKernelExitInsn; case e_call: diff --git a/instructionAPI/src/InstructionDecoderImpl.C b/instructionAPI/src/InstructionDecoderImpl.C index 424f96f706..32090667da 100644 --- a/instructionAPI/src/InstructionDecoderImpl.C +++ b/instructionAPI/src/InstructionDecoderImpl.C @@ -34,6 +34,7 @@ #include "InstructionDecoder-power.h" #include "InstructionDecoder-aarch64.h" #include "AMDGPU/vega/InstructionDecoder-amdgpu-vega.h" +#include "AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h" #include "AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h" #include "BinaryFunction.h" @@ -78,6 +79,8 @@ namespace Dyninst return Ptr(new InstructionDecoder_aarch64(a)); case Arch_amdgpu_vega: return Ptr(new InstructionDecoder_amdgpu_vega(a)); + case Arch_amdgpu_gfx908: + return Ptr(new InstructionDecoder_amdgpu_gfx908(a)); case Arch_amdgpu_cdna2: return Ptr(new InstructionDecoder_amdgpu_cdna2(a)); default: diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index f70ebcf9c7..c87475d4dc 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -92,7 +92,7 @@ namespace Dyninst std::string RegisterAST::format(Architecture arch, formatStyle f) const { - if(arch == Arch_amdgpu_vega || arch == Arch_amdgpu_cdna2){ + if(arch == Arch_amdgpu_vega || arch == Arch_amdgpu_gfx908 || arch == Arch_amdgpu_cdna2){ return RegisterAST::format(f); } return ArchSpecificFormatter::getFormatter(arch).formatRegister(m_Reg.name()); @@ -117,22 +117,22 @@ namespace Dyninst // are the two *::VGPR constants DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP - if( regClass == amdgpu_cdna2::SGPR || regClass == amdgpu_vega::SGPR){ + if(regClass == amdgpu_gfx908::SGPR || regClass == amdgpu_cdna2::SGPR || regClass == amdgpu_vega::SGPR){ return "S["+to_string(id) + ":" + to_string(id+size-1)+"]"; } - if(regClass == amdgpu_cdna2::VGPR || regClass == amdgpu_vega::VGPR){ + if(regClass == amdgpu_gfx908::VGPR || regClass == amdgpu_cdna2::VGPR || regClass == amdgpu_vega::VGPR){ return "V["+to_string(id) + ":" + to_string(id+size-1)+"]"; } DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP - if(regClass == amdgpu_cdna2::ACC_VGPR){ + if(regClass == amdgpu_gfx908::ACC_VGPR || regClass == amdgpu_cdna2::ACC_VGPR){ return "ACC["+to_string(id) + ":" + to_string(id+size-1)+"]"; } - if(m_Reg == amdgpu_cdna2::vcc_lo || m_Reg == amdgpu_vega::vcc_lo) + if(m_Reg == amdgpu_gfx908::vcc_lo || m_Reg == amdgpu_cdna2::vcc_lo || m_Reg == amdgpu_vega::vcc_lo) return "VCC"; - if(m_Reg == amdgpu_cdna2::exec_lo || m_Reg == amdgpu_vega::exec_lo) + if(m_Reg == amdgpu_gfx908::exec_lo || m_Reg == amdgpu_cdna2::exec_lo || m_Reg == amdgpu_vega::exec_lo) return "EXEC"; name += "["+to_string(m_Low)+":"+to_string(m_High)+"]"; diff --git a/instructionAPI/src/amdgpu_branchinsn_table.h b/instructionAPI/src/amdgpu_branchinsn_table.h index c6ecc58feb..3df3e4944a 100644 --- a/instructionAPI/src/amdgpu_branchinsn_table.h +++ b/instructionAPI/src/amdgpu_branchinsn_table.h @@ -14,6 +14,22 @@ case amdgpu_op_s_cbranch_g_fork: case amdgpu_op_s_cbranch_i_fork: case amdgpu_op_s_call_b64: + case amdgpu_gfx908_op_S_BRANCH: + case amdgpu_gfx908_op_S_CBRANCH_SCC0: + case amdgpu_gfx908_op_S_CBRANCH_SCC1: + case amdgpu_gfx908_op_S_CBRANCH_VCCZ: + case amdgpu_gfx908_op_S_CBRANCH_VCCNZ: + case amdgpu_gfx908_op_S_CBRANCH_EXECZ: + case amdgpu_gfx908_op_S_CBRANCH_EXECNZ: + case amdgpu_gfx908_op_S_CBRANCH_CDBGSYS: + case amdgpu_gfx908_op_S_CBRANCH_CDBGUSER: + case amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER: + case amdgpu_gfx908_op_S_SETPC_B64: + case amdgpu_gfx908_op_S_SWAPPC_B64: + case amdgpu_gfx908_op_S_RFE_B64: + case amdgpu_gfx908_op_S_CBRANCH_G_FORK: + case amdgpu_gfx908_op_S_CBRANCH_I_FORK: + case amdgpu_gfx908_op_S_CALL_B64: case amdgpu_cdna2_op_S_BRANCH: case amdgpu_cdna2_op_S_CBRANCH_SCC0: case amdgpu_cdna2_op_S_CBRANCH_SCC1: diff --git a/instructionAPI/src/debug_decode.C b/instructionAPI/src/debug_decode.C new file mode 100644 index 0000000000..79a948df4e --- /dev/null +++ b/instructionAPI/src/debug_decode.C @@ -0,0 +1,77 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include + +#include "debug_decode.h" + +using namespace Dyninst::InstructionAPI; + +int Dyninst::InstructionAPI::dyn_debug_decoding = 0; +int Dyninst::InstructionAPI::dyn_debug_initialized = 0; + +#if defined(_OPENMP) +#include +#endif + +dyn_tls FILE* log_file = NULL; + +int Dyninst::InstructionAPI::decoding_printf_int(const char *format, ...); +int Dyninst::InstructionAPI::decoding_printf_int(const char *format, ...) +{ + if(!dyn_debug_initialized) { + if(getenv("DYNINST_DEBUG_DECODING")) + dyn_debug_decoding = 1; + dyn_debug_initialized = 1; + } + + if(!dyn_debug_decoding) return 0; + if(NULL == format) return -1; + if (log_file == NULL) { + char filename[128]; +#if defined(_OPENMP) + snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_DECODING"), omp_get_thread_num()); +#else + snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_DECODING"), 0); +#endif + + log_file = fopen(filename, "w"); + } + + va_list va; + va_start(va,format); + int ret = vfprintf(log_file, format, va); + fflush(log_file); + va_end(va); + + return ret; +} + diff --git a/instructionAPI/src/debug_decode.h b/instructionAPI/src/debug_decode.h new file mode 100644 index 0000000000..770936550d --- /dev/null +++ b/instructionAPI/src/debug_decode.h @@ -0,0 +1,52 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef _INSTRUCTIONAPI_DEBUG_ +#define _INSTRUCTIONAPI_DEBUG_ + +#include +#include +#include +#include "compiler_annotations.h" + +namespace Dyninst { +namespace InstructionAPI { + extern int INSTRUCTION_EXPORT decoding_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); + extern int dyn_debug_decoding; + extern int dyn_debug_initialized; + +#define decoding_cerr if (dyn_debug_decoding) cerr + +#define dyn_debug_printf(debug_sys, ...) do { if(!dyn_debug_initialized || dyn_debug_##debug_sys) debug_sys##_printf_int(__VA_ARGS__); } while(0) + +#define decoding_printf(...) dyn_debug_printf(decoding, __VA_ARGS__) +} +} +#endif diff --git a/parseAPI/src/IA_IAPI.C b/parseAPI/src/IA_IAPI.C index 948be3001f..fca705a7a7 100644 --- a/parseAPI/src/IA_IAPI.C +++ b/parseAPI/src/IA_IAPI.C @@ -121,8 +121,7 @@ IA_IAPI* IA_IAPI::makePlatformIA_IAPI(Architecture arch, case Arch_aarch64: return new IA_aarch64(dec_, where_, o, r, isrc, curBlk_); case Arch_amdgpu_vega: - - return new IA_amdgpu(dec_, where_, o, r, isrc, curBlk_); + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: return new IA_amdgpu(dec_, where_, o, r, isrc, curBlk_); @@ -146,6 +145,7 @@ void IA_IAPI::initASTs() framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64))); framePtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_aarch64))); framePtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_vega))); + framePtr[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_gfx908))); framePtr[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_cdna2))); } if(stackPtr.empty()) @@ -156,6 +156,7 @@ void IA_IAPI::initASTs() stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64))); stackPtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_aarch64))); stackPtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_vega))); + stackPtr[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_gfx908))); stackPtr[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_cdna2))); } if(thePC.empty()) @@ -166,6 +167,7 @@ void IA_IAPI::initASTs() thePC[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc64))); thePC[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_aarch64))); thePC[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_vega))); + thePC[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_gfx908))); thePC[Arch_amdgpu_cdna2] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_cdna2))); } ANNOTATE_HAPPENS_BEFORE(&IA_IAPI::ptrInit); diff --git a/parseAPI/src/IA_amdgpu.C b/parseAPI/src/IA_amdgpu.C index 463fe7f9c7..26f1cda31e 100644 --- a/parseAPI/src/IA_amdgpu.C +++ b/parseAPI/src/IA_amdgpu.C @@ -74,7 +74,7 @@ bool IA_amdgpu::isNop() const { Instruction ci = curInsn(); auto id = ci.getOperation().getID(); - if(id == amdgpu_op_s_nop || id == amdgpu_cdna2_op_S_NOP ) + if(id == amdgpu_op_s_nop || id == amdgpu_gfx908_op_S_NOP || id == amdgpu_cdna2_op_S_NOP ) return true; return false; } diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index 14fdb2b823..4ea5891198 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -1767,6 +1767,13 @@ Parser::parse_frame_one_iteration(ParseFrame &frame, bool recursive) { // this is special treatment for non-returning instruction // examples are amdgpu_op_s_endpgm and amddgpu_op_s_endpgm_saved //cout << "calling endblock for non-returning instruction " << std::hex <getAddr() << endl; + // + + + parsing_printf("[%s:%d] gpu exit insn 0x%lx: %s \n", + FILE__,__LINE__,curAddr, ah->getInstruction().format().c_str() ); + + end_block(cur,ahPtr); break; } diff --git a/parseAPI/src/SymbolicExpression.C b/parseAPI/src/SymbolicExpression.C index b9f556f28a..f22373a4be 100644 --- a/parseAPI/src/SymbolicExpression.C +++ b/parseAPI/src/SymbolicExpression.C @@ -423,6 +423,7 @@ Address SymbolicExpression::PCValue(Address cur, size_t insnSize, Architecture a case Arch_x86: case Arch_x86_64: case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: return cur + insnSize; case Arch_aarch64: diff --git a/proccontrol/src/process.C b/proccontrol/src/process.C index 8b68f265ea..81f753731e 100644 --- a/proccontrol/src/process.C +++ b/proccontrol/src/process.C @@ -1934,6 +1934,7 @@ int int_process::getAddressWidth() case Arch_intelGen9: return 8; case Arch_amdgpu_vega: // according to the vega architecture, there are 32/64 address mode + case Arch_amdgpu_gfx908: case Arch_amdgpu_cdna2: return 8; case Arch_none: From 63d83f00b0bc43efe05e5f00d7d84786236c31c5 Mon Sep 17 00:00:00 2001 From: Hsuan-Heng Wu Date: Tue, 5 Jul 2022 21:05:36 -0500 Subject: [PATCH 164/505] fix compiler warnings for unused parameter and unused variable for gfx908 --- .../gfx908/amdgpu_gfx908_decoder_impl.C | 1 - .../src/AMDGPU/gfx908/decodeOperands.C | 82 +++++++++---------- .../src/AMDGPU/gfx908/decodeOperands.h | 82 +++++++++---------- 3 files changed, 82 insertions(+), 83 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C index 8727c7a553..4fab484900 100644 --- a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C @@ -1989,7 +1989,6 @@ void InstructionDecoder_amdgpu_gfx908::decodeENC_MIMG(){ } void InstructionDecoder_amdgpu_gfx908::decodeENC_EXP(){ insn_size = 8; - layout_ENC_EXP & layout = insn_layout.ENC_EXP; } void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT(){ insn_size = 8; diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C index 0f85a19260..46eae153ae 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -1,4 +1,4 @@ -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); @@ -259,7 +259,7 @@ case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::attr0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::attr1,0,opr_size); @@ -297,20 +297,20 @@ case 32 : return makeRegisterExpression(amdgpu_gfx908::attr32,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_all,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::p10,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::p20,0,opr_size); @@ -318,13 +318,13 @@ case 2 : return makeRegisterExpression(amdgpu_gfx908::p0,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PC(uint64_t input, uint32_t ){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::pc_all); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -456,20 +456,20 @@ case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size){ switch(input){ case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size){ switch(input){ case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -576,7 +576,7 @@ case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SMEM_OFFSET(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -706,7 +706,7 @@ case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -1194,7 +1194,7 @@ case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); @@ -1455,7 +1455,7 @@ case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size){ switch(input){ case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); @@ -1806,7 +1806,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -2293,7 +2293,7 @@ case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -2780,7 +2780,7 @@ case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_siz default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -3266,7 +3266,7 @@ case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); @@ -3527,7 +3527,7 @@ case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); @@ -4044,7 +4044,7 @@ case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -4173,7 +4173,7 @@ case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -4300,7 +4300,7 @@ case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -4531,7 +4531,7 @@ case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t ){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -4600,7 +4600,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_INLINES(uint64_t input, uint32_t ){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -4695,7 +4695,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -4889,7 +4889,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); @@ -5119,7 +5119,7 @@ case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size){ switch(input){ case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); @@ -5128,25 +5128,25 @@ case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_ default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size){ switch(input){ case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LDS(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t opr_size){ switch(input){ case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size){ switch(input){ case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -5249,25 +5249,25 @@ case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size){ switch(input){ case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size){ switch(input){ case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size){ switch(input){ case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::mrt0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::mrt1,0,opr_size); @@ -5318,7 +5318,7 @@ case 63 : return makeRegisterExpression(amdgpu_gfx908::param31,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TRAP(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TRAP(uint64_t input, uint32_t opr_size){ switch(input){ case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); @@ -5339,20 +5339,20 @@ case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC(uint64_t input, uint32_t ){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::vcc); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); @@ -5613,7 +5613,7 @@ case 255 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size){ switch(input){ case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); @@ -5875,7 +5875,7 @@ case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_XNACK_MASK_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h index 9aed56c56f..82faf3a7cc 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h @@ -1,41 +1,41 @@ -Expression::Ptr decodeOPR_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_ATTR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_PARAM(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_PC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_M0(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_TGT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_TRAP(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size ); From 656c7368a9d7ff8100b211527f14bcd8d573c94b Mon Sep 17 00:00:00 2001 From: Hsuan-Heng Wu Date: Tue, 5 Jul 2022 21:10:08 -0500 Subject: [PATCH 165/505] fix compiler warning for unused parameter and unused variable for cdna2 --- .../src/AMDGPU/cdna2/decodeOperands.C | 82 +++++++++---------- .../src/AMDGPU/cdna2/decodeOperands.h | 82 +++++++++---------- 2 files changed, 82 insertions(+), 82 deletions(-) diff --git a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C index a27ced6083..429cab0b8a 100644 --- a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.C @@ -1,4 +1,4 @@ -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 512 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); case 513 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); @@ -259,7 +259,7 @@ case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ATTR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_ATTR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::attr0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::attr1,0,opr_size); @@ -297,20 +297,20 @@ case 32 : return makeRegisterExpression(amdgpu_cdna2::attr32,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_all,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 102 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_lo,0,opr_size); case 103 : return makeRegisterExpression(amdgpu_cdna2::flat_scratch_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PARAM(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PARAM(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::p10,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::p20,0,opr_size); @@ -318,13 +318,13 @@ case 2 : return makeRegisterExpression(amdgpu_cdna2::p0,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input,uint32_t){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_PC(uint64_t input, uint32_t ){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::pc_all); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -456,20 +456,20 @@ case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_EXEC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size){ switch(input){ case 126 : return makeRegisterExpression(amdgpu_cdna2::exec_lo,0,opr_size); case 127 : return makeRegisterExpression(amdgpu_cdna2::exec_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_M0(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size){ switch(input){ case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -576,7 +576,7 @@ case 101 : return makeRegisterExpression(amdgpu_cdna2::s101,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SMEM_OFFSET(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -706,7 +706,7 @@ case 124 : return makeRegisterExpression(amdgpu_cdna2::m0,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -1193,7 +1193,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 768 : return makeRegisterExpression(amdgpu_cdna2::acc0,0,opr_size); case 769 : return makeRegisterExpression(amdgpu_cdna2::acc1,0,opr_size); @@ -1454,7 +1454,7 @@ case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLDS(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -1941,7 +1941,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -2427,7 +2427,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_SIMPLE(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -2913,7 +2913,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -3174,7 +3174,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -3691,7 +3691,7 @@ case 1023 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -4298,7 +4298,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -4427,7 +4427,7 @@ case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG_NOVCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -4554,7 +4554,7 @@ case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -4785,7 +4785,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input,uint32_t){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t ){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -4854,7 +4854,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input,uint32_t){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_INLINES(uint64_t input, uint32_t ){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -4949,7 +4949,7 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_LANESEL(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -5143,7 +5143,7 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::s0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::s1,0,opr_size); @@ -5373,7 +5373,7 @@ case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id, default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size){ switch(input){ case 235 : return makeRegisterExpression(amdgpu_cdna2::src_shared_base,0,opr_size); case 236 : return makeRegisterExpression(amdgpu_cdna2::src_shared_limit,0,opr_size); @@ -5382,19 +5382,19 @@ case 238 : return makeRegisterExpression(amdgpu_cdna2::src_private_limit,0,opr_s default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size){ switch(input){ case 252 : return makeRegisterExpression(amdgpu_cdna2::src_execz,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size){ switch(input){ case 255 : return makeRegisterExpression(amdgpu_cdna2::src_literal,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -5497,25 +5497,25 @@ case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id, default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size){ switch(input){ case 239 : return makeRegisterExpression(amdgpu_cdna2::src_pops_exiting_wave_id,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size){ switch(input){ case 253 : return makeRegisterExpression(amdgpu_cdna2::src_scc,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size){ switch(input){ case 251 : return makeRegisterExpression(amdgpu_cdna2::src_vccz,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TGT(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TGT(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::mrt0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::mrt1,0,opr_size); @@ -5566,7 +5566,7 @@ case 63 : return makeRegisterExpression(amdgpu_cdna2::param31,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TRAP(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_TRAP(uint64_t input, uint32_t opr_size){ switch(input){ case 108 : return makeRegisterExpression(amdgpu_cdna2::ttmp0,0,opr_size); case 109 : return makeRegisterExpression(amdgpu_cdna2::ttmp1,0,opr_size); @@ -5587,20 +5587,20 @@ case 123 : return makeRegisterExpression(amdgpu_cdna2::ttmp15,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input,uint32_t){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC(uint64_t input, uint32_t ){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::vcc); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 106 : return makeRegisterExpression(amdgpu_cdna2::vcc_lo,0,opr_size); case 107 : return makeRegisterExpression(amdgpu_cdna2::vcc_hi,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -5861,7 +5861,7 @@ case 255 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 1 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -6378,7 +6378,7 @@ case 767 : return makeRegisterExpression(amdgpu_cdna2::acc255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_LDS(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size){ switch(input){ case 256 : return makeRegisterExpression(amdgpu_cdna2::v0,0,opr_size); case 257 : return makeRegisterExpression(amdgpu_cdna2::v1,0,opr_size); @@ -6639,7 +6639,7 @@ case 511 : return makeRegisterExpression(amdgpu_cdna2::v255,0,opr_size); default: return makeRegisterExpression(amdgpu_cdna2::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_XNACK_MASK_LOHI(uint64_t input,uint32_t opr_size ){ +Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size){ switch(input){ case 104 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_lo,0,opr_size); case 105 : return makeRegisterExpression(amdgpu_cdna2::xnack_mask_hi,0,opr_size); diff --git a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h index 8533c5a99a..175b97822b 100644 --- a/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h +++ b/instructionAPI/src/AMDGPU/cdna2/decodeOperands.h @@ -1,41 +1,41 @@ -Expression::Ptr decodeOPR_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_ATTR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_PARAM(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_PC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_M0(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_TGT(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_TRAP(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR_OR_ACCVGPR(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input ,uint32_t opr_size ); -Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input ,uint32_t opr_size ); +Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size ); From 1701ab375200a37861495a24ed30f679ae36bf25 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Wed, 20 Jul 2022 08:19:33 -0500 Subject: [PATCH 166/505] updated based on new xml-isa drop --- instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index 21d2ad3ffd..634672251f 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -9907,8 +9907,8 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); break; case 480:// V_DIV_SCALE_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); @@ -9916,8 +9916,8 @@ break; case 481:// V_DIV_SCALE_F64 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); From 00e9c17818ebec948f303e8a679b7aa434f7aca4 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 6 Sep 2022 18:26:35 -0500 Subject: [PATCH 167/505] fix decoding of operand for v_div_scale based on 220804 isa drop --- instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index 634672251f..21d2ad3ffd 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -9907,8 +9907,8 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); break; case 480:// V_DIV_SCALE_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); @@ -9916,8 +9916,8 @@ break; case 481:// V_DIV_SCALE_F64 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); From bbbcbc2617e7f0fe2c6f2be1d7fff486e6089d6a Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 6 Sep 2022 18:36:21 -0500 Subject: [PATCH 168/505] revert changes related to adding debug interface --- instructionAPI/CMakeLists.txt | 1 - .../gfx908/InstructionDecoder-amdgpu-gfx908.C | 4 - instructionAPI/src/debug_decode.C | 77 ------------------- instructionAPI/src/debug_decode.h | 52 ------------- 4 files changed, 134 deletions(-) delete mode 100644 instructionAPI/src/debug_decode.C delete mode 100644 instructionAPI/src/debug_decode.h diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index 337b3f903c..64940c4324 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -6,7 +6,6 @@ include_directories( ${PROJECT_SOURCE_DIR}/instructionAPI/src/AMDGPU/vega) set(SRC_LIST - src/debug_decode.C src/Instruction.C src/InstructionAST.C src/Operation.C diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C index 852743bda0..cc2d971629 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -30,7 +30,6 @@ #include "Ternary.h" #include "InstructionDecoder-amdgpu-gfx908.h" -#include "debug_decode.h" namespace Dyninst { namespace InstructionAPI { @@ -216,7 +215,6 @@ namespace Dyninst { imm_at_64 = get32bit(b,8); insn_long = ( ((uint64_t) insn_high) << 32) | insn; - decoding_printf("[%s:%d]: setting up insnword, bits = %llu\n",FILE__,__LINE__, insn_long ); } @@ -239,7 +237,6 @@ namespace Dyninst { //cout << "Is Branch Instruction !! , name = " << insn_in_progress -> getOperation().mnemonic << endl; //std::mem_fun(decode_lookup_table[instr_family])(this); } - decoding_printf("[%s:%d]: decoded instruction = %s\n",FILE__,__LINE__, insn_in_progress->getOperation().mnemonic.c_str() ); b.start += insn_in_progress->size(); return *insn_in_progress; } @@ -249,7 +246,6 @@ namespace Dyninst { InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); setupInsnWord(b); mainDecode(); - decoding_printf("[%s:%d]: decoded instruction = %s\n",FILE__,__LINE__, insn_in_progress->getOperation().mnemonic.c_str() ); cout.clear(); Instruction* iptr = const_cast(insn_to_complete); *iptr = *(insn_in_progress.get()); diff --git a/instructionAPI/src/debug_decode.C b/instructionAPI/src/debug_decode.C deleted file mode 100644 index 79a948df4e..0000000000 --- a/instructionAPI/src/debug_decode.C +++ /dev/null @@ -1,77 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include - -#include "debug_decode.h" - -using namespace Dyninst::InstructionAPI; - -int Dyninst::InstructionAPI::dyn_debug_decoding = 0; -int Dyninst::InstructionAPI::dyn_debug_initialized = 0; - -#if defined(_OPENMP) -#include -#endif - -dyn_tls FILE* log_file = NULL; - -int Dyninst::InstructionAPI::decoding_printf_int(const char *format, ...); -int Dyninst::InstructionAPI::decoding_printf_int(const char *format, ...) -{ - if(!dyn_debug_initialized) { - if(getenv("DYNINST_DEBUG_DECODING")) - dyn_debug_decoding = 1; - dyn_debug_initialized = 1; - } - - if(!dyn_debug_decoding) return 0; - if(NULL == format) return -1; - if (log_file == NULL) { - char filename[128]; -#if defined(_OPENMP) - snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_DECODING"), omp_get_thread_num()); -#else - snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_DECODING"), 0); -#endif - - log_file = fopen(filename, "w"); - } - - va_list va; - va_start(va,format); - int ret = vfprintf(log_file, format, va); - fflush(log_file); - va_end(va); - - return ret; -} - diff --git a/instructionAPI/src/debug_decode.h b/instructionAPI/src/debug_decode.h deleted file mode 100644 index 770936550d..0000000000 --- a/instructionAPI/src/debug_decode.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifndef _INSTRUCTIONAPI_DEBUG_ -#define _INSTRUCTIONAPI_DEBUG_ - -#include -#include -#include -#include "compiler_annotations.h" - -namespace Dyninst { -namespace InstructionAPI { - extern int INSTRUCTION_EXPORT decoding_printf_int(const char *format, ...) - DYNINST_PRINTF_ANNOTATION(1, 2); - extern int dyn_debug_decoding; - extern int dyn_debug_initialized; - -#define decoding_cerr if (dyn_debug_decoding) cerr - -#define dyn_debug_printf(debug_sys, ...) do { if(!dyn_debug_initialized || dyn_debug_##debug_sys) debug_sys##_printf_int(__VA_ARGS__); } while(0) - -#define decoding_printf(...) dyn_debug_printf(decoding, __VA_ARGS__) -} -} -#endif From 65d163b8528d88d4928e9d88d5c30a3d1f844d5f Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Fri, 21 Oct 2022 15:59:33 -0500 Subject: [PATCH 169/505] compress finalizeOperands.C by combining cases with same decoding logic --- .../src/AMDGPU/gfx908/finalizeOperands.C | 13171 +++------------- 1 file changed, 2084 insertions(+), 11087 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index 21d2ad3ffd..d0b6027fd1 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -1,11463 +1,2460 @@ void InstructionDecoder_amdgpu_gfx908::finalizeENC_DSOperands(){ layout_ENC_DS & layout = insn_layout.ENC_DS; switch(layout.OP){ -case 0:// DS_ADD_U32 +case 0:case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 13:case 18:case 19:case 21:case 30:case 31:case 84:case 85: +//DS_ADD_U32,DS_SUB_U32,DS_RSUB_U32,DS_INC_U32,DS_DEC_U32,DS_MIN_I32,DS_MAX_I32,DS_MIN_U32,DS_MAX_U32,DS_AND_B32,DS_OR_B32,DS_XOR_B32,DS_WRITE_B32,DS_MIN_F32,DS_MAX_F32,DS_ADD_F32,DS_WRITE_B8,DS_WRITE_B16,DS_WRITE_B8_D16_HI,DS_WRITE_B16_D16_HI insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); break; -case 1:// DS_SUB_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 2:// DS_RSUB_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 3:// DS_INC_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 4:// DS_DEC_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 5:// DS_MIN_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 6:// DS_MAX_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 7:// DS_MIN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 8:// DS_MAX_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 9:// DS_AND_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 10:// DS_OR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 11:// DS_XOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 12:// DS_MSKOR_B32 +case 12:case 14:case 15:case 16:case 17: +//DS_MSKOR_B32,DS_WRITE2_B32,DS_WRITE2ST64_B32,DS_CMPST_B32,DS_CMPST_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); break; -case 13:// DS_WRITE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 20: +//DS_NOP break; -case 14:// DS_WRITE2_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 29:case 153:case 155:case 157: +//DS_WRITE_ADDTID_B32,DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 15:// DS_WRITE2ST64_B32 +case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 45:case 50:case 51:case 53:case 62:case 63: +//DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32,DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32,DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32,DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32,DS_PERMUTE_B32,DS_BPERMUTE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); break; -case 16:// DS_CMPST_B32 +case 44:case 48:case 49:case 52: +//DS_MSKOR_RTN_B32,DS_CMPST_RTN_B32,DS_CMPST_RTN_F32,DS_WRAP_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); break; -case 17:// DS_CMPST_F32 +case 46:case 47: +//DS_WRXCHG2_RTN_B32,DS_WRXCHG2ST64_RTN_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); break; -case 18:// DS_MIN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 19:// DS_MAX_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 20:// DS_NOP -break; -case 21:// DS_ADD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 29:// DS_WRITE_ADDTID_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 30:// DS_WRITE_B8 +case 54:case 57:case 58:case 59:case 60:case 61:case 86:case 87:case 88:case 89:case 90:case 91: +//DS_READ_B32,DS_READ_I8,DS_READ_U8,DS_READ_I16,DS_READ_U16,DS_SWIZZLE_B32,DS_READ_U8_D16,DS_READ_U8_D16_HI,DS_READ_I8_D16,DS_READ_I8_D16_HI,DS_READ_U16_D16,DS_READ_U16_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); break; -case 31:// DS_WRITE_B16 +case 55:case 56:case 118: +//DS_READ2_B32,DS_READ2ST64_B32,DS_READ_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); break; -case 32:// DS_ADD_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 77:case 82:case 83: +//DS_ADD_U64,DS_SUB_U64,DS_RSUB_U64,DS_INC_U64,DS_DEC_U64,DS_MIN_I64,DS_MAX_I64,DS_MIN_U64,DS_MAX_U64,DS_AND_B64,DS_OR_B64,DS_XOR_B64,DS_WRITE_B64,DS_MIN_F64,DS_MAX_F64 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); break; -case 33:// DS_SUB_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 76:case 78:case 79:case 80:case 81: +//DS_MSKOR_B64,DS_WRITE2_B64,DS_WRITE2ST64_B64,DS_CMPST_B64,DS_CMPST_F64 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); break; -case 34:// DS_RSUB_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 109:case 114:case 115:case 126: +//DS_ADD_RTN_U64,DS_SUB_RTN_U64,DS_RSUB_RTN_U64,DS_INC_RTN_U64,DS_DEC_RTN_U64,DS_MIN_RTN_I64,DS_MAX_RTN_I64,DS_MIN_RTN_U64,DS_MAX_RTN_U64,DS_AND_RTN_B64,DS_OR_RTN_B64,DS_XOR_RTN_B64,DS_WRXCHG_RTN_B64,DS_MIN_RTN_F64,DS_MAX_RTN_F64,DS_CONDXCHG32_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); break; -case 35:// DS_INC_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 108:case 112:case 113: +//DS_MSKOR_RTN_B64,DS_CMPST_RTN_B64,DS_CMPST_RTN_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); break; -case 36:// DS_DEC_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 110:case 111: +//DS_WRXCHG2_RTN_B64,DS_WRXCHG2ST64_RTN_B64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); break; -case 37:// DS_MIN_RTN_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 119:case 120:case 255: +//DS_READ2_B64,DS_READ2ST64_B64,DS_READ_B128 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); break; -case 38:// DS_MAX_RTN_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 128:case 129:case 130:case 131:case 132:case 133:case 134:case 135:case 136:case 137:case 138:case 139:case 141:case 146:case 147:case 149:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 205:case 210:case 211: +//DS_ADD_SRC2_U32,DS_SUB_SRC2_U32,DS_RSUB_SRC2_U32,DS_INC_SRC2_U32,DS_DEC_SRC2_U32,DS_MIN_SRC2_I32,DS_MAX_SRC2_I32,DS_MIN_SRC2_U32,DS_MAX_SRC2_U32,DS_AND_SRC2_B32,DS_OR_SRC2_B32,DS_XOR_SRC2_B32,DS_WRITE_SRC2_B32,DS_MIN_SRC2_F32,DS_MAX_SRC2_F32,DS_ADD_SRC2_F32,DS_ADD_SRC2_U64,DS_SUB_SRC2_U64,DS_RSUB_SRC2_U64,DS_INC_SRC2_U64,DS_DEC_SRC2_U64,DS_MIN_SRC2_I64,DS_MAX_SRC2_I64,DS_MIN_SRC2_U64,DS_MAX_SRC2_U64,DS_AND_SRC2_B64,DS_OR_SRC2_B64,DS_XOR_SRC2_B64,DS_WRITE_SRC2_B64,DS_MIN_SRC2_F64,DS_MAX_SRC2_F64 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); break; -case 39:// DS_MIN_RTN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 152:case 154:case 156: +//DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 40:// DS_MAX_RTN_U32 +case 182:case 189:case 190: +//DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 41:// DS_AND_RTN_B32 +case 191: +//DS_ORDERED_COUNT insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 42:// DS_OR_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 222: +//DS_WRITE_B96 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); break; -case 43:// DS_XOR_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 223: +//DS_WRITE_B128 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+3,32),true,false); break; -case 44:// DS_MSKOR_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +case 254: +//DS_READ_B96 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); break; -case 45:// DS_WRXCHG_RTN_B32 +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLATOperands(){ +layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; +switch(layout.OP){ +case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: +//FLAT_LOAD_UBYTE,FLAT_LOAD_SBYTE,FLAT_LOAD_USHORT,FLAT_LOAD_SSHORT,FLAT_LOAD_DWORD,FLAT_LOAD_UBYTE_D16,FLAT_LOAD_UBYTE_D16_HI,FLAT_LOAD_SBYTE_D16,FLAT_LOAD_SBYTE_D16_HI,FLAT_LOAD_SHORT_D16,FLAT_LOAD_SHORT_D16_HI insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 46:// DS_WRXCHG2_RTN_B32 +case 21: +//FLAT_LOAD_DWORDX2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 47:// DS_WRXCHG2ST64_RTN_B32 +case 22: +//FLAT_LOAD_DWORDX3 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); -break; -case 48:// DS_CMPST_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 49:// DS_CMPST_RTN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +case 23: +//FLAT_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 50:// DS_MIN_RTN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 24:case 25:case 26:case 27:case 28: +//FLAT_STORE_BYTE,FLAT_STORE_BYTE_D16_HI,FLAT_STORE_SHORT,FLAT_STORE_SHORT_D16_HI,FLAT_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 51:// DS_MAX_RTN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 29: +//FLAT_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 52:// DS_WRAP_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +case 30: +//FLAT_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 53:// DS_ADD_RTN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 31: +//FLAT_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 54:// DS_READ_B32 +case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76: +//FLAT_ATOMIC_SWAP,FLAT_ATOMIC_ADD,FLAT_ATOMIC_SUB,FLAT_ATOMIC_SMIN,FLAT_ATOMIC_UMIN,FLAT_ATOMIC_SMAX,FLAT_ATOMIC_UMAX,FLAT_ATOMIC_AND,FLAT_ATOMIC_OR,FLAT_ATOMIC_XOR,FLAT_ATOMIC_INC,FLAT_ATOMIC_DEC insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 55:// DS_READ2_B32 +case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: +//FLAT_ATOMIC_CMPSWAP,FLAT_ATOMIC_SWAP_X2,FLAT_ATOMIC_ADD_X2,FLAT_ATOMIC_SUB_X2,FLAT_ATOMIC_SMIN_X2,FLAT_ATOMIC_UMIN_X2,FLAT_ATOMIC_SMAX_X2,FLAT_ATOMIC_UMAX_X2,FLAT_ATOMIC_AND_X2,FLAT_ATOMIC_OR_X2,FLAT_ATOMIC_XOR_X2,FLAT_ATOMIC_INC_X2,FLAT_ATOMIC_DEC_X2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 56:// DS_READ2ST64_B32 +case 97: +//FLAT_ATOMIC_CMPSWAP_X2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 57:// DS_READ_I8 +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_GLBLOperands(){ +layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; +switch(layout.OP){ +case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: +//GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT,GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI,GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16,GLOBAL_LOAD_SHORT_D16_HI insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 58:// DS_READ_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 21: +//GLOBAL_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 59:// DS_READ_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 60:// DS_READ_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 61:// DS_SWIZZLE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 62:// DS_PERMUTE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 63:// DS_BPERMUTE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 64:// DS_ADD_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 65:// DS_SUB_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 66:// DS_RSUB_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 67:// DS_INC_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 68:// DS_DEC_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 69:// DS_MIN_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 70:// DS_MAX_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 71:// DS_MIN_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 72:// DS_MAX_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 73:// DS_AND_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 74:// DS_OR_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 75:// DS_XOR_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 76:// DS_MSKOR_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 77:// DS_WRITE_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 78:// DS_WRITE2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 79:// DS_WRITE2ST64_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 80:// DS_CMPST_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 81:// DS_CMPST_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 82:// DS_MIN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 83:// DS_MAX_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 84:// DS_WRITE_B8_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -break; -case 85:// DS_WRITE_B16_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +case 22: +//GLOBAL_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 86:// DS_READ_U8_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 23: +//GLOBAL_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 87:// DS_READ_U8_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 24:case 25:case 26:case 27:case 28: +//GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT,GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 88:// DS_READ_I8_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 29: +//GLOBAL_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 89:// DS_READ_I8_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 30: +//GLOBAL_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 90:// DS_READ_U16_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +case 31: +//GLOBAL_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 91:// DS_READ_U16_D16_HI +case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78: +//GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN,GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND,GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC,GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 96:// DS_ADD_RTN_U64 +case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: +//GLOBAL_ATOMIC_CMPSWAP,GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2,GLOBAL_ATOMIC_SUB_X2,GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2,GLOBAL_ATOMIC_SMAX_X2,GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2,GLOBAL_ATOMIC_OR_X2,GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2,GLOBAL_ATOMIC_DEC_X2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 97:// DS_SUB_RTN_U64 +case 97: +//GLOBAL_ATOMIC_CMPSWAP_X2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +break; +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_SCRATCHOperands(){ +layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; +switch(layout.OP){ +case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: +//SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT,SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI,SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16,SCRATCH_LOAD_SHORT_D16_HI +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 98:// DS_RSUB_RTN_U64 +case 21: +//SCRATCH_LOAD_DWORDX2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 99:// DS_INC_RTN_U64 +case 22: +//SCRATCH_LOAD_DWORDX3 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 100:// DS_DEC_RTN_U64 +case 23: +//SCRATCH_LOAD_DWORDX4 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 101:// DS_MIN_RTN_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +case 24:case 25:case 26:case 27:case 28: +//SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT,SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 102:// DS_MAX_RTN_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +case 29: +//SCRATCH_STORE_DWORDX2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 103:// DS_MIN_RTN_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +case 30: +//SCRATCH_STORE_DWORDX3 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 104:// DS_MAX_RTN_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +case 31: +//SCRATCH_STORE_DWORDX4 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 105:// DS_AND_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 106:// DS_OR_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 107:// DS_XOR_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 108:// DS_MSKOR_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 109:// DS_WRXCHG_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 110:// DS_WRXCHG2_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 111:// DS_WRXCHG2ST64_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 112:// DS_CMPST_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 113:// DS_CMPST_RTN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); -break; -case 114:// DS_MIN_RTN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 115:// DS_MAX_RTN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 118:// DS_READ_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 119:// DS_READ2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 120:// DS_READ2ST64_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 126:// DS_CONDXCHG32_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -break; -case 128:// DS_ADD_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 129:// DS_SUB_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 130:// DS_RSUB_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 131:// DS_INC_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 132:// DS_DEC_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 133:// DS_MIN_SRC2_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 134:// DS_MAX_SRC2_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 135:// DS_MIN_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 136:// DS_MAX_SRC2_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 137:// DS_AND_SRC2_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 138:// DS_OR_SRC2_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 139:// DS_XOR_SRC2_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 141:// DS_WRITE_SRC2_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 146:// DS_MIN_SRC2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 147:// DS_MAX_SRC2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 149:// DS_ADD_SRC2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 152:// DS_GWS_SEMA_RELEASE_ALL -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 153:// DS_GWS_INIT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 154:// DS_GWS_SEMA_V -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 155:// DS_GWS_SEMA_BR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 156:// DS_GWS_SEMA_P -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 157:// DS_GWS_BARRIER -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 182:// DS_READ_ADDTID_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 189:// DS_CONSUME -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 190:// DS_APPEND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 191:// DS_ORDERED_COUNT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 192:// DS_ADD_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 193:// DS_SUB_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 194:// DS_RSUB_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 195:// DS_INC_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 196:// DS_DEC_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 197:// DS_MIN_SRC2_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 198:// DS_MAX_SRC2_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 199:// DS_MIN_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 200:// DS_MAX_SRC2_U64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 201:// DS_AND_SRC2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 202:// DS_OR_SRC2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 203:// DS_XOR_SRC2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 205:// DS_WRITE_SRC2_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 210:// DS_MIN_SRC2_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 211:// DS_MAX_SRC2_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 222:// DS_WRITE_B96 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); -break; -case 223:// DS_WRITE_B128 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+3,32),true,false); -break; -case 254:// DS_READ_B96 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -case 255:// DS_READ_B128 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLATOperands(){ -layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; -switch(layout.OP){ -case 16:// FLAT_LOAD_UBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 17:// FLAT_LOAD_SBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 18:// FLAT_LOAD_USHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 19:// FLAT_LOAD_SSHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 20:// FLAT_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 21:// FLAT_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 22:// FLAT_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 23:// FLAT_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 24:// FLAT_STORE_BYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 25:// FLAT_STORE_BYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 26:// FLAT_STORE_SHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 27:// FLAT_STORE_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 28:// FLAT_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 29:// FLAT_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 30:// FLAT_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 31:// FLAT_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 32:// FLAT_LOAD_UBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 33:// FLAT_LOAD_UBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 34:// FLAT_LOAD_SBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 35:// FLAT_LOAD_SBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 36:// FLAT_LOAD_SHORT_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 37:// FLAT_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 64:// FLAT_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 65:// FLAT_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 66:// FLAT_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 67:// FLAT_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 68:// FLAT_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 69:// FLAT_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 70:// FLAT_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 71:// FLAT_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 72:// FLAT_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 73:// FLAT_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 74:// FLAT_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 75:// FLAT_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 76:// FLAT_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 96:// FLAT_ATOMIC_SWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 97:// FLAT_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 98:// FLAT_ATOMIC_ADD_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 99:// FLAT_ATOMIC_SUB_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 100:// FLAT_ATOMIC_SMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 101:// FLAT_ATOMIC_UMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 102:// FLAT_ATOMIC_SMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 103:// FLAT_ATOMIC_UMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 104:// FLAT_ATOMIC_AND_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 105:// FLAT_ATOMIC_OR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 106:// FLAT_ATOMIC_XOR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 107:// FLAT_ATOMIC_INC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 108:// FLAT_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_GLBLOperands(){ -layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; -switch(layout.OP){ -case 16:// GLOBAL_LOAD_UBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 17:// GLOBAL_LOAD_SBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 18:// GLOBAL_LOAD_USHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 19:// GLOBAL_LOAD_SSHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 20:// GLOBAL_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 21:// GLOBAL_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 22:// GLOBAL_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 23:// GLOBAL_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 24:// GLOBAL_STORE_BYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 25:// GLOBAL_STORE_BYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 26:// GLOBAL_STORE_SHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 27:// GLOBAL_STORE_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 28:// GLOBAL_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 29:// GLOBAL_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 30:// GLOBAL_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 31:// GLOBAL_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 32:// GLOBAL_LOAD_UBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 33:// GLOBAL_LOAD_UBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 34:// GLOBAL_LOAD_SBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 35:// GLOBAL_LOAD_SBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 36:// GLOBAL_LOAD_SHORT_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 37:// GLOBAL_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 64:// GLOBAL_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 65:// GLOBAL_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 66:// GLOBAL_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 67:// GLOBAL_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 68:// GLOBAL_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 69:// GLOBAL_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 70:// GLOBAL_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 71:// GLOBAL_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 72:// GLOBAL_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 73:// GLOBAL_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 74:// GLOBAL_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 75:// GLOBAL_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 76:// GLOBAL_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 77:// GLOBAL_ATOMIC_ADD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 78:// GLOBAL_ATOMIC_PK_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 96:// GLOBAL_ATOMIC_SWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 97:// GLOBAL_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 98:// GLOBAL_ATOMIC_ADD_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 99:// GLOBAL_ATOMIC_SUB_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 100:// GLOBAL_ATOMIC_SMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 101:// GLOBAL_ATOMIC_UMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 102:// GLOBAL_ATOMIC_SMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 103:// GLOBAL_ATOMIC_UMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 104:// GLOBAL_ATOMIC_AND_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 105:// GLOBAL_ATOMIC_OR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 106:// GLOBAL_ATOMIC_XOR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 107:// GLOBAL_ATOMIC_INC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 108:// GLOBAL_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_SCRATCHOperands(){ -layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; -switch(layout.OP){ -case 16:// SCRATCH_LOAD_UBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 17:// SCRATCH_LOAD_SBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 18:// SCRATCH_LOAD_USHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 19:// SCRATCH_LOAD_SSHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 20:// SCRATCH_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 21:// SCRATCH_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 22:// SCRATCH_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 23:// SCRATCH_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 24:// SCRATCH_STORE_BYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 25:// SCRATCH_STORE_BYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 26:// SCRATCH_STORE_SHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 27:// SCRATCH_STORE_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 28:// SCRATCH_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 29:// SCRATCH_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 30:// SCRATCH_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 31:// SCRATCH_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 32:// SCRATCH_LOAD_UBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 33:// SCRATCH_LOAD_UBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 34:// SCRATCH_LOAD_SBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 35:// SCRATCH_LOAD_SBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 36:// SCRATCH_LOAD_SHORT_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 37:// SCRATCH_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_MIMGOperands(){ -layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; -switch(layout.OP){ -case 0:// IMAGE_LOAD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 1:// IMAGE_LOAD_MIP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 2:// IMAGE_LOAD_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 3:// IMAGE_LOAD_PCK_SGN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 4:// IMAGE_LOAD_MIP_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 5:// IMAGE_LOAD_MIP_PCK_SGN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 8:// IMAGE_STORE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 9:// IMAGE_STORE_MIP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 10:// IMAGE_STORE_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 11:// IMAGE_STORE_MIP_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 14:// IMAGE_GET_RESINFO -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 16:// IMAGE_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 17:// IMAGE_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 18:// IMAGE_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 19:// IMAGE_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 20:// IMAGE_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 21:// IMAGE_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 22:// IMAGE_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 23:// IMAGE_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 24:// IMAGE_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 25:// IMAGE_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 26:// IMAGE_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 27:// IMAGE_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 28:// IMAGE_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -break; -case 32:// IMAGE_SAMPLE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 33:// IMAGE_SAMPLE_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 34:// IMAGE_SAMPLE_D -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 35:// IMAGE_SAMPLE_D_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 36:// IMAGE_SAMPLE_L -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 37:// IMAGE_SAMPLE_B -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 38:// IMAGE_SAMPLE_B_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 39:// IMAGE_SAMPLE_LZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 40:// IMAGE_SAMPLE_C -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 41:// IMAGE_SAMPLE_C_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 42:// IMAGE_SAMPLE_C_D -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 43:// IMAGE_SAMPLE_C_D_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 44:// IMAGE_SAMPLE_C_L -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 45:// IMAGE_SAMPLE_C_B -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 46:// IMAGE_SAMPLE_C_B_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 47:// IMAGE_SAMPLE_C_LZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 48:// IMAGE_SAMPLE_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 49:// IMAGE_SAMPLE_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 50:// IMAGE_SAMPLE_D_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 51:// IMAGE_SAMPLE_D_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 52:// IMAGE_SAMPLE_L_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 53:// IMAGE_SAMPLE_B_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 54:// IMAGE_SAMPLE_B_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 55:// IMAGE_SAMPLE_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 56:// IMAGE_SAMPLE_C_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 57:// IMAGE_SAMPLE_C_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 58:// IMAGE_SAMPLE_C_D_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 59:// IMAGE_SAMPLE_C_D_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 60:// IMAGE_SAMPLE_C_L_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 61:// IMAGE_SAMPLE_C_B_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 62:// IMAGE_SAMPLE_C_B_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 63:// IMAGE_SAMPLE_C_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 64:// IMAGE_GATHER4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 65:// IMAGE_GATHER4_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 66:// IMAGE_GATHER4H -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 68:// IMAGE_GATHER4_L -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 69:// IMAGE_GATHER4_B -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 70:// IMAGE_GATHER4_B_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 71:// IMAGE_GATHER4_LZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 72:// IMAGE_GATHER4_C -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 73:// IMAGE_GATHER4_C_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 74:// IMAGE_GATHER4H_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 75:// IMAGE_GATHER8H_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 76:// IMAGE_GATHER4_C_L -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 77:// IMAGE_GATHER4_C_B -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 78:// IMAGE_GATHER4_C_B_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 79:// IMAGE_GATHER4_C_LZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 80:// IMAGE_GATHER4_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 81:// IMAGE_GATHER4_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 84:// IMAGE_GATHER4_L_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 85:// IMAGE_GATHER4_B_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 86:// IMAGE_GATHER4_B_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 87:// IMAGE_GATHER4_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 88:// IMAGE_GATHER4_C_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 89:// IMAGE_GATHER4_C_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 92:// IMAGE_GATHER4_C_L_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 93:// IMAGE_GATHER4_C_B_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 94:// IMAGE_GATHER4_C_B_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 95:// IMAGE_GATHER4_C_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 96:// IMAGE_GET_LOD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 104:// IMAGE_SAMPLE_CD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 105:// IMAGE_SAMPLE_CD_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 106:// IMAGE_SAMPLE_C_CD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 107:// IMAGE_SAMPLE_C_CD_CL -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 108:// IMAGE_SAMPLE_CD_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 109:// IMAGE_SAMPLE_CD_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 110:// IMAGE_SAMPLE_C_CD_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -case 111:// IMAGE_SAMPLE_C_CD_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_MTBUFOperands(){ -layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; -switch(layout.OP){ -case 0:// TBUFFER_LOAD_FORMAT_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 1:// TBUFFER_LOAD_FORMAT_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 2:// TBUFFER_LOAD_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 3:// TBUFFER_LOAD_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 4:// TBUFFER_STORE_FORMAT_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 5:// TBUFFER_STORE_FORMAT_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 6:// TBUFFER_STORE_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 7:// TBUFFER_STORE_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 8:// TBUFFER_LOAD_FORMAT_D16_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 9:// TBUFFER_LOAD_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 10:// TBUFFER_LOAD_FORMAT_D16_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 11:// TBUFFER_LOAD_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 12:// TBUFFER_STORE_FORMAT_D16_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 13:// TBUFFER_STORE_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 14:// TBUFFER_STORE_FORMAT_D16_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 15:// TBUFFER_STORE_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_MUBUFOperands(){ -layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; -switch(layout.OP){ -case 0:// BUFFER_LOAD_FORMAT_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 1:// BUFFER_LOAD_FORMAT_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 2:// BUFFER_LOAD_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 3:// BUFFER_LOAD_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 4:// BUFFER_STORE_FORMAT_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 5:// BUFFER_STORE_FORMAT_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 6:// BUFFER_STORE_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 7:// BUFFER_STORE_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 8:// BUFFER_LOAD_FORMAT_D16_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 9:// BUFFER_LOAD_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 10:// BUFFER_LOAD_FORMAT_D16_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 11:// BUFFER_LOAD_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 12:// BUFFER_STORE_FORMAT_D16_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 13:// BUFFER_STORE_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 14:// BUFFER_STORE_FORMAT_D16_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 15:// BUFFER_STORE_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 16:// BUFFER_LOAD_UBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 17:// BUFFER_LOAD_SBYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 18:// BUFFER_LOAD_USHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 19:// BUFFER_LOAD_SSHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 20:// BUFFER_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 21:// BUFFER_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 22:// BUFFER_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 23:// BUFFER_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 24:// BUFFER_STORE_BYTE -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 25:// BUFFER_STORE_BYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 26:// BUFFER_STORE_SHORT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 27:// BUFFER_STORE_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 28:// BUFFER_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 29:// BUFFER_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 30:// BUFFER_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 31:// BUFFER_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 32:// BUFFER_LOAD_UBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 33:// BUFFER_LOAD_UBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 34:// BUFFER_LOAD_SBYTE_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 35:// BUFFER_LOAD_SBYTE_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 36:// BUFFER_LOAD_SHORT_D16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 37:// BUFFER_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 38:// BUFFER_LOAD_FORMAT_D16_HI_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 39:// BUFFER_STORE_FORMAT_D16_HI_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 61:// BUFFER_STORE_LDS_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 62:// BUFFER_WBINVL1 -break; -case 63:// BUFFER_WBINVL1_VOL -break; -case 64:// BUFFER_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 65:// BUFFER_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 66:// BUFFER_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 67:// BUFFER_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 68:// BUFFER_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 69:// BUFFER_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 70:// BUFFER_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 71:// BUFFER_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 72:// BUFFER_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 73:// BUFFER_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 74:// BUFFER_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 75:// BUFFER_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 76:// BUFFER_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 77:// BUFFER_ATOMIC_ADD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 78:// BUFFER_ATOMIC_PK_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 96:// BUFFER_ATOMIC_SWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 97:// BUFFER_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 98:// BUFFER_ATOMIC_ADD_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 99:// BUFFER_ATOMIC_SUB_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 100:// BUFFER_ATOMIC_SMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 101:// BUFFER_ATOMIC_UMIN_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 102:// BUFFER_ATOMIC_SMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 103:// BUFFER_ATOMIC_UMAX_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 104:// BUFFER_ATOMIC_AND_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 105:// BUFFER_ATOMIC_OR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 106:// BUFFER_ATOMIC_XOR_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 107:// BUFFER_ATOMIC_INC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -case 108:// BUFFER_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SMEMOperands(){ -layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; -switch(layout.OP){ -case 0:// S_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 1:// S_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 2:// S_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 3:// S_LOAD_DWORDX8 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 4:// S_LOAD_DWORDX16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 5:// S_SCRATCH_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 6:// S_SCRATCH_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 7:// S_SCRATCH_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 8:// S_BUFFER_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 9:// S_BUFFER_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 10:// S_BUFFER_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 11:// S_BUFFER_LOAD_DWORDX8 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 12:// S_BUFFER_LOAD_DWORDX16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 16:// S_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 17:// S_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 18:// S_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 21:// S_SCRATCH_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 22:// S_SCRATCH_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 23:// S_SCRATCH_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 24:// S_BUFFER_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 25:// S_BUFFER_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 26:// S_BUFFER_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 32:// S_DCACHE_INV -break; -case 33:// S_DCACHE_WB -break; -case 34:// S_DCACHE_INV_VOL -break; -case 35:// S_DCACHE_WB_VOL -break; -case 36:// S_MEMTIME -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -break; -case 37:// S_MEMREALTIME -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -break; -case 38:// S_ATC_PROBE -insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 39:// S_ATC_PROBE_BUFFER -insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 40:// S_DCACHE_DISCARD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 41:// S_DCACHE_DISCARD_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 64:// S_BUFFER_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 65:// S_BUFFER_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 66:// S_BUFFER_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 67:// S_BUFFER_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 68:// S_BUFFER_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 69:// S_BUFFER_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 70:// S_BUFFER_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 71:// S_BUFFER_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 72:// S_BUFFER_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 73:// S_BUFFER_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 74:// S_BUFFER_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 75:// S_BUFFER_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 76:// S_BUFFER_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 96:// S_BUFFER_ATOMIC_SWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 97:// S_BUFFER_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 98:// S_BUFFER_ATOMIC_ADD_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 99:// S_BUFFER_ATOMIC_SUB_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 100:// S_BUFFER_ATOMIC_SMIN_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 101:// S_BUFFER_ATOMIC_UMIN_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 102:// S_BUFFER_ATOMIC_SMAX_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 103:// S_BUFFER_ATOMIC_UMAX_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 104:// S_BUFFER_ATOMIC_AND_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 105:// S_BUFFER_ATOMIC_OR_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 106:// S_BUFFER_ATOMIC_XOR_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 107:// S_BUFFER_ATOMIC_INC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 108:// S_BUFFER_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 128:// S_ATOMIC_SWAP -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 129:// S_ATOMIC_CMPSWAP -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 130:// S_ATOMIC_ADD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 131:// S_ATOMIC_SUB -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 132:// S_ATOMIC_SMIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 133:// S_ATOMIC_UMIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 134:// S_ATOMIC_SMAX -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 135:// S_ATOMIC_UMAX -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 136:// S_ATOMIC_AND -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 137:// S_ATOMIC_OR -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 138:// S_ATOMIC_XOR -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 139:// S_ATOMIC_INC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 140:// S_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 160:// S_ATOMIC_SWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 161:// S_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 162:// S_ATOMIC_ADD_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 163:// S_ATOMIC_SUB_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 164:// S_ATOMIC_SMIN_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 165:// S_ATOMIC_UMIN_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 166:// S_ATOMIC_SMAX_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 167:// S_ATOMIC_UMAX_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 168:// S_ATOMIC_AND_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 169:// S_ATOMIC_OR_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 170:// S_ATOMIC_XOR_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 171:// S_ATOMIC_INC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -case 172:// S_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP1Operands(){ -layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; -switch(layout.OP){ -case 0:// S_MOV_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 1:// S_MOV_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 2:// S_CMOV_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 3:// S_CMOV_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 4:// S_NOT_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 5:// S_NOT_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 6:// S_WQM_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 7:// S_WQM_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 8:// S_BREV_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 9:// S_BREV_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 10:// S_BCNT0_I32_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 11:// S_BCNT0_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 12:// S_BCNT1_I32_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 13:// S_BCNT1_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 14:// S_FF0_I32_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 15:// S_FF0_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 16:// S_FF1_I32_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 17:// S_FF1_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 18:// S_FLBIT_I32_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 19:// S_FLBIT_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 20:// S_FLBIT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 21:// S_FLBIT_I32_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 22:// S_SEXT_I32_I8 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -break; -case 23:// S_SEXT_I32_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -break; -case 24:// S_BITSET0_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 25:// S_BITSET0_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 26:// S_BITSET1_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 27:// S_BITSET1_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -case 28:// S_GETPC_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); -break; -case 29:// S_SETPC_B64 -setBranch(); -setModifyPC(); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 30:// S_SWAPPC_B64 -setBranch(); -setModifyPC(); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); -break; -case 31:// S_RFE_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 32:// S_AND_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 33:// S_OR_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 34:// S_XOR_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 35:// S_ANDN2_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 36:// S_ORN2_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 37:// S_NAND_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 38:// S_NOR_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 39:// S_XNOR_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 40:// S_QUADMASK_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 41:// S_QUADMASK_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 42:// S_MOVRELS_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 43:// S_MOVRELS_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 44:// S_MOVRELD_B32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 45:// S_MOVRELD_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 46:// S_CBRANCH_JOIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 48:// S_ABS_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 50:// S_SET_GPR_IDX_IDX -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 51:// S_ANDN1_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 52:// S_ORN1_SAVEEXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 53:// S_ANDN1_WREXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 54:// S_ANDN2_WREXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 55:// S_BITREPLICATE_B64_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP2Operands(){ -layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; -switch(layout.OP){ -case 0:// S_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 1:// S_SUB_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 2:// S_ADD_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 3:// S_SUB_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 4:// S_ADDC_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 5:// S_SUBB_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 6:// S_MIN_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 7:// S_MIN_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 8:// S_MAX_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 9:// S_MAX_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 10:// S_CSELECT_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 11:// S_CSELECT_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 12:// S_AND_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 13:// S_AND_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 14:// S_OR_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 15:// S_OR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 16:// S_XOR_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 17:// S_XOR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 18:// S_ANDN2_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 19:// S_ANDN2_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 20:// S_ORN2_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 21:// S_ORN2_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 22:// S_NAND_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 23:// S_NAND_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 24:// S_NOR_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 25:// S_NOR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 26:// S_XNOR_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 27:// S_XNOR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 28:// S_LSHL_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 29:// S_LSHL_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 30:// S_LSHR_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 31:// S_LSHR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 32:// S_ASHR_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 33:// S_ASHR_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 34:// S_BFM_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 35:// S_BFM_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 36:// S_MUL_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 37:// S_BFE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 38:// S_BFE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 39:// S_BFE_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 40:// S_BFE_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 41:// S_CBRANCH_G_FORK -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 42:// S_ABSDIFF_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 43:// S_RFE_RESTORE_B64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 44:// S_MUL_HI_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 45:// S_MUL_HI_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 46:// S_LSHL1_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 47:// S_LSHL2_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 48:// S_LSHL3_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 49:// S_LSHL4_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 50:// S_PACK_LL_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,16),true,false); -break; -case 51:// S_PACK_LH_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 52:// S_PACK_HH_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPCOperands(){ -layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; -switch(layout.OP){ -case 0:// S_CMP_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 1:// S_CMP_LG_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 2:// S_CMP_GT_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 3:// S_CMP_GE_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 4:// S_CMP_LT_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 5:// S_CMP_LE_I32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 6:// S_CMP_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 7:// S_CMP_LG_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 8:// S_CMP_GT_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 9:// S_CMP_GE_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 10:// S_CMP_LT_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 11:// S_CMP_LE_U32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 12:// S_BITCMP0_B32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 13:// S_BITCMP1_B32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 14:// S_BITCMP0_B64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 15:// S_BITCMP1_B64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 16:// S_SETVSKIP -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -break; -case 17:// S_SET_GPR_IDX_ON -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 18:// S_CMP_EQ_U64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 19:// S_CMP_LG_U64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPKOperands(){ -layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; -switch(layout.OP){ -case 0:// S_MOVK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 1:// S_CMOVK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 2:// S_CMPK_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 3:// S_CMPK_LG_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 4:// S_CMPK_GT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 5:// S_CMPK_GE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 6:// S_CMPK_LT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 7:// S_CMPK_LE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 8:// S_CMPK_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 9:// S_CMPK_LG_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 10:// S_CMPK_GT_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 11:// S_CMPK_GE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 12:// S_CMPK_LT_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 13:// S_CMPK_LE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 14:// S_ADDK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 15:// S_MULK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 16:// S_CBRANCH_I_FORK -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 17:// S_GETREG_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 18:// S_SETREG_B32 -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); -break; -case 21:// S_CALL_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeSOPK_INST_LITERAL_Operands(){ -layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; -switch(layout.OP){ -case 20:// S_SETREG_IMM32_B32 -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); -insn_in_progress->appendOperand(decodeOPR_SIMM32(decodeOPR_LITERAL()),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPPOperands(){ -layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; -switch(layout.OP){ -case 0:// S_NOP -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 1:// S_ENDPGM -break; -case 2:// S_BRANCH -setBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 3:// S_WAKEUP -break; -case 4:// S_CBRANCH_SCC0 -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 5:// S_CBRANCH_SCC1 -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); -break; -case 6:// S_CBRANCH_VCCZ -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 7:// S_CBRANCH_VCCNZ -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 8:// S_CBRANCH_EXECZ -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 9:// S_CBRANCH_EXECNZ -setBranch(); -setConditionalBranch(); -makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); -break; -case 10:// S_BARRIER -break; -case 11:// S_SETKILL -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 12:// S_WAITCNT -insn_in_progress->appendOperand(decodeOPR_WAITCNT(layout.SIMM16),true,false); -break; -case 13:// S_SETHALT -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 14:// S_SLEEP -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 15:// S_SETPRIO -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 16:// S_SENDMSG -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 17:// S_SENDMSGHALT -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 18:// S_TRAP -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 19:// S_ICACHE_INV -break; -case 20:// S_INCPERFLEVEL -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 21:// S_DECPERFLEVEL -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -break; -case 22:// S_TTRACEDATA -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 23:// S_CBRANCH_CDBGSYS -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 24:// S_CBRANCH_CDBGUSER -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 25:// S_CBRANCH_CDBGSYS_OR_USER -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 26:// S_CBRANCH_CDBGSYS_AND_USER -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -break; -case 27:// S_ENDPGM_SAVED -break; -case 28:// S_SET_GPR_IDX_OFF -break; -case 29:// S_SET_GPR_IDX_MODE -insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 30:// S_ENDPGM_ORDERED_PS_DONE -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VINTRPOperands(){ -layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; -switch(layout.OP){ -case 0:// V_INTERP_P1_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 1:// V_INTERP_P2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 2:// V_INTERP_MOV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3Operands(){ -layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; -switch(layout.OP){ -case 624:// V_INTERP_P1_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 625:// V_INTERP_P2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 626:// V_INTERP_MOV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); -break; -case 320:// V_NOP -break; -case 321:// V_MOV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 322:// V_READFIRSTLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); -break; -case 323:// V_CVT_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 324:// V_CVT_F64_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 325:// V_CVT_F32_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 326:// V_CVT_F32_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 327:// V_CVT_U32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 328:// V_CVT_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 330:// V_CVT_F16_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 331:// V_CVT_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 332:// V_CVT_RPI_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 333:// V_CVT_FLR_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 334:// V_CVT_OFF_F32_I4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 335:// V_CVT_F32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 336:// V_CVT_F64_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 337:// V_CVT_F32_UBYTE0 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 338:// V_CVT_F32_UBYTE1 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 339:// V_CVT_F32_UBYTE2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 340:// V_CVT_F32_UBYTE3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 341:// V_CVT_U32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 342:// V_CVT_F64_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 343:// V_TRUNC_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 344:// V_CEIL_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 345:// V_RNDNE_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 346:// V_FLOOR_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 347:// V_FRACT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 348:// V_TRUNC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 349:// V_CEIL_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 350:// V_RNDNE_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 351:// V_FLOOR_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 352:// V_EXP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 353:// V_LOG_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 354:// V_RCP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 355:// V_RCP_IFLAG_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 356:// V_RSQ_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 357:// V_RCP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 358:// V_RSQ_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 359:// V_SQRT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 360:// V_SQRT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 361:// V_SIN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 362:// V_COS_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 363:// V_NOT_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 364:// V_BFREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 365:// V_FFBH_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 366:// V_FFBL_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 367:// V_FFBH_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 368:// V_FREXP_EXP_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 369:// V_FREXP_MANT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 370:// V_FRACT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 371:// V_FREXP_EXP_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 372:// V_FREXP_MANT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 373:// V_CLREXCP -break; -case 375:// V_SCREEN_PARTITION_4SE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 377:// V_CVT_F16_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 378:// V_CVT_F16_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 379:// V_CVT_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 380:// V_CVT_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 381:// V_RCP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 382:// V_SQRT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 383:// V_RSQ_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 384:// V_LOG_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 385:// V_EXP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 386:// V_FREXP_MANT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 387:// V_FREXP_EXP_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 388:// V_FLOOR_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 389:// V_CEIL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 390:// V_TRUNC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 391:// V_RNDNE_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 392:// V_FRACT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 393:// V_SIN_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 394:// V_COS_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 395:// V_EXP_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 396:// V_LOG_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 397:// V_CVT_NORM_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 398:// V_CVT_NORM_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -break; -case 399:// V_SAT_PK_U8_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 401:// V_SWAP_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); -break; -case 256:// V_CNDMASK_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); -break; -case 257:// V_ADD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 258:// V_SUB_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 259:// V_SUBREV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 260:// V_MUL_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 261:// V_MUL_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 262:// V_MUL_I32_I24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 263:// V_MUL_HI_I32_I24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 264:// V_MUL_U32_U24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 265:// V_MUL_HI_U32_U24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 266:// V_MIN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 267:// V_MAX_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 268:// V_MIN_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 269:// V_MAX_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 270:// V_MIN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 271:// V_MAX_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 272:// V_LSHRREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 273:// V_ASHRREV_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 274:// V_LSHLREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 275:// V_AND_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 276:// V_OR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 277:// V_XOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 278:// V_MAC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 287:// V_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 288:// V_SUB_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 289:// V_SUBREV_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 290:// V_MUL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 291:// V_MAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 294:// V_ADD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 295:// V_SUB_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 296:// V_SUBREV_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 297:// V_MUL_LO_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 298:// V_LSHLREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 299:// V_LSHRREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 300:// V_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 301:// V_MAX_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 302:// V_MIN_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 303:// V_MAX_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 304:// V_MAX_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 305:// V_MIN_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 306:// V_MIN_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 307:// V_LDEXP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 308:// V_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 309:// V_SUB_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 310:// V_SUBREV_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 311:// V_DOT2C_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 312:// V_DOT2C_I32_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 313:// V_DOT4C_I32_I8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 314:// V_DOT8C_I32_I4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 315:// V_FMAC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 316:// V_PK_FMAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 317:// V_XNOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 448:// V_MAD_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 449:// V_MAD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 450:// V_MAD_I32_I24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 451:// V_MAD_U32_U24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 452:// V_CUBEID_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 453:// V_CUBESC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 454:// V_CUBETC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 455:// V_CUBEMA_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 456:// V_BFE_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 457:// V_BFE_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 458:// V_BFI_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 459:// V_FMA_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 460:// V_FMA_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 461:// V_LERP_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 462:// V_ALIGNBIT_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 463:// V_ALIGNBYTE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 464:// V_MIN3_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 465:// V_MIN3_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 466:// V_MIN3_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 467:// V_MAX3_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 468:// V_MAX3_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 469:// V_MAX3_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 470:// V_MED3_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 471:// V_MED3_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 472:// V_MED3_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 473:// V_SAD_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 474:// V_SAD_HI_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 475:// V_SAD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 476:// V_SAD_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 477:// V_CVT_PK_U8_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 478:// V_DIV_FIXUP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 479:// V_DIV_FIXUP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 482:// V_DIV_FMAS_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 483:// V_DIV_FMAS_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 484:// V_MSAD_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 485:// V_QSAD_PK_U16_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 486:// V_MQSAD_PK_U16_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 487:// V_MQSAD_U32_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,32),true,false); -break; -case 490:// V_MAD_LEGACY_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 491:// V_MAD_LEGACY_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 492:// V_MAD_LEGACY_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 493:// V_PERM_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 494:// V_FMA_LEGACY_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 495:// V_DIV_FIXUP_LEGACY_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 496:// V_CVT_PKACCUM_U8_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 497:// V_MAD_U32_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 498:// V_MAD_I32_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 499:// V_XAD_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 500:// V_MIN3_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 501:// V_MIN3_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 502:// V_MIN3_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 503:// V_MAX3_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 504:// V_MAX3_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 505:// V_MAX3_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 506:// V_MED3_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 507:// V_MED3_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 508:// V_MED3_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 509:// V_LSHL_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 510:// V_ADD_LSHL_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 511:// V_ADD3_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 512:// V_LSHL_OR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 513:// V_AND_OR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 514:// V_OR3_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 515:// V_MAD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 516:// V_MAD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 517:// V_MAD_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 518:// V_FMA_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 519:// V_DIV_FIXUP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 628:// V_INTERP_P1LL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -break; -case 629:// V_INTERP_P1LV_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); -break; -case 630:// V_INTERP_P2_LEGACY_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); -break; -case 631:// V_INTERP_P2_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); -break; -case 640:// V_ADD_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 641:// V_MUL_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 642:// V_MIN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 643:// V_MAX_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 644:// V_LDEXP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 645:// V_MUL_LO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 646:// V_MUL_HI_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 647:// V_MUL_HI_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 648:// V_LDEXP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 649:// V_READLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); -break; -case 650:// V_WRITELANE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); -break; -case 651:// V_BCNT_U32_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 652:// V_MBCNT_LO_U32_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 653:// V_MBCNT_HI_U32_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 655:// V_LSHLREV_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 656:// V_LSHRREV_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 657:// V_ASHRREV_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 658:// V_TRIG_PREOP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 659:// V_BFM_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 660:// V_CVT_PKNORM_I16_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 661:// V_CVT_PKNORM_U16_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 662:// V_CVT_PKRTZ_F16_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 663:// V_CVT_PK_U16_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 664:// V_CVT_PK_I16_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 665:// V_CVT_PKNORM_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 666:// V_CVT_PKNORM_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 668:// V_ADD_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 669:// V_SUB_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 670:// V_ADD_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 671:// V_SUB_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 672:// V_PACK_B32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 16:// V_CMP_CLASS_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 17:// V_CMPX_CLASS_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 18:// V_CMP_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 19:// V_CMPX_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 20:// V_CMP_CLASS_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 21:// V_CMPX_CLASS_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 32:// V_CMP_F_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 33:// V_CMP_LT_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 34:// V_CMP_EQ_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 35:// V_CMP_LE_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 36:// V_CMP_GT_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 37:// V_CMP_LG_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 38:// V_CMP_GE_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 39:// V_CMP_O_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 40:// V_CMP_U_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 41:// V_CMP_NGE_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 42:// V_CMP_NLG_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 43:// V_CMP_NGT_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 44:// V_CMP_NLE_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 45:// V_CMP_NEQ_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 46:// V_CMP_NLT_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 47:// V_CMP_TRU_F16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 48:// V_CMPX_F_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 49:// V_CMPX_LT_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 50:// V_CMPX_EQ_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 51:// V_CMPX_LE_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 52:// V_CMPX_GT_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 53:// V_CMPX_LG_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 54:// V_CMPX_GE_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 55:// V_CMPX_O_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 56:// V_CMPX_U_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 57:// V_CMPX_NGE_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 58:// V_CMPX_NLG_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 59:// V_CMPX_NGT_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 60:// V_CMPX_NLE_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 61:// V_CMPX_NEQ_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 62:// V_CMPX_NLT_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 63:// V_CMPX_TRU_F16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 64:// V_CMP_F_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 65:// V_CMP_LT_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 66:// V_CMP_EQ_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 67:// V_CMP_LE_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 68:// V_CMP_GT_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 69:// V_CMP_LG_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 70:// V_CMP_GE_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 71:// V_CMP_O_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 72:// V_CMP_U_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 73:// V_CMP_NGE_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 74:// V_CMP_NLG_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 75:// V_CMP_NGT_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 76:// V_CMP_NLE_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 77:// V_CMP_NEQ_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 78:// V_CMP_NLT_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 79:// V_CMP_TRU_F32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 80:// V_CMPX_F_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 81:// V_CMPX_LT_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 82:// V_CMPX_EQ_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 83:// V_CMPX_LE_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 84:// V_CMPX_GT_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 85:// V_CMPX_LG_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 86:// V_CMPX_GE_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 87:// V_CMPX_O_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 88:// V_CMPX_U_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 89:// V_CMPX_NGE_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 90:// V_CMPX_NLG_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 91:// V_CMPX_NGT_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 92:// V_CMPX_NLE_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 93:// V_CMPX_NEQ_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 94:// V_CMPX_NLT_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 95:// V_CMPX_TRU_F32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 96:// V_CMP_F_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 97:// V_CMP_LT_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 98:// V_CMP_EQ_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 99:// V_CMP_LE_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 100:// V_CMP_GT_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 101:// V_CMP_LG_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 102:// V_CMP_GE_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 103:// V_CMP_O_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 104:// V_CMP_U_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 105:// V_CMP_NGE_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 106:// V_CMP_NLG_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 107:// V_CMP_NGT_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 108:// V_CMP_NLE_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 109:// V_CMP_NEQ_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 110:// V_CMP_NLT_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 111:// V_CMP_TRU_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 112:// V_CMPX_F_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 113:// V_CMPX_LT_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 114:// V_CMPX_EQ_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 115:// V_CMPX_LE_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 116:// V_CMPX_GT_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 117:// V_CMPX_LG_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 118:// V_CMPX_GE_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 119:// V_CMPX_O_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 120:// V_CMPX_U_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 121:// V_CMPX_NGE_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 122:// V_CMPX_NLG_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 123:// V_CMPX_NGT_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 124:// V_CMPX_NLE_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 125:// V_CMPX_NEQ_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 126:// V_CMPX_NLT_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 127:// V_CMPX_TRU_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 160:// V_CMP_F_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 161:// V_CMP_LT_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 162:// V_CMP_EQ_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 163:// V_CMP_LE_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 164:// V_CMP_GT_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 165:// V_CMP_NE_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 166:// V_CMP_GE_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 167:// V_CMP_T_I16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 168:// V_CMP_F_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 169:// V_CMP_LT_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 170:// V_CMP_EQ_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 171:// V_CMP_LE_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 172:// V_CMP_GT_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 173:// V_CMP_NE_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 174:// V_CMP_GE_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 175:// V_CMP_T_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 176:// V_CMPX_F_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 177:// V_CMPX_LT_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 178:// V_CMPX_EQ_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 179:// V_CMPX_LE_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 180:// V_CMPX_GT_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 181:// V_CMPX_NE_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 182:// V_CMPX_GE_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 183:// V_CMPX_T_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 184:// V_CMPX_F_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 185:// V_CMPX_LT_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 186:// V_CMPX_EQ_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 187:// V_CMPX_LE_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 188:// V_CMPX_GT_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 189:// V_CMPX_NE_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 190:// V_CMPX_GE_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 191:// V_CMPX_T_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 192:// V_CMP_F_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 193:// V_CMP_LT_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 194:// V_CMP_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 195:// V_CMP_LE_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 196:// V_CMP_GT_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 197:// V_CMP_NE_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 198:// V_CMP_GE_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 199:// V_CMP_T_I32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 200:// V_CMP_F_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 201:// V_CMP_LT_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 202:// V_CMP_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 203:// V_CMP_LE_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 204:// V_CMP_GT_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 205:// V_CMP_NE_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 206:// V_CMP_GE_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 207:// V_CMP_T_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 208:// V_CMPX_F_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 209:// V_CMPX_LT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 210:// V_CMPX_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 211:// V_CMPX_LE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 212:// V_CMPX_GT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 213:// V_CMPX_NE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 214:// V_CMPX_GE_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 215:// V_CMPX_T_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 216:// V_CMPX_F_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 217:// V_CMPX_LT_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 218:// V_CMPX_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 219:// V_CMPX_LE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 220:// V_CMPX_GT_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 221:// V_CMPX_NE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 222:// V_CMPX_GE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 223:// V_CMPX_T_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 224:// V_CMP_F_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 225:// V_CMP_LT_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 226:// V_CMP_EQ_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 227:// V_CMP_LE_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 228:// V_CMP_GT_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 229:// V_CMP_NE_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 230:// V_CMP_GE_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 231:// V_CMP_T_I64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 232:// V_CMP_F_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 233:// V_CMP_LT_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 234:// V_CMP_EQ_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 235:// V_CMP_LE_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 236:// V_CMP_GT_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 237:// V_CMP_NE_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 238:// V_CMP_GE_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 239:// V_CMP_T_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 240:// V_CMPX_F_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 241:// V_CMPX_LT_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 242:// V_CMPX_EQ_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 243:// V_CMPX_LE_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 244:// V_CMPX_GT_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 245:// V_CMPX_NE_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 246:// V_CMPX_GE_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 247:// V_CMPX_T_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 248:// V_CMPX_F_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 249:// V_CMPX_LT_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 250:// V_CMPX_EQ_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 251:// V_CMPX_LE_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 252:// V_CMPX_GT_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 253:// V_CMPX_NE_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 254:// V_CMPX_GE_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 255:// V_CMPX_T_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP1Operands(){ -layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; -switch(layout.OP){ -case 0:// V_NOP -break; -case 1:// V_MOV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 2:// V_READFIRSTLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); -break; -case 3:// V_CVT_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 4:// V_CVT_F64_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 5:// V_CVT_F32_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 6:// V_CVT_F32_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 7:// V_CVT_U32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 8:// V_CVT_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 10:// V_CVT_F16_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 11:// V_CVT_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 12:// V_CVT_RPI_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 13:// V_CVT_FLR_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 14:// V_CVT_OFF_F32_I4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 15:// V_CVT_F32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 16:// V_CVT_F64_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 17:// V_CVT_F32_UBYTE0 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 18:// V_CVT_F32_UBYTE1 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 19:// V_CVT_F32_UBYTE2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 20:// V_CVT_F32_UBYTE3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 21:// V_CVT_U32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 22:// V_CVT_F64_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 23:// V_TRUNC_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 24:// V_CEIL_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 25:// V_RNDNE_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 26:// V_FLOOR_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 27:// V_FRACT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 28:// V_TRUNC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 29:// V_CEIL_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 30:// V_RNDNE_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 31:// V_FLOOR_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 32:// V_EXP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 33:// V_LOG_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 34:// V_RCP_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 35:// V_RCP_IFLAG_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 36:// V_RSQ_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 37:// V_RCP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 38:// V_RSQ_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 39:// V_SQRT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 40:// V_SQRT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 41:// V_SIN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 42:// V_COS_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 43:// V_NOT_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 44:// V_BFREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 45:// V_FFBH_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 46:// V_FFBL_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 47:// V_FFBH_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 48:// V_FREXP_EXP_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 49:// V_FREXP_MANT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 50:// V_FRACT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 51:// V_FREXP_EXP_I32_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 52:// V_FREXP_MANT_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 53:// V_CLREXCP -break; -case 55:// V_SCREEN_PARTITION_4SE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 57:// V_CVT_F16_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 58:// V_CVT_F16_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 59:// V_CVT_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 60:// V_CVT_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 61:// V_RCP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 62:// V_SQRT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 63:// V_RSQ_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 64:// V_LOG_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 65:// V_EXP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 66:// V_FREXP_MANT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 67:// V_FREXP_EXP_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 68:// V_FLOOR_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 69:// V_CEIL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 70:// V_TRUNC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 71:// V_RNDNE_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 72:// V_FRACT_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 73:// V_SIN_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 74:// V_COS_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 75:// V_EXP_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 76:// V_LOG_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 77:// V_CVT_NORM_I16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 78:// V_CVT_NORM_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -break; -case 79:// V_SAT_PK_U8_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 81:// V_SWAP_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2Operands(){ -layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; -switch(layout.OP){ -case 0:// V_CNDMASK_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 1:// V_ADD_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 2:// V_SUB_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 3:// V_SUBREV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 4:// V_MUL_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 5:// V_MUL_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 6:// V_MUL_I32_I24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 7:// V_MUL_HI_I32_I24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 8:// V_MUL_U32_U24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 9:// V_MUL_HI_U32_U24 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 10:// V_MIN_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 11:// V_MAX_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 12:// V_MIN_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 13:// V_MAX_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 14:// V_MIN_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 15:// V_MAX_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 16:// V_LSHRREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 17:// V_ASHRREV_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 18:// V_LSHLREV_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 19:// V_AND_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 20:// V_OR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 21:// V_XOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 22:// V_MAC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 25:// V_ADD_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 26:// V_SUB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 27:// V_SUBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 28:// V_ADDC_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 29:// V_SUBB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 30:// V_SUBBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); -break; -case 31:// V_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 32:// V_SUB_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 33:// V_SUBREV_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 34:// V_MUL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 35:// V_MAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 38:// V_ADD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 39:// V_SUB_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 40:// V_SUBREV_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 41:// V_MUL_LO_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 42:// V_LSHLREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 43:// V_LSHRREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 44:// V_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 45:// V_MAX_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 46:// V_MIN_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 47:// V_MAX_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 48:// V_MAX_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 49:// V_MIN_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 50:// V_MIN_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 51:// V_LDEXP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 52:// V_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 53:// V_SUB_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 54:// V_SUBREV_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 55:// V_DOT2C_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 56:// V_DOT2C_I32_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 57:// V_DOT4C_I32_I8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 58:// V_DOT8C_I32_I4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 59:// V_FMAC_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 60:// V_PK_FMAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 61:// V_XNOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2_LITERALOperands(){ -layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; -switch(layout.OP){ -case 23:// V_MADMK_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 24:// V_MADAK_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -break; -case 36:// V_MADMK_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 37:// V_MADAK_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -break; -} -} -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3BOperands(){ -layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; -switch(layout.OP){ -case 281:// V_ADD_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 282:// V_SUB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 283:// V_SUBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 284:// V_ADDC_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); -break; -case 285:// V_SUBB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); -break; -case 286:// V_SUBBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); -break; -case 480:// V_DIV_SCALE_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 481:// V_DIV_SCALE_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 488:// V_MAD_U64_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -break; -case 489:// V_MAD_I64_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; } } -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3POperands(){ -layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MIMGOperands(){ +layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; switch(layout.OP){ -case 0:// V_PK_MAD_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 1:// V_PK_MUL_LO_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 2:// V_PK_ADD_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 3:// V_PK_SUB_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 4:// V_PK_LSHLREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 5:// V_PK_LSHRREV_B16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 6:// V_PK_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 7:// V_PK_MAX_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 8:// V_PK_MIN_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 9:// V_PK_MAD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 10:// V_PK_ADD_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 11:// V_PK_SUB_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 12:// V_PK_MAX_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 13:// V_PK_MIN_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 14:// V_PK_FMA_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 15:// V_PK_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 16:// V_PK_MUL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 17:// V_PK_MIN_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 18:// V_PK_MAX_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +case 0:case 1:case 2:case 3:case 4:case 5: +//IMAGE_LOAD,IMAGE_LOAD_MIP,IMAGE_LOAD_PCK,IMAGE_LOAD_PCK_SGN,IMAGE_LOAD_MIP_PCK,IMAGE_LOAD_MIP_PCK_SGN +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); break; -case 32:// V_MAD_MIX_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 8:case 9:case 10:case 11: +//IMAGE_STORE,IMAGE_STORE_MIP,IMAGE_STORE_PCK,IMAGE_STORE_MIP_PCK +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); break; -case 33:// V_MAD_MIXLO_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 14: +//IMAGE_GET_RESINFO +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); break; -case 34:// V_MAD_MIXHI_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 16:case 17:case 18:case 19:case 20:case 21:case 22:case 23:case 24:case 25:case 26:case 27:case 28: +//IMAGE_ATOMIC_SWAP,IMAGE_ATOMIC_CMPSWAP,IMAGE_ATOMIC_ADD,IMAGE_ATOMIC_SUB,IMAGE_ATOMIC_SMIN,IMAGE_ATOMIC_UMIN,IMAGE_ATOMIC_SMAX,IMAGE_ATOMIC_UMAX,IMAGE_ATOMIC_AND,IMAGE_ATOMIC_OR,IMAGE_ATOMIC_XOR,IMAGE_ATOMIC_INC,IMAGE_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); break; -case 35:// V_DOT2_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 32:case 39:case 64:case 66:case 71:case 74:case 75:case 96: +//IMAGE_SAMPLE,IMAGE_SAMPLE_LZ,IMAGE_GATHER4,IMAGE_GATHER4H,IMAGE_GATHER4_LZ,IMAGE_GATHER4H_PCK,IMAGE_GATHER8H_PCK,IMAGE_GET_LOD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 38:// V_DOT2_I32_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 33:case 36:case 37:case 40:case 47:case 48:case 55:case 65:case 68:case 69:case 72:case 79:case 80:case 87: +//IMAGE_SAMPLE_CL,IMAGE_SAMPLE_L,IMAGE_SAMPLE_B,IMAGE_SAMPLE_C,IMAGE_SAMPLE_C_LZ,IMAGE_SAMPLE_O,IMAGE_SAMPLE_LZ_O,IMAGE_GATHER4_CL,IMAGE_GATHER4_L,IMAGE_GATHER4_B,IMAGE_GATHER4_C,IMAGE_GATHER4_C_LZ,IMAGE_GATHER4_O,IMAGE_GATHER4_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 39:// V_DOT2_U32_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 34:case 104: +//IMAGE_SAMPLE_D,IMAGE_SAMPLE_CD +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 40:// V_DOT4_I32_I8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 35:case 42:case 50:case 105:case 106:case 108: +//IMAGE_SAMPLE_D_CL,IMAGE_SAMPLE_C_D,IMAGE_SAMPLE_D_O,IMAGE_SAMPLE_CD_CL,IMAGE_SAMPLE_C_CD,IMAGE_SAMPLE_CD_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 41:// V_DOT4_U32_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 38:case 41:case 44:case 45:case 49:case 52:case 53:case 56:case 63:case 70:case 73:case 76:case 77:case 81:case 84:case 85:case 88:case 95: +//IMAGE_SAMPLE_B_CL,IMAGE_SAMPLE_C_CL,IMAGE_SAMPLE_C_L,IMAGE_SAMPLE_C_B,IMAGE_SAMPLE_CL_O,IMAGE_SAMPLE_L_O,IMAGE_SAMPLE_B_O,IMAGE_SAMPLE_C_O,IMAGE_SAMPLE_C_LZ_O,IMAGE_GATHER4_B_CL,IMAGE_GATHER4_C_CL,IMAGE_GATHER4_C_L,IMAGE_GATHER4_C_B,IMAGE_GATHER4_CL_O,IMAGE_GATHER4_L_O,IMAGE_GATHER4_B_O,IMAGE_GATHER4_C_O,IMAGE_GATHER4_C_LZ_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 42:// V_DOT8_I32_I4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 43:case 51:case 58:case 107:case 109:case 110: +//IMAGE_SAMPLE_C_D_CL,IMAGE_SAMPLE_D_CL_O,IMAGE_SAMPLE_C_D_O,IMAGE_SAMPLE_C_CD_CL,IMAGE_SAMPLE_CD_CL_O,IMAGE_SAMPLE_C_CD_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 43:// V_DOT8_U32_U4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +case 46:case 54:case 57:case 60:case 61:case 78:case 86:case 89:case 92:case 93: +//IMAGE_SAMPLE_C_B_CL,IMAGE_SAMPLE_B_CL_O,IMAGE_SAMPLE_C_CL_O,IMAGE_SAMPLE_C_L_O,IMAGE_SAMPLE_C_B_O,IMAGE_GATHER4_C_B_CL,IMAGE_GATHER4_B_CL_O,IMAGE_GATHER4_C_CL_O,IMAGE_GATHER4_C_L_O,IMAGE_GATHER4_C_B_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 88:// V_ACCVGPR_READ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +case 59:case 111: +//IMAGE_SAMPLE_C_D_CL_O,IMAGE_SAMPLE_C_CD_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; -case 89:// V_ACCVGPR_WRITE -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +case 62:case 94: +//IMAGE_SAMPLE_C_B_CL_O,IMAGE_GATHER4_C_B_CL_O +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); break; } } -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3P_MFMAOperands(){ -layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MTBUFOperands(){ +layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; switch(layout.OP){ -case 64:// V_MFMA_F32_32X32X1F32 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 65:// V_MFMA_F32_16X16X1F32 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 66:// V_MFMA_F32_4X4X1F32 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 68:// V_MFMA_F32_32X32X2F32 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 69:// V_MFMA_F32_16X16X4F32 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 72:// V_MFMA_F32_32X32X4F16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 73:// V_MFMA_F32_16X16X4F16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 74:// V_MFMA_F32_4X4X4F16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 76:// V_MFMA_F32_32X32X8F16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 77:// V_MFMA_F32_16X16X16F16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 80:// V_MFMA_I32_32X32X4I8 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 81:// V_MFMA_I32_16X16X4I8 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 82:// V_MFMA_I32_4X4X4I8 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); -break; -case 84:// V_MFMA_I32_32X32X8I8 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 0:case 8:case 9: +//TBUFFER_LOAD_FORMAT_X,TBUFFER_LOAD_FORMAT_D16_X,TBUFFER_LOAD_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 85:// V_MFMA_I32_16X16X16I8 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 1:case 10:case 11: +//TBUFFER_LOAD_FORMAT_XY,TBUFFER_LOAD_FORMAT_D16_XYZ,TBUFFER_LOAD_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 104:// V_MFMA_F32_32X32X2BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 2: +//TBUFFER_LOAD_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 105:// V_MFMA_F32_16X16X2BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 3: +//TBUFFER_LOAD_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 107:// V_MFMA_F32_4X4X2BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 4:case 12:case 13: +//TBUFFER_STORE_FORMAT_X,TBUFFER_STORE_FORMAT_D16_X,TBUFFER_STORE_FORMAT_D16_XY +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 108:// V_MFMA_F32_32X32X4BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 5:case 14:case 15: +//TBUFFER_STORE_FORMAT_XY,TBUFFER_STORE_FORMAT_D16_XYZ,TBUFFER_STORE_FORMAT_D16_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 109:// V_MFMA_F32_16X16X8BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +case 6: +//TBUFFER_STORE_FORMAT_XYZ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +break; +case 7: +//TBUFFER_STORE_FORMAT_XYZW +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; } } -void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOPCOperands(){ -layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; +void InstructionDecoder_amdgpu_gfx908::finalizeENC_MUBUFOperands(){ +layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; switch(layout.OP){ -case 16:// V_CMP_CLASS_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 17:// V_CMPX_CLASS_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 18:// V_CMP_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 19:// V_CMPX_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 20:// V_CMP_CLASS_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 21:// V_CMPX_CLASS_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 0:case 8:case 9:case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38: +//BUFFER_LOAD_FORMAT_X,BUFFER_LOAD_FORMAT_D16_X,BUFFER_LOAD_FORMAT_D16_XY,BUFFER_LOAD_UBYTE,BUFFER_LOAD_SBYTE,BUFFER_LOAD_USHORT,BUFFER_LOAD_SSHORT,BUFFER_LOAD_DWORD,BUFFER_LOAD_UBYTE_D16,BUFFER_LOAD_UBYTE_D16_HI,BUFFER_LOAD_SBYTE_D16,BUFFER_LOAD_SBYTE_D16_HI,BUFFER_LOAD_SHORT_D16,BUFFER_LOAD_SHORT_D16_HI,BUFFER_LOAD_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 32:// V_CMP_F_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 1:case 10:case 11:case 21: +//BUFFER_LOAD_FORMAT_XY,BUFFER_LOAD_FORMAT_D16_XYZ,BUFFER_LOAD_FORMAT_D16_XYZW,BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 33:// V_CMP_LT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 2:case 22: +//BUFFER_LOAD_FORMAT_XYZ,BUFFER_LOAD_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 34:// V_CMP_EQ_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 3:case 23: +//BUFFER_LOAD_FORMAT_XYZW,BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 35:// V_CMP_LE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 4:case 12:case 13:case 24:case 25:case 26:case 27:case 28:case 39: +//BUFFER_STORE_FORMAT_X,BUFFER_STORE_FORMAT_D16_X,BUFFER_STORE_FORMAT_D16_XY,BUFFER_STORE_BYTE,BUFFER_STORE_BYTE_D16_HI,BUFFER_STORE_SHORT,BUFFER_STORE_SHORT_D16_HI,BUFFER_STORE_DWORD,BUFFER_STORE_FORMAT_D16_HI_X +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 36:// V_CMP_GT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 5:case 14:case 15:case 29: +//BUFFER_STORE_FORMAT_XY,BUFFER_STORE_FORMAT_D16_XYZ,BUFFER_STORE_FORMAT_D16_XYZW,BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 37:// V_CMP_LG_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 6:case 30: +//BUFFER_STORE_FORMAT_XYZ,BUFFER_STORE_DWORDX3 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 38:// V_CMP_GE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 7:case 31: +//BUFFER_STORE_FORMAT_XYZW,BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 39:// V_CMP_O_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 61: +//BUFFER_STORE_LDS_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 40:// V_CMP_U_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 62:case 63: +//BUFFER_WBINVL1,BUFFER_WBINVL1_VOL break; -case 41:// V_CMP_NGE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78: +//BUFFER_ATOMIC_SWAP,BUFFER_ATOMIC_ADD,BUFFER_ATOMIC_SUB,BUFFER_ATOMIC_SMIN,BUFFER_ATOMIC_UMIN,BUFFER_ATOMIC_SMAX,BUFFER_ATOMIC_UMAX,BUFFER_ATOMIC_AND,BUFFER_ATOMIC_OR,BUFFER_ATOMIC_XOR,BUFFER_ATOMIC_INC,BUFFER_ATOMIC_DEC,BUFFER_ATOMIC_ADD_F32,BUFFER_ATOMIC_PK_ADD_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 42:// V_CMP_NLG_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: +//BUFFER_ATOMIC_CMPSWAP,BUFFER_ATOMIC_SWAP_X2,BUFFER_ATOMIC_ADD_X2,BUFFER_ATOMIC_SUB_X2,BUFFER_ATOMIC_SMIN_X2,BUFFER_ATOMIC_UMIN_X2,BUFFER_ATOMIC_SMAX_X2,BUFFER_ATOMIC_UMAX_X2,BUFFER_ATOMIC_AND_X2,BUFFER_ATOMIC_OR_X2,BUFFER_ATOMIC_XOR_X2,BUFFER_ATOMIC_INC_X2,BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 43:// V_CMP_NGT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 97: +//BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); break; -case 44:// V_CMP_NLE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SMEMOperands(){ +layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; +switch(layout.OP){ +case 0:case 5: +//S_LOAD_DWORD,S_SCRATCH_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 45:// V_CMP_NEQ_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 1:case 6: +//S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 46:// V_CMP_NLT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 2:case 7: +//S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 47:// V_CMP_TRU_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 3: +//S_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 48:// V_CMPX_F_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 4: +//S_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 49:// V_CMPX_LT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 8: +//S_BUFFER_LOAD_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 50:// V_CMPX_EQ_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 9: +//S_BUFFER_LOAD_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 51:// V_CMPX_LE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 10: +//S_BUFFER_LOAD_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 52:// V_CMPX_GT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 11: +//S_BUFFER_LOAD_DWORDX8 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 53:// V_CMPX_LG_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 12: +//S_BUFFER_LOAD_DWORDX16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 54:// V_CMPX_GE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 16:case 21: +//S_STORE_DWORD,S_SCRATCH_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 55:// V_CMPX_O_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 17:case 22: +//S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 56:// V_CMPX_U_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 18:case 23: +//S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 57:// V_CMPX_NGE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 24: +//S_BUFFER_STORE_DWORD +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 58:// V_CMPX_NLG_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 25: +//S_BUFFER_STORE_DWORDX2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 59:// V_CMPX_NGT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 26: +//S_BUFFER_STORE_DWORDX4 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 60:// V_CMPX_NLE_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 32:case 33:case 34:case 35: +//S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL break; -case 61:// V_CMPX_NEQ_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 36:case 37: +//S_MEMTIME,S_MEMREALTIME +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); break; -case 62:// V_CMPX_NLT_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 38: +//S_ATC_PROBE +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 63:// V_CMPX_TRU_F16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 39: +//S_ATC_PROBE_BUFFER +insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 64:// V_CMP_F_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 40:case 41: +//S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 65:// V_CMP_LT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76: +//S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB,S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX,S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR,S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 66:// V_CMP_EQ_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: +//S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2,S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2,S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2,S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2,S_BUFFER_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +break; +case 97: +//S_BUFFER_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 67:// V_CMP_LE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 128:case 130:case 131:case 132:case 133:case 134:case 135:case 136:case 137:case 138:case 139:case 140: +//S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN,S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND,S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 68:// V_CMP_GT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 129:case 160:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172: +//S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2,S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2,S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2,S_ATOMIC_DEC_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 69:// V_CMP_LG_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 161: +//S_ATOMIC_CMPSWAP_X2 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); break; -case 70:// V_CMP_GE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP1Operands(){ +layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; +switch(layout.OP){ +case 0:case 8:case 14:case 16:case 18:case 20: +//S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32,S_FLBIT_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); break; -case 71:// V_CMP_O_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 1:case 9: +//S_MOV_B64,S_BREV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); break; -case 72:// V_CMP_U_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 2: +//S_CMOV_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 73:// V_CMP_NGE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 3: +//S_CMOV_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 74:// V_CMP_NLG_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 4:case 6:case 10:case 12:case 40:case 48: +//S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32,S_ABS_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 75:// V_CMP_NGT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 5:case 7:case 41: +//S_NOT_B64,S_WQM_B64,S_QUADMASK_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 76:// V_CMP_NLE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 11:case 13: +//S_BCNT0_I32_B64,S_BCNT1_I32_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 77:// V_CMP_NEQ_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 15:case 17:case 19:case 21: +//S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); break; -case 78:// V_CMP_NLT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 22:case 23: +//S_SEXT_I32_I8,S_SEXT_I32_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); break; -case 79:// V_CMP_TRU_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 24:case 26: +//S_BITSET0_B32,S_BITSET1_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); break; -case 80:// V_CMPX_F_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 25:case 27: +//S_BITSET0_B64,S_BITSET1_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); break; -case 81:// V_CMPX_LT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 28: +//S_GETPC_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); break; -case 82:// V_CMPX_EQ_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 29: +//S_SETPC_B64 +setBranch(); +setModifyPC(); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; -case 83:// V_CMPX_LE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 30: +//S_SWAPPC_B64 +setBranch(); +setModifyPC(); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); break; -case 84:// V_CMPX_GT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 31: +//S_RFE_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; -case 85:// V_CMPX_LG_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 51:case 52:case 53:case 54: +//S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64,S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64,S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64,S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); break; -case 86:// V_CMPX_GE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 42: +//S_MOVRELS_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 87:// V_CMPX_O_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 43: +//S_MOVRELS_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 88:// V_CMPX_U_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 44: +//S_MOVRELD_B32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 89:// V_CMPX_NGE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 45: +//S_MOVRELD_B64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 90:// V_CMPX_NLG_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 46: +//S_CBRANCH_JOIN +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; -case 91:// V_CMPX_NGT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 50: +//S_SET_GPR_IDX_IDX +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 92:// V_CMPX_NLE_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 55: +//S_BITREPLICATE_B64_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); break; -case 93:// V_CMPX_NEQ_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP2Operands(){ +layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; +switch(layout.OP){ +case 0:case 1:case 2:case 3:case 6:case 7:case 8:case 9:case 12:case 14:case 16:case 18:case 20:case 22:case 24:case 26:case 28:case 30:case 32:case 37:case 38:case 42:case 46:case 47:case 48:case 49: +//S_ADD_U32,S_SUB_U32,S_ADD_I32,S_SUB_I32,S_MIN_I32,S_MIN_U32,S_MAX_I32,S_MAX_U32,S_AND_B32,S_OR_B32,S_XOR_B32,S_ANDN2_B32,S_ORN2_B32,S_NAND_B32,S_NOR_B32,S_XNOR_B32,S_LSHL_B32,S_LSHR_B32,S_ASHR_I32,S_BFE_U32,S_BFE_I32,S_ABSDIFF_I32,S_LSHL1_ADD_U32,S_LSHL2_ADD_U32,S_LSHL3_ADD_U32,S_LSHL4_ADD_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 94:// V_CMPX_NLT_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 4:case 5: +//S_ADDC_U32,S_SUBB_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 95:// V_CMPX_TRU_F32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 10: +//S_CSELECT_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 96:// V_CMP_F_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 11: +//S_CSELECT_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 97:// V_CMP_LT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 13:case 15:case 17:case 19:case 21:case 23:case 25:case 27: +//S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64,S_NAND_B64,S_NOR_B64,S_XNOR_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +break; +case 29:case 31:case 33:case 39:case 40: +//S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 98:// V_CMP_EQ_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 34:case 36:case 44:case 45:case 52: +//S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_HH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); break; -case 99:// V_CMP_LE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 35: +//S_BFM_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); break; -case 100:// V_CMP_GT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 41: +//S_CBRANCH_G_FORK +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; -case 101:// V_CMP_LG_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 43: +//S_RFE_RESTORE_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); break; -case 102:// V_CMP_GE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 50: +//S_PACK_LL_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,16),true,false); break; -case 103:// V_CMP_O_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 51: +//S_PACK_LH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); break; -case 104:// V_CMP_U_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPCOperands(){ +layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; +switch(layout.OP){ +case 0:case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13: +//S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32,S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32,S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 105:// V_CMP_NGE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 14:case 15: +//S_BITCMP0_B64,S_BITCMP1_B64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 106:// V_CMP_NLG_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 16: +//S_SETVSKIP +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); break; -case 107:// V_CMP_NGT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 17: +//S_SET_GPR_IDX_ON +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 108:// V_CMP_NLE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 18:case 19: +//S_CMP_EQ_U64,S_CMP_LG_U64 +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 109:// V_CMP_NEQ_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPKOperands(){ +layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; +switch(layout.OP){ +case 0:case 17: +//S_MOVK_I32,S_GETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); break; -case 110:// V_CMP_NLT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 1: +//S_CMOVK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 111:// V_CMP_TRU_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13: +//S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32,S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32,S_CMPK_LT_U32,S_CMPK_LE_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 112:// V_CMPX_F_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 14: +//S_ADDK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); break; -case 113:// V_CMPX_LT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 15: +//S_MULK_I32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); break; -case 114:// V_CMPX_EQ_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 16: +//S_CBRANCH_I_FORK +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; -case 115:// V_CMPX_LE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 18: +//S_SETREG_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); break; -case 116:// V_CMPX_GT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 21: +//S_CALL_B64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); break; -case 117:// V_CMPX_LG_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeSOPK_INST_LITERAL_Operands(){ +layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; +switch(layout.OP){ +case 20: +//S_SETREG_IMM32_B32 +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); +insn_in_progress->appendOperand(decodeOPR_SIMM32(decodeOPR_LITERAL()),true,false); break; -case 118:// V_CMPX_GE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPPOperands(){ +layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; +switch(layout.OP){ +case 0:case 11:case 13:case 14:case 15:case 18:case 20:case 21: +//S_NOP,S_SETKILL,S_SETHALT,S_SLEEP,S_SETPRIO,S_TRAP,S_INCPERFLEVEL,S_DECPERFLEVEL +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); break; -case 119:// V_CMPX_O_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 1:case 3:case 10:case 19:case 27:case 28:case 30: +//S_ENDPGM,S_WAKEUP,S_BARRIER,S_ICACHE_INV,S_ENDPGM_SAVED,S_SET_GPR_IDX_OFF,S_ENDPGM_ORDERED_PS_DONE break; -case 120:// V_CMPX_U_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 2: +//S_BRANCH +setBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; -case 121:// V_CMPX_NGE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 4:case 5: +//S_CBRANCH_SCC0,S_CBRANCH_SCC1 +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); break; -case 122:// V_CMPX_NLG_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 6:case 7: +//S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 123:// V_CMPX_NGT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 8:case 9: +//S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ +setBranch(); +setConditionalBranch(); +makeBranchTarget(isCall,isConditional,layout.SIMM16); +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); break; -case 124:// V_CMPX_NLE_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 12: +//S_WAITCNT +insn_in_progress->appendOperand(decodeOPR_WAITCNT(layout.SIMM16),true,false); +break; +case 16:case 17: +//S_SENDMSG,S_SENDMSGHALT +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 125:// V_CMPX_NEQ_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 22: +//S_TTRACEDATA +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 126:// V_CMPX_NLT_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 23:case 24:case 25:case 26: +//S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER,S_CBRANCH_CDBGSYS_AND_USER +insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; -case 127:// V_CMPX_TRU_F64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 29: +//S_SET_GPR_IDX_MODE +insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 160:// V_CMP_F_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VINTRPOperands(){ +layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; +switch(layout.OP){ +case 0: +//V_INTERP_P1_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 161:// V_CMP_LT_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 1: +//V_INTERP_P2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 162:// V_CMP_EQ_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 2: +//V_INTERP_MOV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 163:// V_CMP_LE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3Operands(){ +layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; +switch(layout.OP){ +case 624: +//V_INTERP_P1_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 164:// V_CMP_GT_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 625: +//V_INTERP_P2_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 165:// V_CMP_NE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 626: +//V_INTERP_MOV_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); break; -case 166:// V_CMP_GE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 320:case 373: +//V_NOP,V_CLREXCP break; -case 167:// V_CMP_T_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 321:case 325:case 326:case 327:case 328:case 332:case 333:case 334:case 337:case 338:case 339:case 340:case 347:case 348:case 349:case 350:case 351:case 352:case 353:case 354:case 355:case 356:case 359:case 361:case 362:case 363:case 364:case 365:case 366:case 367:case 371:case 372:case 375:case 395:case 396: +//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); break; -case 168:// V_CMP_F_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 322: +//V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); break; -case 169:// V_CMP_LT_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 323:case 335:case 341:case 368: +//V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); break; -case 170:// V_CMP_EQ_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 324:case 336:case 342: +//V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); break; -case 171:// V_CMP_LE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 330:case 399: +//V_CVT_F16_F32,V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); break; -case 172:// V_CMP_GT_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 331: +//V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); break; -case 173:// V_CMP_NE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 343:case 344:case 345:case 346:case 357:case 358:case 360:case 369:case 370: +//V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64,V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); break; -case 174:// V_CMP_GE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 377:case 378:case 379:case 380:case 381:case 382:case 383:case 384:case 385:case 386:case 387:case 388:case 389:case 390:case 391:case 392:case 393:case 394:case 397:case 398: +//V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); break; -case 175:// V_CMP_T_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 401: +//V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); break; -case 176:// V_CMPX_F_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 256: +//V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); break; -case 177:// V_CMPX_LT_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 257:case 258:case 259:case 260:case 261:case 262:case 263:case 264:case 265:case 266:case 267:case 268:case 269:case 270:case 271:case 275:case 276:case 277:case 308:case 309:case 317:case 645:case 646:case 647:case 648:case 651:case 652:case 653:case 659:case 660:case 661:case 662:case 663:case 664:case 668:case 669: +//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_U32,V_SUB_U32,V_XNOR_B32,V_MUL_LO_U32,V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32,V_BCNT_U32_B32,V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32,V_CVT_PKNORM_I16_F32,V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32,V_CVT_PK_U16_U32,V_CVT_PK_I16_I32,V_ADD_I32,V_SUB_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 178:// V_CMPX_EQ_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 272:case 273:case 274:case 310: +//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 179:// V_CMPX_LE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 278:case 311:case 312:case 313:case 314:case 315:case 316:case 496: +//V_MAC_F32,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16,V_CVT_PKACCUM_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 180:// V_CMPX_GT_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 287:case 288:case 290:case 294:case 295:case 297:case 301:case 302:case 303:case 304:case 305:case 306:case 307:case 670:case 671: +//V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16,V_ADD_I16,V_SUB_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 181:// V_CMPX_NE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 289:case 296:case 298:case 299:case 300: +//V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 182:// V_CMPX_GE_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 291: +//V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 183:// V_CMPX_T_I16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 448:case 449:case 450:case 451:case 452:case 453:case 454:case 455:case 456:case 457:case 458:case 459:case 461:case 462:case 463:case 464:case 465:case 466:case 467:case 468:case 469:case 470:case 471:case 472:case 473:case 474:case 475:case 476:case 477:case 478:case 484:case 493:case 499:case 509:case 510:case 511:case 512:case 513:case 514: +//V_MAD_LEGACY_F32,V_MAD_F32,V_MAD_I32_I24,V_MAD_U32_U24,V_CUBEID_F32,V_CUBESC_F32,V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32,V_BFE_I32,V_BFI_B32,V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32,V_ALIGNBYTE_B32,V_MIN3_F32,V_MIN3_I32,V_MIN3_U32,V_MAX3_F32,V_MAX3_I32,V_MAX3_U32,V_MED3_F32,V_MED3_I32,V_MED3_U32,V_SAD_U8,V_SAD_HI_U8,V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32,V_DIV_FIXUP_F32,V_MSAD_U8,V_PERM_B32,V_XAD_U32,V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32,V_LSHL_OR_B32,V_AND_OR_B32,V_OR3_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 184:// V_CMPX_F_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 460:case 479: +//V_FMA_F64,V_DIV_FIXUP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); break; -case 185:// V_CMPX_LT_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 482: +//V_DIV_FMAS_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 186:// V_CMPX_EQ_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 483: +//V_DIV_FMAS_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 187:// V_CMPX_LE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 485:case 486: +//V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); break; -case 188:// V_CMPX_GT_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 487: +//V_MQSAD_U32_U8 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,32),true,false); break; -case 189:// V_CMPX_NE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 490:case 491:case 492:case 494:case 495:case 500:case 501:case 502:case 503:case 504:case 505:case 506:case 507:case 508:case 515:case 516:case 517:case 518:case 519: +//V_MAD_LEGACY_F16,V_MAD_LEGACY_U16,V_MAD_LEGACY_I16,V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16,V_MIN3_F16,V_MIN3_I16,V_MIN3_U16,V_MAX3_F16,V_MAX3_I16,V_MAX3_U16,V_MED3_F16,V_MED3_I16,V_MED3_U16,V_MAD_F16,V_MAD_U16,V_MAD_I16,V_FMA_F16,V_DIV_FIXUP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +break; +case 497:case 498: +//V_MAD_U32_U16,V_MAD_I32_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 190:// V_CMPX_GE_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 628: +//V_INTERP_P1LL_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); break; -case 191:// V_CMPX_T_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 629:case 630:case 631: +//V_INTERP_P1LV_F16,V_INTERP_P2_LEGACY_F16,V_INTERP_P2_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); break; -case 192:// V_CMP_F_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 640:case 641:case 642:case 643: +//V_ADD_F64,V_MUL_F64,V_MIN_F64,V_MAX_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); break; -case 193:// V_CMP_LT_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 644:case 658: +//V_LDEXP_F64,V_TRIG_PREOP_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 194:// V_CMP_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 649: +//V_READLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); break; -case 195:// V_CMP_LE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 650: +//V_WRITELANE_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); break; -case 196:// V_CMP_GT_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 655:case 656:case 657: +//V_LSHLREV_B64,V_LSHRREV_B64,V_ASHRREV_I64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); break; -case 197:// V_CMP_NE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 665:case 666:case 672: +//V_CVT_PKNORM_I16_F16,V_CVT_PKNORM_U16_F16,V_PACK_B32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 198:// V_CMP_GE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 16:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: +//V_CMP_CLASS_F32,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 199:// V_CMP_T_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 17:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: +//V_CMPX_CLASS_F32,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 200:// V_CMP_F_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 18: +//V_CMP_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 201:// V_CMP_LT_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 19: +//V_CMPX_CLASS_F64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 202:// V_CMP_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175: +//V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 203:// V_CMP_LE_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191: +//V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 204:// V_CMP_GT_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: +//V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); break; -case 205:// V_CMP_NE_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 112:case 113:case 114:case 115:case 116:case 117:case 118:case 119:case 120:case 121:case 122:case 123:case 124:case 125:case 126:case 127:case 240:case 241:case 242:case 243:case 244:case 245:case 246:case 247:case 248:case 249:case 250:case 251:case 252:case 253:case 254:case 255: +//V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64,V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64,V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64,V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64,V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64,V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64,V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64,V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 206:// V_CMP_GE_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP1Operands(){ +layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; +switch(layout.OP){ +case 0:case 53: +//V_NOP,V_CLREXCP break; -case 207:// V_CMP_T_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +case 1:case 5:case 6:case 7:case 8:case 12:case 13:case 14:case 17:case 18:case 19:case 20:case 27:case 28:case 29:case 30:case 31:case 32:case 33:case 34:case 35:case 36:case 39:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 51:case 52:case 55:case 75:case 76: +//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); break; -case 208:// V_CMPX_F_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 2: +//V_READFIRSTLANE_B32 +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); break; -case 209:// V_CMPX_LT_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 3:case 15:case 21:case 48: +//V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); break; -case 210:// V_CMPX_EQ_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +case 4:case 16:case 22: +//V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 211:// V_CMPX_LE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +case 10:case 79: +//V_CVT_F16_F32,V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 212:// V_CMPX_GT_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 11: +//V_CVT_F32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); break; -case 213:// V_CMPX_NE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 23:case 24:case 25:case 26:case 37:case 38:case 40:case 49:case 50: +//V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64,V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); break; -case 214:// V_CMPX_GE_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 77:case 78: +//V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); break; -case 215:// V_CMPX_T_I32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 81: +//V_SWAP_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); break; -case 216:// V_CMPX_F_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2Operands(){ +layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; +switch(layout.OP){ +case 0: +//V_CNDMASK_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 217:// V_CMPX_LT_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13:case 14:case 15:case 19:case 20:case 21:case 52:case 53:case 61: +//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_U32,V_SUB_U32,V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 218:// V_CMPX_EQ_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +case 16:case 17:case 18:case 54: +//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 219:// V_CMPX_LE_U32 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); +case 22:case 55:case 56:case 57:case 58:case 59:case 60: +//V_MAC_F32,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 220:// V_CMPX_GT_U32 +case 25:case 26: +//V_ADD_CO_U32,V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 221:// V_CMPX_NE_U32 +case 27: +//V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 222:// V_CMPX_GE_U32 +case 28:case 29: +//V_ADDC_CO_U32,V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 223:// V_CMPX_T_U32 +case 30: +//V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 224:// V_CMP_F_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 225:// V_CMP_LT_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 31:case 32:case 34:case 38:case 39:case 41:case 45:case 46:case 47:case 48:case 49:case 50:case 51: +//V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); break; -case 226:// V_CMP_EQ_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 33:case 40:case 42:case 43:case 44: +//V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); break; -case 227:// V_CMP_LE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 35: +//V_MAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); break; -case 228:// V_CMP_GT_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2_LITERALOperands(){ +layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; +switch(layout.OP){ +case 23: +//V_MADMK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); break; -case 229:// V_CMP_NE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 24: +//V_MADAK_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); break; -case 230:// V_CMP_GE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 36: +//V_MADMK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); break; -case 231:// V_CMP_T_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 37: +//V_MADAK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); break; -case 232:// V_CMP_F_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3BOperands(){ +layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; +switch(layout.OP){ +case 281:case 282: +//V_ADD_CO_U32,V_SUB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 233:// V_CMP_LT_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 283: +//V_SUBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 234:// V_CMP_EQ_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 284:case 285: +//V_ADDC_CO_U32,V_SUBB_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); break; -case 235:// V_CMP_LE_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 286: +//V_SUBBREV_CO_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); break; -case 236:// V_CMP_GT_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 480: +//V_DIV_SCALE_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 237:// V_CMP_NE_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 481: +//V_DIV_SCALE_F64 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); break; -case 238:// V_CMP_GE_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +case 488:case 489: +//V_MAD_U64_U32,V_MAD_I64_I32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); break; -case 239:// V_CMP_T_U64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3POperands(){ +layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; +switch(layout.OP){ +case 0:case 9:case 14: +//V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); break; -case 240:// V_CMPX_F_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 1:case 2:case 3:case 7:case 8:case 10:case 11:case 12:case 13:case 15:case 16:case 17:case 18: +//V_PK_MUL_LO_U16,V_PK_ADD_I16,V_PK_SUB_I16,V_PK_MAX_I16,V_PK_MIN_I16,V_PK_ADD_U16,V_PK_SUB_U16,V_PK_MAX_U16,V_PK_MIN_U16,V_PK_ADD_F16,V_PK_MUL_F16,V_PK_MIN_F16,V_PK_MAX_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); break; -case 241:// V_CMPX_LT_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 4:case 5:case 6: +//V_PK_LSHLREV_B16,V_PK_LSHRREV_B16,V_PK_ASHRREV_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); break; -case 242:// V_CMPX_EQ_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 32:case 40:case 41:case 42:case 43: +//V_MAD_MIX_F32,V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 243:// V_CMPX_LE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 33:case 34: +//V_MAD_MIXLO_F16,V_MAD_MIXHI_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 244:// V_CMPX_GT_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 35:case 38:case 39: +//V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); break; -case 245:// V_CMPX_NE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 88: +//V_ACCVGPR_READ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); break; -case 246:// V_CMPX_GE_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +case 89: +//V_ACCVGPR_WRITE +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); break; -case 247:// V_CMPX_T_I64 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3P_MFMAOperands(){ +layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; +switch(layout.OP){ +case 64:case 65:case 66:case 68:case 69:case 72:case 73:case 74:case 76:case 77:case 80:case 81:case 82:case 84:case 85:case 104:case 105:case 107:case 108:case 109: +//V_MFMA_F32_32X32X1F32,V_MFMA_F32_16X16X1F32,V_MFMA_F32_4X4X1F32,V_MFMA_F32_32X32X2F32,V_MFMA_F32_16X16X4F32,V_MFMA_F32_32X32X4F16,V_MFMA_F32_16X16X4F16,V_MFMA_F32_4X4X4F16,V_MFMA_F32_32X32X8F16,V_MFMA_F32_16X16X16F16,V_MFMA_I32_32X32X4I8,V_MFMA_I32_16X16X4I8,V_MFMA_I32_4X4X4I8,V_MFMA_I32_32X32X8I8,V_MFMA_I32_16X16X16I8,V_MFMA_F32_32X32X2BF16,V_MFMA_F32_16X16X2BF16,V_MFMA_F32_4X4X2BF16,V_MFMA_F32_32X32X4BF16,V_MFMA_F32_16X16X8BF16 +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); break; -case 248:// V_CMPX_F_U64 +} +} +void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOPCOperands(){ +layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; +switch(layout.OP){ +case 16:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: +//V_CMP_CLASS_F32,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); break; -case 249:// V_CMPX_LT_U64 +case 17:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: +//V_CMPX_CLASS_F32,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 250:// V_CMPX_EQ_U64 +case 18: +//V_CMP_CLASS_F64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); break; -case 251:// V_CMPX_LE_U64 +case 19: +//V_CMPX_CLASS_F64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 252:// V_CMPX_GT_U64 +case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175: +//V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); break; -case 253:// V_CMPX_NE_U64 +case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191: +//V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 254:// V_CMPX_GE_U64 +case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: +//V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); break; -case 255:// V_CMPX_T_U64 +case 112:case 113:case 114:case 115:case 116:case 117:case 118:case 119:case 120:case 121:case 122:case 123:case 124:case 125:case 126:case 127:case 240:case 241:case 242:case 243:case 244:case 245:case 246:case 247:case 248:case 249:case 250:case 251:case 252:case 253:case 254:case 255: +//V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64,V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64,V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64,V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64,V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64,V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64,V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64,V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); From f1144bbb8e2a81eee963ca0c47abda6306942670 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Mon, 24 Oct 2022 16:32:19 -0500 Subject: [PATCH 170/505] add in support for decoding smem_offset operand type, which is still lacking from the ISA spec --- .../gfx908/InstructionDecoder-amdgpu-gfx908.C | 16 +++ .../src/AMDGPU/gfx908/decodeOperands.C | 130 ------------------ .../src/AMDGPU/gfx908/decodeOperands.h | 2 +- .../src/AMDGPU/gfx908/finalizeOperands.C | 50 +++---- instructionAPI/src/ArchSpecificFormatters.C | 2 + 5 files changed, 44 insertions(+), 156 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C index cc2d971629..441bf4f3bc 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -124,6 +124,22 @@ namespace Dyninst { return {}; } + void InstructionDecoder_amdgpu_gfx908::processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout){ + if (layout.IMM ==0 ){ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.OFFSET), true , false ); + }else{ + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET), true , false ); + } + }else{ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false ,false); + }else{ + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false,false); + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET),true ,false); + } + } + } uint32_t InstructionDecoder_amdgpu_gfx908::decodeOPR_LITERAL(){ if (!useImm){ diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C index 46eae153ae..25fbef0cdc 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -576,136 +576,6 @@ case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size){ -switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -default: return makeRegisterExpression(amdgpu_gfx908::invalid); -} -} Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input, uint32_t opr_size){ switch(input){ case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h index 82faf3a7cc..810717a586 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h @@ -8,7 +8,7 @@ Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t opr_size ); Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size ); Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size ); Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SMEM_OFFSET(uint64_t input, uint32_t opr_size ); +void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout ); Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t opr_size ); Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size ); Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size ); diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index d0b6027fd1..d141a8e453 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -1053,7 +1053,7 @@ case 0:case 5: insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 1:case 6: //S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2 @@ -1061,7 +1061,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 2:case 7: //S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4 @@ -1071,7 +1071,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 3: //S_LOAD_DWORDX8 @@ -1085,7 +1085,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 4: //S_LOAD_DWORDX16 @@ -1107,7 +1107,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 8: //S_BUFFER_LOAD_DWORD @@ -1116,7 +1116,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 9: //S_BUFFER_LOAD_DWORDX2 @@ -1126,7 +1126,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 10: //S_BUFFER_LOAD_DWORDX4 @@ -1138,7 +1138,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 11: //S_BUFFER_LOAD_DWORDX8 @@ -1154,7 +1154,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 12: //S_BUFFER_LOAD_DWORDX16 @@ -1178,14 +1178,14 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 16:case 21: //S_STORE_DWORD,S_SCRATCH_STORE_DWORD insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 17:case 22: //S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2 @@ -1193,7 +1193,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 18:case 23: //S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4 @@ -1203,7 +1203,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 24: //S_BUFFER_STORE_DWORD @@ -1212,7 +1212,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 25: //S_BUFFER_STORE_DWORDX2 @@ -1222,7 +1222,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 26: //S_BUFFER_STORE_DWORDX4 @@ -1234,7 +1234,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 32:case 33:case 34:case 35: //S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL @@ -1249,7 +1249,7 @@ case 38: insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 39: //S_ATC_PROBE_BUFFER @@ -1258,13 +1258,13 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 40:case 41: //S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2 insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76: //S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB,S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX,S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR,S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC @@ -1273,7 +1273,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: //S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2,S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2,S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2,S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2,S_BUFFER_ATOMIC_DEC_X2 @@ -1283,7 +1283,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 97: //S_BUFFER_ATOMIC_CMPSWAP_X2 @@ -1295,14 +1295,14 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 128:case 130:case 131:case 132:case 133:case 134:case 135:case 136:case 137:case 138:case 139:case 140: //S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN,S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND,S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 129:case 160:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172: //S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2,S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2,S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2,S_ATOMIC_DEC_X2 @@ -1310,7 +1310,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; case 161: //S_ATOMIC_CMPSWAP_X2 @@ -1320,7 +1320,7 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SMEM_OFFSET(layout.SOFFSET,32),true,false); +processOPR_SMEM_OFFSET(layout); break; } } diff --git a/instructionAPI/src/ArchSpecificFormatters.C b/instructionAPI/src/ArchSpecificFormatters.C index 5f1fe1ec81..5409142f3c 100644 --- a/instructionAPI/src/ArchSpecificFormatters.C +++ b/instructionAPI/src/ArchSpecificFormatters.C @@ -385,6 +385,8 @@ ArchSpecificFormatter& ArchSpecificFormatter::getFormatter(Architecture a) if(found != theFormatters.end()) return *found->second; switch(a) { case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_cdna2: theFormatters[a] = boost::shared_ptr(new AmdgpuFormatter()); break; case Arch_aarch32: From 9d12f3aa05e9dcef2daab166a1a397058c388be8 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 25 Oct 2022 16:48:18 -0500 Subject: [PATCH 171/505] add definition for waitcnt counters --- common/h/dyn_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/common/h/dyn_regs.h b/common/h/dyn_regs.h index 9bbdf5fc3d..d83bc2b2ad 100644 --- a/common/h/dyn_regs.h +++ b/common/h/dyn_regs.h @@ -1708,6 +1708,10 @@ namespace Dyninst DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_gfx908| HWR | BITS_32 | 18, "amdgpu_gfx908"); DEF_REGISTER(src_lds_direct, Arch_amdgpu_gfx908| HWR | BITS_32 | 19 , "amdgpu_gfx908"); + DEF_REGISTER(vmcnt, Arch_amdgpu_gfx908| HWR | BITS_32 | 20 , "amdgpu_gfx908"); + DEF_REGISTER(expcnt, Arch_amdgpu_gfx908| HWR | BITS_32 | 21 , "amdgpu_gfx908"); + DEF_REGISTER(lgkmcnt, Arch_amdgpu_gfx908| HWR | BITS_32 | 22 , "amdgpu_gfx908"); + DEF_REGISTER(ttmp0, Arch_amdgpu_gfx908| TTMP_SGPR | BITS_32 | 0 , "amdgpu_gfx908"); From 496f217a96f09022497bf39ee0b1a724508a2348 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 25 Oct 2022 16:50:56 -0500 Subject: [PATCH 172/505] Add support for formatting consecutive registers as a single operand str --- instructionAPI/h/Register.h | 7 +- .../gfx908/InstructionDecoder-amdgpu-gfx908.C | 1 - .../gfx908/InstructionDecoder-amdgpu-gfx908.h | 7 - .../src/AMDGPU/gfx908/decodeOperands.C | 9300 ++++++++--------- .../src/AMDGPU/gfx908/decodeOperands.h | 80 +- .../src/AMDGPU/gfx908/finalizeOperands.C | 3196 +++--- instructionAPI/src/ArchSpecificFormatters.C | 3 + instructionAPI/src/InstructionDecoderImpl.C | 5 +- instructionAPI/src/InstructionDecoderImpl.h | 5 +- instructionAPI/src/Register.C | 45 +- 10 files changed, 6342 insertions(+), 6307 deletions(-) diff --git a/instructionAPI/h/Register.h b/instructionAPI/h/Register.h index 4b2bc7806c..5c60ce2f7f 100644 --- a/instructionAPI/h/Register.h +++ b/instructionAPI/h/Register.h @@ -55,9 +55,9 @@ namespace Dyninst typedef boost::shared_ptr Ptr; /// Construct a register, assigning it the ID \c id. - RegisterAST(MachRegister r); - RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit); - RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType); + RegisterAST(MachRegister r, uint32_t num_elements = 1 ); + RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, uint32_t num_elements = 1); + RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType, uint32_t num_elements = 1); virtual ~RegisterAST(); @@ -113,6 +113,7 @@ namespace Dyninst MachRegister m_Reg; unsigned int m_Low; unsigned int m_High; + unsigned int m_num_elements; }; /** diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C index 441bf4f3bc..20be07ad32 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -206,7 +206,6 @@ namespace Dyninst { void InstructionDecoder_amdgpu_gfx908::reset(){ immLen = 0; insn_size = 0; - num_elements =1; isBranch = false; isConditional = false; isModifyPC =false; diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h index d05c2971ef..7826af0d24 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h @@ -211,7 +211,6 @@ namespace Dyninst { #define IS_LD_ST() (isLoad || isStore ) - unsigned int num_elements{1}; // the number of elements that will be load or store by each instruction bool isSMEM{}; // this is set when using smem instruction bool isLoad{}; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time bool isStore{}; // similar to isLoad, but for store instructions @@ -266,12 +265,6 @@ namespace Dyninst { - template - void setLoad(){isLoad = true; this->num_elements = num_elements; } - - template - void setStore() {isStore = true;this->num_elements = num_elements;} - void setScratch() {isScratch = true;} void setBuffer() {isBuffer = true;} diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C index 25fbef0cdc..ada3322561 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -1,320 +1,320 @@ -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); -case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); -case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); -case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); -case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); -case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); -case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); -case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); -case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); -case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); -case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); -case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); -case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); -case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); -case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); -case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); -case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); -case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); -case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); -case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); -case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); -case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); -case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); -case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); -case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); -case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); -case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); -case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); -case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); -case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); -case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); -case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); -case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); -case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); -case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); -case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); -case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); -case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); -case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); -case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); -case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); -case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); -case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); -case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); -case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); -case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); -case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); -case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); -case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); -case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); -case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); -case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); -case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); -case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); -case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); -case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); -case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); -case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); -case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); -case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); -case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); -case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); -case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); -case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); -case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); -case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); -case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); -case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); -case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); -case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); -case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); -case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); -case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); -case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); -case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); -case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); -case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); -case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); -case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); -case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); -case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); -case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); -case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); -case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); -case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); -case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); -case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); -case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); -case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); -case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); -case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); -case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); -case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); -case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); -case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); -case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); -case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); -case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); -case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); -case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); -case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); -case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); -case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); -case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); -case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); -case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); -case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); -case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); -case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); -case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); -case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); -case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); -case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); -case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); -case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); -case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); -case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); -case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); -case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); -case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); -case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); -case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); -case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); -case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); -case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); -case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); -case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); -case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); -case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); -case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); -case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); -case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); -case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); -case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); -case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); -case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); -case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); -case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); -case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); -case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); -case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); -case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); -case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); -case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); -case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); -case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); -case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); -case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); -case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); -case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); -case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); -case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); -case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); -case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); -case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); -case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); -case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); -case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); -case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); -case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); -case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); -case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); -case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); -case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); -case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); -case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); -case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); -case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); -case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); -case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); -case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); -case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); -case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); -case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); -case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); -case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); -case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); -case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); -case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); -case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); -case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); -case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); -case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); -case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); -case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); -case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); -case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); -case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); -case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); -case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); -case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); -case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); -case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); -case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); -case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); -case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); -case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); -case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); -case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); -case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); -case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); -case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); -case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); -case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); -case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); -case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); -case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); -case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); -case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); -case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); -case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); -case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); -case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); -case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); -case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); -case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); -case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); -case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); -case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); -case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); -case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); -case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); -case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); -case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); -case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); -case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); -case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); -case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); -case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); -case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); -case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); -case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); -case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); -case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); -case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); -case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); -case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); -case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); -case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); -case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); -case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); -case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); -case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); -case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); -case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); -case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); -case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); -case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); -case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); -case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); -case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); -case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); -case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); -case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); -case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); -case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0, num_elements ); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1, num_elements ); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2, num_elements ); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3, num_elements ); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4, num_elements ); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5, num_elements ); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6, num_elements ); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7, num_elements ); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8, num_elements ); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9, num_elements ); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10, num_elements ); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11, num_elements ); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12, num_elements ); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13, num_elements ); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14, num_elements ); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15, num_elements ); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16, num_elements ); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17, num_elements ); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18, num_elements ); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19, num_elements ); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20, num_elements ); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21, num_elements ); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22, num_elements ); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23, num_elements ); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24, num_elements ); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25, num_elements ); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26, num_elements ); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27, num_elements ); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28, num_elements ); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29, num_elements ); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30, num_elements ); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31, num_elements ); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32, num_elements ); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33, num_elements ); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34, num_elements ); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35, num_elements ); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36, num_elements ); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37, num_elements ); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38, num_elements ); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39, num_elements ); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40, num_elements ); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41, num_elements ); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42, num_elements ); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43, num_elements ); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44, num_elements ); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45, num_elements ); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46, num_elements ); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47, num_elements ); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48, num_elements ); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49, num_elements ); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50, num_elements ); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51, num_elements ); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52, num_elements ); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53, num_elements ); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54, num_elements ); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55, num_elements ); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56, num_elements ); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57, num_elements ); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58, num_elements ); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59, num_elements ); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60, num_elements ); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61, num_elements ); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62, num_elements ); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63, num_elements ); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64, num_elements ); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65, num_elements ); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66, num_elements ); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67, num_elements ); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68, num_elements ); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69, num_elements ); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70, num_elements ); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71, num_elements ); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72, num_elements ); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73, num_elements ); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74, num_elements ); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75, num_elements ); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76, num_elements ); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77, num_elements ); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78, num_elements ); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79, num_elements ); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80, num_elements ); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81, num_elements ); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82, num_elements ); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83, num_elements ); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84, num_elements ); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85, num_elements ); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86, num_elements ); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87, num_elements ); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88, num_elements ); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89, num_elements ); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90, num_elements ); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91, num_elements ); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92, num_elements ); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93, num_elements ); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94, num_elements ); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95, num_elements ); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96, num_elements ); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97, num_elements ); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98, num_elements ); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99, num_elements ); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100, num_elements ); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101, num_elements ); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102, num_elements ); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103, num_elements ); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104, num_elements ); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105, num_elements ); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106, num_elements ); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107, num_elements ); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108, num_elements ); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109, num_elements ); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110, num_elements ); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111, num_elements ); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112, num_elements ); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113, num_elements ); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114, num_elements ); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115, num_elements ); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116, num_elements ); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117, num_elements ); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118, num_elements ); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119, num_elements ); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120, num_elements ); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121, num_elements ); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122, num_elements ); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123, num_elements ); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124, num_elements ); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125, num_elements ); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126, num_elements ); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127, num_elements ); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128, num_elements ); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129, num_elements ); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130, num_elements ); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131, num_elements ); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132, num_elements ); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133, num_elements ); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134, num_elements ); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135, num_elements ); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136, num_elements ); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137, num_elements ); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138, num_elements ); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139, num_elements ); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140, num_elements ); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141, num_elements ); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142, num_elements ); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143, num_elements ); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144, num_elements ); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145, num_elements ); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146, num_elements ); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147, num_elements ); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148, num_elements ); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149, num_elements ); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150, num_elements ); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151, num_elements ); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152, num_elements ); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153, num_elements ); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154, num_elements ); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155, num_elements ); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156, num_elements ); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157, num_elements ); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158, num_elements ); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159, num_elements ); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160, num_elements ); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161, num_elements ); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162, num_elements ); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163, num_elements ); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164, num_elements ); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165, num_elements ); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166, num_elements ); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167, num_elements ); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168, num_elements ); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169, num_elements ); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170, num_elements ); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171, num_elements ); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172, num_elements ); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173, num_elements ); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174, num_elements ); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175, num_elements ); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176, num_elements ); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177, num_elements ); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178, num_elements ); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179, num_elements ); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180, num_elements ); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181, num_elements ); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182, num_elements ); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183, num_elements ); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184, num_elements ); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185, num_elements ); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186, num_elements ); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187, num_elements ); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188, num_elements ); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189, num_elements ); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190, num_elements ); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191, num_elements ); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192, num_elements ); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193, num_elements ); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194, num_elements ); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195, num_elements ); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196, num_elements ); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197, num_elements ); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198, num_elements ); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199, num_elements ); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200, num_elements ); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201, num_elements ); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202, num_elements ); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203, num_elements ); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204, num_elements ); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205, num_elements ); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206, num_elements ); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207, num_elements ); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208, num_elements ); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209, num_elements ); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210, num_elements ); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211, num_elements ); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212, num_elements ); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213, num_elements ); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214, num_elements ); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215, num_elements ); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216, num_elements ); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217, num_elements ); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218, num_elements ); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219, num_elements ); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220, num_elements ); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221, num_elements ); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222, num_elements ); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223, num_elements ); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224, num_elements ); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225, num_elements ); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226, num_elements ); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227, num_elements ); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228, num_elements ); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229, num_elements ); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230, num_elements ); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231, num_elements ); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232, num_elements ); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233, num_elements ); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234, num_elements ); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235, num_elements ); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236, num_elements ); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237, num_elements ); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238, num_elements ); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239, num_elements ); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240, num_elements ); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241, num_elements ); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242, num_elements ); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243, num_elements ); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244, num_elements ); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245, num_elements ); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246, num_elements ); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247, num_elements ); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248, num_elements ); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249, num_elements ); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250, num_elements ); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251, num_elements ); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252, num_elements ); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253, num_elements ); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254, num_elements ); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::attr0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::attr1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::attr2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::attr3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::attr4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::attr5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::attr6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::attr7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::attr8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::attr9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::attr10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::attr11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::attr12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::attr13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::attr14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::attr15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::attr16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::attr17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::attr18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::attr19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::attr20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::attr21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::attr22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::attr23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::attr24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::attr25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::attr26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::attr27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::attr28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::attr29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::attr30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::attr31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::attr32,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::attr0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::attr1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::attr2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::attr3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::attr4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::attr5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::attr6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::attr7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::attr8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::attr9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::attr10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::attr11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::attr12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::attr13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::attr14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::attr15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::attr16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::attr17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::attr18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::attr19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::attr20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::attr21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::attr22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::attr23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::attr24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::attr25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::attr26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::attr27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::attr28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::attr29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::attr30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::attr31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::attr32, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_all,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_all, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t num_elements){ switch(input){ -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::p10,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::p20,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::p0,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::p10, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::p20, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::p0, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -324,387 +324,387 @@ case 0 : return makeRegisterExpression(amdgpu_gfx908::pc_all); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input, uint32_t num_elements){ switch(input){ -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input, uint32_t num_elements){ switch(input){ -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -795,794 +795,794 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); -case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elements ); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); -case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); -case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); -case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); -case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); -case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); -case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); -case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); -case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); -case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); -case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); -case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); -case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); -case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); -case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); -case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); -case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); -case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); -case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); -case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); -case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); -case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); -case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); -case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); -case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); -case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); -case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); -case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); -case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); -case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); -case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); -case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); -case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); -case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); -case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); -case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); -case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); -case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); -case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); -case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); -case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); -case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); -case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); -case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); -case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); -case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); -case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); -case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); -case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); -case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); -case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); -case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); -case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); -case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); -case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); -case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); -case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); -case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); -case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); -case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); -case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); -case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); -case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); -case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); -case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); -case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); -case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); -case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); -case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); -case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); -case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); -case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); -case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); -case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); -case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); -case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); -case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); -case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); -case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); -case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); -case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); -case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); -case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); -case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); -case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); -case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); -case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); -case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); -case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); -case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); -case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); -case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); -case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); -case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); -case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); -case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); -case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); -case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); -case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); -case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); -case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); -case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); -case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); -case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); -case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); -case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); -case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); -case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); -case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); -case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); -case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); -case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); -case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); -case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); -case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); -case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); -case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); -case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); -case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); -case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); -case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); -case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); -case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); -case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); -case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); -case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); -case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); -case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); -case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); -case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); -case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); -case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); -case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); -case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); -case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); -case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); -case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); -case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); -case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); -case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); -case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); -case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); -case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); -case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); -case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); -case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); -case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); -case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); -case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); -case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); -case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); -case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); -case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); -case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); -case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); -case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); -case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); -case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); -case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); -case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); -case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); -case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); -case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); -case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); -case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); -case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); -case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); -case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); -case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); -case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); -case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); -case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); -case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); -case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); -case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); -case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); -case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); -case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); -case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); -case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); -case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); -case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); -case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); -case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); -case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); -case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); -case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); -case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); -case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); -case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); -case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); -case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); -case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); -case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); -case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); -case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); -case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); -case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); -case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); -case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); -case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); -case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); -case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); -case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); -case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); -case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); -case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); -case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); -case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); -case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); -case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); -case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); -case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); -case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); -case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); -case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); -case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); -case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); -case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); -case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); -case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); -case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); -case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); -case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); -case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); -case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); -case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); -case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); -case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); -case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); -case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); -case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); -case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); -case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); -case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); -case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); -case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); -case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); -case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); -case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); -case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); -case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); -case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); -case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); -case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); -case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); -case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); -case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); -case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); -case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); -case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); -case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); -case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); -case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); -case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); -case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0, num_elements ); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1, num_elements ); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2, num_elements ); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3, num_elements ); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4, num_elements ); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5, num_elements ); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6, num_elements ); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7, num_elements ); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8, num_elements ); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9, num_elements ); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10, num_elements ); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11, num_elements ); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12, num_elements ); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13, num_elements ); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14, num_elements ); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15, num_elements ); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16, num_elements ); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17, num_elements ); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18, num_elements ); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19, num_elements ); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20, num_elements ); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21, num_elements ); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22, num_elements ); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23, num_elements ); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24, num_elements ); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25, num_elements ); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26, num_elements ); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27, num_elements ); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28, num_elements ); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29, num_elements ); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30, num_elements ); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31, num_elements ); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32, num_elements ); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33, num_elements ); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34, num_elements ); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35, num_elements ); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36, num_elements ); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37, num_elements ); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38, num_elements ); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39, num_elements ); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40, num_elements ); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41, num_elements ); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42, num_elements ); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43, num_elements ); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44, num_elements ); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45, num_elements ); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46, num_elements ); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47, num_elements ); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48, num_elements ); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49, num_elements ); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50, num_elements ); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51, num_elements ); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52, num_elements ); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53, num_elements ); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54, num_elements ); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55, num_elements ); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56, num_elements ); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57, num_elements ); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58, num_elements ); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59, num_elements ); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60, num_elements ); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61, num_elements ); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62, num_elements ); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63, num_elements ); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64, num_elements ); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65, num_elements ); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66, num_elements ); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67, num_elements ); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68, num_elements ); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69, num_elements ); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70, num_elements ); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71, num_elements ); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72, num_elements ); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73, num_elements ); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74, num_elements ); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75, num_elements ); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76, num_elements ); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77, num_elements ); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78, num_elements ); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79, num_elements ); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80, num_elements ); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81, num_elements ); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82, num_elements ); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83, num_elements ); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84, num_elements ); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85, num_elements ); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86, num_elements ); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87, num_elements ); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88, num_elements ); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89, num_elements ); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90, num_elements ); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91, num_elements ); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92, num_elements ); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93, num_elements ); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94, num_elements ); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95, num_elements ); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96, num_elements ); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97, num_elements ); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98, num_elements ); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99, num_elements ); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100, num_elements ); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101, num_elements ); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102, num_elements ); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103, num_elements ); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104, num_elements ); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105, num_elements ); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106, num_elements ); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107, num_elements ); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108, num_elements ); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109, num_elements ); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110, num_elements ); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111, num_elements ); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112, num_elements ); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113, num_elements ); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114, num_elements ); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115, num_elements ); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116, num_elements ); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117, num_elements ); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118, num_elements ); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119, num_elements ); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120, num_elements ); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121, num_elements ); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122, num_elements ); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123, num_elements ); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124, num_elements ); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125, num_elements ); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126, num_elements ); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127, num_elements ); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128, num_elements ); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129, num_elements ); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130, num_elements ); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131, num_elements ); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132, num_elements ); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133, num_elements ); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134, num_elements ); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135, num_elements ); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136, num_elements ); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137, num_elements ); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138, num_elements ); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139, num_elements ); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140, num_elements ); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141, num_elements ); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142, num_elements ); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143, num_elements ); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144, num_elements ); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145, num_elements ); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146, num_elements ); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147, num_elements ); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148, num_elements ); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149, num_elements ); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150, num_elements ); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151, num_elements ); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152, num_elements ); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153, num_elements ); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154, num_elements ); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155, num_elements ); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156, num_elements ); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157, num_elements ); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158, num_elements ); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159, num_elements ); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160, num_elements ); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161, num_elements ); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162, num_elements ); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163, num_elements ); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164, num_elements ); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165, num_elements ); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166, num_elements ); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167, num_elements ); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168, num_elements ); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169, num_elements ); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170, num_elements ); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171, num_elements ); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172, num_elements ); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173, num_elements ); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174, num_elements ); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175, num_elements ); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176, num_elements ); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177, num_elements ); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178, num_elements ); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179, num_elements ); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180, num_elements ); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181, num_elements ); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182, num_elements ); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183, num_elements ); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184, num_elements ); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185, num_elements ); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186, num_elements ); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187, num_elements ); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188, num_elements ); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189, num_elements ); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190, num_elements ); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191, num_elements ); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192, num_elements ); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193, num_elements ); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194, num_elements ); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195, num_elements ); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196, num_elements ); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197, num_elements ); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198, num_elements ); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199, num_elements ); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200, num_elements ); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201, num_elements ); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202, num_elements ); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203, num_elements ); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204, num_elements ); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205, num_elements ); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206, num_elements ); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207, num_elements ); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208, num_elements ); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209, num_elements ); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210, num_elements ); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211, num_elements ); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212, num_elements ); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213, num_elements ); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214, num_elements ); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215, num_elements ); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216, num_elements ); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217, num_elements ); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218, num_elements ); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219, num_elements ); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220, num_elements ); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221, num_elements ); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222, num_elements ); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223, num_elements ); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224, num_elements ); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225, num_elements ); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226, num_elements ); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227, num_elements ); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228, num_elements ); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229, num_elements ); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230, num_elements ); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231, num_elements ); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232, num_elements ); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233, num_elements ); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234, num_elements ); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235, num_elements ); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236, num_elements ); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237, num_elements ); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238, num_elements ); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239, num_elements ); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240, num_elements ); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241, num_elements ); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242, num_elements ); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243, num_elements ); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244, num_elements ); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245, num_elements ); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246, num_elements ); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247, num_elements ); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248, num_elements ); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249, num_elements ); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250, num_elements ); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251, num_elements ); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252, num_elements ); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253, num_elements ); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254, num_elements ); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t num_elements){ switch(input){ -case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); -case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); -case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); -case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); -case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); -case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); -case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); -case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); -case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); -case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); -case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); -case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); -case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); -case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); -case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); -case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); -case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); -case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); -case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); -case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); -case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); -case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); -case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); -case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); -case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); -case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); -case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); -case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); -case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); -case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); -case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); -case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); -case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); -case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); -case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); -case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); -case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); -case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); -case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); -case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); -case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); -case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); -case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); -case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); -case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); -case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); -case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); -case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); -case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); -case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); -case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); -case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); -case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); -case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); -case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); -case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); -case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); -case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); -case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); -case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); -case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); -case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); -case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); -case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); -case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); -case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); -case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); -case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); -case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); -case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); -case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); -case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); -case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); -case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); -case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); -case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); -case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); -case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); -case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); -case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); -case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); -case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); -case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); -case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); -case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); -case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); -case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); -case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); -case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); -case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); -case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); -case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); -case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); -case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); -case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); -case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); -case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); -case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); -case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); -case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); -case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); -case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); -case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); -case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); -case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); -case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); -case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); -case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); -case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); -case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); -case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); -case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); -case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); -case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); -case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); -case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); -case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); -case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); -case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); -case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); -case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); -case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); -case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); -case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); -case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); -case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); -case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); -case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); -case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); -case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); -case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); -case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); -case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); -case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); -case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); -case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); -case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); -case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); -case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); -case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); -case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); -case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); -case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); -case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); -case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); -case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); -case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); -case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); -case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); -case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); -case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); -case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); -case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); -case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); -case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); -case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); -case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); -case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); -case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); -case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); -case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); -case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); -case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); -case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); -case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); -case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); -case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); -case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); -case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); -case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); -case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); -case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); -case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); -case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); -case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); -case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); -case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); -case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); -case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); -case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); -case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); -case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); -case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); -case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); -case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); -case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); -case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); -case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); -case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); -case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); -case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); -case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); -case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); -case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); -case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); -case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); -case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); -case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); -case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); -case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); -case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); -case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); -case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); -case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); -case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); -case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); -case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); -case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); -case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); -case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); -case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); -case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); -case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); -case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); -case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); -case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); -case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); -case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); -case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); -case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); -case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); -case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); -case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); -case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); -case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); -case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); -case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); -case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); -case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); -case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); -case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); -case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); -case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); -case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); -case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); -case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); -case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); -case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); -case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); -case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); -case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); -case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); -case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); -case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); -case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); -case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); -case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); -case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); -case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); -case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); -case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); -case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); -case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); -case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); -case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); -case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0, num_elements ); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1, num_elements ); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2, num_elements ); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3, num_elements ); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4, num_elements ); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5, num_elements ); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6, num_elements ); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7, num_elements ); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8, num_elements ); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9, num_elements ); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10, num_elements ); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11, num_elements ); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12, num_elements ); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13, num_elements ); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14, num_elements ); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15, num_elements ); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16, num_elements ); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17, num_elements ); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18, num_elements ); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19, num_elements ); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20, num_elements ); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21, num_elements ); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22, num_elements ); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23, num_elements ); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24, num_elements ); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25, num_elements ); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26, num_elements ); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27, num_elements ); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28, num_elements ); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29, num_elements ); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30, num_elements ); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31, num_elements ); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32, num_elements ); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33, num_elements ); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34, num_elements ); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35, num_elements ); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36, num_elements ); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37, num_elements ); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38, num_elements ); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39, num_elements ); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40, num_elements ); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41, num_elements ); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42, num_elements ); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43, num_elements ); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44, num_elements ); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45, num_elements ); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46, num_elements ); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47, num_elements ); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48, num_elements ); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49, num_elements ); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50, num_elements ); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51, num_elements ); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52, num_elements ); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53, num_elements ); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54, num_elements ); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55, num_elements ); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56, num_elements ); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57, num_elements ); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58, num_elements ); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59, num_elements ); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60, num_elements ); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61, num_elements ); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62, num_elements ); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63, num_elements ); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64, num_elements ); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65, num_elements ); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66, num_elements ); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67, num_elements ); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68, num_elements ); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69, num_elements ); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70, num_elements ); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71, num_elements ); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72, num_elements ); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73, num_elements ); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74, num_elements ); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75, num_elements ); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76, num_elements ); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77, num_elements ); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78, num_elements ); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79, num_elements ); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80, num_elements ); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81, num_elements ); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82, num_elements ); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83, num_elements ); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84, num_elements ); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85, num_elements ); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86, num_elements ); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87, num_elements ); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88, num_elements ); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89, num_elements ); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90, num_elements ); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91, num_elements ); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92, num_elements ); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93, num_elements ); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94, num_elements ); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95, num_elements ); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96, num_elements ); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97, num_elements ); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98, num_elements ); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99, num_elements ); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100, num_elements ); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101, num_elements ); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102, num_elements ); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103, num_elements ); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104, num_elements ); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105, num_elements ); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106, num_elements ); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107, num_elements ); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108, num_elements ); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109, num_elements ); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110, num_elements ); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111, num_elements ); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112, num_elements ); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113, num_elements ); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114, num_elements ); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115, num_elements ); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116, num_elements ); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117, num_elements ); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118, num_elements ); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119, num_elements ); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120, num_elements ); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121, num_elements ); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122, num_elements ); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123, num_elements ); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124, num_elements ); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125, num_elements ); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126, num_elements ); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127, num_elements ); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128, num_elements ); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129, num_elements ); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130, num_elements ); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131, num_elements ); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132, num_elements ); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133, num_elements ); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134, num_elements ); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135, num_elements ); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136, num_elements ); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137, num_elements ); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138, num_elements ); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139, num_elements ); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140, num_elements ); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141, num_elements ); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142, num_elements ); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143, num_elements ); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144, num_elements ); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145, num_elements ); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146, num_elements ); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147, num_elements ); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148, num_elements ); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149, num_elements ); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150, num_elements ); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151, num_elements ); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152, num_elements ); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153, num_elements ); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154, num_elements ); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155, num_elements ); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156, num_elements ); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157, num_elements ); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158, num_elements ); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159, num_elements ); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160, num_elements ); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161, num_elements ); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162, num_elements ); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163, num_elements ); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164, num_elements ); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165, num_elements ); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166, num_elements ); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167, num_elements ); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168, num_elements ); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169, num_elements ); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170, num_elements ); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171, num_elements ); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172, num_elements ); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173, num_elements ); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174, num_elements ); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175, num_elements ); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176, num_elements ); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177, num_elements ); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178, num_elements ); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179, num_elements ); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180, num_elements ); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181, num_elements ); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182, num_elements ); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183, num_elements ); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184, num_elements ); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185, num_elements ); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186, num_elements ); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187, num_elements ); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188, num_elements ); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189, num_elements ); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190, num_elements ); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191, num_elements ); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192, num_elements ); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193, num_elements ); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194, num_elements ); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195, num_elements ); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196, num_elements ); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197, num_elements ); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198, num_elements ); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199, num_elements ); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200, num_elements ); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201, num_elements ); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202, num_elements ); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203, num_elements ); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204, num_elements ); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205, num_elements ); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206, num_elements ); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207, num_elements ); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208, num_elements ); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209, num_elements ); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210, num_elements ); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211, num_elements ); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212, num_elements ); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213, num_elements ); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214, num_elements ); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215, num_elements ); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216, num_elements ); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217, num_elements ); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218, num_elements ); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219, num_elements ); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220, num_elements ); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221, num_elements ); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222, num_elements ); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223, num_elements ); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224, num_elements ); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225, num_elements ); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226, num_elements ); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227, num_elements ); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228, num_elements ); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229, num_elements ); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230, num_elements ); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231, num_elements ); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232, num_elements ); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233, num_elements ); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234, num_elements ); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235, num_elements ); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236, num_elements ); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237, num_elements ); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238, num_elements ); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239, num_elements ); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240, num_elements ); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241, num_elements ); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242, num_elements ); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243, num_elements ); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244, num_elements ); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245, num_elements ); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246, num_elements ); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247, num_elements ); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248, num_elements ); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249, num_elements ); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250, num_elements ); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251, num_elements ); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252, num_elements ); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253, num_elements ); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254, num_elements ); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -1676,135 +1676,135 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -1895,403 +1895,403 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -2382,403 +2382,403 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); -case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -2869,1436 +2869,1436 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); -case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0,0,opr_size); -case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1,0,opr_size); -case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2,0,opr_size); -case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3,0,opr_size); -case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4,0,opr_size); -case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5,0,opr_size); -case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6,0,opr_size); -case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7,0,opr_size); -case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8,0,opr_size); -case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9,0,opr_size); -case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10,0,opr_size); -case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11,0,opr_size); -case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12,0,opr_size); -case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13,0,opr_size); -case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14,0,opr_size); -case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15,0,opr_size); -case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16,0,opr_size); -case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17,0,opr_size); -case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18,0,opr_size); -case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19,0,opr_size); -case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20,0,opr_size); -case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21,0,opr_size); -case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22,0,opr_size); -case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23,0,opr_size); -case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24,0,opr_size); -case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25,0,opr_size); -case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26,0,opr_size); -case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27,0,opr_size); -case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28,0,opr_size); -case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29,0,opr_size); -case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30,0,opr_size); -case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31,0,opr_size); -case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32,0,opr_size); -case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33,0,opr_size); -case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34,0,opr_size); -case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35,0,opr_size); -case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36,0,opr_size); -case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37,0,opr_size); -case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38,0,opr_size); -case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39,0,opr_size); -case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40,0,opr_size); -case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41,0,opr_size); -case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42,0,opr_size); -case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43,0,opr_size); -case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44,0,opr_size); -case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45,0,opr_size); -case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46,0,opr_size); -case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47,0,opr_size); -case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48,0,opr_size); -case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49,0,opr_size); -case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50,0,opr_size); -case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51,0,opr_size); -case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52,0,opr_size); -case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53,0,opr_size); -case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54,0,opr_size); -case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55,0,opr_size); -case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56,0,opr_size); -case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57,0,opr_size); -case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58,0,opr_size); -case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59,0,opr_size); -case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60,0,opr_size); -case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61,0,opr_size); -case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62,0,opr_size); -case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63,0,opr_size); -case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64,0,opr_size); -case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65,0,opr_size); -case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66,0,opr_size); -case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67,0,opr_size); -case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68,0,opr_size); -case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69,0,opr_size); -case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70,0,opr_size); -case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71,0,opr_size); -case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72,0,opr_size); -case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73,0,opr_size); -case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74,0,opr_size); -case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75,0,opr_size); -case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76,0,opr_size); -case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77,0,opr_size); -case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78,0,opr_size); -case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79,0,opr_size); -case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80,0,opr_size); -case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81,0,opr_size); -case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82,0,opr_size); -case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83,0,opr_size); -case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84,0,opr_size); -case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85,0,opr_size); -case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86,0,opr_size); -case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87,0,opr_size); -case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88,0,opr_size); -case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89,0,opr_size); -case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90,0,opr_size); -case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91,0,opr_size); -case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92,0,opr_size); -case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93,0,opr_size); -case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94,0,opr_size); -case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95,0,opr_size); -case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96,0,opr_size); -case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97,0,opr_size); -case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98,0,opr_size); -case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99,0,opr_size); -case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100,0,opr_size); -case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101,0,opr_size); -case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102,0,opr_size); -case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103,0,opr_size); -case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104,0,opr_size); -case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105,0,opr_size); -case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106,0,opr_size); -case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107,0,opr_size); -case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108,0,opr_size); -case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109,0,opr_size); -case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110,0,opr_size); -case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111,0,opr_size); -case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112,0,opr_size); -case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113,0,opr_size); -case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114,0,opr_size); -case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115,0,opr_size); -case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116,0,opr_size); -case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117,0,opr_size); -case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118,0,opr_size); -case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119,0,opr_size); -case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120,0,opr_size); -case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121,0,opr_size); -case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122,0,opr_size); -case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123,0,opr_size); -case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124,0,opr_size); -case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125,0,opr_size); -case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126,0,opr_size); -case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127,0,opr_size); -case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128,0,opr_size); -case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129,0,opr_size); -case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130,0,opr_size); -case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131,0,opr_size); -case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132,0,opr_size); -case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133,0,opr_size); -case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134,0,opr_size); -case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135,0,opr_size); -case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136,0,opr_size); -case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137,0,opr_size); -case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138,0,opr_size); -case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139,0,opr_size); -case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140,0,opr_size); -case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141,0,opr_size); -case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142,0,opr_size); -case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143,0,opr_size); -case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144,0,opr_size); -case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145,0,opr_size); -case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146,0,opr_size); -case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147,0,opr_size); -case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148,0,opr_size); -case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149,0,opr_size); -case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150,0,opr_size); -case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151,0,opr_size); -case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152,0,opr_size); -case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153,0,opr_size); -case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154,0,opr_size); -case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155,0,opr_size); -case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156,0,opr_size); -case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157,0,opr_size); -case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158,0,opr_size); -case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159,0,opr_size); -case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160,0,opr_size); -case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161,0,opr_size); -case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162,0,opr_size); -case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163,0,opr_size); -case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164,0,opr_size); -case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165,0,opr_size); -case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166,0,opr_size); -case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167,0,opr_size); -case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168,0,opr_size); -case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169,0,opr_size); -case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170,0,opr_size); -case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171,0,opr_size); -case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172,0,opr_size); -case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173,0,opr_size); -case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174,0,opr_size); -case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175,0,opr_size); -case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176,0,opr_size); -case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177,0,opr_size); -case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178,0,opr_size); -case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179,0,opr_size); -case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180,0,opr_size); -case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181,0,opr_size); -case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182,0,opr_size); -case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183,0,opr_size); -case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184,0,opr_size); -case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185,0,opr_size); -case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186,0,opr_size); -case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187,0,opr_size); -case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188,0,opr_size); -case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189,0,opr_size); -case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190,0,opr_size); -case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191,0,opr_size); -case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192,0,opr_size); -case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193,0,opr_size); -case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194,0,opr_size); -case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195,0,opr_size); -case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196,0,opr_size); -case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197,0,opr_size); -case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198,0,opr_size); -case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199,0,opr_size); -case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200,0,opr_size); -case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201,0,opr_size); -case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202,0,opr_size); -case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203,0,opr_size); -case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204,0,opr_size); -case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205,0,opr_size); -case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206,0,opr_size); -case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207,0,opr_size); -case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208,0,opr_size); -case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209,0,opr_size); -case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210,0,opr_size); -case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211,0,opr_size); -case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212,0,opr_size); -case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213,0,opr_size); -case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214,0,opr_size); -case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215,0,opr_size); -case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216,0,opr_size); -case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217,0,opr_size); -case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218,0,opr_size); -case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219,0,opr_size); -case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220,0,opr_size); -case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221,0,opr_size); -case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222,0,opr_size); -case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223,0,opr_size); -case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224,0,opr_size); -case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225,0,opr_size); -case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226,0,opr_size); -case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227,0,opr_size); -case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228,0,opr_size); -case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229,0,opr_size); -case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230,0,opr_size); -case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231,0,opr_size); -case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232,0,opr_size); -case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233,0,opr_size); -case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234,0,opr_size); -case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235,0,opr_size); -case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236,0,opr_size); -case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237,0,opr_size); -case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238,0,opr_size); -case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239,0,opr_size); -case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240,0,opr_size); -case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241,0,opr_size); -case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242,0,opr_size); -case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243,0,opr_size); -case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244,0,opr_size); -case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245,0,opr_size); -case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246,0,opr_size); -case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247,0,opr_size); -case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248,0,opr_size); -case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249,0,opr_size); -case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250,0,opr_size); -case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251,0,opr_size); -case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252,0,opr_size); -case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253,0,opr_size); -case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254,0,opr_size); -case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255,0,opr_size); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); +case 768 : return makeRegisterExpression(amdgpu_gfx908::acc0, num_elements ); +case 769 : return makeRegisterExpression(amdgpu_gfx908::acc1, num_elements ); +case 770 : return makeRegisterExpression(amdgpu_gfx908::acc2, num_elements ); +case 771 : return makeRegisterExpression(amdgpu_gfx908::acc3, num_elements ); +case 772 : return makeRegisterExpression(amdgpu_gfx908::acc4, num_elements ); +case 773 : return makeRegisterExpression(amdgpu_gfx908::acc5, num_elements ); +case 774 : return makeRegisterExpression(amdgpu_gfx908::acc6, num_elements ); +case 775 : return makeRegisterExpression(amdgpu_gfx908::acc7, num_elements ); +case 776 : return makeRegisterExpression(amdgpu_gfx908::acc8, num_elements ); +case 777 : return makeRegisterExpression(amdgpu_gfx908::acc9, num_elements ); +case 778 : return makeRegisterExpression(amdgpu_gfx908::acc10, num_elements ); +case 779 : return makeRegisterExpression(amdgpu_gfx908::acc11, num_elements ); +case 780 : return makeRegisterExpression(amdgpu_gfx908::acc12, num_elements ); +case 781 : return makeRegisterExpression(amdgpu_gfx908::acc13, num_elements ); +case 782 : return makeRegisterExpression(amdgpu_gfx908::acc14, num_elements ); +case 783 : return makeRegisterExpression(amdgpu_gfx908::acc15, num_elements ); +case 784 : return makeRegisterExpression(amdgpu_gfx908::acc16, num_elements ); +case 785 : return makeRegisterExpression(amdgpu_gfx908::acc17, num_elements ); +case 786 : return makeRegisterExpression(amdgpu_gfx908::acc18, num_elements ); +case 787 : return makeRegisterExpression(amdgpu_gfx908::acc19, num_elements ); +case 788 : return makeRegisterExpression(amdgpu_gfx908::acc20, num_elements ); +case 789 : return makeRegisterExpression(amdgpu_gfx908::acc21, num_elements ); +case 790 : return makeRegisterExpression(amdgpu_gfx908::acc22, num_elements ); +case 791 : return makeRegisterExpression(amdgpu_gfx908::acc23, num_elements ); +case 792 : return makeRegisterExpression(amdgpu_gfx908::acc24, num_elements ); +case 793 : return makeRegisterExpression(amdgpu_gfx908::acc25, num_elements ); +case 794 : return makeRegisterExpression(amdgpu_gfx908::acc26, num_elements ); +case 795 : return makeRegisterExpression(amdgpu_gfx908::acc27, num_elements ); +case 796 : return makeRegisterExpression(amdgpu_gfx908::acc28, num_elements ); +case 797 : return makeRegisterExpression(amdgpu_gfx908::acc29, num_elements ); +case 798 : return makeRegisterExpression(amdgpu_gfx908::acc30, num_elements ); +case 799 : return makeRegisterExpression(amdgpu_gfx908::acc31, num_elements ); +case 800 : return makeRegisterExpression(amdgpu_gfx908::acc32, num_elements ); +case 801 : return makeRegisterExpression(amdgpu_gfx908::acc33, num_elements ); +case 802 : return makeRegisterExpression(amdgpu_gfx908::acc34, num_elements ); +case 803 : return makeRegisterExpression(amdgpu_gfx908::acc35, num_elements ); +case 804 : return makeRegisterExpression(amdgpu_gfx908::acc36, num_elements ); +case 805 : return makeRegisterExpression(amdgpu_gfx908::acc37, num_elements ); +case 806 : return makeRegisterExpression(amdgpu_gfx908::acc38, num_elements ); +case 807 : return makeRegisterExpression(amdgpu_gfx908::acc39, num_elements ); +case 808 : return makeRegisterExpression(amdgpu_gfx908::acc40, num_elements ); +case 809 : return makeRegisterExpression(amdgpu_gfx908::acc41, num_elements ); +case 810 : return makeRegisterExpression(amdgpu_gfx908::acc42, num_elements ); +case 811 : return makeRegisterExpression(amdgpu_gfx908::acc43, num_elements ); +case 812 : return makeRegisterExpression(amdgpu_gfx908::acc44, num_elements ); +case 813 : return makeRegisterExpression(amdgpu_gfx908::acc45, num_elements ); +case 814 : return makeRegisterExpression(amdgpu_gfx908::acc46, num_elements ); +case 815 : return makeRegisterExpression(amdgpu_gfx908::acc47, num_elements ); +case 816 : return makeRegisterExpression(amdgpu_gfx908::acc48, num_elements ); +case 817 : return makeRegisterExpression(amdgpu_gfx908::acc49, num_elements ); +case 818 : return makeRegisterExpression(amdgpu_gfx908::acc50, num_elements ); +case 819 : return makeRegisterExpression(amdgpu_gfx908::acc51, num_elements ); +case 820 : return makeRegisterExpression(amdgpu_gfx908::acc52, num_elements ); +case 821 : return makeRegisterExpression(amdgpu_gfx908::acc53, num_elements ); +case 822 : return makeRegisterExpression(amdgpu_gfx908::acc54, num_elements ); +case 823 : return makeRegisterExpression(amdgpu_gfx908::acc55, num_elements ); +case 824 : return makeRegisterExpression(amdgpu_gfx908::acc56, num_elements ); +case 825 : return makeRegisterExpression(amdgpu_gfx908::acc57, num_elements ); +case 826 : return makeRegisterExpression(amdgpu_gfx908::acc58, num_elements ); +case 827 : return makeRegisterExpression(amdgpu_gfx908::acc59, num_elements ); +case 828 : return makeRegisterExpression(amdgpu_gfx908::acc60, num_elements ); +case 829 : return makeRegisterExpression(amdgpu_gfx908::acc61, num_elements ); +case 830 : return makeRegisterExpression(amdgpu_gfx908::acc62, num_elements ); +case 831 : return makeRegisterExpression(amdgpu_gfx908::acc63, num_elements ); +case 832 : return makeRegisterExpression(amdgpu_gfx908::acc64, num_elements ); +case 833 : return makeRegisterExpression(amdgpu_gfx908::acc65, num_elements ); +case 834 : return makeRegisterExpression(amdgpu_gfx908::acc66, num_elements ); +case 835 : return makeRegisterExpression(amdgpu_gfx908::acc67, num_elements ); +case 836 : return makeRegisterExpression(amdgpu_gfx908::acc68, num_elements ); +case 837 : return makeRegisterExpression(amdgpu_gfx908::acc69, num_elements ); +case 838 : return makeRegisterExpression(amdgpu_gfx908::acc70, num_elements ); +case 839 : return makeRegisterExpression(amdgpu_gfx908::acc71, num_elements ); +case 840 : return makeRegisterExpression(amdgpu_gfx908::acc72, num_elements ); +case 841 : return makeRegisterExpression(amdgpu_gfx908::acc73, num_elements ); +case 842 : return makeRegisterExpression(amdgpu_gfx908::acc74, num_elements ); +case 843 : return makeRegisterExpression(amdgpu_gfx908::acc75, num_elements ); +case 844 : return makeRegisterExpression(amdgpu_gfx908::acc76, num_elements ); +case 845 : return makeRegisterExpression(amdgpu_gfx908::acc77, num_elements ); +case 846 : return makeRegisterExpression(amdgpu_gfx908::acc78, num_elements ); +case 847 : return makeRegisterExpression(amdgpu_gfx908::acc79, num_elements ); +case 848 : return makeRegisterExpression(amdgpu_gfx908::acc80, num_elements ); +case 849 : return makeRegisterExpression(amdgpu_gfx908::acc81, num_elements ); +case 850 : return makeRegisterExpression(amdgpu_gfx908::acc82, num_elements ); +case 851 : return makeRegisterExpression(amdgpu_gfx908::acc83, num_elements ); +case 852 : return makeRegisterExpression(amdgpu_gfx908::acc84, num_elements ); +case 853 : return makeRegisterExpression(amdgpu_gfx908::acc85, num_elements ); +case 854 : return makeRegisterExpression(amdgpu_gfx908::acc86, num_elements ); +case 855 : return makeRegisterExpression(amdgpu_gfx908::acc87, num_elements ); +case 856 : return makeRegisterExpression(amdgpu_gfx908::acc88, num_elements ); +case 857 : return makeRegisterExpression(amdgpu_gfx908::acc89, num_elements ); +case 858 : return makeRegisterExpression(amdgpu_gfx908::acc90, num_elements ); +case 859 : return makeRegisterExpression(amdgpu_gfx908::acc91, num_elements ); +case 860 : return makeRegisterExpression(amdgpu_gfx908::acc92, num_elements ); +case 861 : return makeRegisterExpression(amdgpu_gfx908::acc93, num_elements ); +case 862 : return makeRegisterExpression(amdgpu_gfx908::acc94, num_elements ); +case 863 : return makeRegisterExpression(amdgpu_gfx908::acc95, num_elements ); +case 864 : return makeRegisterExpression(amdgpu_gfx908::acc96, num_elements ); +case 865 : return makeRegisterExpression(amdgpu_gfx908::acc97, num_elements ); +case 866 : return makeRegisterExpression(amdgpu_gfx908::acc98, num_elements ); +case 867 : return makeRegisterExpression(amdgpu_gfx908::acc99, num_elements ); +case 868 : return makeRegisterExpression(amdgpu_gfx908::acc100, num_elements ); +case 869 : return makeRegisterExpression(amdgpu_gfx908::acc101, num_elements ); +case 870 : return makeRegisterExpression(amdgpu_gfx908::acc102, num_elements ); +case 871 : return makeRegisterExpression(amdgpu_gfx908::acc103, num_elements ); +case 872 : return makeRegisterExpression(amdgpu_gfx908::acc104, num_elements ); +case 873 : return makeRegisterExpression(amdgpu_gfx908::acc105, num_elements ); +case 874 : return makeRegisterExpression(amdgpu_gfx908::acc106, num_elements ); +case 875 : return makeRegisterExpression(amdgpu_gfx908::acc107, num_elements ); +case 876 : return makeRegisterExpression(amdgpu_gfx908::acc108, num_elements ); +case 877 : return makeRegisterExpression(amdgpu_gfx908::acc109, num_elements ); +case 878 : return makeRegisterExpression(amdgpu_gfx908::acc110, num_elements ); +case 879 : return makeRegisterExpression(amdgpu_gfx908::acc111, num_elements ); +case 880 : return makeRegisterExpression(amdgpu_gfx908::acc112, num_elements ); +case 881 : return makeRegisterExpression(amdgpu_gfx908::acc113, num_elements ); +case 882 : return makeRegisterExpression(amdgpu_gfx908::acc114, num_elements ); +case 883 : return makeRegisterExpression(amdgpu_gfx908::acc115, num_elements ); +case 884 : return makeRegisterExpression(amdgpu_gfx908::acc116, num_elements ); +case 885 : return makeRegisterExpression(amdgpu_gfx908::acc117, num_elements ); +case 886 : return makeRegisterExpression(amdgpu_gfx908::acc118, num_elements ); +case 887 : return makeRegisterExpression(amdgpu_gfx908::acc119, num_elements ); +case 888 : return makeRegisterExpression(amdgpu_gfx908::acc120, num_elements ); +case 889 : return makeRegisterExpression(amdgpu_gfx908::acc121, num_elements ); +case 890 : return makeRegisterExpression(amdgpu_gfx908::acc122, num_elements ); +case 891 : return makeRegisterExpression(amdgpu_gfx908::acc123, num_elements ); +case 892 : return makeRegisterExpression(amdgpu_gfx908::acc124, num_elements ); +case 893 : return makeRegisterExpression(amdgpu_gfx908::acc125, num_elements ); +case 894 : return makeRegisterExpression(amdgpu_gfx908::acc126, num_elements ); +case 895 : return makeRegisterExpression(amdgpu_gfx908::acc127, num_elements ); +case 896 : return makeRegisterExpression(amdgpu_gfx908::acc128, num_elements ); +case 897 : return makeRegisterExpression(amdgpu_gfx908::acc129, num_elements ); +case 898 : return makeRegisterExpression(amdgpu_gfx908::acc130, num_elements ); +case 899 : return makeRegisterExpression(amdgpu_gfx908::acc131, num_elements ); +case 900 : return makeRegisterExpression(amdgpu_gfx908::acc132, num_elements ); +case 901 : return makeRegisterExpression(amdgpu_gfx908::acc133, num_elements ); +case 902 : return makeRegisterExpression(amdgpu_gfx908::acc134, num_elements ); +case 903 : return makeRegisterExpression(amdgpu_gfx908::acc135, num_elements ); +case 904 : return makeRegisterExpression(amdgpu_gfx908::acc136, num_elements ); +case 905 : return makeRegisterExpression(amdgpu_gfx908::acc137, num_elements ); +case 906 : return makeRegisterExpression(amdgpu_gfx908::acc138, num_elements ); +case 907 : return makeRegisterExpression(amdgpu_gfx908::acc139, num_elements ); +case 908 : return makeRegisterExpression(amdgpu_gfx908::acc140, num_elements ); +case 909 : return makeRegisterExpression(amdgpu_gfx908::acc141, num_elements ); +case 910 : return makeRegisterExpression(amdgpu_gfx908::acc142, num_elements ); +case 911 : return makeRegisterExpression(amdgpu_gfx908::acc143, num_elements ); +case 912 : return makeRegisterExpression(amdgpu_gfx908::acc144, num_elements ); +case 913 : return makeRegisterExpression(amdgpu_gfx908::acc145, num_elements ); +case 914 : return makeRegisterExpression(amdgpu_gfx908::acc146, num_elements ); +case 915 : return makeRegisterExpression(amdgpu_gfx908::acc147, num_elements ); +case 916 : return makeRegisterExpression(amdgpu_gfx908::acc148, num_elements ); +case 917 : return makeRegisterExpression(amdgpu_gfx908::acc149, num_elements ); +case 918 : return makeRegisterExpression(amdgpu_gfx908::acc150, num_elements ); +case 919 : return makeRegisterExpression(amdgpu_gfx908::acc151, num_elements ); +case 920 : return makeRegisterExpression(amdgpu_gfx908::acc152, num_elements ); +case 921 : return makeRegisterExpression(amdgpu_gfx908::acc153, num_elements ); +case 922 : return makeRegisterExpression(amdgpu_gfx908::acc154, num_elements ); +case 923 : return makeRegisterExpression(amdgpu_gfx908::acc155, num_elements ); +case 924 : return makeRegisterExpression(amdgpu_gfx908::acc156, num_elements ); +case 925 : return makeRegisterExpression(amdgpu_gfx908::acc157, num_elements ); +case 926 : return makeRegisterExpression(amdgpu_gfx908::acc158, num_elements ); +case 927 : return makeRegisterExpression(amdgpu_gfx908::acc159, num_elements ); +case 928 : return makeRegisterExpression(amdgpu_gfx908::acc160, num_elements ); +case 929 : return makeRegisterExpression(amdgpu_gfx908::acc161, num_elements ); +case 930 : return makeRegisterExpression(amdgpu_gfx908::acc162, num_elements ); +case 931 : return makeRegisterExpression(amdgpu_gfx908::acc163, num_elements ); +case 932 : return makeRegisterExpression(amdgpu_gfx908::acc164, num_elements ); +case 933 : return makeRegisterExpression(amdgpu_gfx908::acc165, num_elements ); +case 934 : return makeRegisterExpression(amdgpu_gfx908::acc166, num_elements ); +case 935 : return makeRegisterExpression(amdgpu_gfx908::acc167, num_elements ); +case 936 : return makeRegisterExpression(amdgpu_gfx908::acc168, num_elements ); +case 937 : return makeRegisterExpression(amdgpu_gfx908::acc169, num_elements ); +case 938 : return makeRegisterExpression(amdgpu_gfx908::acc170, num_elements ); +case 939 : return makeRegisterExpression(amdgpu_gfx908::acc171, num_elements ); +case 940 : return makeRegisterExpression(amdgpu_gfx908::acc172, num_elements ); +case 941 : return makeRegisterExpression(amdgpu_gfx908::acc173, num_elements ); +case 942 : return makeRegisterExpression(amdgpu_gfx908::acc174, num_elements ); +case 943 : return makeRegisterExpression(amdgpu_gfx908::acc175, num_elements ); +case 944 : return makeRegisterExpression(amdgpu_gfx908::acc176, num_elements ); +case 945 : return makeRegisterExpression(amdgpu_gfx908::acc177, num_elements ); +case 946 : return makeRegisterExpression(amdgpu_gfx908::acc178, num_elements ); +case 947 : return makeRegisterExpression(amdgpu_gfx908::acc179, num_elements ); +case 948 : return makeRegisterExpression(amdgpu_gfx908::acc180, num_elements ); +case 949 : return makeRegisterExpression(amdgpu_gfx908::acc181, num_elements ); +case 950 : return makeRegisterExpression(amdgpu_gfx908::acc182, num_elements ); +case 951 : return makeRegisterExpression(amdgpu_gfx908::acc183, num_elements ); +case 952 : return makeRegisterExpression(amdgpu_gfx908::acc184, num_elements ); +case 953 : return makeRegisterExpression(amdgpu_gfx908::acc185, num_elements ); +case 954 : return makeRegisterExpression(amdgpu_gfx908::acc186, num_elements ); +case 955 : return makeRegisterExpression(amdgpu_gfx908::acc187, num_elements ); +case 956 : return makeRegisterExpression(amdgpu_gfx908::acc188, num_elements ); +case 957 : return makeRegisterExpression(amdgpu_gfx908::acc189, num_elements ); +case 958 : return makeRegisterExpression(amdgpu_gfx908::acc190, num_elements ); +case 959 : return makeRegisterExpression(amdgpu_gfx908::acc191, num_elements ); +case 960 : return makeRegisterExpression(amdgpu_gfx908::acc192, num_elements ); +case 961 : return makeRegisterExpression(amdgpu_gfx908::acc193, num_elements ); +case 962 : return makeRegisterExpression(amdgpu_gfx908::acc194, num_elements ); +case 963 : return makeRegisterExpression(amdgpu_gfx908::acc195, num_elements ); +case 964 : return makeRegisterExpression(amdgpu_gfx908::acc196, num_elements ); +case 965 : return makeRegisterExpression(amdgpu_gfx908::acc197, num_elements ); +case 966 : return makeRegisterExpression(amdgpu_gfx908::acc198, num_elements ); +case 967 : return makeRegisterExpression(amdgpu_gfx908::acc199, num_elements ); +case 968 : return makeRegisterExpression(amdgpu_gfx908::acc200, num_elements ); +case 969 : return makeRegisterExpression(amdgpu_gfx908::acc201, num_elements ); +case 970 : return makeRegisterExpression(amdgpu_gfx908::acc202, num_elements ); +case 971 : return makeRegisterExpression(amdgpu_gfx908::acc203, num_elements ); +case 972 : return makeRegisterExpression(amdgpu_gfx908::acc204, num_elements ); +case 973 : return makeRegisterExpression(amdgpu_gfx908::acc205, num_elements ); +case 974 : return makeRegisterExpression(amdgpu_gfx908::acc206, num_elements ); +case 975 : return makeRegisterExpression(amdgpu_gfx908::acc207, num_elements ); +case 976 : return makeRegisterExpression(amdgpu_gfx908::acc208, num_elements ); +case 977 : return makeRegisterExpression(amdgpu_gfx908::acc209, num_elements ); +case 978 : return makeRegisterExpression(amdgpu_gfx908::acc210, num_elements ); +case 979 : return makeRegisterExpression(amdgpu_gfx908::acc211, num_elements ); +case 980 : return makeRegisterExpression(amdgpu_gfx908::acc212, num_elements ); +case 981 : return makeRegisterExpression(amdgpu_gfx908::acc213, num_elements ); +case 982 : return makeRegisterExpression(amdgpu_gfx908::acc214, num_elements ); +case 983 : return makeRegisterExpression(amdgpu_gfx908::acc215, num_elements ); +case 984 : return makeRegisterExpression(amdgpu_gfx908::acc216, num_elements ); +case 985 : return makeRegisterExpression(amdgpu_gfx908::acc217, num_elements ); +case 986 : return makeRegisterExpression(amdgpu_gfx908::acc218, num_elements ); +case 987 : return makeRegisterExpression(amdgpu_gfx908::acc219, num_elements ); +case 988 : return makeRegisterExpression(amdgpu_gfx908::acc220, num_elements ); +case 989 : return makeRegisterExpression(amdgpu_gfx908::acc221, num_elements ); +case 990 : return makeRegisterExpression(amdgpu_gfx908::acc222, num_elements ); +case 991 : return makeRegisterExpression(amdgpu_gfx908::acc223, num_elements ); +case 992 : return makeRegisterExpression(amdgpu_gfx908::acc224, num_elements ); +case 993 : return makeRegisterExpression(amdgpu_gfx908::acc225, num_elements ); +case 994 : return makeRegisterExpression(amdgpu_gfx908::acc226, num_elements ); +case 995 : return makeRegisterExpression(amdgpu_gfx908::acc227, num_elements ); +case 996 : return makeRegisterExpression(amdgpu_gfx908::acc228, num_elements ); +case 997 : return makeRegisterExpression(amdgpu_gfx908::acc229, num_elements ); +case 998 : return makeRegisterExpression(amdgpu_gfx908::acc230, num_elements ); +case 999 : return makeRegisterExpression(amdgpu_gfx908::acc231, num_elements ); +case 1000 : return makeRegisterExpression(amdgpu_gfx908::acc232, num_elements ); +case 1001 : return makeRegisterExpression(amdgpu_gfx908::acc233, num_elements ); +case 1002 : return makeRegisterExpression(amdgpu_gfx908::acc234, num_elements ); +case 1003 : return makeRegisterExpression(amdgpu_gfx908::acc235, num_elements ); +case 1004 : return makeRegisterExpression(amdgpu_gfx908::acc236, num_elements ); +case 1005 : return makeRegisterExpression(amdgpu_gfx908::acc237, num_elements ); +case 1006 : return makeRegisterExpression(amdgpu_gfx908::acc238, num_elements ); +case 1007 : return makeRegisterExpression(amdgpu_gfx908::acc239, num_elements ); +case 1008 : return makeRegisterExpression(amdgpu_gfx908::acc240, num_elements ); +case 1009 : return makeRegisterExpression(amdgpu_gfx908::acc241, num_elements ); +case 1010 : return makeRegisterExpression(amdgpu_gfx908::acc242, num_elements ); +case 1011 : return makeRegisterExpression(amdgpu_gfx908::acc243, num_elements ); +case 1012 : return makeRegisterExpression(amdgpu_gfx908::acc244, num_elements ); +case 1013 : return makeRegisterExpression(amdgpu_gfx908::acc245, num_elements ); +case 1014 : return makeRegisterExpression(amdgpu_gfx908::acc246, num_elements ); +case 1015 : return makeRegisterExpression(amdgpu_gfx908::acc247, num_elements ); +case 1016 : return makeRegisterExpression(amdgpu_gfx908::acc248, num_elements ); +case 1017 : return makeRegisterExpression(amdgpu_gfx908::acc249, num_elements ); +case 1018 : return makeRegisterExpression(amdgpu_gfx908::acc250, num_elements ); +case 1019 : return makeRegisterExpression(amdgpu_gfx908::acc251, num_elements ); +case 1020 : return makeRegisterExpression(amdgpu_gfx908::acc252, num_elements ); +case 1021 : return makeRegisterExpression(amdgpu_gfx908::acc253, num_elements ); +case 1022 : return makeRegisterExpression(amdgpu_gfx908::acc254, num_elements ); +case 1023 : return makeRegisterExpression(amdgpu_gfx908::acc255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -4389,15 +4389,15 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -4565,133 +4565,133 @@ case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -4759,135 +4759,135 @@ case 191 : return Immediate::makeImmediate(Result(u32, 63)); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::s0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::s1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::s2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::s3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::s4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::s5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::s6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::s7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::s8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::s9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::s10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::s11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::s12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::s13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::s14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::s15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::s16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::s17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::s18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::s19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::s20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::s21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::s22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::s23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::s24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::s25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::s26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::s27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::s28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::s29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::s30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::s31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::s32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::s33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::s34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::s35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::s36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::s37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::s38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::s39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::s40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::s41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::s42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::s43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::s44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::s45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::s46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::s47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::s48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::s49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::s50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::s51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::s52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::s53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::s54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::s55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::s56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::s57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::s58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::s59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::s60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::s61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::s62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::s63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::s64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::s65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::s66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::s67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::s68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::s69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::s70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::s71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::s72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::s73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::s74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::s75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::s76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::s77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::s78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::s79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::s80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::s81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::s82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::s83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::s84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::s85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::s86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::s87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::s88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::s89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::s90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::s91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::s92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::s93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::s94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::s95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::s96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::s97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::s98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::s99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::s100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::s101,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::m0,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::s0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::s1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::s2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::s3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::s4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::s5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::s6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::s7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::s8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::s9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::s10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::s11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::s12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::s13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::s14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::s15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::s16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::s17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::s18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::s19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::s20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::s21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::s22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::s23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::s24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::s25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::s26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::s27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::s28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::s29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::s30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::s31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::s32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::s33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::s34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::s35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::s36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::s37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::s38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::s39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::s40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::s41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::s42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::s43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::s44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::s45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::s46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::s47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::s48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::s49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::s50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::s51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::s52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::s53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::s54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::s55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::s56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::s57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::s58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::s59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::s60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::s61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::s62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::s63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::s64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::s65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::s66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::s67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::s68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::s69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::s70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::s71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::s72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::s73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::s74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::s75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::s76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::s77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::s78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::s79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::s80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::s81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::s82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::s83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::s84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::s85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::s86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::s87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::s88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::s89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::s90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::s91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::s92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::s93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::s94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::s95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::s96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::s97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::s98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::s99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::s100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::s101, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::m0, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::exec_lo, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::exec_hi, num_elements ); case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); case 130 : return Immediate::makeImmediate(Result(u32, 2)); @@ -4978,45 +4978,45 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t num_elements){ switch(input){ -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t num_elements){ switch(input){ -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t num_elements){ switch(input){ -case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t num_elements){ switch(input){ -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal,0,opr_size); +case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t num_elements){ switch(input){ case 128 : return Immediate::makeImmediate(Result(u32, 0)); case 129 : return Immediate::makeImmediate(Result(u32, 1)); @@ -5108,104 +5108,104 @@ case 245 : return Immediate::makeImmediate(Result(sp_float, -2.0)); case 246 : return Immediate::makeImmediate(Result(sp_float, 4.0)); case 247 : return Immediate::makeImmediate(Result(sp_float, -4.0)); case 248 : return Immediate::makeImmediate(Result(sp_float, 0.15915494)); -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::src_execz, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::src_shared_base, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t num_elements){ switch(input){ -case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id,0,opr_size); +case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t num_elements){ switch(input){ -case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc,0,opr_size); +case 253 : return makeRegisterExpression(amdgpu_gfx908::src_scc, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t num_elements){ switch(input){ -case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz,0,opr_size); +case 251 : return makeRegisterExpression(amdgpu_gfx908::src_vccz, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::mrt0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::mrt1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::mrt2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::mrt3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::mrt4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::mrt5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::mrt6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::mrt7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::mrtz,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::null,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::pos0,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::pos1,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::pos2,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::pos3,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::param0,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::param1,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::param2,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::param3,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::param4,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::param5,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::param6,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::param7,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::param8,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::param9,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::param10,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::param11,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::param12,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::param13,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::param14,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::param15,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::param16,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::param17,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::param18,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::param19,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::param20,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::param21,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::param22,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::param23,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::param24,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::param25,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::param26,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::param27,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::param28,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::param29,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::param30,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::param31,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::mrt0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::mrt1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::mrt2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::mrt3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::mrt4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::mrt5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::mrt6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::mrt7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::mrtz, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::null, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::pos0, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::pos1, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::pos2, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::pos3, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::param0, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::param1, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::param2, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::param3, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::param4, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::param5, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::param6, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::param7, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::param8, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::param9, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::param10, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::param11, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::param12, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::param13, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::param14, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::param15, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::param16, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::param17, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::param18, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::param19, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::param20, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::param21, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::param22, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::param23, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::param24, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::param25, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::param26, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::param27, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::param28, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::param29, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::param30, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::param31, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TRAP(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TRAP(uint64_t input, uint32_t num_elements){ switch(input){ -case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15,0,opr_size); +case 108 : return makeRegisterExpression(amdgpu_gfx908::ttmp0, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::ttmp1, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::ttmp2, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::ttmp3, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::ttmp4, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::ttmp5, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::ttmp6, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::ttmp7, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::ttmp8, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::ttmp9, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::ttmp10, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::ttmp11, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::ttmp12, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::ttmp13, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::ttmp14, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::ttmp15, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -5215,540 +5215,540 @@ case 0 : return makeRegisterExpression(amdgpu_gfx908::vcc); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC_LOHI(uint64_t input, uint32_t num_elements){ switch(input){ -case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi,0,opr_size); +case 106 : return makeRegisterExpression(amdgpu_gfx908::vcc_lo, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::vcc_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input, uint32_t num_elements){ switch(input){ -case 0 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 1 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 2 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 3 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 4 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 5 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 6 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 7 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 8 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 9 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 10 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 11 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 12 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 13 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 14 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 15 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 16 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 17 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 18 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 19 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 20 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 21 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 22 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 23 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 24 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 25 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 26 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 27 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 28 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 29 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 30 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 31 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 32 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 33 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 34 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 35 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 36 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 37 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 38 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 39 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 40 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 41 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 42 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 43 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 44 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 45 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 46 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 47 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 48 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 49 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 50 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 51 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 52 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 53 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 54 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 55 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 56 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 57 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 58 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 59 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 60 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 61 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 62 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 63 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 64 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 65 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 66 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 67 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 68 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 69 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 70 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 71 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 72 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 73 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 74 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 75 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 76 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 77 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 78 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 79 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 80 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 81 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 82 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 83 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 84 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 85 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 86 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 87 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 88 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 89 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 90 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 91 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 92 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 93 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 94 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 95 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 96 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 97 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 98 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 99 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 100 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 101 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 102 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 103 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 104 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 106 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 107 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 108 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 109 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 110 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 111 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 112 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 113 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 114 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 115 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 116 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 117 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 118 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 119 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 120 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 121 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 122 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 123 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 124 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 125 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 126 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 127 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 128 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 129 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 130 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 131 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 132 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 133 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 134 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 135 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 136 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 137 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 138 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 139 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 140 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 141 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 142 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 143 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 144 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 145 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 146 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 147 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 148 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 149 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 150 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 151 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 152 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 153 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 154 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 155 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 156 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 157 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 158 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 159 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 160 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 161 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 162 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 163 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 164 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 165 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 166 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 167 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 168 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 169 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 170 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 171 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 172 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 173 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 174 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 175 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 176 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 177 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 178 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 179 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 180 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 181 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 182 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 183 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 184 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 185 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 186 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 187 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 188 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 189 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 190 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 191 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 192 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 193 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 194 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 195 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 196 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 197 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 198 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 199 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 200 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 201 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 202 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 203 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 204 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 205 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 206 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 207 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 208 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 209 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 210 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 211 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 212 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 213 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 214 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 215 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 216 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 217 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 218 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 219 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 220 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 221 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 222 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 223 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 224 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 225 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 226 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 227 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 228 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 229 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 230 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 231 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 232 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 233 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 234 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 235 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 236 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 237 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 238 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 239 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 240 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 241 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 242 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 243 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 244 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 245 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 246 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 247 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 248 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 249 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 250 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 251 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 252 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 253 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 254 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 255 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 0 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 1 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 2 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 3 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 4 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 5 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 6 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 7 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 8 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 9 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 10 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 11 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 12 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 13 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 14 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 15 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 16 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 17 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 18 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 19 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 20 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 21 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 22 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 23 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 24 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 25 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 26 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 27 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 28 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 29 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 30 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 31 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 32 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 33 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 34 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 35 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 36 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 37 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 38 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 39 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 40 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 41 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 42 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 43 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 44 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 45 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 46 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 47 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 48 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 49 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 50 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 51 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 52 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 53 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 54 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 55 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 56 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 57 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 58 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 59 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 60 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 61 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 62 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 63 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 64 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 65 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 66 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 67 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 68 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 69 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 70 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 71 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 72 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 73 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 74 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 75 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 76 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 77 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 78 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 79 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 80 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 81 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 82 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 83 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 84 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 85 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 86 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 87 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 88 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 89 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 90 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 91 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 92 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 93 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 94 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 95 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 96 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 97 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 98 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 99 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 100 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 101 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 102 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 103 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 104 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 106 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 107 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 108 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 109 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 110 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 111 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 112 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 113 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 114 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 115 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 116 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 117 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 118 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 119 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 120 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 121 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 122 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 123 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 124 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 125 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 126 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 127 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 128 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 129 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 130 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 131 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 132 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 133 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 134 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 135 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 136 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 137 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 138 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 139 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 140 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 141 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 142 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 143 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 144 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 145 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 146 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 147 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 148 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 149 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 150 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 151 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 152 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 153 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 154 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 155 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 156 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 157 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 158 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 159 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 160 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 161 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 162 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 163 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 164 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 165 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 166 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 167 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 168 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 169 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 170 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 171 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 172 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 173 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 174 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 175 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 176 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 177 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 178 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 179 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 180 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 181 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 182 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 183 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 184 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 185 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 186 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 187 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 188 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 189 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 190 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 191 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 192 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 193 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 194 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 195 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 196 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 197 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 198 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 199 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 200 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 201 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 202 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 203 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 204 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 205 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 206 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 207 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 208 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 209 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 210 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 211 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 212 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 213 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 214 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 215 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 216 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 217 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 218 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 219 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 220 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 221 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 222 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 223 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 224 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 225 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 226 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 227 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 228 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 229 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 230 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 231 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 232 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 233 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 234 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 235 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 236 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 237 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 238 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 239 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 240 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 241 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 242 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 243 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 244 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 245 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 246 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 247 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 248 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 249 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 250 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 251 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 252 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 253 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 254 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 255 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t num_elements){ switch(input){ -case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct,0,opr_size); -case 256 : return makeRegisterExpression(amdgpu_gfx908::v0,0,opr_size); -case 257 : return makeRegisterExpression(amdgpu_gfx908::v1,0,opr_size); -case 258 : return makeRegisterExpression(amdgpu_gfx908::v2,0,opr_size); -case 259 : return makeRegisterExpression(amdgpu_gfx908::v3,0,opr_size); -case 260 : return makeRegisterExpression(amdgpu_gfx908::v4,0,opr_size); -case 261 : return makeRegisterExpression(amdgpu_gfx908::v5,0,opr_size); -case 262 : return makeRegisterExpression(amdgpu_gfx908::v6,0,opr_size); -case 263 : return makeRegisterExpression(amdgpu_gfx908::v7,0,opr_size); -case 264 : return makeRegisterExpression(amdgpu_gfx908::v8,0,opr_size); -case 265 : return makeRegisterExpression(amdgpu_gfx908::v9,0,opr_size); -case 266 : return makeRegisterExpression(amdgpu_gfx908::v10,0,opr_size); -case 267 : return makeRegisterExpression(amdgpu_gfx908::v11,0,opr_size); -case 268 : return makeRegisterExpression(amdgpu_gfx908::v12,0,opr_size); -case 269 : return makeRegisterExpression(amdgpu_gfx908::v13,0,opr_size); -case 270 : return makeRegisterExpression(amdgpu_gfx908::v14,0,opr_size); -case 271 : return makeRegisterExpression(amdgpu_gfx908::v15,0,opr_size); -case 272 : return makeRegisterExpression(amdgpu_gfx908::v16,0,opr_size); -case 273 : return makeRegisterExpression(amdgpu_gfx908::v17,0,opr_size); -case 274 : return makeRegisterExpression(amdgpu_gfx908::v18,0,opr_size); -case 275 : return makeRegisterExpression(amdgpu_gfx908::v19,0,opr_size); -case 276 : return makeRegisterExpression(amdgpu_gfx908::v20,0,opr_size); -case 277 : return makeRegisterExpression(amdgpu_gfx908::v21,0,opr_size); -case 278 : return makeRegisterExpression(amdgpu_gfx908::v22,0,opr_size); -case 279 : return makeRegisterExpression(amdgpu_gfx908::v23,0,opr_size); -case 280 : return makeRegisterExpression(amdgpu_gfx908::v24,0,opr_size); -case 281 : return makeRegisterExpression(amdgpu_gfx908::v25,0,opr_size); -case 282 : return makeRegisterExpression(amdgpu_gfx908::v26,0,opr_size); -case 283 : return makeRegisterExpression(amdgpu_gfx908::v27,0,opr_size); -case 284 : return makeRegisterExpression(amdgpu_gfx908::v28,0,opr_size); -case 285 : return makeRegisterExpression(amdgpu_gfx908::v29,0,opr_size); -case 286 : return makeRegisterExpression(amdgpu_gfx908::v30,0,opr_size); -case 287 : return makeRegisterExpression(amdgpu_gfx908::v31,0,opr_size); -case 288 : return makeRegisterExpression(amdgpu_gfx908::v32,0,opr_size); -case 289 : return makeRegisterExpression(amdgpu_gfx908::v33,0,opr_size); -case 290 : return makeRegisterExpression(amdgpu_gfx908::v34,0,opr_size); -case 291 : return makeRegisterExpression(amdgpu_gfx908::v35,0,opr_size); -case 292 : return makeRegisterExpression(amdgpu_gfx908::v36,0,opr_size); -case 293 : return makeRegisterExpression(amdgpu_gfx908::v37,0,opr_size); -case 294 : return makeRegisterExpression(amdgpu_gfx908::v38,0,opr_size); -case 295 : return makeRegisterExpression(amdgpu_gfx908::v39,0,opr_size); -case 296 : return makeRegisterExpression(amdgpu_gfx908::v40,0,opr_size); -case 297 : return makeRegisterExpression(amdgpu_gfx908::v41,0,opr_size); -case 298 : return makeRegisterExpression(amdgpu_gfx908::v42,0,opr_size); -case 299 : return makeRegisterExpression(amdgpu_gfx908::v43,0,opr_size); -case 300 : return makeRegisterExpression(amdgpu_gfx908::v44,0,opr_size); -case 301 : return makeRegisterExpression(amdgpu_gfx908::v45,0,opr_size); -case 302 : return makeRegisterExpression(amdgpu_gfx908::v46,0,opr_size); -case 303 : return makeRegisterExpression(amdgpu_gfx908::v47,0,opr_size); -case 304 : return makeRegisterExpression(amdgpu_gfx908::v48,0,opr_size); -case 305 : return makeRegisterExpression(amdgpu_gfx908::v49,0,opr_size); -case 306 : return makeRegisterExpression(amdgpu_gfx908::v50,0,opr_size); -case 307 : return makeRegisterExpression(amdgpu_gfx908::v51,0,opr_size); -case 308 : return makeRegisterExpression(amdgpu_gfx908::v52,0,opr_size); -case 309 : return makeRegisterExpression(amdgpu_gfx908::v53,0,opr_size); -case 310 : return makeRegisterExpression(amdgpu_gfx908::v54,0,opr_size); -case 311 : return makeRegisterExpression(amdgpu_gfx908::v55,0,opr_size); -case 312 : return makeRegisterExpression(amdgpu_gfx908::v56,0,opr_size); -case 313 : return makeRegisterExpression(amdgpu_gfx908::v57,0,opr_size); -case 314 : return makeRegisterExpression(amdgpu_gfx908::v58,0,opr_size); -case 315 : return makeRegisterExpression(amdgpu_gfx908::v59,0,opr_size); -case 316 : return makeRegisterExpression(amdgpu_gfx908::v60,0,opr_size); -case 317 : return makeRegisterExpression(amdgpu_gfx908::v61,0,opr_size); -case 318 : return makeRegisterExpression(amdgpu_gfx908::v62,0,opr_size); -case 319 : return makeRegisterExpression(amdgpu_gfx908::v63,0,opr_size); -case 320 : return makeRegisterExpression(amdgpu_gfx908::v64,0,opr_size); -case 321 : return makeRegisterExpression(amdgpu_gfx908::v65,0,opr_size); -case 322 : return makeRegisterExpression(amdgpu_gfx908::v66,0,opr_size); -case 323 : return makeRegisterExpression(amdgpu_gfx908::v67,0,opr_size); -case 324 : return makeRegisterExpression(amdgpu_gfx908::v68,0,opr_size); -case 325 : return makeRegisterExpression(amdgpu_gfx908::v69,0,opr_size); -case 326 : return makeRegisterExpression(amdgpu_gfx908::v70,0,opr_size); -case 327 : return makeRegisterExpression(amdgpu_gfx908::v71,0,opr_size); -case 328 : return makeRegisterExpression(amdgpu_gfx908::v72,0,opr_size); -case 329 : return makeRegisterExpression(amdgpu_gfx908::v73,0,opr_size); -case 330 : return makeRegisterExpression(amdgpu_gfx908::v74,0,opr_size); -case 331 : return makeRegisterExpression(amdgpu_gfx908::v75,0,opr_size); -case 332 : return makeRegisterExpression(amdgpu_gfx908::v76,0,opr_size); -case 333 : return makeRegisterExpression(amdgpu_gfx908::v77,0,opr_size); -case 334 : return makeRegisterExpression(amdgpu_gfx908::v78,0,opr_size); -case 335 : return makeRegisterExpression(amdgpu_gfx908::v79,0,opr_size); -case 336 : return makeRegisterExpression(amdgpu_gfx908::v80,0,opr_size); -case 337 : return makeRegisterExpression(amdgpu_gfx908::v81,0,opr_size); -case 338 : return makeRegisterExpression(amdgpu_gfx908::v82,0,opr_size); -case 339 : return makeRegisterExpression(amdgpu_gfx908::v83,0,opr_size); -case 340 : return makeRegisterExpression(amdgpu_gfx908::v84,0,opr_size); -case 341 : return makeRegisterExpression(amdgpu_gfx908::v85,0,opr_size); -case 342 : return makeRegisterExpression(amdgpu_gfx908::v86,0,opr_size); -case 343 : return makeRegisterExpression(amdgpu_gfx908::v87,0,opr_size); -case 344 : return makeRegisterExpression(amdgpu_gfx908::v88,0,opr_size); -case 345 : return makeRegisterExpression(amdgpu_gfx908::v89,0,opr_size); -case 346 : return makeRegisterExpression(amdgpu_gfx908::v90,0,opr_size); -case 347 : return makeRegisterExpression(amdgpu_gfx908::v91,0,opr_size); -case 348 : return makeRegisterExpression(amdgpu_gfx908::v92,0,opr_size); -case 349 : return makeRegisterExpression(amdgpu_gfx908::v93,0,opr_size); -case 350 : return makeRegisterExpression(amdgpu_gfx908::v94,0,opr_size); -case 351 : return makeRegisterExpression(amdgpu_gfx908::v95,0,opr_size); -case 352 : return makeRegisterExpression(amdgpu_gfx908::v96,0,opr_size); -case 353 : return makeRegisterExpression(amdgpu_gfx908::v97,0,opr_size); -case 354 : return makeRegisterExpression(amdgpu_gfx908::v98,0,opr_size); -case 355 : return makeRegisterExpression(amdgpu_gfx908::v99,0,opr_size); -case 356 : return makeRegisterExpression(amdgpu_gfx908::v100,0,opr_size); -case 357 : return makeRegisterExpression(amdgpu_gfx908::v101,0,opr_size); -case 358 : return makeRegisterExpression(amdgpu_gfx908::v102,0,opr_size); -case 359 : return makeRegisterExpression(amdgpu_gfx908::v103,0,opr_size); -case 360 : return makeRegisterExpression(amdgpu_gfx908::v104,0,opr_size); -case 361 : return makeRegisterExpression(amdgpu_gfx908::v105,0,opr_size); -case 362 : return makeRegisterExpression(amdgpu_gfx908::v106,0,opr_size); -case 363 : return makeRegisterExpression(amdgpu_gfx908::v107,0,opr_size); -case 364 : return makeRegisterExpression(amdgpu_gfx908::v108,0,opr_size); -case 365 : return makeRegisterExpression(amdgpu_gfx908::v109,0,opr_size); -case 366 : return makeRegisterExpression(amdgpu_gfx908::v110,0,opr_size); -case 367 : return makeRegisterExpression(amdgpu_gfx908::v111,0,opr_size); -case 368 : return makeRegisterExpression(amdgpu_gfx908::v112,0,opr_size); -case 369 : return makeRegisterExpression(amdgpu_gfx908::v113,0,opr_size); -case 370 : return makeRegisterExpression(amdgpu_gfx908::v114,0,opr_size); -case 371 : return makeRegisterExpression(amdgpu_gfx908::v115,0,opr_size); -case 372 : return makeRegisterExpression(amdgpu_gfx908::v116,0,opr_size); -case 373 : return makeRegisterExpression(amdgpu_gfx908::v117,0,opr_size); -case 374 : return makeRegisterExpression(amdgpu_gfx908::v118,0,opr_size); -case 375 : return makeRegisterExpression(amdgpu_gfx908::v119,0,opr_size); -case 376 : return makeRegisterExpression(amdgpu_gfx908::v120,0,opr_size); -case 377 : return makeRegisterExpression(amdgpu_gfx908::v121,0,opr_size); -case 378 : return makeRegisterExpression(amdgpu_gfx908::v122,0,opr_size); -case 379 : return makeRegisterExpression(amdgpu_gfx908::v123,0,opr_size); -case 380 : return makeRegisterExpression(amdgpu_gfx908::v124,0,opr_size); -case 381 : return makeRegisterExpression(amdgpu_gfx908::v125,0,opr_size); -case 382 : return makeRegisterExpression(amdgpu_gfx908::v126,0,opr_size); -case 383 : return makeRegisterExpression(amdgpu_gfx908::v127,0,opr_size); -case 384 : return makeRegisterExpression(amdgpu_gfx908::v128,0,opr_size); -case 385 : return makeRegisterExpression(amdgpu_gfx908::v129,0,opr_size); -case 386 : return makeRegisterExpression(amdgpu_gfx908::v130,0,opr_size); -case 387 : return makeRegisterExpression(amdgpu_gfx908::v131,0,opr_size); -case 388 : return makeRegisterExpression(amdgpu_gfx908::v132,0,opr_size); -case 389 : return makeRegisterExpression(amdgpu_gfx908::v133,0,opr_size); -case 390 : return makeRegisterExpression(amdgpu_gfx908::v134,0,opr_size); -case 391 : return makeRegisterExpression(amdgpu_gfx908::v135,0,opr_size); -case 392 : return makeRegisterExpression(amdgpu_gfx908::v136,0,opr_size); -case 393 : return makeRegisterExpression(amdgpu_gfx908::v137,0,opr_size); -case 394 : return makeRegisterExpression(amdgpu_gfx908::v138,0,opr_size); -case 395 : return makeRegisterExpression(amdgpu_gfx908::v139,0,opr_size); -case 396 : return makeRegisterExpression(amdgpu_gfx908::v140,0,opr_size); -case 397 : return makeRegisterExpression(amdgpu_gfx908::v141,0,opr_size); -case 398 : return makeRegisterExpression(amdgpu_gfx908::v142,0,opr_size); -case 399 : return makeRegisterExpression(amdgpu_gfx908::v143,0,opr_size); -case 400 : return makeRegisterExpression(amdgpu_gfx908::v144,0,opr_size); -case 401 : return makeRegisterExpression(amdgpu_gfx908::v145,0,opr_size); -case 402 : return makeRegisterExpression(amdgpu_gfx908::v146,0,opr_size); -case 403 : return makeRegisterExpression(amdgpu_gfx908::v147,0,opr_size); -case 404 : return makeRegisterExpression(amdgpu_gfx908::v148,0,opr_size); -case 405 : return makeRegisterExpression(amdgpu_gfx908::v149,0,opr_size); -case 406 : return makeRegisterExpression(amdgpu_gfx908::v150,0,opr_size); -case 407 : return makeRegisterExpression(amdgpu_gfx908::v151,0,opr_size); -case 408 : return makeRegisterExpression(amdgpu_gfx908::v152,0,opr_size); -case 409 : return makeRegisterExpression(amdgpu_gfx908::v153,0,opr_size); -case 410 : return makeRegisterExpression(amdgpu_gfx908::v154,0,opr_size); -case 411 : return makeRegisterExpression(amdgpu_gfx908::v155,0,opr_size); -case 412 : return makeRegisterExpression(amdgpu_gfx908::v156,0,opr_size); -case 413 : return makeRegisterExpression(amdgpu_gfx908::v157,0,opr_size); -case 414 : return makeRegisterExpression(amdgpu_gfx908::v158,0,opr_size); -case 415 : return makeRegisterExpression(amdgpu_gfx908::v159,0,opr_size); -case 416 : return makeRegisterExpression(amdgpu_gfx908::v160,0,opr_size); -case 417 : return makeRegisterExpression(amdgpu_gfx908::v161,0,opr_size); -case 418 : return makeRegisterExpression(amdgpu_gfx908::v162,0,opr_size); -case 419 : return makeRegisterExpression(amdgpu_gfx908::v163,0,opr_size); -case 420 : return makeRegisterExpression(amdgpu_gfx908::v164,0,opr_size); -case 421 : return makeRegisterExpression(amdgpu_gfx908::v165,0,opr_size); -case 422 : return makeRegisterExpression(amdgpu_gfx908::v166,0,opr_size); -case 423 : return makeRegisterExpression(amdgpu_gfx908::v167,0,opr_size); -case 424 : return makeRegisterExpression(amdgpu_gfx908::v168,0,opr_size); -case 425 : return makeRegisterExpression(amdgpu_gfx908::v169,0,opr_size); -case 426 : return makeRegisterExpression(amdgpu_gfx908::v170,0,opr_size); -case 427 : return makeRegisterExpression(amdgpu_gfx908::v171,0,opr_size); -case 428 : return makeRegisterExpression(amdgpu_gfx908::v172,0,opr_size); -case 429 : return makeRegisterExpression(amdgpu_gfx908::v173,0,opr_size); -case 430 : return makeRegisterExpression(amdgpu_gfx908::v174,0,opr_size); -case 431 : return makeRegisterExpression(amdgpu_gfx908::v175,0,opr_size); -case 432 : return makeRegisterExpression(amdgpu_gfx908::v176,0,opr_size); -case 433 : return makeRegisterExpression(amdgpu_gfx908::v177,0,opr_size); -case 434 : return makeRegisterExpression(amdgpu_gfx908::v178,0,opr_size); -case 435 : return makeRegisterExpression(amdgpu_gfx908::v179,0,opr_size); -case 436 : return makeRegisterExpression(amdgpu_gfx908::v180,0,opr_size); -case 437 : return makeRegisterExpression(amdgpu_gfx908::v181,0,opr_size); -case 438 : return makeRegisterExpression(amdgpu_gfx908::v182,0,opr_size); -case 439 : return makeRegisterExpression(amdgpu_gfx908::v183,0,opr_size); -case 440 : return makeRegisterExpression(amdgpu_gfx908::v184,0,opr_size); -case 441 : return makeRegisterExpression(amdgpu_gfx908::v185,0,opr_size); -case 442 : return makeRegisterExpression(amdgpu_gfx908::v186,0,opr_size); -case 443 : return makeRegisterExpression(amdgpu_gfx908::v187,0,opr_size); -case 444 : return makeRegisterExpression(amdgpu_gfx908::v188,0,opr_size); -case 445 : return makeRegisterExpression(amdgpu_gfx908::v189,0,opr_size); -case 446 : return makeRegisterExpression(amdgpu_gfx908::v190,0,opr_size); -case 447 : return makeRegisterExpression(amdgpu_gfx908::v191,0,opr_size); -case 448 : return makeRegisterExpression(amdgpu_gfx908::v192,0,opr_size); -case 449 : return makeRegisterExpression(amdgpu_gfx908::v193,0,opr_size); -case 450 : return makeRegisterExpression(amdgpu_gfx908::v194,0,opr_size); -case 451 : return makeRegisterExpression(amdgpu_gfx908::v195,0,opr_size); -case 452 : return makeRegisterExpression(amdgpu_gfx908::v196,0,opr_size); -case 453 : return makeRegisterExpression(amdgpu_gfx908::v197,0,opr_size); -case 454 : return makeRegisterExpression(amdgpu_gfx908::v198,0,opr_size); -case 455 : return makeRegisterExpression(amdgpu_gfx908::v199,0,opr_size); -case 456 : return makeRegisterExpression(amdgpu_gfx908::v200,0,opr_size); -case 457 : return makeRegisterExpression(amdgpu_gfx908::v201,0,opr_size); -case 458 : return makeRegisterExpression(amdgpu_gfx908::v202,0,opr_size); -case 459 : return makeRegisterExpression(amdgpu_gfx908::v203,0,opr_size); -case 460 : return makeRegisterExpression(amdgpu_gfx908::v204,0,opr_size); -case 461 : return makeRegisterExpression(amdgpu_gfx908::v205,0,opr_size); -case 462 : return makeRegisterExpression(amdgpu_gfx908::v206,0,opr_size); -case 463 : return makeRegisterExpression(amdgpu_gfx908::v207,0,opr_size); -case 464 : return makeRegisterExpression(amdgpu_gfx908::v208,0,opr_size); -case 465 : return makeRegisterExpression(amdgpu_gfx908::v209,0,opr_size); -case 466 : return makeRegisterExpression(amdgpu_gfx908::v210,0,opr_size); -case 467 : return makeRegisterExpression(amdgpu_gfx908::v211,0,opr_size); -case 468 : return makeRegisterExpression(amdgpu_gfx908::v212,0,opr_size); -case 469 : return makeRegisterExpression(amdgpu_gfx908::v213,0,opr_size); -case 470 : return makeRegisterExpression(amdgpu_gfx908::v214,0,opr_size); -case 471 : return makeRegisterExpression(amdgpu_gfx908::v215,0,opr_size); -case 472 : return makeRegisterExpression(amdgpu_gfx908::v216,0,opr_size); -case 473 : return makeRegisterExpression(amdgpu_gfx908::v217,0,opr_size); -case 474 : return makeRegisterExpression(amdgpu_gfx908::v218,0,opr_size); -case 475 : return makeRegisterExpression(amdgpu_gfx908::v219,0,opr_size); -case 476 : return makeRegisterExpression(amdgpu_gfx908::v220,0,opr_size); -case 477 : return makeRegisterExpression(amdgpu_gfx908::v221,0,opr_size); -case 478 : return makeRegisterExpression(amdgpu_gfx908::v222,0,opr_size); -case 479 : return makeRegisterExpression(amdgpu_gfx908::v223,0,opr_size); -case 480 : return makeRegisterExpression(amdgpu_gfx908::v224,0,opr_size); -case 481 : return makeRegisterExpression(amdgpu_gfx908::v225,0,opr_size); -case 482 : return makeRegisterExpression(amdgpu_gfx908::v226,0,opr_size); -case 483 : return makeRegisterExpression(amdgpu_gfx908::v227,0,opr_size); -case 484 : return makeRegisterExpression(amdgpu_gfx908::v228,0,opr_size); -case 485 : return makeRegisterExpression(amdgpu_gfx908::v229,0,opr_size); -case 486 : return makeRegisterExpression(amdgpu_gfx908::v230,0,opr_size); -case 487 : return makeRegisterExpression(amdgpu_gfx908::v231,0,opr_size); -case 488 : return makeRegisterExpression(amdgpu_gfx908::v232,0,opr_size); -case 489 : return makeRegisterExpression(amdgpu_gfx908::v233,0,opr_size); -case 490 : return makeRegisterExpression(amdgpu_gfx908::v234,0,opr_size); -case 491 : return makeRegisterExpression(amdgpu_gfx908::v235,0,opr_size); -case 492 : return makeRegisterExpression(amdgpu_gfx908::v236,0,opr_size); -case 493 : return makeRegisterExpression(amdgpu_gfx908::v237,0,opr_size); -case 494 : return makeRegisterExpression(amdgpu_gfx908::v238,0,opr_size); -case 495 : return makeRegisterExpression(amdgpu_gfx908::v239,0,opr_size); -case 496 : return makeRegisterExpression(amdgpu_gfx908::v240,0,opr_size); -case 497 : return makeRegisterExpression(amdgpu_gfx908::v241,0,opr_size); -case 498 : return makeRegisterExpression(amdgpu_gfx908::v242,0,opr_size); -case 499 : return makeRegisterExpression(amdgpu_gfx908::v243,0,opr_size); -case 500 : return makeRegisterExpression(amdgpu_gfx908::v244,0,opr_size); -case 501 : return makeRegisterExpression(amdgpu_gfx908::v245,0,opr_size); -case 502 : return makeRegisterExpression(amdgpu_gfx908::v246,0,opr_size); -case 503 : return makeRegisterExpression(amdgpu_gfx908::v247,0,opr_size); -case 504 : return makeRegisterExpression(amdgpu_gfx908::v248,0,opr_size); -case 505 : return makeRegisterExpression(amdgpu_gfx908::v249,0,opr_size); -case 506 : return makeRegisterExpression(amdgpu_gfx908::v250,0,opr_size); -case 507 : return makeRegisterExpression(amdgpu_gfx908::v251,0,opr_size); -case 508 : return makeRegisterExpression(amdgpu_gfx908::v252,0,opr_size); -case 509 : return makeRegisterExpression(amdgpu_gfx908::v253,0,opr_size); -case 510 : return makeRegisterExpression(amdgpu_gfx908::v254,0,opr_size); -case 511 : return makeRegisterExpression(amdgpu_gfx908::v255,0,opr_size); +case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elements ); +case 256 : return makeRegisterExpression(amdgpu_gfx908::v0, num_elements ); +case 257 : return makeRegisterExpression(amdgpu_gfx908::v1, num_elements ); +case 258 : return makeRegisterExpression(amdgpu_gfx908::v2, num_elements ); +case 259 : return makeRegisterExpression(amdgpu_gfx908::v3, num_elements ); +case 260 : return makeRegisterExpression(amdgpu_gfx908::v4, num_elements ); +case 261 : return makeRegisterExpression(amdgpu_gfx908::v5, num_elements ); +case 262 : return makeRegisterExpression(amdgpu_gfx908::v6, num_elements ); +case 263 : return makeRegisterExpression(amdgpu_gfx908::v7, num_elements ); +case 264 : return makeRegisterExpression(amdgpu_gfx908::v8, num_elements ); +case 265 : return makeRegisterExpression(amdgpu_gfx908::v9, num_elements ); +case 266 : return makeRegisterExpression(amdgpu_gfx908::v10, num_elements ); +case 267 : return makeRegisterExpression(amdgpu_gfx908::v11, num_elements ); +case 268 : return makeRegisterExpression(amdgpu_gfx908::v12, num_elements ); +case 269 : return makeRegisterExpression(amdgpu_gfx908::v13, num_elements ); +case 270 : return makeRegisterExpression(amdgpu_gfx908::v14, num_elements ); +case 271 : return makeRegisterExpression(amdgpu_gfx908::v15, num_elements ); +case 272 : return makeRegisterExpression(amdgpu_gfx908::v16, num_elements ); +case 273 : return makeRegisterExpression(amdgpu_gfx908::v17, num_elements ); +case 274 : return makeRegisterExpression(amdgpu_gfx908::v18, num_elements ); +case 275 : return makeRegisterExpression(amdgpu_gfx908::v19, num_elements ); +case 276 : return makeRegisterExpression(amdgpu_gfx908::v20, num_elements ); +case 277 : return makeRegisterExpression(amdgpu_gfx908::v21, num_elements ); +case 278 : return makeRegisterExpression(amdgpu_gfx908::v22, num_elements ); +case 279 : return makeRegisterExpression(amdgpu_gfx908::v23, num_elements ); +case 280 : return makeRegisterExpression(amdgpu_gfx908::v24, num_elements ); +case 281 : return makeRegisterExpression(amdgpu_gfx908::v25, num_elements ); +case 282 : return makeRegisterExpression(amdgpu_gfx908::v26, num_elements ); +case 283 : return makeRegisterExpression(amdgpu_gfx908::v27, num_elements ); +case 284 : return makeRegisterExpression(amdgpu_gfx908::v28, num_elements ); +case 285 : return makeRegisterExpression(amdgpu_gfx908::v29, num_elements ); +case 286 : return makeRegisterExpression(amdgpu_gfx908::v30, num_elements ); +case 287 : return makeRegisterExpression(amdgpu_gfx908::v31, num_elements ); +case 288 : return makeRegisterExpression(amdgpu_gfx908::v32, num_elements ); +case 289 : return makeRegisterExpression(amdgpu_gfx908::v33, num_elements ); +case 290 : return makeRegisterExpression(amdgpu_gfx908::v34, num_elements ); +case 291 : return makeRegisterExpression(amdgpu_gfx908::v35, num_elements ); +case 292 : return makeRegisterExpression(amdgpu_gfx908::v36, num_elements ); +case 293 : return makeRegisterExpression(amdgpu_gfx908::v37, num_elements ); +case 294 : return makeRegisterExpression(amdgpu_gfx908::v38, num_elements ); +case 295 : return makeRegisterExpression(amdgpu_gfx908::v39, num_elements ); +case 296 : return makeRegisterExpression(amdgpu_gfx908::v40, num_elements ); +case 297 : return makeRegisterExpression(amdgpu_gfx908::v41, num_elements ); +case 298 : return makeRegisterExpression(amdgpu_gfx908::v42, num_elements ); +case 299 : return makeRegisterExpression(amdgpu_gfx908::v43, num_elements ); +case 300 : return makeRegisterExpression(amdgpu_gfx908::v44, num_elements ); +case 301 : return makeRegisterExpression(amdgpu_gfx908::v45, num_elements ); +case 302 : return makeRegisterExpression(amdgpu_gfx908::v46, num_elements ); +case 303 : return makeRegisterExpression(amdgpu_gfx908::v47, num_elements ); +case 304 : return makeRegisterExpression(amdgpu_gfx908::v48, num_elements ); +case 305 : return makeRegisterExpression(amdgpu_gfx908::v49, num_elements ); +case 306 : return makeRegisterExpression(amdgpu_gfx908::v50, num_elements ); +case 307 : return makeRegisterExpression(amdgpu_gfx908::v51, num_elements ); +case 308 : return makeRegisterExpression(amdgpu_gfx908::v52, num_elements ); +case 309 : return makeRegisterExpression(amdgpu_gfx908::v53, num_elements ); +case 310 : return makeRegisterExpression(amdgpu_gfx908::v54, num_elements ); +case 311 : return makeRegisterExpression(amdgpu_gfx908::v55, num_elements ); +case 312 : return makeRegisterExpression(amdgpu_gfx908::v56, num_elements ); +case 313 : return makeRegisterExpression(amdgpu_gfx908::v57, num_elements ); +case 314 : return makeRegisterExpression(amdgpu_gfx908::v58, num_elements ); +case 315 : return makeRegisterExpression(amdgpu_gfx908::v59, num_elements ); +case 316 : return makeRegisterExpression(amdgpu_gfx908::v60, num_elements ); +case 317 : return makeRegisterExpression(amdgpu_gfx908::v61, num_elements ); +case 318 : return makeRegisterExpression(amdgpu_gfx908::v62, num_elements ); +case 319 : return makeRegisterExpression(amdgpu_gfx908::v63, num_elements ); +case 320 : return makeRegisterExpression(amdgpu_gfx908::v64, num_elements ); +case 321 : return makeRegisterExpression(amdgpu_gfx908::v65, num_elements ); +case 322 : return makeRegisterExpression(amdgpu_gfx908::v66, num_elements ); +case 323 : return makeRegisterExpression(amdgpu_gfx908::v67, num_elements ); +case 324 : return makeRegisterExpression(amdgpu_gfx908::v68, num_elements ); +case 325 : return makeRegisterExpression(amdgpu_gfx908::v69, num_elements ); +case 326 : return makeRegisterExpression(amdgpu_gfx908::v70, num_elements ); +case 327 : return makeRegisterExpression(amdgpu_gfx908::v71, num_elements ); +case 328 : return makeRegisterExpression(amdgpu_gfx908::v72, num_elements ); +case 329 : return makeRegisterExpression(amdgpu_gfx908::v73, num_elements ); +case 330 : return makeRegisterExpression(amdgpu_gfx908::v74, num_elements ); +case 331 : return makeRegisterExpression(amdgpu_gfx908::v75, num_elements ); +case 332 : return makeRegisterExpression(amdgpu_gfx908::v76, num_elements ); +case 333 : return makeRegisterExpression(amdgpu_gfx908::v77, num_elements ); +case 334 : return makeRegisterExpression(amdgpu_gfx908::v78, num_elements ); +case 335 : return makeRegisterExpression(amdgpu_gfx908::v79, num_elements ); +case 336 : return makeRegisterExpression(amdgpu_gfx908::v80, num_elements ); +case 337 : return makeRegisterExpression(amdgpu_gfx908::v81, num_elements ); +case 338 : return makeRegisterExpression(amdgpu_gfx908::v82, num_elements ); +case 339 : return makeRegisterExpression(amdgpu_gfx908::v83, num_elements ); +case 340 : return makeRegisterExpression(amdgpu_gfx908::v84, num_elements ); +case 341 : return makeRegisterExpression(amdgpu_gfx908::v85, num_elements ); +case 342 : return makeRegisterExpression(amdgpu_gfx908::v86, num_elements ); +case 343 : return makeRegisterExpression(amdgpu_gfx908::v87, num_elements ); +case 344 : return makeRegisterExpression(amdgpu_gfx908::v88, num_elements ); +case 345 : return makeRegisterExpression(amdgpu_gfx908::v89, num_elements ); +case 346 : return makeRegisterExpression(amdgpu_gfx908::v90, num_elements ); +case 347 : return makeRegisterExpression(amdgpu_gfx908::v91, num_elements ); +case 348 : return makeRegisterExpression(amdgpu_gfx908::v92, num_elements ); +case 349 : return makeRegisterExpression(amdgpu_gfx908::v93, num_elements ); +case 350 : return makeRegisterExpression(amdgpu_gfx908::v94, num_elements ); +case 351 : return makeRegisterExpression(amdgpu_gfx908::v95, num_elements ); +case 352 : return makeRegisterExpression(amdgpu_gfx908::v96, num_elements ); +case 353 : return makeRegisterExpression(amdgpu_gfx908::v97, num_elements ); +case 354 : return makeRegisterExpression(amdgpu_gfx908::v98, num_elements ); +case 355 : return makeRegisterExpression(amdgpu_gfx908::v99, num_elements ); +case 356 : return makeRegisterExpression(amdgpu_gfx908::v100, num_elements ); +case 357 : return makeRegisterExpression(amdgpu_gfx908::v101, num_elements ); +case 358 : return makeRegisterExpression(amdgpu_gfx908::v102, num_elements ); +case 359 : return makeRegisterExpression(amdgpu_gfx908::v103, num_elements ); +case 360 : return makeRegisterExpression(amdgpu_gfx908::v104, num_elements ); +case 361 : return makeRegisterExpression(amdgpu_gfx908::v105, num_elements ); +case 362 : return makeRegisterExpression(amdgpu_gfx908::v106, num_elements ); +case 363 : return makeRegisterExpression(amdgpu_gfx908::v107, num_elements ); +case 364 : return makeRegisterExpression(amdgpu_gfx908::v108, num_elements ); +case 365 : return makeRegisterExpression(amdgpu_gfx908::v109, num_elements ); +case 366 : return makeRegisterExpression(amdgpu_gfx908::v110, num_elements ); +case 367 : return makeRegisterExpression(amdgpu_gfx908::v111, num_elements ); +case 368 : return makeRegisterExpression(amdgpu_gfx908::v112, num_elements ); +case 369 : return makeRegisterExpression(amdgpu_gfx908::v113, num_elements ); +case 370 : return makeRegisterExpression(amdgpu_gfx908::v114, num_elements ); +case 371 : return makeRegisterExpression(amdgpu_gfx908::v115, num_elements ); +case 372 : return makeRegisterExpression(amdgpu_gfx908::v116, num_elements ); +case 373 : return makeRegisterExpression(amdgpu_gfx908::v117, num_elements ); +case 374 : return makeRegisterExpression(amdgpu_gfx908::v118, num_elements ); +case 375 : return makeRegisterExpression(amdgpu_gfx908::v119, num_elements ); +case 376 : return makeRegisterExpression(amdgpu_gfx908::v120, num_elements ); +case 377 : return makeRegisterExpression(amdgpu_gfx908::v121, num_elements ); +case 378 : return makeRegisterExpression(amdgpu_gfx908::v122, num_elements ); +case 379 : return makeRegisterExpression(amdgpu_gfx908::v123, num_elements ); +case 380 : return makeRegisterExpression(amdgpu_gfx908::v124, num_elements ); +case 381 : return makeRegisterExpression(amdgpu_gfx908::v125, num_elements ); +case 382 : return makeRegisterExpression(amdgpu_gfx908::v126, num_elements ); +case 383 : return makeRegisterExpression(amdgpu_gfx908::v127, num_elements ); +case 384 : return makeRegisterExpression(amdgpu_gfx908::v128, num_elements ); +case 385 : return makeRegisterExpression(amdgpu_gfx908::v129, num_elements ); +case 386 : return makeRegisterExpression(amdgpu_gfx908::v130, num_elements ); +case 387 : return makeRegisterExpression(amdgpu_gfx908::v131, num_elements ); +case 388 : return makeRegisterExpression(amdgpu_gfx908::v132, num_elements ); +case 389 : return makeRegisterExpression(amdgpu_gfx908::v133, num_elements ); +case 390 : return makeRegisterExpression(amdgpu_gfx908::v134, num_elements ); +case 391 : return makeRegisterExpression(amdgpu_gfx908::v135, num_elements ); +case 392 : return makeRegisterExpression(amdgpu_gfx908::v136, num_elements ); +case 393 : return makeRegisterExpression(amdgpu_gfx908::v137, num_elements ); +case 394 : return makeRegisterExpression(amdgpu_gfx908::v138, num_elements ); +case 395 : return makeRegisterExpression(amdgpu_gfx908::v139, num_elements ); +case 396 : return makeRegisterExpression(amdgpu_gfx908::v140, num_elements ); +case 397 : return makeRegisterExpression(amdgpu_gfx908::v141, num_elements ); +case 398 : return makeRegisterExpression(amdgpu_gfx908::v142, num_elements ); +case 399 : return makeRegisterExpression(amdgpu_gfx908::v143, num_elements ); +case 400 : return makeRegisterExpression(amdgpu_gfx908::v144, num_elements ); +case 401 : return makeRegisterExpression(amdgpu_gfx908::v145, num_elements ); +case 402 : return makeRegisterExpression(amdgpu_gfx908::v146, num_elements ); +case 403 : return makeRegisterExpression(amdgpu_gfx908::v147, num_elements ); +case 404 : return makeRegisterExpression(amdgpu_gfx908::v148, num_elements ); +case 405 : return makeRegisterExpression(amdgpu_gfx908::v149, num_elements ); +case 406 : return makeRegisterExpression(amdgpu_gfx908::v150, num_elements ); +case 407 : return makeRegisterExpression(amdgpu_gfx908::v151, num_elements ); +case 408 : return makeRegisterExpression(amdgpu_gfx908::v152, num_elements ); +case 409 : return makeRegisterExpression(amdgpu_gfx908::v153, num_elements ); +case 410 : return makeRegisterExpression(amdgpu_gfx908::v154, num_elements ); +case 411 : return makeRegisterExpression(amdgpu_gfx908::v155, num_elements ); +case 412 : return makeRegisterExpression(amdgpu_gfx908::v156, num_elements ); +case 413 : return makeRegisterExpression(amdgpu_gfx908::v157, num_elements ); +case 414 : return makeRegisterExpression(amdgpu_gfx908::v158, num_elements ); +case 415 : return makeRegisterExpression(amdgpu_gfx908::v159, num_elements ); +case 416 : return makeRegisterExpression(amdgpu_gfx908::v160, num_elements ); +case 417 : return makeRegisterExpression(amdgpu_gfx908::v161, num_elements ); +case 418 : return makeRegisterExpression(amdgpu_gfx908::v162, num_elements ); +case 419 : return makeRegisterExpression(amdgpu_gfx908::v163, num_elements ); +case 420 : return makeRegisterExpression(amdgpu_gfx908::v164, num_elements ); +case 421 : return makeRegisterExpression(amdgpu_gfx908::v165, num_elements ); +case 422 : return makeRegisterExpression(amdgpu_gfx908::v166, num_elements ); +case 423 : return makeRegisterExpression(amdgpu_gfx908::v167, num_elements ); +case 424 : return makeRegisterExpression(amdgpu_gfx908::v168, num_elements ); +case 425 : return makeRegisterExpression(amdgpu_gfx908::v169, num_elements ); +case 426 : return makeRegisterExpression(amdgpu_gfx908::v170, num_elements ); +case 427 : return makeRegisterExpression(amdgpu_gfx908::v171, num_elements ); +case 428 : return makeRegisterExpression(amdgpu_gfx908::v172, num_elements ); +case 429 : return makeRegisterExpression(amdgpu_gfx908::v173, num_elements ); +case 430 : return makeRegisterExpression(amdgpu_gfx908::v174, num_elements ); +case 431 : return makeRegisterExpression(amdgpu_gfx908::v175, num_elements ); +case 432 : return makeRegisterExpression(amdgpu_gfx908::v176, num_elements ); +case 433 : return makeRegisterExpression(amdgpu_gfx908::v177, num_elements ); +case 434 : return makeRegisterExpression(amdgpu_gfx908::v178, num_elements ); +case 435 : return makeRegisterExpression(amdgpu_gfx908::v179, num_elements ); +case 436 : return makeRegisterExpression(amdgpu_gfx908::v180, num_elements ); +case 437 : return makeRegisterExpression(amdgpu_gfx908::v181, num_elements ); +case 438 : return makeRegisterExpression(amdgpu_gfx908::v182, num_elements ); +case 439 : return makeRegisterExpression(amdgpu_gfx908::v183, num_elements ); +case 440 : return makeRegisterExpression(amdgpu_gfx908::v184, num_elements ); +case 441 : return makeRegisterExpression(amdgpu_gfx908::v185, num_elements ); +case 442 : return makeRegisterExpression(amdgpu_gfx908::v186, num_elements ); +case 443 : return makeRegisterExpression(amdgpu_gfx908::v187, num_elements ); +case 444 : return makeRegisterExpression(amdgpu_gfx908::v188, num_elements ); +case 445 : return makeRegisterExpression(amdgpu_gfx908::v189, num_elements ); +case 446 : return makeRegisterExpression(amdgpu_gfx908::v190, num_elements ); +case 447 : return makeRegisterExpression(amdgpu_gfx908::v191, num_elements ); +case 448 : return makeRegisterExpression(amdgpu_gfx908::v192, num_elements ); +case 449 : return makeRegisterExpression(amdgpu_gfx908::v193, num_elements ); +case 450 : return makeRegisterExpression(amdgpu_gfx908::v194, num_elements ); +case 451 : return makeRegisterExpression(amdgpu_gfx908::v195, num_elements ); +case 452 : return makeRegisterExpression(amdgpu_gfx908::v196, num_elements ); +case 453 : return makeRegisterExpression(amdgpu_gfx908::v197, num_elements ); +case 454 : return makeRegisterExpression(amdgpu_gfx908::v198, num_elements ); +case 455 : return makeRegisterExpression(amdgpu_gfx908::v199, num_elements ); +case 456 : return makeRegisterExpression(amdgpu_gfx908::v200, num_elements ); +case 457 : return makeRegisterExpression(amdgpu_gfx908::v201, num_elements ); +case 458 : return makeRegisterExpression(amdgpu_gfx908::v202, num_elements ); +case 459 : return makeRegisterExpression(amdgpu_gfx908::v203, num_elements ); +case 460 : return makeRegisterExpression(amdgpu_gfx908::v204, num_elements ); +case 461 : return makeRegisterExpression(amdgpu_gfx908::v205, num_elements ); +case 462 : return makeRegisterExpression(amdgpu_gfx908::v206, num_elements ); +case 463 : return makeRegisterExpression(amdgpu_gfx908::v207, num_elements ); +case 464 : return makeRegisterExpression(amdgpu_gfx908::v208, num_elements ); +case 465 : return makeRegisterExpression(amdgpu_gfx908::v209, num_elements ); +case 466 : return makeRegisterExpression(amdgpu_gfx908::v210, num_elements ); +case 467 : return makeRegisterExpression(amdgpu_gfx908::v211, num_elements ); +case 468 : return makeRegisterExpression(amdgpu_gfx908::v212, num_elements ); +case 469 : return makeRegisterExpression(amdgpu_gfx908::v213, num_elements ); +case 470 : return makeRegisterExpression(amdgpu_gfx908::v214, num_elements ); +case 471 : return makeRegisterExpression(amdgpu_gfx908::v215, num_elements ); +case 472 : return makeRegisterExpression(amdgpu_gfx908::v216, num_elements ); +case 473 : return makeRegisterExpression(amdgpu_gfx908::v217, num_elements ); +case 474 : return makeRegisterExpression(amdgpu_gfx908::v218, num_elements ); +case 475 : return makeRegisterExpression(amdgpu_gfx908::v219, num_elements ); +case 476 : return makeRegisterExpression(amdgpu_gfx908::v220, num_elements ); +case 477 : return makeRegisterExpression(amdgpu_gfx908::v221, num_elements ); +case 478 : return makeRegisterExpression(amdgpu_gfx908::v222, num_elements ); +case 479 : return makeRegisterExpression(amdgpu_gfx908::v223, num_elements ); +case 480 : return makeRegisterExpression(amdgpu_gfx908::v224, num_elements ); +case 481 : return makeRegisterExpression(amdgpu_gfx908::v225, num_elements ); +case 482 : return makeRegisterExpression(amdgpu_gfx908::v226, num_elements ); +case 483 : return makeRegisterExpression(amdgpu_gfx908::v227, num_elements ); +case 484 : return makeRegisterExpression(amdgpu_gfx908::v228, num_elements ); +case 485 : return makeRegisterExpression(amdgpu_gfx908::v229, num_elements ); +case 486 : return makeRegisterExpression(amdgpu_gfx908::v230, num_elements ); +case 487 : return makeRegisterExpression(amdgpu_gfx908::v231, num_elements ); +case 488 : return makeRegisterExpression(amdgpu_gfx908::v232, num_elements ); +case 489 : return makeRegisterExpression(amdgpu_gfx908::v233, num_elements ); +case 490 : return makeRegisterExpression(amdgpu_gfx908::v234, num_elements ); +case 491 : return makeRegisterExpression(amdgpu_gfx908::v235, num_elements ); +case 492 : return makeRegisterExpression(amdgpu_gfx908::v236, num_elements ); +case 493 : return makeRegisterExpression(amdgpu_gfx908::v237, num_elements ); +case 494 : return makeRegisterExpression(amdgpu_gfx908::v238, num_elements ); +case 495 : return makeRegisterExpression(amdgpu_gfx908::v239, num_elements ); +case 496 : return makeRegisterExpression(amdgpu_gfx908::v240, num_elements ); +case 497 : return makeRegisterExpression(amdgpu_gfx908::v241, num_elements ); +case 498 : return makeRegisterExpression(amdgpu_gfx908::v242, num_elements ); +case 499 : return makeRegisterExpression(amdgpu_gfx908::v243, num_elements ); +case 500 : return makeRegisterExpression(amdgpu_gfx908::v244, num_elements ); +case 501 : return makeRegisterExpression(amdgpu_gfx908::v245, num_elements ); +case 502 : return makeRegisterExpression(amdgpu_gfx908::v246, num_elements ); +case 503 : return makeRegisterExpression(amdgpu_gfx908::v247, num_elements ); +case 504 : return makeRegisterExpression(amdgpu_gfx908::v248, num_elements ); +case 505 : return makeRegisterExpression(amdgpu_gfx908::v249, num_elements ); +case 506 : return makeRegisterExpression(amdgpu_gfx908::v250, num_elements ); +case 507 : return makeRegisterExpression(amdgpu_gfx908::v251, num_elements ); +case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); +case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); +case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); +case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t num_elements){ switch(input){ -case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo,0,opr_size); -case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi,0,opr_size); +case 104 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, num_elements ); +case 105 : return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, num_elements ); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h index 810717a586..dadf2f8f7d 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.h @@ -1,41 +1,41 @@ -Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_FLAT_SCRATCH_LOHI(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SGPR(uint64_t input, uint32_t num_elements = 1 ); void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout ); -Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t opr_size ); -Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t opr_size ); +Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_0_63_INLINES(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_INLINES(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_APERTURE(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_EXECZ(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LDS(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_NOLIT(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_POPS_EXITING_WAVE_ID(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_SSRC_SPECIAL_VCCZ(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_TRAP(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_VCC_LOHI(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t num_elements = 1 ); +Expression::Ptr decodeOPR_XNACK_MASK_LOHI(uint64_t input, uint32_t num_elements = 1 ); diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index d141a8e453..499b9f9c83 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -3,147 +3,147 @@ layout_ENC_DS & layout = insn_layout.ENC_DS; switch(layout.OP){ case 0:case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 13:case 18:case 19:case 21:case 30:case 31:case 84:case 85: //DS_ADD_U32,DS_SUB_U32,DS_RSUB_U32,DS_INC_U32,DS_DEC_U32,DS_MIN_I32,DS_MAX_I32,DS_MIN_U32,DS_MAX_U32,DS_AND_B32,DS_OR_B32,DS_XOR_B32,DS_WRITE_B32,DS_MIN_F32,DS_MAX_F32,DS_ADD_F32,DS_WRITE_B8,DS_WRITE_B16,DS_WRITE_B8_D16_HI,DS_WRITE_B16_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); break; case 12:case 14:case 15:case 16:case 17: //DS_MSKOR_B32,DS_WRITE2_B32,DS_WRITE2ST64_B32,DS_CMPST_B32,DS_CMPST_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1),true,false); break; case 20: //DS_NOP break; case 29:case 153:case 155:case 157: //DS_WRITE_ADDTID_B32,DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 45:case 50:case 51:case 53:case 62:case 63: //DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32,DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32,DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32,DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32,DS_PERMUTE_B32,DS_BPERMUTE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); break; case 44:case 48:case 49:case 52: //DS_MSKOR_RTN_B32,DS_CMPST_RTN_B32,DS_CMPST_RTN_F32,DS_WRAP_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1),true,false); break; case 46:case 47: //DS_WRXCHG2_RTN_B32,DS_WRXCHG2ST64_RTN_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1),true,false); break; case 54:case 57:case 58:case 59:case 60:case 61:case 86:case 87:case 88:case 89:case 90:case 91: //DS_READ_B32,DS_READ_I8,DS_READ_U8,DS_READ_I16,DS_READ_U16,DS_SWIZZLE_B32,DS_READ_U8_D16,DS_READ_U8_D16_HI,DS_READ_I8_D16,DS_READ_I8_D16_HI,DS_READ_U16_D16,DS_READ_U16_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; case 55:case 56:case 118: //DS_READ2_B32,DS_READ2ST64_B32,DS_READ_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 77:case 82:case 83: //DS_ADD_U64,DS_SUB_U64,DS_RSUB_U64,DS_INC_U64,DS_DEC_U64,DS_MIN_I64,DS_MAX_I64,DS_MIN_U64,DS_MAX_U64,DS_AND_B64,DS_OR_B64,DS_XOR_B64,DS_WRITE_B64,DS_MIN_F64,DS_MAX_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); break; case 76:case 78:case 79:case 80:case 81: //DS_MSKOR_B64,DS_WRITE2_B64,DS_WRITE2ST64_B64,DS_CMPST_B64,DS_CMPST_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,0),true,false); break; case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 109:case 114:case 115:case 126: //DS_ADD_RTN_U64,DS_SUB_RTN_U64,DS_RSUB_RTN_U64,DS_INC_RTN_U64,DS_DEC_RTN_U64,DS_MIN_RTN_I64,DS_MAX_RTN_I64,DS_MIN_RTN_U64,DS_MAX_RTN_U64,DS_AND_RTN_B64,DS_OR_RTN_B64,DS_XOR_RTN_B64,DS_WRXCHG_RTN_B64,DS_MIN_RTN_F64,DS_MAX_RTN_F64,DS_CONDXCHG32_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); break; case 108:case 112:case 113: //DS_MSKOR_RTN_B64,DS_CMPST_RTN_B64,DS_CMPST_RTN_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,0),true,false); break; case 110:case 111: //DS_WRXCHG2_RTN_B64,DS_WRXCHG2ST64_RTN_B64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA1+1,0),true,false); break; case 119:case 120:case 255: //DS_READ2_B64,DS_READ2ST64_B64,DS_READ_B128 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; case 128:case 129:case 130:case 131:case 132:case 133:case 134:case 135:case 136:case 137:case 138:case 139:case 141:case 146:case 147:case 149:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 205:case 210:case 211: //DS_ADD_SRC2_U32,DS_SUB_SRC2_U32,DS_RSUB_SRC2_U32,DS_INC_SRC2_U32,DS_DEC_SRC2_U32,DS_MIN_SRC2_I32,DS_MAX_SRC2_I32,DS_MIN_SRC2_U32,DS_MAX_SRC2_U32,DS_AND_SRC2_B32,DS_OR_SRC2_B32,DS_XOR_SRC2_B32,DS_WRITE_SRC2_B32,DS_MIN_SRC2_F32,DS_MAX_SRC2_F32,DS_ADD_SRC2_F32,DS_ADD_SRC2_U64,DS_SUB_SRC2_U64,DS_RSUB_SRC2_U64,DS_INC_SRC2_U64,DS_DEC_SRC2_U64,DS_MIN_SRC2_I64,DS_MAX_SRC2_I64,DS_MIN_SRC2_U64,DS_MAX_SRC2_U64,DS_AND_SRC2_B64,DS_OR_SRC2_B64,DS_XOR_SRC2_B64,DS_WRITE_SRC2_B64,DS_MIN_SRC2_F64,DS_MAX_SRC2_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; case 152:case 154:case 156: //DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 182:case 189:case 190: //DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 191: //DS_ORDERED_COUNT -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 222: //DS_WRITE_B96 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,0),true,false); break; case 223: //DS_WRITE_B128 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0+3,0),true,false); break; case 254: //DS_READ_B96 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; } } @@ -152,114 +152,136 @@ layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; switch(layout.OP){ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: //FLAT_LOAD_UBYTE,FLAT_LOAD_SBYTE,FLAT_LOAD_USHORT,FLAT_LOAD_SSHORT,FLAT_LOAD_DWORD,FLAT_LOAD_UBYTE_D16,FLAT_LOAD_UBYTE_D16_HI,FLAT_LOAD_SBYTE_D16,FLAT_LOAD_SBYTE_D16_HI,FLAT_LOAD_SHORT_D16,FLAT_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 21: //FLAT_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 22: //FLAT_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 23: //FLAT_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 24:case 25:case 26:case 27:case 28: //FLAT_STORE_BYTE,FLAT_STORE_BYTE_D16_HI,FLAT_STORE_SHORT,FLAT_STORE_SHORT_D16_HI,FLAT_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 29: //FLAT_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 30: //FLAT_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 31: //FLAT_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76: //FLAT_ATOMIC_SWAP,FLAT_ATOMIC_ADD,FLAT_ATOMIC_SUB,FLAT_ATOMIC_SMIN,FLAT_ATOMIC_UMIN,FLAT_ATOMIC_SMAX,FLAT_ATOMIC_UMAX,FLAT_ATOMIC_AND,FLAT_ATOMIC_OR,FLAT_ATOMIC_XOR,FLAT_ATOMIC_INC,FLAT_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: //FLAT_ATOMIC_CMPSWAP,FLAT_ATOMIC_SWAP_X2,FLAT_ATOMIC_ADD_X2,FLAT_ATOMIC_SUB_X2,FLAT_ATOMIC_SMIN_X2,FLAT_ATOMIC_UMIN_X2,FLAT_ATOMIC_SMAX_X2,FLAT_ATOMIC_UMAX_X2,FLAT_ATOMIC_AND_X2,FLAT_ATOMIC_OR_X2,FLAT_ATOMIC_XOR_X2,FLAT_ATOMIC_INC_X2,FLAT_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 97: //FLAT_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; } } @@ -268,125 +290,169 @@ layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; switch(layout.OP){ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: //GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT,GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI,GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16,GLOBAL_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 21: //GLOBAL_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 22: //GLOBAL_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 23: //GLOBAL_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 24:case 25:case 26:case 27:case 28: //GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT,GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 29: //GLOBAL_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 30: //GLOBAL_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 31: //GLOBAL_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78: //GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN,GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND,GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC,GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: //GLOBAL_ATOMIC_CMPSWAP,GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2,GLOBAL_ATOMIC_SUB_X2,GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2,GLOBAL_ATOMIC_SMAX_X2,GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2,GLOBAL_ATOMIC_OR_X2,GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2,GLOBAL_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 97: //GLOBAL_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); +} +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; } } @@ -395,79 +461,111 @@ layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; switch(layout.OP){ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: //SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT,SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI,SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16,SCRATCH_LOAD_SHORT_D16_HI -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 21: //SCRATCH_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 22: //SCRATCH_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 23: //SCRATCH_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 24:case 25:case 26:case 27:case 28: //SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT,SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 29: //SCRATCH_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 30: //SCRATCH_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 31: //SCRATCH_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0,64),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); +if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +} +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; } } @@ -476,314 +574,327 @@ layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; switch(layout.OP){ case 0:case 1:case 2:case 3:case 4:case 5: //IMAGE_LOAD,IMAGE_LOAD_MIP,IMAGE_LOAD_PCK,IMAGE_LOAD_PCK_SGN,IMAGE_LOAD_MIP_PCK,IMAGE_LOAD_MIP_PCK_SGN -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 8:case 9:case 10:case 11: //IMAGE_STORE,IMAGE_STORE_MIP,IMAGE_STORE_PCK,IMAGE_STORE_MIP_PCK -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 14: //IMAGE_GET_RESINFO -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 16:case 17:case 18:case 19:case 20:case 21:case 22:case 23:case 24:case 25:case 26:case 27:case 28: //IMAGE_ATOMIC_SWAP,IMAGE_ATOMIC_CMPSWAP,IMAGE_ATOMIC_ADD,IMAGE_ATOMIC_SUB,IMAGE_ATOMIC_SMIN,IMAGE_ATOMIC_UMIN,IMAGE_ATOMIC_SMAX,IMAGE_ATOMIC_UMAX,IMAGE_ATOMIC_AND,IMAGE_ATOMIC_OR,IMAGE_ATOMIC_XOR,IMAGE_ATOMIC_INC,IMAGE_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 32:case 39:case 64:case 66:case 71:case 74:case 75:case 96: //IMAGE_SAMPLE,IMAGE_SAMPLE_LZ,IMAGE_GATHER4,IMAGE_GATHER4H,IMAGE_GATHER4_LZ,IMAGE_GATHER4H_PCK,IMAGE_GATHER8H_PCK,IMAGE_GET_LOD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 33:case 36:case 37:case 40:case 47:case 48:case 55:case 65:case 68:case 69:case 72:case 79:case 80:case 87: //IMAGE_SAMPLE_CL,IMAGE_SAMPLE_L,IMAGE_SAMPLE_B,IMAGE_SAMPLE_C,IMAGE_SAMPLE_C_LZ,IMAGE_SAMPLE_O,IMAGE_SAMPLE_LZ_O,IMAGE_GATHER4_CL,IMAGE_GATHER4_L,IMAGE_GATHER4_B,IMAGE_GATHER4_C,IMAGE_GATHER4_C_LZ,IMAGE_GATHER4_O,IMAGE_GATHER4_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 34:case 104: //IMAGE_SAMPLE_D,IMAGE_SAMPLE_CD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,9),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 35:case 42:case 50:case 105:case 106:case 108: //IMAGE_SAMPLE_D_CL,IMAGE_SAMPLE_C_D,IMAGE_SAMPLE_D_O,IMAGE_SAMPLE_CD_CL,IMAGE_SAMPLE_C_CD,IMAGE_SAMPLE_CD_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,10),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 38:case 41:case 44:case 45:case 49:case 52:case 53:case 56:case 63:case 70:case 73:case 76:case 77:case 81:case 84:case 85:case 88:case 95: //IMAGE_SAMPLE_B_CL,IMAGE_SAMPLE_C_CL,IMAGE_SAMPLE_C_L,IMAGE_SAMPLE_C_B,IMAGE_SAMPLE_CL_O,IMAGE_SAMPLE_L_O,IMAGE_SAMPLE_B_O,IMAGE_SAMPLE_C_O,IMAGE_SAMPLE_C_LZ_O,IMAGE_GATHER4_B_CL,IMAGE_GATHER4_C_CL,IMAGE_GATHER4_C_L,IMAGE_GATHER4_C_B,IMAGE_GATHER4_CL_O,IMAGE_GATHER4_L_O,IMAGE_GATHER4_B_O,IMAGE_GATHER4_C_O,IMAGE_GATHER4_C_LZ_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,5),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 43:case 51:case 58:case 107:case 109:case 110: //IMAGE_SAMPLE_C_D_CL,IMAGE_SAMPLE_D_CL_O,IMAGE_SAMPLE_C_D_O,IMAGE_SAMPLE_C_CD_CL,IMAGE_SAMPLE_CD_CL_O,IMAGE_SAMPLE_C_CD_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,11),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 46:case 54:case 57:case 60:case 61:case 78:case 86:case 89:case 92:case 93: //IMAGE_SAMPLE_C_B_CL,IMAGE_SAMPLE_B_CL_O,IMAGE_SAMPLE_C_CL_O,IMAGE_SAMPLE_C_L_O,IMAGE_SAMPLE_C_B_O,IMAGE_GATHER4_C_B_CL,IMAGE_GATHER4_B_CL_O,IMAGE_GATHER4_C_CL_O,IMAGE_GATHER4_C_L_O,IMAGE_GATHER4_C_B_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,6),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 59:case 111: //IMAGE_SAMPLE_C_D_CL_O,IMAGE_SAMPLE_C_CD_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,12),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+8,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+9,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+10,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+11,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 62:case 94: //IMAGE_SAMPLE_C_B_CL_O,IMAGE_GATHER4_C_B_CL_O -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,7),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,8),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+4,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+5,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+6,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+7,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSAMP+3,0),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; } } @@ -792,103 +903,111 @@ layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; switch(layout.OP){ case 0:case 8:case 9: //TBUFFER_LOAD_FORMAT_X,TBUFFER_LOAD_FORMAT_D16_X,TBUFFER_LOAD_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 1:case 10:case 11: //TBUFFER_LOAD_FORMAT_XY,TBUFFER_LOAD_FORMAT_D16_XYZ,TBUFFER_LOAD_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 2: //TBUFFER_LOAD_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 3: //TBUFFER_LOAD_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 4:case 12:case 13: //TBUFFER_STORE_FORMAT_X,TBUFFER_STORE_FORMAT_D16_X,TBUFFER_STORE_FORMAT_D16_XY -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 5:case 14:case 15: //TBUFFER_STORE_FORMAT_XY,TBUFFER_STORE_FORMAT_D16_XYZ,TBUFFER_STORE_FORMAT_D16_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 6: //TBUFFER_STORE_FORMAT_XYZ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 7: //TBUFFER_STORE_FORMAT_XYZW -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; } } @@ -897,151 +1016,164 @@ layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; switch(layout.OP){ case 0:case 8:case 9:case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38: //BUFFER_LOAD_FORMAT_X,BUFFER_LOAD_FORMAT_D16_X,BUFFER_LOAD_FORMAT_D16_XY,BUFFER_LOAD_UBYTE,BUFFER_LOAD_SBYTE,BUFFER_LOAD_USHORT,BUFFER_LOAD_SSHORT,BUFFER_LOAD_DWORD,BUFFER_LOAD_UBYTE_D16,BUFFER_LOAD_UBYTE_D16_HI,BUFFER_LOAD_SBYTE_D16,BUFFER_LOAD_SBYTE_D16_HI,BUFFER_LOAD_SHORT_D16,BUFFER_LOAD_SHORT_D16_HI,BUFFER_LOAD_FORMAT_D16_HI_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 1:case 10:case 11:case 21: //BUFFER_LOAD_FORMAT_XY,BUFFER_LOAD_FORMAT_D16_XYZ,BUFFER_LOAD_FORMAT_D16_XYZW,BUFFER_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 2:case 22: //BUFFER_LOAD_FORMAT_XYZ,BUFFER_LOAD_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,3),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 3:case 23: //BUFFER_LOAD_FORMAT_XYZW,BUFFER_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 4:case 12:case 13:case 24:case 25:case 26:case 27:case 28:case 39: //BUFFER_STORE_FORMAT_X,BUFFER_STORE_FORMAT_D16_X,BUFFER_STORE_FORMAT_D16_XY,BUFFER_STORE_BYTE,BUFFER_STORE_BYTE_D16_HI,BUFFER_STORE_SHORT,BUFFER_STORE_SHORT_D16_HI,BUFFER_STORE_DWORD,BUFFER_STORE_FORMAT_D16_HI_X -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 5:case 14:case 15:case 29: //BUFFER_STORE_FORMAT_XY,BUFFER_STORE_FORMAT_D16_XYZ,BUFFER_STORE_FORMAT_D16_XYZW,BUFFER_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 6:case 30: //BUFFER_STORE_FORMAT_XYZ,BUFFER_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,3),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 7:case 31: //BUFFER_STORE_FORMAT_XYZW,BUFFER_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 61: //BUFFER_STORE_LDS_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 62:case 63: //BUFFER_WBINVL1,BUFFER_WBINVL1_VOL +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78: //BUFFER_ATOMIC_SWAP,BUFFER_ATOMIC_ADD,BUFFER_ATOMIC_SUB,BUFFER_ATOMIC_SMIN,BUFFER_ATOMIC_UMIN,BUFFER_ATOMIC_SMAX,BUFFER_ATOMIC_UMAX,BUFFER_ATOMIC_AND,BUFFER_ATOMIC_OR,BUFFER_ATOMIC_XOR,BUFFER_ATOMIC_INC,BUFFER_ATOMIC_DEC,BUFFER_ATOMIC_ADD_F32,BUFFER_ATOMIC_PK_ADD_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: //BUFFER_ATOMIC_CMPSWAP,BUFFER_ATOMIC_SWAP_X2,BUFFER_ATOMIC_ADD_X2,BUFFER_ATOMIC_SUB_X2,BUFFER_ATOMIC_SMIN_X2,BUFFER_ATOMIC_UMIN_X2,BUFFER_ATOMIC_SMAX_X2,BUFFER_ATOMIC_UMAX_X2,BUFFER_ATOMIC_AND_X2,BUFFER_ATOMIC_OR_X2,BUFFER_ATOMIC_XOR_X2,BUFFER_ATOMIC_INC_X2,BUFFER_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,2),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; case 97: //BUFFER_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+0,4),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+2,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDATA+3,0),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VADDR+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRSRC+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SOFFSET),true,false); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); break; } } @@ -1050,438 +1182,460 @@ layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; switch(layout.OP){ case 0:case 5: //S_LOAD_DWORD,S_SCRATCH_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 1:case 6: //S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 2:case 7: //S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 3: //S_LOAD_DWORDX8 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,8),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 4: //S_LOAD_DWORDX16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 8: //S_BUFFER_LOAD_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 9: //S_BUFFER_LOAD_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 10: //S_BUFFER_LOAD_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 11: //S_BUFFER_LOAD_DWORDX8 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,8),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 12: //S_BUFFER_LOAD_DWORDX16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,16),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+4,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+5,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+6,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+7,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+8,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+9,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+10,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+11,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+12,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+13,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+14,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+15,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 16:case 21: //S_STORE_DWORD,S_SCRATCH_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 17:case 22: //S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 18:case 23: //S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 24: //S_BUFFER_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 25: //S_BUFFER_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 26: //S_BUFFER_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 32:case 33:case 34:case 35: //S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 36:case 37: //S_MEMTIME,S_MEMREALTIME -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),false,true); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 38: //S_ATC_PROBE insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 39: //S_ATC_PROBE_BUFFER insn_in_progress->appendOperand(decodeOPR_SIMM8(layout.SDATA),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 40:case 41: //S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76: //S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB,S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX,S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR,S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108: //S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2,S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2,S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2,S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2,S_BUFFER_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 97: //S_BUFFER_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+3,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 128:case 130:case 131:case 132:case 133:case 134:case 135:case 136:case 137:case 138:case 139:case 140: //S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN,S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND,S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 129:case 160:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172: //S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2,S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2,S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2,S_ATOMIC_DEC_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,2),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; case 161: //S_ATOMIC_CMPSWAP_X2 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+0,4),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+2,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDATA+3,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SBASE+1,0),true,false); processOPR_SMEM_OFFSET(layout); +insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; } } void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP1Operands(){ layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; switch(layout.OP){ -case 0:case 8:case 14:case 16:case 18:case 20: -//S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32,S_FLBIT_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +case 0:case 8:case 14:case 16:case 18:case 20:case 22:case 23: +//S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32,S_FLBIT_I32,S_SEXT_I32_I8,S_SEXT_I32_I16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); break; case 1:case 9: //S_MOV_B64,S_BREV_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); break; case 2: //S_CMOV_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 3: //S_CMOV_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 4:case 6:case 10:case 12:case 40:case 48: //S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32,S_ABS_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 5:case 7:case 41: //S_NOT_B64,S_WQM_B64,S_QUADMASK_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 11:case 13: //S_BCNT0_I32_B64,S_BCNT1_I32_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 15:case 17:case 19:case 21: //S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -break; -case 22:case 23: -//S_SEXT_I32_I8,S_SEXT_I32_I16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); break; case 24:case 26: //S_BITSET0_B32,S_BITSET1_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); break; case 25:case 27: //S_BITSET0_B64,S_BITSET1_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); break; case 28: //S_GETPC_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); break; case 29: //S_SETPC_B64 setBranch(); setModifyPC(); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); break; case 30: //S_SWAPPC_B64 setBranch(); setModifyPC(); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); break; case 31: //S_RFE_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); break; case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 51:case 52:case 53:case 54: //S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64,S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64,S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64,S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false); break; case 42: //S_MOVRELS_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 43: //S_MOVRELS_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 44: //S_MOVRELD_B32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 45: //S_MOVRELD_B64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 46: //S_CBRANCH_JOIN -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); break; case 50: //S_SET_GPR_IDX_IDX -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 55: //S_BITREPLICATE_B64_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); break; } } @@ -1490,94 +1644,82 @@ layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; switch(layout.OP){ case 0:case 1:case 2:case 3:case 6:case 7:case 8:case 9:case 12:case 14:case 16:case 18:case 20:case 22:case 24:case 26:case 28:case 30:case 32:case 37:case 38:case 42:case 46:case 47:case 48:case 49: //S_ADD_U32,S_SUB_U32,S_ADD_I32,S_SUB_I32,S_MIN_I32,S_MIN_U32,S_MAX_I32,S_MAX_U32,S_AND_B32,S_OR_B32,S_XOR_B32,S_ANDN2_B32,S_ORN2_B32,S_NAND_B32,S_NOR_B32,S_XNOR_B32,S_LSHL_B32,S_LSHR_B32,S_ASHR_I32,S_BFE_U32,S_BFE_I32,S_ABSDIFF_I32,S_LSHL1_ADD_U32,S_LSHL2_ADD_U32,S_LSHL3_ADD_U32,S_LSHL4_ADD_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 4:case 5: //S_ADDC_U32,S_SUBB_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 10: //S_CSELECT_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 11: //S_CSELECT_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 13:case 15:case 17:case 19:case 21:case 23:case 25:case 27: //S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64,S_NAND_B64,S_NOR_B64,S_XNOR_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 29:case 31:case 33:case 39:case 40: //S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); -break; -case 34:case 36:case 44:case 45:case 52: -//S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_HH_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +break; +case 34:case 36:case 44:case 45:case 50:case 51:case 52: +//S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_LL_B32_B16,S_PACK_LH_B32_B16,S_PACK_HH_B32_B16 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); break; case 35: //S_BFM_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); break; case 41: //S_CBRANCH_G_FORK -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); break; case 43: //S_RFE_RESTORE_B64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -break; -case 50: -//S_PACK_LL_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,16),true,false); -break; -case 51: -//S_PACK_LH_B32_B16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); break; } } @@ -1586,36 +1728,36 @@ layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; switch(layout.OP){ case 0:case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13: //S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32,S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32,S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 14:case 15: //S_BITCMP0_B64,S_BITCMP1_B64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 16: //S_SETVSKIP -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); break; case 17: //S_SET_GPR_IDX_ON -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 18:case 19: //S_CMP_EQ_U64,S_CMP_LG_U64 -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; } } @@ -1624,50 +1766,50 @@ layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; switch(layout.OP){ case 0:case 17: //S_MOVK_I32,S_GETREG_B32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); break; case 1: //S_CMOVK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13: //S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32,S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32,S_CMPK_LT_U32,S_CMPK_LE_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 14: //S_ADDK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); break; case 15: //S_MULK_I32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); break; case 16: //S_CBRANCH_I_FORK -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; case 18: //S_SETREG_B32 insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,false); break; case 21: //S_CALL_B64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,32),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); break; } } @@ -1703,7 +1845,7 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253,1),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); break; case 6:case 7: //S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ @@ -1711,7 +1853,7 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); break; case 8:case 9: //S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ @@ -1719,20 +1861,35 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false); break; case 12: //S_WAITCNT -insn_in_progress->appendOperand(decodeOPR_WAITCNT(layout.SIMM16),true,false); -break; -case 16:case 17: +{ +uint32_t vmcnt = ((0x3& (layout.SIMM16 >>14))<<4) | (layout.SIMM16 & 0xf); +uint32_t expcnt ((layout.SIMM16>>4) & 0x7); +uint32_t lgkmcnt ((layout.SIMM16>>8) & 0xf); +if (vmcnt != 0x3f) { + insn_in_progress->appendOperand( makeRegisterExpression(amdgpu_gfx908::vmcnt, 0 ,32),false,true); + insn_in_progress->appendOperand( Immediate::makeImmediate(Result(u32,vmcnt)),false,false); +} +if (expcnt != 0x7) { + insn_in_progress->appendOperand( makeRegisterExpression(amdgpu_gfx908::expcnt, 0 ,32),false,true); + insn_in_progress->appendOperand( Immediate::makeImmediate(Result(u32,expcnt)),false,false); +} +if (lgkmcnt != 0xf) { + insn_in_progress->appendOperand( makeRegisterExpression(amdgpu_gfx908::lgkmcnt, 0 ,32),false,true); + insn_in_progress->appendOperand( Immediate::makeImmediate(Result(u32,lgkmcnt)),false,false); +} +} +break;case 16:case 17: //S_SENDMSG,S_SENDMSGHALT insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 22: //S_TTRACEDATA -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 23:case 24:case 25:case 26: //S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER,S_CBRANCH_CDBGSYS_AND_USER @@ -1741,8 +1898,8 @@ break; case 29: //S_SET_GPR_IDX_MODE insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; } } @@ -1751,24 +1908,24 @@ layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; switch(layout.OP){ case 0: //V_INTERP_P1_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 1: //V_INTERP_P2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 2: //V_INTERP_MOV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; } } @@ -1777,318 +1934,250 @@ layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; switch(layout.OP){ case 624: //V_INTERP_P1_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 625: //V_INTERP_P2_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 626: //V_INTERP_MOV_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); break; case 320:case 373: //V_NOP,V_CLREXCP break; -case 321:case 325:case 326:case 327:case 328:case 332:case 333:case 334:case 337:case 338:case 339:case 340:case 347:case 348:case 349:case 350:case 351:case 352:case 353:case 354:case 355:case 356:case 359:case 361:case 362:case 363:case 364:case 365:case 366:case 367:case 371:case 372:case 375:case 395:case 396: -//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +case 321:case 325:case 326:case 327:case 328:case 330:case 331:case 332:case 333:case 334:case 337:case 338:case 339:case 340:case 347:case 348:case 349:case 350:case 351:case 352:case 353:case 354:case 355:case 356:case 359:case 361:case 362:case 363:case 364:case 365:case 366:case 367:case 371:case 372:case 375:case 377:case 378:case 379:case 380:case 381:case 382:case 383:case 384:case 385:case 386:case 387:case 388:case 389:case 390:case 391:case 392:case 393:case 394:case 395:case 396:case 397:case 398:case 399: +//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); break; case 322: //V_READFIRSTLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0),true,false); break; case 323:case 335:case 341:case 368: //V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); break; case 324:case 336:case 342: //V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 330:case 399: -//V_CVT_F16_F32,V_SAT_PK_U8_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -break; -case 331: -//V_CVT_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); break; case 343:case 344:case 345:case 346:case 357:case 358:case 360:case 369:case 370: //V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64,V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -break; -case 377:case 378:case 379:case 380:case 381:case 382:case 383:case 384:case 385:case 386:case 387:case 388:case 389:case 390:case 391:case 392:case 393:case 394:case 397:case 398: -//V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); break; case 401: //V_SWAP_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0),true,true); break; case 256: //V_CNDMASK_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); -break; -case 257:case 258:case 259:case 260:case 261:case 262:case 263:case 264:case 265:case 266:case 267:case 268:case 269:case 270:case 271:case 275:case 276:case 277:case 308:case 309:case 317:case 645:case 646:case 647:case 648:case 651:case 652:case 653:case 659:case 660:case 661:case 662:case 663:case 664:case 668:case 669: -//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_U32,V_SUB_U32,V_XNOR_B32,V_MUL_LO_U32,V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32,V_BCNT_U32_B32,V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32,V_CVT_PKNORM_I16_F32,V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32,V_CVT_PK_U16_U32,V_CVT_PK_I16_I32,V_ADD_I32,V_SUB_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 272:case 273:case 274:case 310: -//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 278:case 311:case 312:case 313:case 314:case 315:case 316:case 496: -//V_MAC_F32,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16,V_CVT_PKACCUM_U8_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 287:case 288:case 290:case 294:case 295:case 297:case 301:case 302:case 303:case 304:case 305:case 306:case 307:case 670:case 671: -//V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16,V_ADD_I16,V_SUB_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 289:case 296:case 298:case 299:case 300: -//V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 291: -//V_MAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 448:case 449:case 450:case 451:case 452:case 453:case 454:case 455:case 456:case 457:case 458:case 459:case 461:case 462:case 463:case 464:case 465:case 466:case 467:case 468:case 469:case 470:case 471:case 472:case 473:case 474:case 475:case 476:case 477:case 478:case 484:case 493:case 499:case 509:case 510:case 511:case 512:case 513:case 514: -//V_MAD_LEGACY_F32,V_MAD_F32,V_MAD_I32_I24,V_MAD_U32_U24,V_CUBEID_F32,V_CUBESC_F32,V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32,V_BFE_I32,V_BFI_B32,V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32,V_ALIGNBYTE_B32,V_MIN3_F32,V_MIN3_I32,V_MIN3_U32,V_MAX3_F32,V_MAX3_I32,V_MAX3_U32,V_MED3_F32,V_MED3_I32,V_MED3_U32,V_SAD_U8,V_SAD_HI_U8,V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32,V_DIV_FIXUP_F32,V_MSAD_U8,V_PERM_B32,V_XAD_U32,V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32,V_LSHL_OR_B32,V_AND_OR_B32,V_OR3_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,0),true,false); +break; +case 257:case 258:case 259:case 260:case 261:case 262:case 263:case 264:case 265:case 266:case 267:case 268:case 269:case 270:case 271:case 275:case 276:case 277:case 287:case 288:case 290:case 294:case 295:case 297:case 301:case 302:case 303:case 304:case 305:case 306:case 307:case 308:case 309:case 317:case 645:case 646:case 647:case 648:case 651:case 652:case 653:case 659:case 660:case 661:case 662:case 663:case 664:case 665:case 666:case 668:case 669:case 670:case 671:case 672: +//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32,V_MUL_LO_U32,V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32,V_BCNT_U32_B32,V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32,V_CVT_PKNORM_I16_F32,V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32,V_CVT_PK_U16_U32,V_CVT_PK_I16_I32,V_CVT_PKNORM_I16_F16,V_CVT_PKNORM_U16_F16,V_ADD_I32,V_SUB_I32,V_ADD_I16,V_SUB_I16,V_PACK_B32_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +break; +case 272:case 273:case 274:case 289:case 296:case 298:case 299:case 300:case 310: +//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16,V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +break; +case 278:case 291:case 311:case 312:case 313:case 314:case 315:case 316:case 496: +//V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16,V_CVT_PKACCUM_U8_F32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +break; +case 448:case 449:case 450:case 451:case 452:case 453:case 454:case 455:case 456:case 457:case 458:case 459:case 461:case 462:case 463:case 464:case 465:case 466:case 467:case 468:case 469:case 470:case 471:case 472:case 473:case 474:case 475:case 476:case 477:case 478:case 484:case 490:case 491:case 492:case 493:case 494:case 495:case 497:case 498:case 499:case 500:case 501:case 502:case 503:case 504:case 505:case 506:case 507:case 508:case 509:case 510:case 511:case 512:case 513:case 514:case 515:case 516:case 517:case 518:case 519: +//V_MAD_LEGACY_F32,V_MAD_F32,V_MAD_I32_I24,V_MAD_U32_U24,V_CUBEID_F32,V_CUBESC_F32,V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32,V_BFE_I32,V_BFI_B32,V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32,V_ALIGNBYTE_B32,V_MIN3_F32,V_MIN3_I32,V_MIN3_U32,V_MAX3_F32,V_MAX3_I32,V_MAX3_U32,V_MED3_F32,V_MED3_I32,V_MED3_U32,V_SAD_U8,V_SAD_HI_U8,V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32,V_DIV_FIXUP_F32,V_MSAD_U8,V_MAD_LEGACY_F16,V_MAD_LEGACY_U16,V_MAD_LEGACY_I16,V_PERM_B32,V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16,V_MAD_U32_U16,V_MAD_I32_I16,V_XAD_U32,V_MIN3_F16,V_MIN3_I16,V_MIN3_U16,V_MAX3_F16,V_MAX3_I16,V_MAX3_U16,V_MED3_F16,V_MED3_I16,V_MED3_U16,V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32,V_LSHL_OR_B32,V_AND_OR_B32,V_OR3_B32,V_MAD_F16,V_MAD_U16,V_MAD_I16,V_FMA_F16,V_DIV_FIXUP_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2),true,false); break; case 460:case 479: //V_FMA_F64,V_DIV_FIXUP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); break; case 482: //V_DIV_FMAS_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); break; case 483: //V_DIV_FMAS_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); break; case 485:case 486: //V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); break; case 487: //V_MQSAD_U32_U8 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,32),true,false); -break; -case 490:case 491:case 492:case 494:case 495:case 500:case 501:case 502:case 503:case 504:case 505:case 506:case 507:case 508:case 515:case 516:case 517:case 518:case 519: -//V_MAD_LEGACY_F16,V_MAD_LEGACY_U16,V_MAD_LEGACY_I16,V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16,V_MIN3_F16,V_MIN3_I16,V_MIN3_U16,V_MAX3_F16,V_MAX3_I16,V_MAX3_U16,V_MED3_F16,V_MED3_I16,V_MED3_U16,V_MAD_F16,V_MAD_U16,V_MAD_I16,V_FMA_F16,V_DIV_FIXUP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); -break; -case 497:case 498: -//V_MAD_U32_U16,V_MAD_I32_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+0,4),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+2,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2+3,0),true,false); break; case 628: //V_INTERP_P1LL_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); break; case 629:case 630:case 631: //V_INTERP_P1LV_F16,V_INTERP_P2_LEGACY_F16,V_INTERP_P2_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC2),true,false); break; case 640:case 641:case 642:case 643: //V_ADD_F64,V_MUL_F64,V_MIN_F64,V_MAX_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); break; case 644:case 658: //V_LDEXP_F64,V_TRIG_PREOP_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 649: //V_READLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1),true,false); break; case 650: //V_WRITELANE_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(layout.SRC1),true,false); break; case 655:case 656:case 657: //V_LSHLREV_B64,V_LSHRREV_B64,V_ASHRREV_I64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -break; -case 665:case 666:case 672: -//V_CVT_PKNORM_I16_F16,V_CVT_PKNORM_U16_F16,V_PACK_B32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 16:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: -//V_CMP_CLASS_F32,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 17:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: -//V_CMPX_CLASS_F32,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); +break; +case 16:case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: +//V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +break; +case 17:case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: +//V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; case 18: //V_CMP_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 19: //V_CMPX_CLASS_F64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175: -//V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -break; -case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191: -//V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: //V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); break; case 112:case 113:case 114:case 115:case 116:case 117:case 118:case 119:case 120:case 121:case 122:case 123:case 124:case 125:case 126:case 127:case 240:case 241:case 242:case 243:case 244:case 245:case 246:case 247:case 248:case 249:case 250:case 251:case 252:case 253:case 254:case 255: //V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64,V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64,V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64,V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64,V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64,V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64,V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64,V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64 -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; } } @@ -2098,54 +2187,39 @@ switch(layout.OP){ case 0:case 53: //V_NOP,V_CLREXCP break; -case 1:case 5:case 6:case 7:case 8:case 12:case 13:case 14:case 17:case 18:case 19:case 20:case 27:case 28:case 29:case 30:case 31:case 32:case 33:case 34:case 35:case 36:case 39:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 51:case 52:case 55:case 75:case 76: -//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); +case 1:case 5:case 6:case 7:case 8:case 10:case 11:case 12:case 13:case 14:case 17:case 18:case 19:case 20:case 27:case 28:case 29:case 30:case 31:case 32:case 33:case 34:case 35:case 36:case 39:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 51:case 52:case 55:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79: +//V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32,V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); break; case 2: //V_READFIRSTLANE_B32 -insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(layout.SRC0),true,false); break; case 3:case 15:case 21:case 48: //V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); break; case 4:case 16:case 22: //V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 10:case 79: -//V_CVT_F16_F32,V_SAT_PK_U8_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -break; -case 11: -//V_CVT_F32_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); break; case 23:case 24:case 25:case 26:case 37:case 38:case 40:case 49:case 50: //V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64,V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -break; -case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 77:case 78: -//V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16,V_COS_F16,V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); break; case 81: //V_SWAP_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0,32),true,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC0),true,true); break; } } @@ -2154,108 +2228,76 @@ layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; switch(layout.OP){ case 0: //V_CNDMASK_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13:case 14:case 15:case 19:case 20:case 21:case 52:case 53:case 61: -//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_U32,V_SUB_U32,V_XNOR_B32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13:case 14:case 15:case 19:case 20:case 21:case 31:case 32:case 34:case 38:case 39:case 41:case 45:case 46:case 47:case 48:case 49:case 50:case 51:case 52:case 53:case 61: +//V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32,V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; -case 16:case 17:case 18:case 54: -//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 16:case 17:case 18:case 33:case 40:case 42:case 43:case 44:case 54: +//V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16,V_SUBREV_U32 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; -case 22:case 55:case 56:case 57:case 58:case 59:case 60: -//V_MAC_F32,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 22:case 35:case 55:case 56:case 57:case 58:case 59:case 60: +//V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; case 25:case 26: //V_ADD_CO_U32,V_SUB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; case 27: //V_SUBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; case 28:case 29: //V_ADDC_CO_U32,V_SUBB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; case 30: //V_SUBBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0,64),true,false); break; -case 31:case 32:case 34:case 38:case 39:case 41:case 45:case 46:case 47:case 48:case 49:case 50:case 51: -//V_ADD_F16,V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 33:case 40:case 42:case 43:case 44: -//V_SUBREV_F16,V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 35: -//V_MAC_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),true,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; } } void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2_LITERALOperands(){ layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; switch(layout.OP){ -case 23: -//V_MADMK_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -break; -case 24: -//V_MADAK_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +case 23:case 36: +//V_MADMK_F32,V_MADMK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; -case 36: -//V_MADMK_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 37: -//V_MADAK_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); +case 24:case 37: +//V_MADAK_F32,V_MADAK_F16 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM32(layout.SIMM32),true,false); break; } @@ -2265,127 +2307,106 @@ layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; switch(layout.OP){ case 281:case 282: //V_ADD_CO_U32,V_SUB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 283: //V_SUBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 284:case 285: //V_ADDC_CO_U32,V_SUBB_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,0),true,false); break; case 286: //V_SUBBREV_CO_U32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SRC2+1,0),true,false); break; case 480: //V_DIV_SCALE_F32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2),true,false); break; case 481: //V_DIV_SCALE_F64 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VCC(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); break; case 488:case 489: //V_MAD_U64_U32,V_MAD_I64_I32 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); break; } } void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3POperands(){ layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; switch(layout.OP){ -case 0:case 9:case 14: -//V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,16),true,false); +case 0:case 9:case 14:case 32:case 33:case 34:case 35:case 38:case 39:case 40:case 41:case 42:case 43: +//V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16,V_MAD_MIX_F32,V_MAD_MIXLO_F16,V_MAD_MIXHI_F16,V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16,V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4 +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2),true,false); break; case 1:case 2:case 3:case 7:case 8:case 10:case 11:case 12:case 13:case 15:case 16:case 17:case 18: //V_PK_MUL_LO_U16,V_PK_ADD_I16,V_PK_SUB_I16,V_PK_MAX_I16,V_PK_MIN_I16,V_PK_ADD_U16,V_PK_SUB_U16,V_PK_MAX_U16,V_PK_MIN_U16,V_PK_ADD_F16,V_PK_MUL_F16,V_PK_MIN_F16,V_PK_MAX_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 4:case 5:case 6: //V_PK_LSHLREV_B16,V_PK_LSHRREV_B16,V_PK_ASHRREV_I16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -break; -case 32:case 40:case 41:case 42:case 43: -//V_MAD_MIX_F32,V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 33:case 34: -//V_MAD_MIXLO_F16,V_MAD_MIXHI_F16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,16),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); -break; -case 35:case 38:case 39: -//V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); break; case 88: //V_ACCVGPR_READ -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(layout.SRC0),true,false); break; case 89: //V_ACCVGPR_WRITE -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); break; } } @@ -2394,73 +2415,60 @@ layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; switch(layout.OP){ case 64:case 65:case 66:case 68:case 69:case 72:case 73:case 74:case 76:case 77:case 80:case 81:case 82:case 84:case 85:case 104:case 105:case 107:case 108:case 109: //V_MFMA_F32_32X32X1F32,V_MFMA_F32_16X16X1F32,V_MFMA_F32_4X4X1F32,V_MFMA_F32_32X32X2F32,V_MFMA_F32_16X16X4F32,V_MFMA_F32_32X32X4F16,V_MFMA_F32_16X16X4F16,V_MFMA_F32_4X4X4F16,V_MFMA_F32_32X32X8F16,V_MFMA_F32_16X16X16F16,V_MFMA_I32_32X32X4I8,V_MFMA_I32_16X16X4I8,V_MFMA_I32_4X4X4I8,V_MFMA_I32_32X32X8I8,V_MFMA_I32_16X16X16I8,V_MFMA_F32_32X32X2BF16,V_MFMA_F32_16X16X2BF16,V_MFMA_F32_4X4X2BF16,V_MFMA_F32_32X32X4BF16,V_MFMA_F32_16X16X8BF16 -insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST,32),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,32),true,false); +insn_in_progress->appendOperand(decodeOPR_ACCVGPR(layout.VDST),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2),true,false); break; } } void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOPCOperands(){ layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; switch(layout.OP){ -case 16:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: -//V_CMP_CLASS_F32,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 +case 16:case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 64:case 65:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78:case 79:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175:case 192:case 193:case 194:case 195:case 196:case 197:case 198:case 199:case 200:case 201:case 202:case 203:case 204:case 205:case 206:case 207: +//V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32,V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32,V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32,V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32,V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32,V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32,V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32,V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32,V_CMP_GE_U32,V_CMP_T_U32 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; -case 17:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: -//V_CMPX_CLASS_F32,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 +case 17:case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 80:case 81:case 82:case 83:case 84:case 85:case 86:case 87:case 88:case 89:case 90:case 91:case 92:case 93:case 94:case 95:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191:case 208:case 209:case 210:case 211:case 212:case 213:case 214:case 215:case 216:case 217:case 218:case 219:case 220:case 221:case 222:case 223: +//V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32,V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32,V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32,V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32,V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32,V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32,V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32,V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32,V_CMPX_GE_U32,V_CMPX_T_U32 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; case 18: //V_CMP_CLASS_F64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); break; case 19: //V_CMPX_CLASS_F64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); -break; -case 20:case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 44:case 45:case 46:case 47:case 160:case 161:case 162:case 163:case 164:case 165:case 166:case 167:case 168:case 169:case 170:case 171:case 172:case 173:case 174:case 175: -//V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16,V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16,V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16,V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16,V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16,V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16,V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -break; -case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55:case 56:case 57:case 58:case 59:case 60:case 61:case 62:case 63:case 176:case 177:case 178:case 179:case 180:case 181:case 182:case 183:case 184:case 185:case 186:case 187:case 188:case 189:case 190:case 191: -//V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16,V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16,V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16,V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16,V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_I16,V_CMPX_LT_I16,V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16,V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16,V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16,V_CMPX_GE_U16,V_CMPX_T_U16 -insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0,16),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1,16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: //V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,0),true,false); break; case 112:case 113:case 114:case 115:case 116:case 117:case 118:case 119:case 120:case 121:case 122:case 123:case 124:case 125:case 126:case 127:case 240:case 241:case 242:case 243:case 244:case 245:case 246:case 247:case 248:case 249:case 250:case 251:case 252:case 253:case 254:case 255: //V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64,V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64,V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64,V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64,V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64,V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64,V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64,V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64 insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,32),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,32),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126,64),false,true); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,0),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); break; } } diff --git a/instructionAPI/src/ArchSpecificFormatters.C b/instructionAPI/src/ArchSpecificFormatters.C index 5409142f3c..91f9ab0420 100644 --- a/instructionAPI/src/ArchSpecificFormatters.C +++ b/instructionAPI/src/ArchSpecificFormatters.C @@ -186,6 +186,9 @@ std::string AmdgpuFormatter::getInstructionString(std::vector opera std::string out; for(std::vector::iterator itr = operands.begin(); itr != operands.end(); itr++) { + if (*itr == "") + continue; + out += *itr; if(itr != operands.end() - 1) out += ", "; diff --git a/instructionAPI/src/InstructionDecoderImpl.C b/instructionAPI/src/InstructionDecoderImpl.C index 32090667da..d88e400dae 100644 --- a/instructionAPI/src/InstructionDecoderImpl.C +++ b/instructionAPI/src/InstructionDecoderImpl.C @@ -135,13 +135,13 @@ namespace Dyninst { return make_shared(singleton_object_pool::construct(addrToDereference, resultType)); } - Expression::Ptr InstructionDecoderImpl::makeRegisterExpression(MachRegister registerID) + Expression::Ptr InstructionDecoderImpl::makeRegisterExpression(MachRegister registerID, uint32_t num_elements ) { int newID = registerID.val(); int minusArch = newID & ~(registerID.getArchitecture()); int convertedID = minusArch | m_Arch; MachRegister converted(convertedID); - return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8)); + return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8,num_elements)); } @@ -171,7 +171,6 @@ namespace Dyninst MachRegister converted(convertedID); return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8)); } - } } diff --git a/instructionAPI/src/InstructionDecoderImpl.h b/instructionAPI/src/InstructionDecoderImpl.h index b59257c586..068d467446 100644 --- a/instructionAPI/src/InstructionDecoderImpl.h +++ b/instructionAPI/src/InstructionDecoderImpl.h @@ -67,7 +67,10 @@ class InstructionDecoderImpl virtual Expression::Ptr makeRightLogicalShiftExpression(Expression::Ptr lhs, Expression::Ptr rhs, Result_Type resultType); virtual Expression::Ptr makeRightRotateExpression(Expression::Ptr lhs, Expression::Ptr rhs, Result_Type resultType); virtual Expression::Ptr makeDereferenceExpression(Expression::Ptr addrToDereference, Result_Type resultType); - virtual Expression::Ptr makeRegisterExpression(MachRegister reg); + + + + virtual Expression::Ptr makeRegisterExpression(MachRegister reg, uint32_t num_elements = 1); // added version to support loading partial values out of register virtual Expression::Ptr makeRegisterExpression(MachRegister reg, unsigned int start , unsigned int end); virtual Expression::Ptr makeMaskRegisterExpression(MachRegister reg); diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index c87475d4dc..53a728ba91 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -49,19 +49,19 @@ namespace Dyninst { namespace InstructionAPI { - RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit) : - Expression(r), m_Reg(r), m_Low(lowbit), m_High(highbit) + RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit ,uint32_t num_elements) : + Expression(r), m_Reg(r), m_Low(lowbit), m_High(highbit) , m_num_elements(num_elements) { } - RegisterAST::RegisterAST(MachRegister r) : - Expression(r), m_Reg(r), m_Low(0) + RegisterAST::RegisterAST(MachRegister r, uint32_t num_elements) : + Expression(r), m_Reg(r), m_Low(0), m_num_elements(num_elements) { m_High = r.size() * 8; } - RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType): - Expression(regType), m_Reg(r), m_Low(lowbit), m_High(highbit) + RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType, uint32_t num_elements): + Expression(regType), m_Reg(r), m_Low(lowbit), m_High(highbit), m_num_elements(num_elements) { } @@ -106,8 +106,37 @@ namespace Dyninst { name = name.substr(substr + 2, name.length()); } + if( m_num_elements ==0 ){ + return ""; + }else if ( m_num_elements > 1){ + uint32_t id = m_Reg & 0xff ; + uint32_t regClass = m_Reg.regClass(); + + uint32_t size = m_num_elements; + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + + if(regClass == amdgpu_gfx908::SGPR || regClass == amdgpu_cdna2::SGPR || regClass == amdgpu_vega::SGPR){ + return "S["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_gfx908::VGPR || regClass == amdgpu_cdna2::VGPR || regClass == amdgpu_vega::VGPR){ + return "V["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + + DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP + + if(regClass == amdgpu_gfx908::ACC_VGPR || regClass == amdgpu_cdna2::ACC_VGPR){ + return "ACC["+to_string(id) + ":" + to_string(id+size-1)+"]"; + } + if(m_Reg == amdgpu_gfx908::vcc_lo || m_Reg == amdgpu_cdna2::vcc_lo || m_Reg == amdgpu_vega::vcc_lo) + return "VCC"; + if(m_Reg == amdgpu_gfx908::exec_lo || m_Reg == amdgpu_cdna2::exec_lo || m_Reg == amdgpu_vega::exec_lo) + return "EXEC"; + + + }else if ( m_High -m_Low > 32 && m_Reg.size()*8 != m_High - m_Low){ + // Size of base register * 8 != m_High - mLow ( in bits) when we it is a register vector - if ( m_High -m_Low > 32 && m_Reg.size()*8 != m_High - m_Low){ uint32_t id = m_Reg & 0xff ; uint32_t regClass = m_Reg.regClass(); uint32_t size = (m_High - m_Low ) / 32; @@ -136,7 +165,7 @@ namespace Dyninst return "EXEC"; name += "["+to_string(m_Low)+":"+to_string(m_High)+"]"; - } + } /* we have moved to AT&T syntax (lowercase registers) */ for(char &c : name) c = std::toupper(c); From 02818df43ea6d019ac85c90df51db1a0c67220c5 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 25 Oct 2022 17:11:06 -0500 Subject: [PATCH 173/505] fix formatting regarding implicit operands --- .../src/AMDGPU/gfx908/finalizeOperands.C | 228 +++++++++--------- instructionAPI/src/ArchSpecificFormatters.C | 8 +- 2 files changed, 118 insertions(+), 118 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index 499b9f9c83..9a43efd888 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -18,7 +18,7 @@ break; case 29:case 153:case 155:case 157: //DS_WRITE_ADDTID_B32,DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 40:case 41:case 42:case 43:case 45:case 50:case 51:case 53:case 62:case 63: //DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32,DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32,DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32,DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32,DS_PERMUTE_B32,DS_BPERMUTE_B32 @@ -110,18 +110,18 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); break; case 152:case 154:case 156: //DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 182:case 189:case 190: //DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 191: //DS_ORDERED_COUNT insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 222: //DS_WRITE_B96 @@ -155,8 +155,8 @@ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -166,8 +166,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -178,8 +178,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -191,8 +191,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -201,8 +201,8 @@ case 24:case 25:case 26:case 27:case 28: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -212,8 +212,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -224,8 +224,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -237,8 +237,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -248,8 +248,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -261,8 +261,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -278,8 +278,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -297,7 +297,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -311,7 +311,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -326,7 +326,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -342,7 +342,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -355,7 +355,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -369,7 +369,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -384,7 +384,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -400,7 +400,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -414,7 +414,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -430,7 +430,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -450,7 +450,7 @@ if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -466,8 +466,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -479,8 +479,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -493,8 +493,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -508,8 +508,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -520,8 +520,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -533,8 +533,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -547,8 +547,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -562,8 +562,8 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); } -insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); break; @@ -1502,7 +1502,7 @@ case 2: //S_CMOV_B32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 3: //S_CMOV_B64 @@ -1510,13 +1510,13 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),true,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),true,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 4:case 6:case 10:case 12:case 40:case 48: //S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32,S_ABS_I32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 5:case 7:case 41: //S_NOT_B64,S_WQM_B64,S_QUADMASK_B64 @@ -1524,14 +1524,14 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 11:case 13: //S_BCNT0_I32_B64,S_BCNT1_I32_B64 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 15:case 17:case 19:case 21: //S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64 @@ -1554,7 +1554,7 @@ case 28: //S_GETPC_B64 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false,true); break; case 29: //S_SETPC_B64 @@ -1562,7 +1562,7 @@ setBranch(); setModifyPC(); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); break; case 30: //S_SWAPPC_B64 @@ -1572,14 +1572,14 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false,true); break; case 31: //S_RFE_B64 insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); break; case 32:case 33:case 34:case 35:case 36:case 37:case 38:case 39:case 51:case 52:case 53:case 54: //S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64,S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64,S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64,S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64 @@ -1587,15 +1587,15 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false,true); break; case 42: //S_MOVRELS_B32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 43: //S_MOVRELS_B64 @@ -1603,13 +1603,13 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 44: //S_MOVRELD_B32 insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 45: //S_MOVRELD_B64 @@ -1617,19 +1617,19 @@ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 46: //S_CBRANCH_JOIN insn_in_progress->appendOperand(decodeOPR_SREG(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); break; case 50: //S_SET_GPR_IDX_IDX insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 55: //S_BITREPLICATE_B64_B32 @@ -1647,22 +1647,22 @@ case 0:case 1:case 2:case 3:case 6:case 7:case 8:case 9:case 12:case 14:case 16: insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 4:case 5: //S_ADDC_U32,S_SUBB_U32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 10: //S_CSELECT_B32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 11: //S_CSELECT_B64 @@ -1672,7 +1672,7 @@ insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 13:case 15:case 17:case 19:case 21:case 23:case 25:case 27: //S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64,S_NAND_B64,S_NOR_B64,S_XNOR_B64 @@ -1682,7 +1682,7 @@ insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 29:case 31:case 33:case 39:case 40: //S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64 @@ -1691,7 +1691,7 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 34:case 36:case 44:case 45:case 50:case 51:case 52: //S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_LL_B32_B16,S_PACK_LH_B32_B16,S_PACK_HH_B32_B16 @@ -1712,14 +1712,14 @@ insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+0,2),true,fals insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(layout.SSRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); break; case 43: //S_RFE_RESTORE_B64 insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); break; } } @@ -1730,14 +1730,14 @@ case 0:case 1:case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:ca //S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32,S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32,S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32 insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 14:case 15: //S_BITCMP0_B64,S_BITCMP1_B64 insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 16: //S_SETVSKIP @@ -1748,8 +1748,8 @@ case 17: //S_SET_GPR_IDX_ON insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM4(layout.SSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 18:case 19: //S_CMP_EQ_U64,S_CMP_LG_U64 @@ -1757,7 +1757,7 @@ insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC(layout.SSRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; } } @@ -1773,19 +1773,19 @@ case 1: //S_CMOVK_I32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 2:case 3:case 4:case 5:case 6:case 7:case 8:case 9:case 10:case 11:case 12:case 13: //S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32,S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32,S_CMPK_LT_U32,S_CMPK_LE_U32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,false); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 14: //S_ADDK_I32 insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST),true,true); insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),false,true,true); break; case 15: //S_MULK_I32 @@ -1808,8 +1808,8 @@ case 21: insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.SDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_PC(0),false,true); -insn_in_progress->appendOperand(decodeOPR_PC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_PC(0),false,true,true); +insn_in_progress->appendOperand(decodeOPR_PC(0),true,false,true); break; } } @@ -1845,7 +1845,7 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false); +insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 6:case 7: //S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ @@ -1853,7 +1853,7 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false,true); break; case 8:case 9: //S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ @@ -1861,7 +1861,7 @@ setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false,true); break; case 12: //S_WAITCNT @@ -1885,11 +1885,11 @@ if (lgkmcnt != 0xf) { break;case 16:case 17: //S_SENDMSG,S_SENDMSGHALT insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 22: //S_TTRACEDATA -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 23:case 24:case 25:case 26: //S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER,S_CBRANCH_CDBGSYS_AND_USER @@ -1898,8 +1898,8 @@ break; case 29: //S_SET_GPR_IDX_MODE insn_in_progress->appendOperand(decodeOPR_SIMM16(layout.SIMM16),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),false,true,true); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; } } @@ -1911,21 +1911,21 @@ case 0: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 1: //V_INTERP_P2_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 2: //V_INTERP_MOV_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_PARAM(layout.VSRC),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.ATTR),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; } } @@ -1937,21 +1937,21 @@ case 624: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 625: //V_INTERP_P2_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),true,true); insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(layout.SRC1),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 626: //V_INTERP_MOV_F32 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_PARAM(layout.SRC1),true,false); insn_in_progress->appendOperand(decodeOPR_ATTR(layout.SRC0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false); +insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); break; case 320:case 373: //V_NOP,V_CLREXCP @@ -2040,7 +2040,7 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false,true); break; case 483: //V_DIV_FMAS_F64 @@ -2052,7 +2052,7 @@ insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC2+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false); +insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false,true); break; case 485:case 486: //V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8 @@ -2141,7 +2141,7 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; case 18: //V_CMP_CLASS_F64 @@ -2158,7 +2158,7 @@ insn_in_progress->appendOperand(decodeOPR_SDST(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: //V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 @@ -2177,7 +2177,7 @@ insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+0,2),true,false) insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(layout.SRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(layout.SRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; } } @@ -2436,7 +2436,7 @@ case 17:case 21:case 48:case 49:case 50:case 51:case 52:case 53:case 54:case 55: insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; case 18: //V_CMP_CLASS_F64 @@ -2451,7 +2451,7 @@ insn_in_progress->appendOperand(decodeOPR_VCC(0,64),false,true); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; case 96:case 97:case 98:case 99:case 100:case 101:case 102:case 103:case 104:case 105:case 106:case 107:case 108:case 109:case 110:case 111:case 224:case 225:case 226:case 227:case 228:case 229:case 230:case 231:case 232:case 233:case 234:case 235:case 236:case 237:case 238:case 239: //V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64,V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64,V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64,V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64,V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64,V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64,V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64,V_CMP_GE_U64,V_CMP_T_U64 @@ -2468,7 +2468,7 @@ insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SRC(layout.SRC0+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VSRC1+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true); +insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),false,true,true); break; } } diff --git a/instructionAPI/src/ArchSpecificFormatters.C b/instructionAPI/src/ArchSpecificFormatters.C index 91f9ab0420..0f6cc1dde0 100644 --- a/instructionAPI/src/ArchSpecificFormatters.C +++ b/instructionAPI/src/ArchSpecificFormatters.C @@ -184,14 +184,14 @@ std::string AmdgpuFormatter::formatDeref(std::string addrString) { std::string AmdgpuFormatter::getInstructionString(std::vector operands) { std::string out; - + bool printed = false; for(std::vector::iterator itr = operands.begin(); itr != operands.end(); itr++) { if (*itr == "") continue; - - out += *itr; - if(itr != operands.end() - 1) + if(printed) out += ", "; + out += *itr; + printed = true; } return out; From 38bf84ba65038225a909e27e8943a2dbd645478c Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 25 Oct 2022 18:54:14 -0500 Subject: [PATCH 174/505] remove duplicate branch target operand --- instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C | 4 ---- 1 file changed, 4 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index 9a43efd888..e4f8cbca63 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -1837,14 +1837,12 @@ case 2: //S_BRANCH setBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); break; case 4:case 5: //S_CBRANCH_SCC0,S_CBRANCH_SCC1 setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(253),true,false,true); break; case 6:case 7: @@ -1852,7 +1850,6 @@ case 6:case 7: setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_VCC(0),true,false,true); break; case 8:case 9: @@ -1860,7 +1857,6 @@ case 8:case 9: setBranch(); setConditionalBranch(); makeBranchTarget(isCall,isConditional,layout.SIMM16); -insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(126),true,false,true); break; case 12: From 84182fbee5a626a14b87dc8c2aa9af685e2264b7 Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Tue, 25 Oct 2022 20:14:50 -0500 Subject: [PATCH 175/505] fix the logic for operands addr and saddr for flat instruction encoding family based on the manual --- .../src/AMDGPU/gfx908/finalizeOperands.C | 165 +++++++++++++----- 1 file changed, 119 insertions(+), 46 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C index e4f8cbca63..4f96de7a0b 100644 --- a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -291,9 +291,12 @@ switch(layout.OP){ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: //GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT,GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI,GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16,GLOBAL_LOAD_SHORT_D16_HI insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -if(layout.SADDR != 0x7f){ +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } @@ -305,9 +308,12 @@ case 21: //GLOBAL_LOAD_DWORDX2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -if(layout.SADDR != 0x7f){ +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } @@ -320,9 +326,12 @@ case 22: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -if(layout.SADDR != 0x7f){ +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } @@ -336,9 +345,12 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -if(layout.SADDR != 0x7f){ +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } @@ -348,9 +360,12 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 24:case 25:case 26:case 27:case 28: //GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT,GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); @@ -361,9 +376,12 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 29: //GLOBAL_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); @@ -375,9 +393,12 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 30: //GLOBAL_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); if(layout.SADDR != 0x7f){ @@ -390,9 +411,12 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 31: //GLOBAL_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); @@ -407,9 +431,12 @@ break; case 64:case 66:case 67:case 68:case 69:case 70:case 71:case 72:case 73:case 74:case 75:case 76:case 77:case 78: //GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN,GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND,GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC,GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); @@ -422,9 +449,12 @@ case 65:case 96:case 98:case 99:case 100:case 101:case 102:case 103:case 104:cas //GLOBAL_ATOMIC_CMPSWAP,GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2,GLOBAL_ATOMIC_SUB_X2,GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2,GLOBAL_ATOMIC_SMAX_X2,GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2,GLOBAL_ATOMIC_OR_X2,GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2,GLOBAL_ATOMIC_DEC_X2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); if(layout.SADDR != 0x7f){ insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+0,2),true,false); @@ -440,9 +470,12 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); @@ -462,9 +495,14 @@ switch(layout.OP){ case 16:case 17:case 18:case 19:case 20:case 32:case 33:case 34:case 35:case 36:case 37: //SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT,SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI,SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16,SCRATCH_LOAD_SHORT_D16_HI insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -475,9 +513,14 @@ case 21: //SCRATCH_LOAD_DWORDX2 insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,2),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -489,9 +532,14 @@ case 22: insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,3),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -504,9 +552,14 @@ insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+0,4),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+1,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+2,0),false,true); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.VDST+3,0),false,true); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}if(layout.SADDR != 0x7f){ +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -515,10 +568,15 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 24:case 25:case 26:case 27:case 28: //SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT,SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA),true,false); if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -527,11 +585,16 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 29: //SCRATCH_STORE_DWORDX2 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,2),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -540,12 +603,17 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 30: //SCRATCH_STORE_DWORDX3 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,3),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); @@ -554,13 +622,18 @@ insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0, break; case 31: //SCRATCH_STORE_DWORDX4 -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR),true,false); -insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); +if(layout.SADDR == 0x7f){ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR+1,0),true,false); +}else{ +insn_in_progress->appendOperand(decodeOPR_VGPR(layout.ADDR,1),true,false); +}insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+0,4),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+1,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+2,0),true,false); insn_in_progress->appendOperand(decodeOPR_VGPR(layout.DATA+3,0),true,false); if(layout.SADDR != 0x7f){ -insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR,2),true,false); +insn_in_progress->appendOperand(decodeOPR_SREG(layout.SADDR+1,0),true,false); } insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(0),true,false,true); insn_in_progress->appendOperand(decodeOPR_SDST_M0(124),true,false,true); From 2473f27ef87af2c2ea41d17e20970cdbcd83435f Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Wed, 30 Nov 2022 06:42:55 -0600 Subject: [PATCH 176/505] fix logic for decoding src_literal, so it correctly consume the next 32 bit as data instead of decoding them as instruction --- instructionAPI/src/AMDGPU/gfx908/decodeOperands.C | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C index ada3322561..e50befb97c 100644 --- a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -1060,7 +1060,7 @@ case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elements ); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); +case 255 : return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -2159,7 +2159,7 @@ case 508 : return makeRegisterExpression(amdgpu_gfx908::v252, num_elements ); case 509 : return makeRegisterExpression(amdgpu_gfx908::v253, num_elements ); case 510 : return makeRegisterExpression(amdgpu_gfx908::v254, num_elements ); case 511 : return makeRegisterExpression(amdgpu_gfx908::v255, num_elements ); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); +case 255 : return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -4397,7 +4397,7 @@ case 236 : return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, num_el case 237 : return makeRegisterExpression(amdgpu_gfx908::src_private_base, num_elements ); case 238 : return makeRegisterExpression(amdgpu_gfx908::src_private_limit, num_elements ); case 239 : return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, num_elements ); -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); +case 255 : return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } @@ -5010,9 +5010,9 @@ case 254 : return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, num_elem default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } -Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t num_elements){ +Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_LIT(uint64_t input, uint32_t ){ switch(input){ -case 255 : return makeRegisterExpression(amdgpu_gfx908::src_literal, num_elements ); +case 255 : return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); default: return makeRegisterExpression(amdgpu_gfx908::invalid); } } From 73e59912986c623e4f8f21f2697693cc9d2c356f Mon Sep 17 00:00:00 2001 From: Bolo Date: Tue, 21 Feb 2023 15:13:54 -0600 Subject: [PATCH 177/505] Fix all-through instructions for newly added AMD gpu gfx908 Fixes #1375 for gfx908 (mi25 and mi200 already fixed) --- instructionAPI/src/Instruction.C | 2 ++ 1 file changed, 2 insertions(+) diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index c517190ab7..03fe44b3f3 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -542,6 +542,8 @@ namespace Dyninst case e_syscall: case amdgpu_op_s_setpc_b64: case amdgpu_op_s_swappc_b64: + case amdgpu_gfx908_op_S_SETPC_B64: + case amdgpu_gfx908_op_S_SWAPPC_B64: case amdgpu_cdna2_op_S_SETPC_B64: case amdgpu_cdna2_op_S_SWAPPC_B64: return false; From 52225454955728d2c262e22b978d55ef5823582d Mon Sep 17 00:00:00 2001 From: wuxx1279 Date: Wed, 22 Feb 2023 07:52:30 -0600 Subject: [PATCH 178/505] remove trailing usage of cout.clear --- .../src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C | 1 - 1 file changed, 1 deletion(-) diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C index 20be07ad32..47eea4d748 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -261,7 +261,6 @@ namespace Dyninst { InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); setupInsnWord(b); mainDecode(); - cout.clear(); Instruction* iptr = const_cast(insn_to_complete); *iptr = *(insn_in_progress.get()); } From 358db4610e4919690d928797713bef3cf67ef61d Mon Sep 17 00:00:00 2001 From: kupsch Date: Wed, 22 Feb 2023 09:51:01 -0600 Subject: [PATCH 179/505] explicitly include (#1384) - std::array is used in this file, but not included explicitly as on many systems this header is implicitly included recursively via another included file. On new versions of headers this may no longer be the case, so explicitly include it. --- instructionAPI/src/InstructionDecoder-aarch64.h | 1 + 1 file changed, 1 insertion(+) diff --git a/instructionAPI/src/InstructionDecoder-aarch64.h b/instructionAPI/src/InstructionDecoder-aarch64.h index 7994d0b1cc..ae516232a6 100644 --- a/instructionAPI/src/InstructionDecoder-aarch64.h +++ b/instructionAPI/src/InstructionDecoder-aarch64.h @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "InstructionDecoderImpl.h" #include #include "Immediate.h" From 0cd2b8b7858f48cd60e070010bb6600a1f44180e Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 22 Feb 2023 15:03:20 -0600 Subject: [PATCH 180/505] Add missing includes (#1385) These were showing up on ufront@rice. --- .../src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C | 1 + .../src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C | 1 + instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C | 1 + 3 files changed, 3 insertions(+) diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C index e852f47437..f62b1f5463 100644 --- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C +++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C @@ -30,6 +30,7 @@ #include "Ternary.h" #include "InstructionDecoder-amdgpu-cdna2.h" +#include namespace Dyninst { namespace InstructionAPI { diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C index 47eea4d748..70d9edc6f9 100644 --- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -30,6 +30,7 @@ #include "Ternary.h" #include "InstructionDecoder-amdgpu-gfx908.h" +#include namespace Dyninst { namespace InstructionAPI { diff --git a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C index 449255ae00..3093ece410 100644 --- a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C +++ b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C @@ -30,6 +30,7 @@ #include "Ternary.h" #include "InstructionDecoder-amdgpu-vega.h" +#include namespace Dyninst { namespace InstructionAPI { From 066e00e3c41e799bcc8031862ee016d551dcb3c4 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 22 Feb 2023 15:36:07 -0600 Subject: [PATCH 181/505] Update CHANGELOG --- CHANGELOG.md | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3d13d7b7d0..816b675d30 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,33 @@ # Change Log +## [12.3.0](https://github.com/dyninst/dyninst/tree/v12.3.0) (2023-02-22) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.2.1...v12.3.0) + +- Add missing includes ([1385](https://github.com/dyninst/dyninst/issues/1385)) +- explicitly include ([1384](https://github.com/dyninst/dyninst/issues/1384)) +- remove trailing usage of cout.clear ([1383](https://github.com/dyninst/dyninst/issues/1383)) +- Fix all-through instructions for newly added AMD gpu gfx908 ([1381](https://github.com/dyninst/dyninst/issues/1381)) +- Added support for gfx908 based on the XML-ISA-DROP for MI100 ([1283](https://github.com/dyninst/dyninst/issues/1283)) +- Allow CFG analysis based on instructionAPI alone w/out semantics ([1379](https://github.com/dyninst/dyninst/issues/1379)) +- Prevent fall-through analysis of amd gpu swap/set pc instructions ([1376](https://github.com/dyninst/dyninst/issues/1376)) +- x86 8-bit immediate values were interpreted incorrectly cross-platform. ([1373](https://github.com/dyninst/dyninst/issues/1373)) +- update spack.yaml for spack v0.19.1 ([1367](https://github.com/dyninst/dyninst/issues/1367)) +- Remove use of couts in the AMDGPU instruction decoders ([1371](https://github.com/dyninst/dyninst/issues/1371)) +- handle ENDBR64 ([1368](https://github.com/dyninst/dyninst/issues/1368)) +- Fixed nullptr issues in dyninstAPI/src/mapped_object.C ([1361](https://github.com/dyninst/dyninst/issues/1361)) +- Fix sema type for vex2 encoded vpand ([1364](https://github.com/dyninst/dyninst/issues/1364)) +- Replace DwarfWalker::findString with DwarfWalker::find_call_file ([1360](https://github.com/dyninst/dyninst/issues/1360)) +- Update detection of DWARF languages ([1357](https://github.com/dyninst/dyninst/issues/1357)) +- Remove AObject::pickLanguage ([1358](https://github.com/dyninst/dyninst/issues/1358)) +- BPatch_snippet::generateArrayRef - fix possible null pointer access ([1356](https://github.com/dyninst/dyninst/issues/1356)) +- Use instrumentation logging in baseTramp::guarded ([1354](https://github.com/dyninst/dyninst/issues/1354)) +- Remove special global ctor/dtor search in ppc for static binaries ([1353](https://github.com/dyninst/dyninst/issues/1353)) +- Refactor common/src/Types.h ([1351](https://github.com/dyninst/dyninst/issues/1351)) +- add missing include file ([1344](https://github.com/dyninst/dyninst/issues/1344)) +- Remove dead implementation of IA_power::isLinkerStub ([1342](https://github.com/dyninst/dyninst/issues/1342)) +- Lookup functions in the binding table directly ([1337](https://github.com/dyninst/dyninst/issues/1337)) +- Remove outdated Boost version checks ([1329](https://github.com/dyninst/dyninst/issues/1329)) + ## [12.2.1](https://github.com/dyninst/dyninst/tree/v12.2.1) (2022-11-21) [Full Changelog](https://github.com/dyninst/dyninst/compare/v12.2.0...v12.2.1) From 726cf1def17a473808385fb89750dee4b5a8fcb9 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 22 Feb 2023 15:36:24 -0600 Subject: [PATCH 182/505] Remove 'Branch states' from README --- README.md | 7 ------- 1 file changed, 7 deletions(-) diff --git a/README.md b/README.md index dc8f82095f..a0c1a2134b 100644 --- a/README.md +++ b/README.md @@ -1,12 +1,5 @@ # Dyninst -## Branch states - -| Branch | Status | Notes | -| --------------------------------------- |:-------------:|:--------------------------------------------------:| -| master | stable | See below | -| aarch32 | experimental | Contact Ray Chen (rchen at cs dot umd dot edu) | - ## Notes * Known issues should have open issues associated with them. From 334b6856e28fd34a698ad74aa277f1399a814183 Mon Sep 17 00:00:00 2001 From: Tim Haines Date: Wed, 22 Feb 2023 15:39:56 -0600 Subject: [PATCH 183/505] Documentation updates for v12.3.0 release (#1386) * Update version * Update documentation * Update copyright to 2023 --- COPYRIGHT | 2 +- cmake/shared.cmake | 4 ++-- common/doc/manual_frontpage.tex | 4 ++-- dataflowAPI/doc/dataflowAPI.pdf | Bin 349833 -> 360735 bytes dynC_API/doc/dynC_API.pdf | Bin 298530 -> 306884 bytes dyninstAPI/doc/dyninstAPI.docx | Bin 151289 -> 151965 bytes dyninstAPI/doc/dyninstAPI.pdf | Bin 422302 -> 418605 bytes instructionAPI/doc/instructionAPI.pdf | Bin 563449 -> 579919 bytes parseAPI/doc/parseAPI.pdf | Bin 404155 -> 424703 bytes parseAPI/h/SymLiteCodeSource.h | 2 +- parseAPI/src/CodeSource.C | 2 +- parseAPI/src/SymLiteCodeSource.C | 2 +- patchAPI/doc/patchAPI.pdf | Bin 614205 -> 625942 bytes proccontrol/doc/proccontrol.docx | Bin 108244 -> 108632 bytes proccontrol/doc/proccontrol.pdf | Bin 370687 -> 372111 bytes stackwalk/doc/stackwalk.pdf | Bin 318608 -> 328761 bytes symtabAPI/doc/symtabAPI.pdf | Bin 457099 -> 466345 bytes 17 files changed, 8 insertions(+), 8 deletions(-) diff --git a/COPYRIGHT b/COPYRIGHT index 9160abe3e5..3e3665702d 100644 --- a/COPYRIGHT +++ b/COPYRIGHT @@ -1,4 +1,4 @@ -Paradyn is Copyright (c) 1996-2022 Barton P. Miller +Paradyn is Copyright (c) 1996-2023 Barton P. Miller Contributions to Paradyn were developed by LLNS and have the following copyright: Copyright (c) 2012-2013, Lawrence Livermore National Security, LLC. Produced at diff --git a/cmake/shared.cmake b/cmake/shared.cmake index 15045380fe..c0e48ab1f1 100644 --- a/cmake/shared.cmake +++ b/cmake/shared.cmake @@ -1,6 +1,6 @@ set(DYNINST_MAJOR_VERSION 12) -set(DYNINST_MINOR_VERSION 2) -set(DYNINST_PATCH_VERSION 1) +set(DYNINST_MINOR_VERSION 3) +set(DYNINST_PATCH_VERSION 0) set(SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") set(LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") diff --git a/common/doc/manual_frontpage.tex b/common/doc/manual_frontpage.tex index 160610633d..35036e7b00 100644 --- a/common/doc/manual_frontpage.tex +++ b/common/doc/manual_frontpage.tex @@ -42,9 +42,9 @@ % }; \node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$) - {\fontsize{24}{32}\selectfont 12.2 Release}; + {\fontsize{24}{32}\selectfont 12.3 Release}; \node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$) - {\fontsize{24}{32}\selectfont July 2022}; + {\fontsize{24}{32}\selectfont February 2023}; % Contact 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